Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

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stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.869789 # Number of seconds simulated 4sim_ticks 2869788970000 # Number of ticks simulated 5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.869789 # Number of seconds simulated 4sim_ticks 2869788970000 # Number of ticks simulated 5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 932940 # Simulator instruction rate (inst/s) 8host_op_rate 1128445 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20351712140 # Simulator tick rate (ticks/s) 10host_mem_usage 661084 # Number of bytes of host memory used 11host_seconds 141.01 # Real time elapsed on the host	7host_inst_rate 540600 # Simulator instruction rate (inst/s) 8host_op_rate 653886 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11792964574 # Simulator tick rate (ticks/s) 10host_mem_usage 618088 # Number of bytes of host memory used 11host_seconds 243.35 # Real time elapsed on the host
12sim_insts 131553574 # Number of instructions simulated 13sim_ops 159121622 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 567572 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 385664 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12103024 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1162532 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 146452 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1308984 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8649280 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8666844 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26618 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20544 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 133714 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 2443 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 8889 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.l2cache.prefetcher 6026 # Number of read requests responded to by this memory 42system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 43system.physmem.num_reads::total 198258 # Number of read requests responded to by this memory 44system.physmem.num_writes::writebacks 135145 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 47system.physmem.num_writes::total 139536 # Number of write requests responded to by this memory 48system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 405093 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 446574 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.l2cache.prefetcher 2981995 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 51032 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 197775 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.l2cache.prefetcher 134388 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::total 4217392 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu0.inst 405093 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::cpu1.inst 51032 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::total 456126 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_write::writebacks 3013908 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::total 3020028 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_total::writebacks 3013908 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 405093 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 452680 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.l2cache.prefetcher 2981995 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 51032 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 197789 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.l2cache.prefetcher 134388 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::total 7237420 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.readReqs 198258 # Number of read requests accepted 77system.physmem.writeReqs 139536 # Number of write requests accepted 78system.physmem.readBursts 198258 # Number of DRAM read bursts, including those serviced by the write queue 79system.physmem.writeBursts 139536 # Number of DRAM write bursts, including those merged in the write queue 80system.physmem.bytesReadDRAM 12678976 # Total number of bytes read from DRAM 81system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue 82system.physmem.bytesWritten 8679232 # Total number of bytes written to DRAM 83system.physmem.bytesReadSys 12103024 # Total read bytes from the system interface side 84system.physmem.bytesWrittenSys 8666844 # Total written bytes from the system interface side 85system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue 86system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 87system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 88system.physmem.perBankRdBursts::0 11529 # Per bank write bursts 89system.physmem.perBankRdBursts::1 11853 # Per bank write bursts 90system.physmem.perBankRdBursts::2 12105 # Per bank write bursts 91system.physmem.perBankRdBursts::3 12154 # Per bank write bursts 92system.physmem.perBankRdBursts::4 20931 # Per bank write bursts 93system.physmem.perBankRdBursts::5 12788 # Per bank write bursts 94system.physmem.perBankRdBursts::6 12012 # Per bank write bursts 95system.physmem.perBankRdBursts::7 12170 # Per bank write bursts 96system.physmem.perBankRdBursts::8 12327 # Per bank write bursts 97system.physmem.perBankRdBursts::9 12530 # Per bank write bursts 98system.physmem.perBankRdBursts::10 11492 # Per bank write bursts 99system.physmem.perBankRdBursts::11 10989 # Per bank write bursts 100system.physmem.perBankRdBursts::12 11634 # Per bank write bursts 101system.physmem.perBankRdBursts::13 11866 # Per bank write bursts 102system.physmem.perBankRdBursts::14 10750 # Per bank write bursts 103system.physmem.perBankRdBursts::15 10979 # Per bank write bursts 104system.physmem.perBankWrBursts::0 8343 # Per bank write bursts 105system.physmem.perBankWrBursts::1 8774 # Per bank write bursts 106system.physmem.perBankWrBursts::2 9050 # Per bank write bursts 107system.physmem.perBankWrBursts::3 8765 # Per bank write bursts 108system.physmem.perBankWrBursts::4 8633 # Per bank write bursts 109system.physmem.perBankWrBursts::5 9228 # Per bank write bursts 110system.physmem.perBankWrBursts::6 8690 # Per bank write bursts 111system.physmem.perBankWrBursts::7 8516 # Per bank write bursts 112system.physmem.perBankWrBursts::8 8766 # Per bank write bursts 113system.physmem.perBankWrBursts::9 8956 # Per bank write bursts 114system.physmem.perBankWrBursts::10 8280 # Per bank write bursts 115system.physmem.perBankWrBursts::11 8060 # Per bank write bursts 116system.physmem.perBankWrBursts::12 8431 # Per bank write bursts 117system.physmem.perBankWrBursts::13 8106 # Per bank write bursts 118system.physmem.perBankWrBursts::14 7529 # Per bank write bursts 119system.physmem.perBankWrBursts::15 7486 # Per bank write bursts 120system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 121system.physmem.numWrRetry 45 # Number of times write queue was full causing retry 122system.physmem.totGap 2869788469000 # Total gap between requests 123system.physmem.readPktSize::0 0 # Read request sizes (log2) 124system.physmem.readPktSize::1 0 # Read request sizes (log2) 125system.physmem.readPktSize::2 9732 # Read request sizes (log2) 126system.physmem.readPktSize::3 28 # Read request sizes (log2) 127system.physmem.readPktSize::4 0 # Read request sizes (log2) 128system.physmem.readPktSize::5 0 # Read request sizes (log2) 129system.physmem.readPktSize::6 188498 # Read request sizes (log2) 130system.physmem.writePktSize::0 0 # Write request sizes (log2) 131system.physmem.writePktSize::1 0 # Write request sizes (log2) 132system.physmem.writePktSize::2 4391 # Write request sizes (log2) 133system.physmem.writePktSize::3 0 # Write request sizes (log2) 134system.physmem.writePktSize::4 0 # Write request sizes (log2) 135system.physmem.writePktSize::5 0 # Write request sizes (log2) 136system.physmem.writePktSize::6 135145 # Write request sizes (log2) 137system.physmem.rdQLenPdf::0 138706 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::1 15839 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::2 10261 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::3 8725 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::4 6930 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::5 5461 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::6 4641 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::7 3898 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::8 3401 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::9 95 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::10 62 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::11 46 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::13 12 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 169system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::15 2819 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::16 3840 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::18 5706 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::19 6587 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::20 6581 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::21 7205 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::22 7662 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::23 8640 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::24 8482 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::25 9948 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::26 10382 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::28 8458 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::29 9785 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::30 8058 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::31 7351 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::32 7133 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::36 141 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::42 177 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::46 192 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::47 145 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::48 96 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::50 116 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::52 72 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::53 55 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see 233system.physmem.bytesPerActivate::samples 89189 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::mean 239.470607 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::gmean 135.176312 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::stdev 302.792926 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::0-127 47900 53.71% 53.71% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::128-255 17682 19.83% 73.53% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::256-383 5838 6.55% 80.08% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::384-511 3495 3.92% 84.00% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::512-639 2471 2.77% 86.77% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::640-767 1457 1.63% 88.40% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::896-1023 998 1.12% 90.69% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::1024-1151 8300 9.31% 100.00% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::total 89189 # Bytes accessed per row activation 247system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::mean 29.638989 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::stdev 578.089254 # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::0-2047 6683 99.99% 99.99% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 20.289198 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 18.751921 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 12.518584 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16-19 5662 84.71% 84.71% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::20-23 280 4.19% 88.90% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::24-27 70 1.05% 89.95% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::28-31 44 0.66% 90.60% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::32-35 285 4.26% 94.87% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::36-39 29 0.43% 95.30% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::40-43 28 0.42% 95.72% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::44-47 27 0.40% 96.13% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::48-51 17 0.25% 96.38% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::52-55 10 0.15% 96.53% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::56-59 5 0.07% 96.60% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::60-63 9 0.13% 96.74% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::64-67 159 2.38% 99.12% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::68-71 2 0.03% 99.15% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::72-75 11 0.16% 99.31% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::76-79 1 0.01% 99.33% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::80-83 9 0.13% 99.46% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::100-103 1 0.01% 99.54% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::120-123 2 0.03% 99.66% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::128-131 8 0.12% 99.78% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::132-135 5 0.07% 99.85% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::140-143 1 0.01% 99.87% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::148-151 2 0.03% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads 290system.physmem.totQLat 4572903146 # Total ticks spent queuing 291system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM 292system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers 293system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst 294system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 295system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst 296system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s 297system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s 298system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s 299system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s 300system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 301system.physmem.busUtil 0.06 # Data bus utilization in percentage 302system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 303system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 304system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 305system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing 306system.physmem.readRowHits 165757 # Number of row buffer hits during reads 307system.physmem.writeRowHits 78775 # Number of row buffer hits during writes 308system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads 309system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes 310system.physmem.avgGap 8495676.27 # Average gap between requests 311system.physmem.pageHitRate 73.27 # Row buffer hit rate, read and write combined 312system.physmem_0.actEnergy 348221160 # Energy for activate commands per rank (pJ) 313system.physmem_0.preEnergy 190001625 # Energy for precharge commands per rank (pJ) 314system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ) 315system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ) 316system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) 317system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ) 318system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ) 319system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ) 320system.physmem_0.averagePower 669.573415 # Core power per rank (mW) 321system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states 322system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states 323system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 324system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states 325system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 326system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ) 327system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ) 328system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ) 329system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ) 330system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) 331system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ) 332system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ) 333system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ) 334system.physmem_1.averagePower 669.487743 # Core power per rank (mW) 335system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states 336system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states 337system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 338system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states 339system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 340system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 341system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 347system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 349system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 350system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 358system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 359system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 360system.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 361system.bridge.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 362system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 631 # Number of DMA write transactions. 368system.cpu_clk_domain.clock 500 # Clock period in ticks 369system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 379system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 380system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 381system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 382system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 383system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 384system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 385system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 386system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 387system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 388system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 389system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 390system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 391system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 392system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 394system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 395system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 396system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 397system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 398system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 399system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 400system.cpu0.dtb.walker.walks 7943 # Table walker walks requested 401system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors 402system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate 403system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6442 # Level at which table walker walks with short descriptors terminate 404system.cpu0.dtb.walker.walkWaitTime::samples 7943 # Table walker wait (enqueue to first request) latency 405system.cpu0.dtb.walker.walkWaitTime::0 7943 100.00% 100.00% # Table walker wait (enqueue to first request) latency 406system.cpu0.dtb.walker.walkWaitTime::total 7943 # Table walker wait (enqueue to first request) latency 407system.cpu0.dtb.walker.walkCompletionTime::samples 6549 # Table walker service (enqueue to completion) latency 408system.cpu0.dtb.walker.walkCompletionTime::mean 12300.885631 # Table walker service (enqueue to completion) latency 409system.cpu0.dtb.walker.walkCompletionTime::gmean 11415.801761 # Table walker service (enqueue to completion) latency 410system.cpu0.dtb.walker.walkCompletionTime::stdev 5728.954139 # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::0-16383 6064 92.59% 92.59% # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::16384-32767 441 6.73% 99.33% # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.85% # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.91% # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::total 6549 # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution 421system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution 422system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution 423system.cpu0.dtb.walker.walkPageSizes::4K 5087 77.68% 77.68% # Table walker page sizes translated 424system.cpu0.dtb.walker.walkPageSizes::1M 1462 22.32% 100.00% # Table walker page sizes translated 425system.cpu0.dtb.walker.walkPageSizes::total 6549 # Table walker page sizes translated 426system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7943 # Table walker requests started/completed, data/inst 427system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7943 # Table walker requests started/completed, data/inst 429system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6549 # Table walker requests started/completed, data/inst 430system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 # Table walker requests started/completed, data/inst 432system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst 433system.cpu0.dtb.inst_hits 0 # ITB inst hits 434system.cpu0.dtb.inst_misses 0 # ITB inst misses 435system.cpu0.dtb.read_hits 25156508 # DTB read hits 436system.cpu0.dtb.read_misses 6829 # DTB read misses 437system.cpu0.dtb.write_hits 18749941 # DTB write hits 438system.cpu0.dtb.write_misses 1114 # DTB write misses 439system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 440system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 441system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 442system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	12sim_insts 131553574 # Number of instructions simulated 13sim_ops 159121622 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 567572 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 385664 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12103024 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1162532 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 146452 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1308984 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8649280 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8666844 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26618 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20544 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 133714 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.inst 2443 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 8889 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.l2cache.prefetcher 6026 # Number of read requests responded to by this memory 42system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 43system.physmem.num_reads::total 198258 # Number of read requests responded to by this memory 44system.physmem.num_writes::writebacks 135145 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 47system.physmem.num_writes::total 139536 # Number of write requests responded to by this memory 48system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 405093 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 446574 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.l2cache.prefetcher 2981995 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.inst 51032 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 197775 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.l2cache.prefetcher 134388 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::total 4217392 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu0.inst 405093 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::cpu1.inst 51032 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::total 456126 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_write::writebacks 3013908 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::total 3020028 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_total::writebacks 3013908 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 405093 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 452680 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.l2cache.prefetcher 2981995 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.inst 51032 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 197789 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.l2cache.prefetcher 134388 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::total 7237420 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.readReqs 198258 # Number of read requests accepted 77system.physmem.writeReqs 139536 # Number of write requests accepted 78system.physmem.readBursts 198258 # Number of DRAM read bursts, including those serviced by the write queue 79system.physmem.writeBursts 139536 # Number of DRAM write bursts, including those merged in the write queue 80system.physmem.bytesReadDRAM 12678976 # Total number of bytes read from DRAM 81system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue 82system.physmem.bytesWritten 8679232 # Total number of bytes written to DRAM 83system.physmem.bytesReadSys 12103024 # Total read bytes from the system interface side 84system.physmem.bytesWrittenSys 8666844 # Total written bytes from the system interface side 85system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue 86system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one 87system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 88system.physmem.perBankRdBursts::0 11529 # Per bank write bursts 89system.physmem.perBankRdBursts::1 11853 # Per bank write bursts 90system.physmem.perBankRdBursts::2 12105 # Per bank write bursts 91system.physmem.perBankRdBursts::3 12154 # Per bank write bursts 92system.physmem.perBankRdBursts::4 20931 # Per bank write bursts 93system.physmem.perBankRdBursts::5 12788 # Per bank write bursts 94system.physmem.perBankRdBursts::6 12012 # Per bank write bursts 95system.physmem.perBankRdBursts::7 12170 # Per bank write bursts 96system.physmem.perBankRdBursts::8 12327 # Per bank write bursts 97system.physmem.perBankRdBursts::9 12530 # Per bank write bursts 98system.physmem.perBankRdBursts::10 11492 # Per bank write bursts 99system.physmem.perBankRdBursts::11 10989 # Per bank write bursts 100system.physmem.perBankRdBursts::12 11634 # Per bank write bursts 101system.physmem.perBankRdBursts::13 11866 # Per bank write bursts 102system.physmem.perBankRdBursts::14 10750 # Per bank write bursts 103system.physmem.perBankRdBursts::15 10979 # Per bank write bursts 104system.physmem.perBankWrBursts::0 8343 # Per bank write bursts 105system.physmem.perBankWrBursts::1 8774 # Per bank write bursts 106system.physmem.perBankWrBursts::2 9050 # Per bank write bursts 107system.physmem.perBankWrBursts::3 8765 # Per bank write bursts 108system.physmem.perBankWrBursts::4 8633 # Per bank write bursts 109system.physmem.perBankWrBursts::5 9228 # Per bank write bursts 110system.physmem.perBankWrBursts::6 8690 # Per bank write bursts 111system.physmem.perBankWrBursts::7 8516 # Per bank write bursts 112system.physmem.perBankWrBursts::8 8766 # Per bank write bursts 113system.physmem.perBankWrBursts::9 8956 # Per bank write bursts 114system.physmem.perBankWrBursts::10 8280 # Per bank write bursts 115system.physmem.perBankWrBursts::11 8060 # Per bank write bursts 116system.physmem.perBankWrBursts::12 8431 # Per bank write bursts 117system.physmem.perBankWrBursts::13 8106 # Per bank write bursts 118system.physmem.perBankWrBursts::14 7529 # Per bank write bursts 119system.physmem.perBankWrBursts::15 7486 # Per bank write bursts 120system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 121system.physmem.numWrRetry 45 # Number of times write queue was full causing retry 122system.physmem.totGap 2869788469000 # Total gap between requests 123system.physmem.readPktSize::0 0 # Read request sizes (log2) 124system.physmem.readPktSize::1 0 # Read request sizes (log2) 125system.physmem.readPktSize::2 9732 # Read request sizes (log2) 126system.physmem.readPktSize::3 28 # Read request sizes (log2) 127system.physmem.readPktSize::4 0 # Read request sizes (log2) 128system.physmem.readPktSize::5 0 # Read request sizes (log2) 129system.physmem.readPktSize::6 188498 # Read request sizes (log2) 130system.physmem.writePktSize::0 0 # Write request sizes (log2) 131system.physmem.writePktSize::1 0 # Write request sizes (log2) 132system.physmem.writePktSize::2 4391 # Write request sizes (log2) 133system.physmem.writePktSize::3 0 # Write request sizes (log2) 134system.physmem.writePktSize::4 0 # Write request sizes (log2) 135system.physmem.writePktSize::5 0 # Write request sizes (log2) 136system.physmem.writePktSize::6 135145 # Write request sizes (log2) 137system.physmem.rdQLenPdf::0 138706 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::1 15839 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::2 10261 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::3 8725 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::4 6930 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::5 5461 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::6 4641 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::7 3898 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::8 3401 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::9 95 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::10 62 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::11 46 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::13 12 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 169system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::15 2819 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::16 3840 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::18 5706 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::19 6587 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::20 6581 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::21 7205 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::22 7662 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::23 8640 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::24 8482 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::25 9948 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::26 10382 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::28 8458 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::29 9785 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::30 8058 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::31 7351 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::32 7133 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::36 141 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::42 177 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::46 192 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::47 145 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::48 96 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::50 116 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::52 72 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::53 55 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see 233system.physmem.bytesPerActivate::samples 89189 # Bytes accessed per row activation 234system.physmem.bytesPerActivate::mean 239.470607 # Bytes accessed per row activation 235system.physmem.bytesPerActivate::gmean 135.176312 # Bytes accessed per row activation 236system.physmem.bytesPerActivate::stdev 302.792926 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::0-127 47900 53.71% 53.71% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::128-255 17682 19.83% 73.53% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::256-383 5838 6.55% 80.08% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::384-511 3495 3.92% 84.00% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::512-639 2471 2.77% 86.77% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::640-767 1457 1.63% 88.40% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::896-1023 998 1.12% 90.69% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::1024-1151 8300 9.31% 100.00% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::total 89189 # Bytes accessed per row activation 247system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes 248system.physmem.rdPerTurnAround::mean 29.638989 # Reads before turning the bus around for writes 249system.physmem.rdPerTurnAround::stdev 578.089254 # Reads before turning the bus around for writes 250system.physmem.rdPerTurnAround::0-2047 6683 99.99% 99.99% # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes 253system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::mean 20.289198 # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::gmean 18.751921 # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::stdev 12.518584 # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::16-19 5662 84.71% 84.71% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::20-23 280 4.19% 88.90% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::24-27 70 1.05% 89.95% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::28-31 44 0.66% 90.60% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::32-35 285 4.26% 94.87% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::36-39 29 0.43% 95.30% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::40-43 28 0.42% 95.72% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::44-47 27 0.40% 96.13% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::48-51 17 0.25% 96.38% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::52-55 10 0.15% 96.53% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::56-59 5 0.07% 96.60% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::60-63 9 0.13% 96.74% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::64-67 159 2.38% 99.12% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::68-71 2 0.03% 99.15% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::72-75 11 0.16% 99.31% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::76-79 1 0.01% 99.33% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::80-83 9 0.13% 99.46% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::100-103 1 0.01% 99.54% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::120-123 2 0.03% 99.66% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::128-131 8 0.12% 99.78% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::132-135 5 0.07% 99.85% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::140-143 1 0.01% 99.87% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::148-151 2 0.03% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads 290system.physmem.totQLat 4572903146 # Total ticks spent queuing 291system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM 292system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers 293system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst 294system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 295system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst 296system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s 297system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s 298system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s 299system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s 300system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 301system.physmem.busUtil 0.06 # Data bus utilization in percentage 302system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 303system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 304system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 305system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing 306system.physmem.readRowHits 165757 # Number of row buffer hits during reads 307system.physmem.writeRowHits 78775 # Number of row buffer hits during writes 308system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads 309system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes 310system.physmem.avgGap 8495676.27 # Average gap between requests 311system.physmem.pageHitRate 73.27 # Row buffer hit rate, read and write combined 312system.physmem_0.actEnergy 348221160 # Energy for activate commands per rank (pJ) 313system.physmem_0.preEnergy 190001625 # Energy for precharge commands per rank (pJ) 314system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ) 315system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ) 316system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) 317system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ) 318system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ) 319system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ) 320system.physmem_0.averagePower 669.573415 # Core power per rank (mW) 321system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states 322system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states 323system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 324system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states 325system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 326system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ) 327system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ) 328system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ) 329system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ) 330system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) 331system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ) 332system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ) 333system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ) 334system.physmem_1.averagePower 669.487743 # Core power per rank (mW) 335system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states 336system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states 337system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 338system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states 339system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 340system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 341system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 342system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 344system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 347system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 349system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 350system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 358system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 359system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 360system.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 361system.bridge.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 362system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 631 # Number of DMA write transactions. 368system.cpu_clk_domain.clock 500 # Clock period in ticks 369system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 379system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 380system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 381system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 382system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 383system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 384system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 385system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 386system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 387system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 388system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 389system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 390system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 391system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 392system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 393system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 394system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 395system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 396system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 397system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 398system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 399system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 400system.cpu0.dtb.walker.walks 7943 # Table walker walks requested 401system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors 402system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate 403system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6442 # Level at which table walker walks with short descriptors terminate 404system.cpu0.dtb.walker.walkWaitTime::samples 7943 # Table walker wait (enqueue to first request) latency 405system.cpu0.dtb.walker.walkWaitTime::0 7943 100.00% 100.00% # Table walker wait (enqueue to first request) latency 406system.cpu0.dtb.walker.walkWaitTime::total 7943 # Table walker wait (enqueue to first request) latency 407system.cpu0.dtb.walker.walkCompletionTime::samples 6549 # Table walker service (enqueue to completion) latency 408system.cpu0.dtb.walker.walkCompletionTime::mean 12300.885631 # Table walker service (enqueue to completion) latency 409system.cpu0.dtb.walker.walkCompletionTime::gmean 11415.801761 # Table walker service (enqueue to completion) latency 410system.cpu0.dtb.walker.walkCompletionTime::stdev 5728.954139 # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::0-16383 6064 92.59% 92.59% # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::16384-32767 441 6.73% 99.33% # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.85% # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.91% # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::total 6549 # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution 421system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution 422system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution 423system.cpu0.dtb.walker.walkPageSizes::4K 5087 77.68% 77.68% # Table walker page sizes translated 424system.cpu0.dtb.walker.walkPageSizes::1M 1462 22.32% 100.00% # Table walker page sizes translated 425system.cpu0.dtb.walker.walkPageSizes::total 6549 # Table walker page sizes translated 426system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7943 # Table walker requests started/completed, data/inst 427system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 428system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7943 # Table walker requests started/completed, data/inst 429system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6549 # Table walker requests started/completed, data/inst 430system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 431system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 # Table walker requests started/completed, data/inst 432system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst 433system.cpu0.dtb.inst_hits 0 # ITB inst hits 434system.cpu0.dtb.inst_misses 0 # ITB inst misses 435system.cpu0.dtb.read_hits 25156508 # DTB read hits 436system.cpu0.dtb.read_misses 6829 # DTB read misses 437system.cpu0.dtb.write_hits 18749941 # DTB write hits 438system.cpu0.dtb.write_misses 1114 # DTB write misses 439system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 440system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 441system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 442system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
443system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB	443system.cpu0.dtb.flush_entries 3392 # Number of entries that have been flushed from TLB
444system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 445system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch 446system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 448system.cpu0.dtb.read_accesses 25163337 # DTB read accesses 449system.cpu0.dtb.write_accesses 18751055 # DTB write accesses 450system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 451system.cpu0.dtb.hits 43906449 # DTB hits 452system.cpu0.dtb.misses 7943 # DTB misses 453system.cpu0.dtb.accesses 43914392 # DTB accesses 454system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 455system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 456system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 463system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 464system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 465system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 466system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 467system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 468system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 469system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 470system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 471system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 472system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 473system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 474system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 475system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 476system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 478system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 479system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 480system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 481system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 482system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 483system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 484system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 485system.cpu0.itb.walker.walks 3349 # Table walker walks requested 486system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors 487system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate 488system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 489system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency 490system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency 491system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency 492system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency 493system.cpu0.itb.walker.walkCompletionTime::mean 12856.622375 # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::gmean 12024.130170 # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::stdev 5718.443506 # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::0-8191 360 15.43% 15.43% # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::8192-16383 1695 72.65% 88.08% # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::16384-24575 216 9.26% 97.34% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.24% 98.59% # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::32768-40959 29 1.24% 99.83% # Table walker service (enqueue to completion) latency 501system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency 502system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency 503system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 504system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 505system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency 506system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution 507system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution 508system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution 509system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated 510system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated 511system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated 512system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 513system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst 514system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst 515system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 516system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst 517system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst 518system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst 519system.cpu0.itb.inst_hits 119016789 # ITB inst hits 520system.cpu0.itb.inst_misses 3349 # ITB inst misses 521system.cpu0.itb.read_hits 0 # DTB read hits 522system.cpu0.itb.read_misses 0 # DTB read misses 523system.cpu0.itb.write_hits 0 # DTB write hits 524system.cpu0.itb.write_misses 0 # DTB write misses 525system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 526system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 527system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 528system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	444system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 445system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch 446system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 448system.cpu0.dtb.read_accesses 25163337 # DTB read accesses 449system.cpu0.dtb.write_accesses 18751055 # DTB write accesses 450system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 451system.cpu0.dtb.hits 43906449 # DTB hits 452system.cpu0.dtb.misses 7943 # DTB misses 453system.cpu0.dtb.accesses 43914392 # DTB accesses 454system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 455system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 456system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 463system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 464system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 465system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 466system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 467system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 468system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 469system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 470system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 471system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 472system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 473system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 474system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 475system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 476system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 478system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 479system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 480system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 481system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 482system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 483system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 484system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 485system.cpu0.itb.walker.walks 3349 # Table walker walks requested 486system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors 487system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate 488system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate 489system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency 490system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency 491system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency 492system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency 493system.cpu0.itb.walker.walkCompletionTime::mean 12856.622375 # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walkCompletionTime::gmean 12024.130170 # Table walker service (enqueue to completion) latency 495system.cpu0.itb.walker.walkCompletionTime::stdev 5718.443506 # Table walker service (enqueue to completion) latency 496system.cpu0.itb.walker.walkCompletionTime::0-8191 360 15.43% 15.43% # Table walker service (enqueue to completion) latency 497system.cpu0.itb.walker.walkCompletionTime::8192-16383 1695 72.65% 88.08% # Table walker service (enqueue to completion) latency 498system.cpu0.itb.walker.walkCompletionTime::16384-24575 216 9.26% 97.34% # Table walker service (enqueue to completion) latency 499system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.24% 98.59% # Table walker service (enqueue to completion) latency 500system.cpu0.itb.walker.walkCompletionTime::32768-40959 29 1.24% 99.83% # Table walker service (enqueue to completion) latency 501system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency 502system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency 503system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 504system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 505system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency 506system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution 507system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution 508system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution 509system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated 510system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated 511system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated 512system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 513system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst 514system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst 515system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 516system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst 517system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst 518system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst 519system.cpu0.itb.inst_hits 119016789 # ITB inst hits 520system.cpu0.itb.inst_misses 3349 # ITB inst misses 521system.cpu0.itb.read_hits 0 # DTB read hits 522system.cpu0.itb.read_misses 0 # DTB read misses 523system.cpu0.itb.write_hits 0 # DTB write hits 524system.cpu0.itb.write_misses 0 # DTB write misses 525system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 526system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 527system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 528system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
529system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB	529system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB
530system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 531system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 532system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 533system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 534system.cpu0.itb.read_accesses 0 # DTB read accesses 535system.cpu0.itb.write_accesses 0 # DTB write accesses 536system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses 537system.cpu0.itb.hits 119016789 # DTB hits 538system.cpu0.itb.misses 3349 # DTB misses 539system.cpu0.itb.accesses 119020138 # DTB accesses 540system.cpu0.numPwrStateTransitions 3732 # Number of power state transitions 541system.cpu0.pwrStateClkGateDist::samples 1866 # Distribution of time spent in the clock gated state 542system.cpu0.pwrStateClkGateDist::mean 1464105256.698285 # Distribution of time spent in the clock gated state 543system.cpu0.pwrStateClkGateDist::stdev 23703834177.511120 # Distribution of time spent in the clock gated state 544system.cpu0.pwrStateClkGateDist::underflows 1075 57.61% 57.61% # Distribution of time spent in the clock gated state 545system.cpu0.pwrStateClkGateDist::1000-5e+10 786 42.12% 99.73% # Distribution of time spent in the clock gated state 546system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state 547system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state 548system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 549system.cpu0.pwrStateClkGateDist::max_value 499964077872 # Distribution of time spent in the clock gated state 550system.cpu0.pwrStateClkGateDist::total 1866 # Distribution of time spent in the clock gated state 551system.cpu0.pwrStateResidencyTicks::ON 137768561001 # Cumulative time (in ticks) in various power states 552system.cpu0.pwrStateResidencyTicks::CLK_GATED 2732020408999 # Cumulative time (in ticks) in various power states 553system.cpu0.numCycles 5739577940 # number of cpu cycles simulated 554system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 555system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 556system.cpu0.kern.inst.arm 0 # number of arm instructions executed 557system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed 558system.cpu0.committedInsts 115352405 # Number of instructions committed 559system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed 560system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses 561system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses 562system.cpu0.num_func_calls 12675179 # number of times a function call or return occured 563system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls 564system.cpu0.num_int_insts 123360698 # number of integer instructions 565system.cpu0.num_fp_insts 9756 # number of float instructions 566system.cpu0.num_int_register_reads 227063318 # number of times the integer registers were read 567system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written 568system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read 569system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 570system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read 571system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written 572system.cpu0.num_mem_refs 45042977 # number of memory refs 573system.cpu0.num_load_insts 25408336 # Number of load instructions 574system.cpu0.num_store_insts 19634641 # Number of store instructions 575system.cpu0.num_idle_cycles 5464040817.996096 # Number of idle cycles 576system.cpu0.num_busy_cycles 275537122.003904 # Number of busy cycles 577system.cpu0.not_idle_fraction 0.048007 # Percentage of non-idle cycles 578system.cpu0.idle_fraction 0.951993 # Percentage of idle cycles 579system.cpu0.Branches 29113703 # Number of branches fetched 580system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 581system.cpu0.op_class::IntAlu 97981864 68.45% 68.45% # Class of executed instruction 582system.cpu0.op_class::IntMult 109763 0.08% 68.53% # Class of executed instruction 583system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction 584system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction 585system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction 586system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction 587system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction 588system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction 589system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction 590system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction 591system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction 592system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction 593system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction 594system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction 595system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction 596system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction 597system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction 598system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction 599system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction 600system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction 601system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction 602system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction 603system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction 604system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction 605system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction 606system.cpu0.op_class::SimdFloatMisc 8197 0.01% 68.53% # Class of executed instruction 607system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction 608system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction 609system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction 610system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction 611system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction 612system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 613system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 614system.cpu0.op_class::total 143145074 # Class of executed instruction 615system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 616system.cpu0.dcache.tags.replacements 692159 # number of replacements 617system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use 618system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks. 619system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. 620system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks. 621system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. 622system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor 623system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy 624system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy 625system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 626system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 627system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 628system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id 629system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 630system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses 631system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses 632system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 633system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits 634system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits 635system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits 636system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits 637system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits 638system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits 639system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits 640system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits 641system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits 642system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits 643system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits 644system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits 645system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits 646system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits 647system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses 648system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses 649system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses 650system.cpu0.dcache.WriteReq_misses::total 325040 # number of WriteReq misses 651system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127692 # number of SoftPFReq misses 652system.cpu0.dcache.SoftPFReq_misses::total 127692 # number of SoftPFReq misses 653system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21584 # number of LoadLockedReq misses 654system.cpu0.dcache.LoadLockedReq_misses::total 21584 # number of LoadLockedReq misses 655system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19801 # number of StoreCondReq misses 656system.cpu0.dcache.StoreCondReq_misses::total 19801 # number of StoreCondReq misses 657system.cpu0.dcache.demand_misses::cpu0.data 721136 # number of demand (read+write) misses 658system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses 659system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses 660system.cpu0.dcache.overall_misses::total 848828 # number of overall misses 661system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles 662system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles 663system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles 664system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles 665system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles 666system.cpu0.dcache.LoadLockedReq_miss_latency::total 329182500 # number of LoadLockedReq miss cycles 667system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 # number of StoreCondReq miss cycles 668system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles 669system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles 670system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles 671system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles 672system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles 673system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles 674system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles 675system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses) 676system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses) 677system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses) 678system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses) 679system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses) 680system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses) 681system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses) 682system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses) 683system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses) 684system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses) 685system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses 686system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses 687system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses 688system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses 689system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses 690system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses 691system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses 692system.cpu0.dcache.WriteReq_miss_rate::total 0.017720 # miss rate for WriteReq accesses 693system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285794 # miss rate for SoftPFReq accesses 694system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285794 # miss rate for SoftPFReq accesses 695system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055760 # miss rate for LoadLockedReq accesses 696system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055760 # miss rate for LoadLockedReq accesses 697system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051813 # miss rate for StoreCondReq accesses 698system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051813 # miss rate for StoreCondReq accesses 699system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 # miss rate for demand accesses 700system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses 701system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses 702system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses 703system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency 704system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency 705system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency 706system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency 707system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency 708system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15251.227761 # average LoadLockedReq miss latency 709system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 # average StoreCondReq miss latency 710system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency 711system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 712system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 713system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency 714system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency 715system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency 716system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency 717system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 718system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 720system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 722system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu0.dcache.writebacks::writebacks 692159 # number of writebacks 724system.cpu0.dcache.writebacks::total 692159 # number of writebacks 725system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25284 # number of ReadReq MSHR hits 726system.cpu0.dcache.ReadReq_mshr_hits::total 25284 # number of ReadReq MSHR hits 727system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15032 # number of LoadLockedReq MSHR hits 728system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15032 # number of LoadLockedReq MSHR hits 729system.cpu0.dcache.demand_mshr_hits::cpu0.data 25284 # number of demand (read+write) MSHR hits 730system.cpu0.dcache.demand_mshr_hits::total 25284 # number of demand (read+write) MSHR hits 731system.cpu0.dcache.overall_mshr_hits::cpu0.data 25284 # number of overall MSHR hits 732system.cpu0.dcache.overall_mshr_hits::total 25284 # number of overall MSHR hits 733system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370812 # number of ReadReq MSHR misses 734system.cpu0.dcache.ReadReq_mshr_misses::total 370812 # number of ReadReq MSHR misses 735system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325040 # number of WriteReq MSHR misses 736system.cpu0.dcache.WriteReq_mshr_misses::total 325040 # number of WriteReq MSHR misses 737system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100482 # number of SoftPFReq MSHR misses 738system.cpu0.dcache.SoftPFReq_mshr_misses::total 100482 # number of SoftPFReq MSHR misses 739system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6552 # number of LoadLockedReq MSHR misses 740system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6552 # number of LoadLockedReq MSHR misses 741system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19801 # number of StoreCondReq MSHR misses 742system.cpu0.dcache.StoreCondReq_mshr_misses::total 19801 # number of StoreCondReq MSHR misses 743system.cpu0.dcache.demand_mshr_misses::cpu0.data 695852 # number of demand (read+write) MSHR misses 744system.cpu0.dcache.demand_mshr_misses::total 695852 # number of demand (read+write) MSHR misses 745system.cpu0.dcache.overall_mshr_misses::cpu0.data 796334 # number of overall MSHR misses 746system.cpu0.dcache.overall_mshr_misses::total 796334 # number of overall MSHR misses 747system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable 748system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31792 # number of ReadReq MSHR uncacheable 749system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 750system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable 751system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 752system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses 753system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles 754system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles 755system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles 756system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles 757system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles 758system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615427000 # number of SoftPFReq MSHR miss cycles 759system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98795500 # number of LoadLockedReq MSHR miss cycles 760system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98795500 # number of LoadLockedReq MSHR miss cycles 761system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 # number of StoreCondReq MSHR miss cycles 762system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles 763system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles 764system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles 765system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles 766system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles 767system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles 768system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles 769system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles 770system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles 771system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles 772system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628901000 # number of overall MSHR uncacheable cycles 773system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015265 # mshr miss rate for ReadReq accesses 774system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015265 # mshr miss rate for ReadReq accesses 775system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017720 # mshr miss rate for WriteReq accesses 776system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses 777system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224894 # mshr miss rate for SoftPFReq accesses 778system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224894 # mshr miss rate for SoftPFReq accesses 779system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016927 # mshr miss rate for LoadLockedReq accesses 780system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016927 # mshr miss rate for LoadLockedReq accesses 781system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051813 # mshr miss rate for StoreCondReq accesses 782system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051813 # mshr miss rate for StoreCondReq accesses 783system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 # mshr miss rate for demand accesses 784system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses 785system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses 786system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses 787system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency 788system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency 789system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency 790system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency 791system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency 792system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.779921 # average SoftPFReq mshr miss latency 793system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15078.678266 # average LoadLockedReq mshr miss latency 794system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15078.678266 # average LoadLockedReq mshr miss latency 795system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 # average StoreCondReq mshr miss latency 796system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency 797system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 798system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 799system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency 800system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency 801system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency 802system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency 803system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency 804system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency 805system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency 806system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency 807system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 808system.cpu0.icache.tags.replacements 1103881 # number of replacements 809system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use 810system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks. 811system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks. 812system.cpu0.icache.tags.avg_refs 106.766692 # Average number of references to valid blocks. 813system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit. 814system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor 815system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy 816system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy 817system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 818system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 819system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 820system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id 821system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 822system.cpu0.icache.tags.tag_accesses 239137980 # Number of tag accesses 823system.cpu0.icache.tags.data_accesses 239137980 # Number of data accesses 824system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 825system.cpu0.icache.ReadReq_hits::cpu0.inst 117912387 # number of ReadReq hits 826system.cpu0.icache.ReadReq_hits::total 117912387 # number of ReadReq hits 827system.cpu0.icache.demand_hits::cpu0.inst 117912387 # number of demand (read+write) hits 828system.cpu0.icache.demand_hits::total 117912387 # number of demand (read+write) hits 829system.cpu0.icache.overall_hits::cpu0.inst 117912387 # number of overall hits 830system.cpu0.icache.overall_hits::total 117912387 # number of overall hits 831system.cpu0.icache.ReadReq_misses::cpu0.inst 1104402 # number of ReadReq misses 832system.cpu0.icache.ReadReq_misses::total 1104402 # number of ReadReq misses 833system.cpu0.icache.demand_misses::cpu0.inst 1104402 # number of demand (read+write) misses 834system.cpu0.icache.demand_misses::total 1104402 # number of demand (read+write) misses 835system.cpu0.icache.overall_misses::cpu0.inst 1104402 # number of overall misses 836system.cpu0.icache.overall_misses::total 1104402 # number of overall misses 837system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11028665000 # number of ReadReq miss cycles 838system.cpu0.icache.ReadReq_miss_latency::total 11028665000 # number of ReadReq miss cycles 839system.cpu0.icache.demand_miss_latency::cpu0.inst 11028665000 # number of demand (read+write) miss cycles 840system.cpu0.icache.demand_miss_latency::total 11028665000 # number of demand (read+write) miss cycles 841system.cpu0.icache.overall_miss_latency::cpu0.inst 11028665000 # number of overall miss cycles 842system.cpu0.icache.overall_miss_latency::total 11028665000 # number of overall miss cycles 843system.cpu0.icache.ReadReq_accesses::cpu0.inst 119016789 # number of ReadReq accesses(hits+misses) 844system.cpu0.icache.ReadReq_accesses::total 119016789 # number of ReadReq accesses(hits+misses) 845system.cpu0.icache.demand_accesses::cpu0.inst 119016789 # number of demand (read+write) accesses 846system.cpu0.icache.demand_accesses::total 119016789 # number of demand (read+write) accesses 847system.cpu0.icache.overall_accesses::cpu0.inst 119016789 # number of overall (read+write) accesses 848system.cpu0.icache.overall_accesses::total 119016789 # number of overall (read+write) accesses 849system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009279 # miss rate for ReadReq accesses 850system.cpu0.icache.ReadReq_miss_rate::total 0.009279 # miss rate for ReadReq accesses 851system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009279 # miss rate for demand accesses 852system.cpu0.icache.demand_miss_rate::total 0.009279 # miss rate for demand accesses 853system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009279 # miss rate for overall accesses 854system.cpu0.icache.overall_miss_rate::total 0.009279 # miss rate for overall accesses 855system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9986.096548 # average ReadReq miss latency 856system.cpu0.icache.ReadReq_avg_miss_latency::total 9986.096548 # average ReadReq miss latency 857system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency 858system.cpu0.icache.demand_avg_miss_latency::total 9986.096548 # average overall miss latency 859system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency 860system.cpu0.icache.overall_avg_miss_latency::total 9986.096548 # average overall miss latency 861system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 862system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 863system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 864system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 865system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 866system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 867system.cpu0.icache.writebacks::writebacks 1103881 # number of writebacks 868system.cpu0.icache.writebacks::total 1103881 # number of writebacks 869system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104402 # number of ReadReq MSHR misses 870system.cpu0.icache.ReadReq_mshr_misses::total 1104402 # number of ReadReq MSHR misses 871system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104402 # number of demand (read+write) MSHR misses 872system.cpu0.icache.demand_mshr_misses::total 1104402 # number of demand (read+write) MSHR misses 873system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104402 # number of overall MSHR misses 874system.cpu0.icache.overall_mshr_misses::total 1104402 # number of overall MSHR misses 875system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 876system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 877system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 878system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 879system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10476464000 # number of ReadReq MSHR miss cycles 880system.cpu0.icache.ReadReq_mshr_miss_latency::total 10476464000 # number of ReadReq MSHR miss cycles 881system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10476464000 # number of demand (read+write) MSHR miss cycles 882system.cpu0.icache.demand_mshr_miss_latency::total 10476464000 # number of demand (read+write) MSHR miss cycles 883system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10476464000 # number of overall MSHR miss cycles 884system.cpu0.icache.overall_mshr_miss_latency::total 10476464000 # number of overall MSHR miss cycles 885system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles 886system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles 887system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles 888system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles 889system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for ReadReq accesses 890system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009279 # mshr miss rate for ReadReq accesses 891system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for demand accesses 892system.cpu0.icache.demand_mshr_miss_rate::total 0.009279 # mshr miss rate for demand accesses 893system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for overall accesses 894system.cpu0.icache.overall_mshr_miss_rate::total 0.009279 # mshr miss rate for overall accesses 895system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average ReadReq mshr miss latency 896system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9486.096548 # average ReadReq mshr miss latency 897system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency 898system.cpu0.icache.demand_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency 899system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency 900system.cpu0.icache.overall_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency 901system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency 902system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency 903system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency 904system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency 905system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 906system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued 907system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified 908system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue 909system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 910system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 911system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing 912system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 913system.cpu0.l2cache.tags.replacements 266444 # number of replacements 914system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use 915system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks. 916system.cpu0.l2cache.tags.sampled_refs 282538 # Sample count of references to valid blocks. 917system.cpu0.l2cache.tags.avg_refs 10.354310 # Average number of references to valid blocks. 918system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 919system.cpu0.l2cache.tags.occ_blocks::writebacks 14606.769244 # Average occupied blocks per requestor 920system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.268403 # Average occupied blocks per requestor 921system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.133561 # Average occupied blocks per requestor 922system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1470.339456 # Average occupied blocks per requestor 923system.cpu0.l2cache.tags.occ_percent::writebacks 0.891526 # Average percentage of cache occupancy 924system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000138 # Average percentage of cache occupancy 925system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 926system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.089742 # Average percentage of cache occupancy 927system.cpu0.l2cache.tags.occ_percent::total 0.981415 # Average percentage of cache occupancy 928system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id 929system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 930system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 932system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 289 # Occupied blocks per task id 933system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 351 # Occupied blocks per task id 934system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 399 # Occupied blocks per task id 935system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 938system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id 939system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id 940system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7676 # Occupied blocks per task id 941system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3752 # Occupied blocks per task id 942system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id 943system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 944system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id 945system.cpu0.l2cache.tags.tag_accesses 60110945 # Number of tag accesses 946system.cpu0.l2cache.tags.data_accesses 60110945 # Number of data accesses 947system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 948system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10236 # number of ReadReq hits 949system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4573 # number of ReadReq hits 950system.cpu0.l2cache.ReadReq_hits::total 14809 # number of ReadReq hits 951system.cpu0.l2cache.WritebackDirty_hits::writebacks 476837 # number of WritebackDirty hits 952system.cpu0.l2cache.WritebackDirty_hits::total 476837 # number of WritebackDirty hits 953system.cpu0.l2cache.WritebackClean_hits::writebacks 1291246 # number of WritebackClean hits 954system.cpu0.l2cache.WritebackClean_hits::total 1291246 # number of WritebackClean hits 955system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227142 # number of ReadExReq hits 956system.cpu0.l2cache.ReadExReq_hits::total 227142 # number of ReadExReq hits 957system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1059122 # number of ReadCleanReq hits 958system.cpu0.l2cache.ReadCleanReq_hits::total 1059122 # number of ReadCleanReq hits 959system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 383679 # number of ReadSharedReq hits 960system.cpu0.l2cache.ReadSharedReq_hits::total 383679 # number of ReadSharedReq hits 961system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10236 # number of demand (read+write) hits 962system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4573 # number of demand (read+write) hits 963system.cpu0.l2cache.demand_hits::cpu0.inst 1059122 # number of demand (read+write) hits 964system.cpu0.l2cache.demand_hits::cpu0.data 610821 # number of demand (read+write) hits 965system.cpu0.l2cache.demand_hits::total 1684752 # number of demand (read+write) hits 966system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10236 # number of overall hits 967system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4573 # number of overall hits 968system.cpu0.l2cache.overall_hits::cpu0.inst 1059122 # number of overall hits 969system.cpu0.l2cache.overall_hits::cpu0.data 610821 # number of overall hits 970system.cpu0.l2cache.overall_hits::total 1684752 # number of overall hits 971system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 226 # number of ReadReq misses 972system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses 973system.cpu0.l2cache.ReadReq_misses::total 366 # number of ReadReq misses 974system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55088 # number of UpgradeReq misses 975system.cpu0.l2cache.UpgradeReq_misses::total 55088 # number of UpgradeReq misses 976system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses 977system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses 978system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 979system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 980system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42810 # number of ReadExReq misses 981system.cpu0.l2cache.ReadExReq_misses::total 42810 # number of ReadExReq misses 982system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 45280 # number of ReadCleanReq misses 983system.cpu0.l2cache.ReadCleanReq_misses::total 45280 # number of ReadCleanReq misses 984system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94167 # number of ReadSharedReq misses 985system.cpu0.l2cache.ReadSharedReq_misses::total 94167 # number of ReadSharedReq misses 986system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 226 # number of demand (read+write) misses 987system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses 988system.cpu0.l2cache.demand_misses::cpu0.inst 45280 # number of demand (read+write) misses 989system.cpu0.l2cache.demand_misses::cpu0.data 136977 # number of demand (read+write) misses 990system.cpu0.l2cache.demand_misses::total 182623 # number of demand (read+write) misses 991system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 226 # number of overall misses 992system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses 993system.cpu0.l2cache.overall_misses::cpu0.inst 45280 # number of overall misses 994system.cpu0.l2cache.overall_misses::cpu0.data 136977 # number of overall misses 995system.cpu0.l2cache.overall_misses::total 182623 # number of overall misses 996system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5649500 # number of ReadReq miss cycles 997system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3340000 # number of ReadReq miss cycles 998system.cpu0.l2cache.ReadReq_miss_latency::total 8989500 # number of ReadReq miss cycles 999system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 99195500 # number of UpgradeReq miss cycles 1000system.cpu0.l2cache.UpgradeReq_miss_latency::total 99195500 # number of UpgradeReq miss cycles 1001system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22445500 # number of SCUpgradeReq miss cycles 1002system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22445500 # number of SCUpgradeReq miss cycles 1003system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1343499 # number of SCUpgradeFailReq miss cycles 1004system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1343499 # number of SCUpgradeFailReq miss cycles 1005system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 # number of ReadExReq miss cycles 1006system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles 1007system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles 1008system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles 1009system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles 1010system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles 1011system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles 1012system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles 1013system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles 1014system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles 1015system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles 1016system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles 1017system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles 1018system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles 1019system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles 1020system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles 1021system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses) 1022system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses) 1023system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses) 1024system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476837 # number of WritebackDirty accesses(hits+misses) 1025system.cpu0.l2cache.WritebackDirty_accesses::total 476837 # number of WritebackDirty accesses(hits+misses) 1026system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291246 # number of WritebackClean accesses(hits+misses) 1027system.cpu0.l2cache.WritebackClean_accesses::total 1291246 # number of WritebackClean accesses(hits+misses) 1028system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55088 # number of UpgradeReq accesses(hits+misses) 1029system.cpu0.l2cache.UpgradeReq_accesses::total 55088 # number of UpgradeReq accesses(hits+misses) 1030system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19799 # number of SCUpgradeReq accesses(hits+misses) 1031system.cpu0.l2cache.SCUpgradeReq_accesses::total 19799 # number of SCUpgradeReq accesses(hits+misses) 1032system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1033system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1034system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269952 # number of ReadExReq accesses(hits+misses) 1035system.cpu0.l2cache.ReadExReq_accesses::total 269952 # number of ReadExReq accesses(hits+misses) 1036system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104402 # number of ReadCleanReq accesses(hits+misses) 1037system.cpu0.l2cache.ReadCleanReq_accesses::total 1104402 # number of ReadCleanReq accesses(hits+misses) 1038system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477846 # number of ReadSharedReq accesses(hits+misses) 1039system.cpu0.l2cache.ReadSharedReq_accesses::total 477846 # number of ReadSharedReq accesses(hits+misses) 1040system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10462 # number of demand (read+write) accesses 1041system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4713 # number of demand (read+write) accesses 1042system.cpu0.l2cache.demand_accesses::cpu0.inst 1104402 # number of demand (read+write) accesses 1043system.cpu0.l2cache.demand_accesses::cpu0.data 747798 # number of demand (read+write) accesses 1044system.cpu0.l2cache.demand_accesses::total 1867375 # number of demand (read+write) accesses 1045system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10462 # number of overall (read+write) accesses 1046system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4713 # number of overall (read+write) accesses 1047system.cpu0.l2cache.overall_accesses::cpu0.inst 1104402 # number of overall (read+write) accesses 1048system.cpu0.l2cache.overall_accesses::cpu0.data 747798 # number of overall (read+write) accesses 1049system.cpu0.l2cache.overall_accesses::total 1867375 # number of overall (read+write) accesses 1050system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for ReadReq accesses 1051system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029705 # miss rate for ReadReq accesses 1052system.cpu0.l2cache.ReadReq_miss_rate::total 0.024119 # miss rate for ReadReq accesses 1053system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1054system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1055system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1056system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1057system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1058system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1059system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.158584 # miss rate for ReadExReq accesses 1060system.cpu0.l2cache.ReadExReq_miss_rate::total 0.158584 # miss rate for ReadExReq accesses 1061system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041000 # miss rate for ReadCleanReq accesses 1062system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041000 # miss rate for ReadCleanReq accesses 1063system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.197066 # miss rate for ReadSharedReq accesses 1064system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.197066 # miss rate for ReadSharedReq accesses 1065system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for demand accesses 1066system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029705 # miss rate for demand accesses 1067system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041000 # miss rate for demand accesses 1068system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183174 # miss rate for demand accesses 1069system.cpu0.l2cache.demand_miss_rate::total 0.097797 # miss rate for demand accesses 1070system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for overall accesses 1071system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029705 # miss rate for overall accesses 1072system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041000 # miss rate for overall accesses 1073system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183174 # miss rate for overall accesses 1074system.cpu0.l2cache.overall_miss_rate::total 0.097797 # miss rate for overall accesses 1075system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average ReadReq miss latency 1076system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.142857 # average ReadReq miss latency 1077system.cpu0.l2cache.ReadReq_avg_miss_latency::total 24561.475410 # average ReadReq miss latency 1078system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1800.673468 # average UpgradeReq miss latency 1079system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1800.673468 # average UpgradeReq miss latency 1080system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1133.668367 # average SCUpgradeReq miss latency 1081system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1133.668367 # average SCUpgradeReq miss latency 1082system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 671749.500000 # average SCUpgradeFailReq miss latency 1083system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 671749.500000 # average SCUpgradeFailReq miss latency 1084system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 # average ReadExReq miss latency 1085system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency 1086system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency 1087system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency 1088system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency 1089system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency 1090system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency 1091system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency 1092system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency 1093system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency 1094system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency 1095system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency 1096system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency 1097system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency 1098system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency 1099system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency 1100system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1101system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1102system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1103system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1104system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1105system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1106system.cpu0.l2cache.unused_prefetches 10477 # number of HardPF blocks evicted w/o reference 1107system.cpu0.l2cache.writebacks::writebacks 227975 # number of writebacks 1108system.cpu0.l2cache.writebacks::total 227975 # number of writebacks 1109system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1162 # number of ReadExReq MSHR hits 1110system.cpu0.l2cache.ReadExReq_mshr_hits::total 1162 # number of ReadExReq MSHR hits 1111system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits 1112system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits 1113system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1192 # number of demand (read+write) MSHR hits 1114system.cpu0.l2cache.demand_mshr_hits::total 1192 # number of demand (read+write) MSHR hits 1115system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1192 # number of overall MSHR hits 1116system.cpu0.l2cache.overall_mshr_hits::total 1192 # number of overall MSHR hits 1117system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 226 # number of ReadReq MSHR misses 1118system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 140 # number of ReadReq MSHR misses 1119system.cpu0.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 1120system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of HardPFReq MSHR misses 1121system.cpu0.l2cache.HardPFReq_mshr_misses::total 259577 # number of HardPFReq MSHR misses 1122system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55088 # number of UpgradeReq MSHR misses 1123system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55088 # number of UpgradeReq MSHR misses 1124system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19799 # number of SCUpgradeReq MSHR misses 1125system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19799 # number of SCUpgradeReq MSHR misses 1126system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1127system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1128system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41648 # number of ReadExReq MSHR misses 1129system.cpu0.l2cache.ReadExReq_mshr_misses::total 41648 # number of ReadExReq MSHR misses 1130system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 45280 # number of ReadCleanReq MSHR misses 1131system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 45280 # number of ReadCleanReq MSHR misses 1132system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94137 # number of ReadSharedReq MSHR misses 1133system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94137 # number of ReadSharedReq MSHR misses 1134system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 226 # number of demand (read+write) MSHR misses 1135system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 140 # number of demand (read+write) MSHR misses 1136system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 45280 # number of demand (read+write) MSHR misses 1137system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135785 # number of demand (read+write) MSHR misses 1138system.cpu0.l2cache.demand_mshr_misses::total 181431 # number of demand (read+write) MSHR misses 1139system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 226 # number of overall MSHR misses 1140system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 140 # number of overall MSHR misses 1141system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 45280 # number of overall MSHR misses 1142system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135785 # number of overall MSHR misses 1143system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of overall MSHR misses 1144system.cpu0.l2cache.overall_mshr_misses::total 441008 # number of overall MSHR misses 1145system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1146system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable 1147system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40814 # number of ReadReq MSHR uncacheable 1148system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 1149system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable 1150system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1151system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 1152system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 # number of overall MSHR uncacheable misses 1153system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles 1154system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles 1155system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles 1156system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles 1157system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles 1158system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles 1159system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles 1160system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles 1161system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304568000 # number of SCUpgradeReq MSHR miss cycles 1162system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097499 # number of SCUpgradeFailReq MSHR miss cycles 1163system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097499 # number of SCUpgradeFailReq MSHR miss cycles 1164system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500 # number of ReadExReq MSHR miss cycles 1165system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles 1166system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles 1167system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles 1168system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles 1169system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles 1170system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles 1171system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles 1172system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles 1173system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles 1174system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles 1175system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles 1176system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles 1177system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles 1178system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles 1179system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles 1180system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles 1181system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles 1182system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles 1183system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles 1184system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles 1185system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6374150500 # number of overall MSHR uncacheable cycles 1186system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117902000 # number of overall MSHR uncacheable cycles 1187system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for ReadReq accesses 1188system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for ReadReq accesses 1189system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024119 # mshr miss rate for ReadReq accesses 1190system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1191system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1192system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1193system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1194system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1195system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1196system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1197system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1198system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154279 # mshr miss rate for ReadExReq accesses 1199system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154279 # mshr miss rate for ReadExReq accesses 1200system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for ReadCleanReq accesses 1201system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041000 # mshr miss rate for ReadCleanReq accesses 1202system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197003 # mshr miss rate for ReadSharedReq accesses 1203system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197003 # mshr miss rate for ReadSharedReq accesses 1204system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for demand accesses 1205system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for demand accesses 1206system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for demand accesses 1207system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for demand accesses 1208system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097158 # mshr miss rate for demand accesses 1209system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for overall accesses 1210system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for overall accesses 1211system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for overall accesses 1212system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for overall accesses 1213system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1214system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 # mshr miss rate for overall accesses 1215system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency 1216system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency 1217system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency 1218system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency 1219system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency 1220system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency 1221system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency 1222system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency 1223system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15382.999141 # average SCUpgradeReq mshr miss latency 1224system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 548749.500000 # average SCUpgradeFailReq mshr miss latency 1225system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 548749.500000 # average SCUpgradeFailReq mshr miss latency 1226system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 # average ReadExReq mshr miss latency 1227system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency 1228system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency 1229system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency 1230system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency 1231system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency 1232system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency 1233system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency 1234system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency 1235system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency 1236system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency 1237system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency 1238system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency 1239system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency 1240system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency 1241system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency 1242system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency 1243system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency 1244system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency 1245system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency 1246system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency 1247system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency 1248system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency 1249system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter. 1250system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1251system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27957 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1252system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter. 1253system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1254system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1255system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1256system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution 1257system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution 1258system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution 1259system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution 1260system.cpu0.toL2Bus.trans_dist::WritebackDirty 705040 # Transaction distribution 1261system.cpu0.toL2Bus.trans_dist::WritebackClean 1319203 # Transaction distribution 1262system.cpu0.toL2Bus.trans_dist::CleanEvict 185302 # Transaction distribution 1263system.cpu0.toL2Bus.trans_dist::HardPFReq 307927 # Transaction distribution 1264system.cpu0.toL2Bus.trans_dist::UpgradeReq 87515 # Transaction distribution 1265system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42104 # Transaction distribution 1266system.cpu0.toL2Bus.trans_dist::UpgradeResp 112492 # Transaction distribution 1267system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution 1268system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution 1269system.cpu0.toL2Bus.trans_dist::ReadExReq 289204 # Transaction distribution 1270system.cpu0.toL2Bus.trans_dist::ReadExResp 285566 # Transaction distribution 1271system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104402 # Transaction distribution 1272system.cpu0.toL2Bus.trans_dist::ReadSharedReq 556293 # Transaction distribution 1273system.cpu0.toL2Bus.trans_dist::InvalidateReq 3323 # Transaction distribution 1274system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330729 # Packet count per connected master and slave (bytes) 1275system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2559536 # Packet count per connected master and slave (bytes) 1276system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11112 # Packet count per connected master and slave (bytes) 1277system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24847 # Packet count per connected master and slave (bytes) 1278system.cpu0.toL2Bus.pkt_count::total 5926224 # Packet count per connected master and slave (bytes) 1279system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141366200 # Cumulative packet size per connected master and slave (bytes) 1280system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96437860 # Cumulative packet size per connected master and slave (bytes) 1281system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18852 # Cumulative packet size per connected master and slave (bytes) 1282system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41848 # Cumulative packet size per connected master and slave (bytes) 1283system.cpu0.toL2Bus.pkt_size::total 237864760 # Cumulative packet size per connected master and slave (bytes) 1284system.cpu0.toL2Bus.snoops 984362 # Total snoops (count) 1285system.cpu0.toL2Bus.snoop_fanout::samples 2894410 # Request fanout histogram 1286system.cpu0.toL2Bus.snoop_fanout::mean 0.124539 # Request fanout histogram 1287system.cpu0.toL2Bus.snoop_fanout::stdev 0.334666 # Request fanout histogram 1288system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1289system.cpu0.toL2Bus.snoop_fanout::0 2538244 87.69% 87.69% # Request fanout histogram 1290system.cpu0.toL2Bus.snoop_fanout::1 351865 12.16% 99.85% # Request fanout histogram 1291system.cpu0.toL2Bus.snoop_fanout::2 4301 0.15% 100.00% # Request fanout histogram 1292system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1293system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1294system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1295system.cpu0.toL2Bus.snoop_fanout::total 2894410 # Request fanout histogram 1296system.cpu0.toL2Bus.reqLayer0.occupancy 3716866999 # Layer occupancy (ticks) 1297system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1298system.cpu0.toL2Bus.snoopLayer0.occupancy 114649584 # Layer occupancy (ticks) 1299system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1300system.cpu0.toL2Bus.respLayer0.occupancy 1665625000 # Layer occupancy (ticks) 1301system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1302system.cpu0.toL2Bus.respLayer1.occupancy 1205216982 # Layer occupancy (ticks) 1303system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1304system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) 1305system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1306system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks) 1307system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1308system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1309system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1310system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1311system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1312system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1313system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1314system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1315system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1316system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1317system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1318system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1319system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1320system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1321system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1322system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1323system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1324system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1325system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1326system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1327system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1328system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1329system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1330system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1331system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1332system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1333system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1334system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1335system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1336system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1337system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1338system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1339system.cpu1.dtb.walker.walks 3352 # Table walker walks requested 1340system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors 1341system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate 1342system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate 1343system.cpu1.dtb.walker.walkWaitTime::samples 3352 # Table walker wait (enqueue to first request) latency 1344system.cpu1.dtb.walker.walkWaitTime::0 3352 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1345system.cpu1.dtb.walker.walkWaitTime::total 3352 # Table walker wait (enqueue to first request) latency 1346system.cpu1.dtb.walker.walkCompletionTime::samples 2582 # Table walker service (enqueue to completion) latency 1347system.cpu1.dtb.walker.walkCompletionTime::mean 11816.227730 # Table walker service (enqueue to completion) latency 1348system.cpu1.dtb.walker.walkCompletionTime::gmean 11080.373538 # Table walker service (enqueue to completion) latency 1349system.cpu1.dtb.walker.walkCompletionTime::stdev 4768.875507 # Table walker service (enqueue to completion) latency 1350system.cpu1.dtb.walker.walkCompletionTime::0-4095 5 0.19% 0.19% # Table walker service (enqueue to completion) latency 1351system.cpu1.dtb.walker.walkCompletionTime::4096-8191 626 24.24% 24.44% # Table walker service (enqueue to completion) latency 1352system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1198 46.40% 70.84% # Table walker service (enqueue to completion) latency 1353system.cpu1.dtb.walker.walkCompletionTime::12288-16383 544 21.07% 91.91% # Table walker service (enqueue to completion) latency 1354system.cpu1.dtb.walker.walkCompletionTime::16384-20479 85 3.29% 95.20% # Table walker service (enqueue to completion) latency 1355system.cpu1.dtb.walker.walkCompletionTime::20480-24575 56 2.17% 97.37% # Table walker service (enqueue to completion) latency 1356system.cpu1.dtb.walker.walkCompletionTime::24576-28671 31 1.20% 98.57% # Table walker service (enqueue to completion) latency 1357system.cpu1.dtb.walker.walkCompletionTime::28672-32767 20 0.77% 99.34% # Table walker service (enqueue to completion) latency 1358system.cpu1.dtb.walker.walkCompletionTime::32768-36863 3 0.12% 99.46% # Table walker service (enqueue to completion) latency 1359system.cpu1.dtb.walker.walkCompletionTime::36864-40959 8 0.31% 99.77% # Table walker service (enqueue to completion) latency 1360system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency 1361system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.12% 100.00% # Table walker service (enqueue to completion) latency 1362system.cpu1.dtb.walker.walkCompletionTime::total 2582 # Table walker service (enqueue to completion) latency 1363system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution 1364system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution 1365system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution 1366system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.90% 74.90% # Table walker page sizes translated 1367system.cpu1.dtb.walker.walkPageSizes::1M 648 25.10% 100.00% # Table walker page sizes translated 1368system.cpu1.dtb.walker.walkPageSizes::total 2582 # Table walker page sizes translated 1369system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3352 # Table walker requests started/completed, data/inst 1370system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1371system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3352 # Table walker requests started/completed, data/inst 1372system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2582 # Table walker requests started/completed, data/inst 1373system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1374system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst 1375system.cpu1.dtb.walker.walkRequestOrigin::total 5934 # Table walker requests started/completed, data/inst 1376system.cpu1.dtb.inst_hits 0 # ITB inst hits 1377system.cpu1.dtb.inst_misses 0 # ITB inst misses 1378system.cpu1.dtb.read_hits 3941258 # DTB read hits 1379system.cpu1.dtb.read_misses 2845 # DTB read misses 1380system.cpu1.dtb.write_hits 3419362 # DTB write hits 1381system.cpu1.dtb.write_misses 507 # DTB write misses 1382system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1383system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1384system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1385system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	530system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 531system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 532system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 533system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 534system.cpu0.itb.read_accesses 0 # DTB read accesses 535system.cpu0.itb.write_accesses 0 # DTB write accesses 536system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses 537system.cpu0.itb.hits 119016789 # DTB hits 538system.cpu0.itb.misses 3349 # DTB misses 539system.cpu0.itb.accesses 119020138 # DTB accesses 540system.cpu0.numPwrStateTransitions 3732 # Number of power state transitions 541system.cpu0.pwrStateClkGateDist::samples 1866 # Distribution of time spent in the clock gated state 542system.cpu0.pwrStateClkGateDist::mean 1464105256.698285 # Distribution of time spent in the clock gated state 543system.cpu0.pwrStateClkGateDist::stdev 23703834177.511120 # Distribution of time spent in the clock gated state 544system.cpu0.pwrStateClkGateDist::underflows 1075 57.61% 57.61% # Distribution of time spent in the clock gated state 545system.cpu0.pwrStateClkGateDist::1000-5e+10 786 42.12% 99.73% # Distribution of time spent in the clock gated state 546system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state 547system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state 548system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 549system.cpu0.pwrStateClkGateDist::max_value 499964077872 # Distribution of time spent in the clock gated state 550system.cpu0.pwrStateClkGateDist::total 1866 # Distribution of time spent in the clock gated state 551system.cpu0.pwrStateResidencyTicks::ON 137768561001 # Cumulative time (in ticks) in various power states 552system.cpu0.pwrStateResidencyTicks::CLK_GATED 2732020408999 # Cumulative time (in ticks) in various power states 553system.cpu0.numCycles 5739577940 # number of cpu cycles simulated 554system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 555system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 556system.cpu0.kern.inst.arm 0 # number of arm instructions executed 557system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed 558system.cpu0.committedInsts 115352405 # Number of instructions committed 559system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed 560system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses 561system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses 562system.cpu0.num_func_calls 12675179 # number of times a function call or return occured 563system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls 564system.cpu0.num_int_insts 123360698 # number of integer instructions 565system.cpu0.num_fp_insts 9756 # number of float instructions 566system.cpu0.num_int_register_reads 227063318 # number of times the integer registers were read 567system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written 568system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read 569system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 570system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read 571system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written 572system.cpu0.num_mem_refs 45042977 # number of memory refs 573system.cpu0.num_load_insts 25408336 # Number of load instructions 574system.cpu0.num_store_insts 19634641 # Number of store instructions 575system.cpu0.num_idle_cycles 5464040817.996096 # Number of idle cycles 576system.cpu0.num_busy_cycles 275537122.003904 # Number of busy cycles 577system.cpu0.not_idle_fraction 0.048007 # Percentage of non-idle cycles 578system.cpu0.idle_fraction 0.951993 # Percentage of idle cycles 579system.cpu0.Branches 29113703 # Number of branches fetched 580system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 581system.cpu0.op_class::IntAlu 97981864 68.45% 68.45% # Class of executed instruction 582system.cpu0.op_class::IntMult 109763 0.08% 68.53% # Class of executed instruction 583system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction 584system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction 585system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction 586system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction 587system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction 588system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction 589system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction 590system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction 591system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction 592system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction 593system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction 594system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction 595system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction 596system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction 597system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction 598system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction 599system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction 600system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction 601system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction 602system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction 603system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction 604system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction 605system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction 606system.cpu0.op_class::SimdFloatMisc 8197 0.01% 68.53% # Class of executed instruction 607system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction 608system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction 609system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction 610system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction 611system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction 612system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 613system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 614system.cpu0.op_class::total 143145074 # Class of executed instruction 615system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 616system.cpu0.dcache.tags.replacements 692159 # number of replacements 617system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use 618system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks. 619system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. 620system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks. 621system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. 622system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor 623system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy 624system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy 625system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 626system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 627system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 628system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id 629system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 630system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses 631system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses 632system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 633system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits 634system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits 635system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits 636system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits 637system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits 638system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits 639system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits 640system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits 641system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits 642system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits 643system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits 644system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits 645system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits 646system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits 647system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses 648system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses 649system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses 650system.cpu0.dcache.WriteReq_misses::total 325040 # number of WriteReq misses 651system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127692 # number of SoftPFReq misses 652system.cpu0.dcache.SoftPFReq_misses::total 127692 # number of SoftPFReq misses 653system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21584 # number of LoadLockedReq misses 654system.cpu0.dcache.LoadLockedReq_misses::total 21584 # number of LoadLockedReq misses 655system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19801 # number of StoreCondReq misses 656system.cpu0.dcache.StoreCondReq_misses::total 19801 # number of StoreCondReq misses 657system.cpu0.dcache.demand_misses::cpu0.data 721136 # number of demand (read+write) misses 658system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses 659system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses 660system.cpu0.dcache.overall_misses::total 848828 # number of overall misses 661system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles 662system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles 663system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles 664system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles 665system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles 666system.cpu0.dcache.LoadLockedReq_miss_latency::total 329182500 # number of LoadLockedReq miss cycles 667system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 # number of StoreCondReq miss cycles 668system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles 669system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles 670system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles 671system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles 672system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles 673system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles 674system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles 675system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses) 676system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses) 677system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses) 678system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses) 679system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses) 680system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses) 681system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses) 682system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses) 683system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses) 684system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses) 685system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses 686system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses 687system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses 688system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses 689system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses 690system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses 691system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses 692system.cpu0.dcache.WriteReq_miss_rate::total 0.017720 # miss rate for WriteReq accesses 693system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285794 # miss rate for SoftPFReq accesses 694system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285794 # miss rate for SoftPFReq accesses 695system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055760 # miss rate for LoadLockedReq accesses 696system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055760 # miss rate for LoadLockedReq accesses 697system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051813 # miss rate for StoreCondReq accesses 698system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051813 # miss rate for StoreCondReq accesses 699system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 # miss rate for demand accesses 700system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses 701system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses 702system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses 703system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency 704system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency 705system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency 706system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency 707system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency 708system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15251.227761 # average LoadLockedReq miss latency 709system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 # average StoreCondReq miss latency 710system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency 711system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 712system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 713system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency 714system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency 715system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency 716system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency 717system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 718system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 719system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 720system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 721system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 722system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 723system.cpu0.dcache.writebacks::writebacks 692159 # number of writebacks 724system.cpu0.dcache.writebacks::total 692159 # number of writebacks 725system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25284 # number of ReadReq MSHR hits 726system.cpu0.dcache.ReadReq_mshr_hits::total 25284 # number of ReadReq MSHR hits 727system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15032 # number of LoadLockedReq MSHR hits 728system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15032 # number of LoadLockedReq MSHR hits 729system.cpu0.dcache.demand_mshr_hits::cpu0.data 25284 # number of demand (read+write) MSHR hits 730system.cpu0.dcache.demand_mshr_hits::total 25284 # number of demand (read+write) MSHR hits 731system.cpu0.dcache.overall_mshr_hits::cpu0.data 25284 # number of overall MSHR hits 732system.cpu0.dcache.overall_mshr_hits::total 25284 # number of overall MSHR hits 733system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370812 # number of ReadReq MSHR misses 734system.cpu0.dcache.ReadReq_mshr_misses::total 370812 # number of ReadReq MSHR misses 735system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325040 # number of WriteReq MSHR misses 736system.cpu0.dcache.WriteReq_mshr_misses::total 325040 # number of WriteReq MSHR misses 737system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100482 # number of SoftPFReq MSHR misses 738system.cpu0.dcache.SoftPFReq_mshr_misses::total 100482 # number of SoftPFReq MSHR misses 739system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6552 # number of LoadLockedReq MSHR misses 740system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6552 # number of LoadLockedReq MSHR misses 741system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19801 # number of StoreCondReq MSHR misses 742system.cpu0.dcache.StoreCondReq_mshr_misses::total 19801 # number of StoreCondReq MSHR misses 743system.cpu0.dcache.demand_mshr_misses::cpu0.data 695852 # number of demand (read+write) MSHR misses 744system.cpu0.dcache.demand_mshr_misses::total 695852 # number of demand (read+write) MSHR misses 745system.cpu0.dcache.overall_mshr_misses::cpu0.data 796334 # number of overall MSHR misses 746system.cpu0.dcache.overall_mshr_misses::total 796334 # number of overall MSHR misses 747system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable 748system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31792 # number of ReadReq MSHR uncacheable 749system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 750system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable 751system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 752system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses 753system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles 754system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles 755system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles 756system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles 757system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles 758system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615427000 # number of SoftPFReq MSHR miss cycles 759system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98795500 # number of LoadLockedReq MSHR miss cycles 760system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98795500 # number of LoadLockedReq MSHR miss cycles 761system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 # number of StoreCondReq MSHR miss cycles 762system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles 763system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles 764system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles 765system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles 766system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles 767system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles 768system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles 769system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles 770system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles 771system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles 772system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628901000 # number of overall MSHR uncacheable cycles 773system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015265 # mshr miss rate for ReadReq accesses 774system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015265 # mshr miss rate for ReadReq accesses 775system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017720 # mshr miss rate for WriteReq accesses 776system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses 777system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224894 # mshr miss rate for SoftPFReq accesses 778system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224894 # mshr miss rate for SoftPFReq accesses 779system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016927 # mshr miss rate for LoadLockedReq accesses 780system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016927 # mshr miss rate for LoadLockedReq accesses 781system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051813 # mshr miss rate for StoreCondReq accesses 782system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051813 # mshr miss rate for StoreCondReq accesses 783system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 # mshr miss rate for demand accesses 784system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses 785system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses 786system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses 787system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency 788system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency 789system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency 790system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency 791system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency 792system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.779921 # average SoftPFReq mshr miss latency 793system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15078.678266 # average LoadLockedReq mshr miss latency 794system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15078.678266 # average LoadLockedReq mshr miss latency 795system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 # average StoreCondReq mshr miss latency 796system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency 797system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 798system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 799system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency 800system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency 801system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency 802system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency 803system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency 804system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency 805system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency 806system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency 807system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 808system.cpu0.icache.tags.replacements 1103881 # number of replacements 809system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use 810system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks. 811system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks. 812system.cpu0.icache.tags.avg_refs 106.766692 # Average number of references to valid blocks. 813system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit. 814system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor 815system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy 816system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy 817system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 818system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 819system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 820system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id 821system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 822system.cpu0.icache.tags.tag_accesses 239137980 # Number of tag accesses 823system.cpu0.icache.tags.data_accesses 239137980 # Number of data accesses 824system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 825system.cpu0.icache.ReadReq_hits::cpu0.inst 117912387 # number of ReadReq hits 826system.cpu0.icache.ReadReq_hits::total 117912387 # number of ReadReq hits 827system.cpu0.icache.demand_hits::cpu0.inst 117912387 # number of demand (read+write) hits 828system.cpu0.icache.demand_hits::total 117912387 # number of demand (read+write) hits 829system.cpu0.icache.overall_hits::cpu0.inst 117912387 # number of overall hits 830system.cpu0.icache.overall_hits::total 117912387 # number of overall hits 831system.cpu0.icache.ReadReq_misses::cpu0.inst 1104402 # number of ReadReq misses 832system.cpu0.icache.ReadReq_misses::total 1104402 # number of ReadReq misses 833system.cpu0.icache.demand_misses::cpu0.inst 1104402 # number of demand (read+write) misses 834system.cpu0.icache.demand_misses::total 1104402 # number of demand (read+write) misses 835system.cpu0.icache.overall_misses::cpu0.inst 1104402 # number of overall misses 836system.cpu0.icache.overall_misses::total 1104402 # number of overall misses 837system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11028665000 # number of ReadReq miss cycles 838system.cpu0.icache.ReadReq_miss_latency::total 11028665000 # number of ReadReq miss cycles 839system.cpu0.icache.demand_miss_latency::cpu0.inst 11028665000 # number of demand (read+write) miss cycles 840system.cpu0.icache.demand_miss_latency::total 11028665000 # number of demand (read+write) miss cycles 841system.cpu0.icache.overall_miss_latency::cpu0.inst 11028665000 # number of overall miss cycles 842system.cpu0.icache.overall_miss_latency::total 11028665000 # number of overall miss cycles 843system.cpu0.icache.ReadReq_accesses::cpu0.inst 119016789 # number of ReadReq accesses(hits+misses) 844system.cpu0.icache.ReadReq_accesses::total 119016789 # number of ReadReq accesses(hits+misses) 845system.cpu0.icache.demand_accesses::cpu0.inst 119016789 # number of demand (read+write) accesses 846system.cpu0.icache.demand_accesses::total 119016789 # number of demand (read+write) accesses 847system.cpu0.icache.overall_accesses::cpu0.inst 119016789 # number of overall (read+write) accesses 848system.cpu0.icache.overall_accesses::total 119016789 # number of overall (read+write) accesses 849system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009279 # miss rate for ReadReq accesses 850system.cpu0.icache.ReadReq_miss_rate::total 0.009279 # miss rate for ReadReq accesses 851system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009279 # miss rate for demand accesses 852system.cpu0.icache.demand_miss_rate::total 0.009279 # miss rate for demand accesses 853system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009279 # miss rate for overall accesses 854system.cpu0.icache.overall_miss_rate::total 0.009279 # miss rate for overall accesses 855system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9986.096548 # average ReadReq miss latency 856system.cpu0.icache.ReadReq_avg_miss_latency::total 9986.096548 # average ReadReq miss latency 857system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency 858system.cpu0.icache.demand_avg_miss_latency::total 9986.096548 # average overall miss latency 859system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency 860system.cpu0.icache.overall_avg_miss_latency::total 9986.096548 # average overall miss latency 861system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 862system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 863system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 864system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 865system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 866system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 867system.cpu0.icache.writebacks::writebacks 1103881 # number of writebacks 868system.cpu0.icache.writebacks::total 1103881 # number of writebacks 869system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104402 # number of ReadReq MSHR misses 870system.cpu0.icache.ReadReq_mshr_misses::total 1104402 # number of ReadReq MSHR misses 871system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104402 # number of demand (read+write) MSHR misses 872system.cpu0.icache.demand_mshr_misses::total 1104402 # number of demand (read+write) MSHR misses 873system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104402 # number of overall MSHR misses 874system.cpu0.icache.overall_mshr_misses::total 1104402 # number of overall MSHR misses 875system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 876system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 877system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 878system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 879system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10476464000 # number of ReadReq MSHR miss cycles 880system.cpu0.icache.ReadReq_mshr_miss_latency::total 10476464000 # number of ReadReq MSHR miss cycles 881system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10476464000 # number of demand (read+write) MSHR miss cycles 882system.cpu0.icache.demand_mshr_miss_latency::total 10476464000 # number of demand (read+write) MSHR miss cycles 883system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10476464000 # number of overall MSHR miss cycles 884system.cpu0.icache.overall_mshr_miss_latency::total 10476464000 # number of overall MSHR miss cycles 885system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles 886system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles 887system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles 888system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles 889system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for ReadReq accesses 890system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009279 # mshr miss rate for ReadReq accesses 891system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for demand accesses 892system.cpu0.icache.demand_mshr_miss_rate::total 0.009279 # mshr miss rate for demand accesses 893system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for overall accesses 894system.cpu0.icache.overall_mshr_miss_rate::total 0.009279 # mshr miss rate for overall accesses 895system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average ReadReq mshr miss latency 896system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9486.096548 # average ReadReq mshr miss latency 897system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency 898system.cpu0.icache.demand_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency 899system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency 900system.cpu0.icache.overall_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency 901system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency 902system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency 903system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency 904system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency 905system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 906system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued 907system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified 908system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue 909system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 910system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 911system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing 912system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 913system.cpu0.l2cache.tags.replacements 266444 # number of replacements 914system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use 915system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks. 916system.cpu0.l2cache.tags.sampled_refs 282538 # Sample count of references to valid blocks. 917system.cpu0.l2cache.tags.avg_refs 10.354310 # Average number of references to valid blocks. 918system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 919system.cpu0.l2cache.tags.occ_blocks::writebacks 14606.769244 # Average occupied blocks per requestor 920system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.268403 # Average occupied blocks per requestor 921system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.133561 # Average occupied blocks per requestor 922system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1470.339456 # Average occupied blocks per requestor 923system.cpu0.l2cache.tags.occ_percent::writebacks 0.891526 # Average percentage of cache occupancy 924system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000138 # Average percentage of cache occupancy 925system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 926system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.089742 # Average percentage of cache occupancy 927system.cpu0.l2cache.tags.occ_percent::total 0.981415 # Average percentage of cache occupancy 928system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id 929system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 930system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 932system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 289 # Occupied blocks per task id 933system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 351 # Occupied blocks per task id 934system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 399 # Occupied blocks per task id 935system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 938system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id 939system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id 940system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7676 # Occupied blocks per task id 941system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3752 # Occupied blocks per task id 942system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id 943system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 944system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id 945system.cpu0.l2cache.tags.tag_accesses 60110945 # Number of tag accesses 946system.cpu0.l2cache.tags.data_accesses 60110945 # Number of data accesses 947system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 948system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10236 # number of ReadReq hits 949system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4573 # number of ReadReq hits 950system.cpu0.l2cache.ReadReq_hits::total 14809 # number of ReadReq hits 951system.cpu0.l2cache.WritebackDirty_hits::writebacks 476837 # number of WritebackDirty hits 952system.cpu0.l2cache.WritebackDirty_hits::total 476837 # number of WritebackDirty hits 953system.cpu0.l2cache.WritebackClean_hits::writebacks 1291246 # number of WritebackClean hits 954system.cpu0.l2cache.WritebackClean_hits::total 1291246 # number of WritebackClean hits 955system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227142 # number of ReadExReq hits 956system.cpu0.l2cache.ReadExReq_hits::total 227142 # number of ReadExReq hits 957system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1059122 # number of ReadCleanReq hits 958system.cpu0.l2cache.ReadCleanReq_hits::total 1059122 # number of ReadCleanReq hits 959system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 383679 # number of ReadSharedReq hits 960system.cpu0.l2cache.ReadSharedReq_hits::total 383679 # number of ReadSharedReq hits 961system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10236 # number of demand (read+write) hits 962system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4573 # number of demand (read+write) hits 963system.cpu0.l2cache.demand_hits::cpu0.inst 1059122 # number of demand (read+write) hits 964system.cpu0.l2cache.demand_hits::cpu0.data 610821 # number of demand (read+write) hits 965system.cpu0.l2cache.demand_hits::total 1684752 # number of demand (read+write) hits 966system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10236 # number of overall hits 967system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4573 # number of overall hits 968system.cpu0.l2cache.overall_hits::cpu0.inst 1059122 # number of overall hits 969system.cpu0.l2cache.overall_hits::cpu0.data 610821 # number of overall hits 970system.cpu0.l2cache.overall_hits::total 1684752 # number of overall hits 971system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 226 # number of ReadReq misses 972system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses 973system.cpu0.l2cache.ReadReq_misses::total 366 # number of ReadReq misses 974system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55088 # number of UpgradeReq misses 975system.cpu0.l2cache.UpgradeReq_misses::total 55088 # number of UpgradeReq misses 976system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses 977system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses 978system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses 979system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses 980system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42810 # number of ReadExReq misses 981system.cpu0.l2cache.ReadExReq_misses::total 42810 # number of ReadExReq misses 982system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 45280 # number of ReadCleanReq misses 983system.cpu0.l2cache.ReadCleanReq_misses::total 45280 # number of ReadCleanReq misses 984system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94167 # number of ReadSharedReq misses 985system.cpu0.l2cache.ReadSharedReq_misses::total 94167 # number of ReadSharedReq misses 986system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 226 # number of demand (read+write) misses 987system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses 988system.cpu0.l2cache.demand_misses::cpu0.inst 45280 # number of demand (read+write) misses 989system.cpu0.l2cache.demand_misses::cpu0.data 136977 # number of demand (read+write) misses 990system.cpu0.l2cache.demand_misses::total 182623 # number of demand (read+write) misses 991system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 226 # number of overall misses 992system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses 993system.cpu0.l2cache.overall_misses::cpu0.inst 45280 # number of overall misses 994system.cpu0.l2cache.overall_misses::cpu0.data 136977 # number of overall misses 995system.cpu0.l2cache.overall_misses::total 182623 # number of overall misses 996system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5649500 # number of ReadReq miss cycles 997system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3340000 # number of ReadReq miss cycles 998system.cpu0.l2cache.ReadReq_miss_latency::total 8989500 # number of ReadReq miss cycles 999system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 99195500 # number of UpgradeReq miss cycles 1000system.cpu0.l2cache.UpgradeReq_miss_latency::total 99195500 # number of UpgradeReq miss cycles 1001system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22445500 # number of SCUpgradeReq miss cycles 1002system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22445500 # number of SCUpgradeReq miss cycles 1003system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1343499 # number of SCUpgradeFailReq miss cycles 1004system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1343499 # number of SCUpgradeFailReq miss cycles 1005system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 # number of ReadExReq miss cycles 1006system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles 1007system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles 1008system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles 1009system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles 1010system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles 1011system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles 1012system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles 1013system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles 1014system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles 1015system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles 1016system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles 1017system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles 1018system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles 1019system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles 1020system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles 1021system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses) 1022system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses) 1023system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses) 1024system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476837 # number of WritebackDirty accesses(hits+misses) 1025system.cpu0.l2cache.WritebackDirty_accesses::total 476837 # number of WritebackDirty accesses(hits+misses) 1026system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291246 # number of WritebackClean accesses(hits+misses) 1027system.cpu0.l2cache.WritebackClean_accesses::total 1291246 # number of WritebackClean accesses(hits+misses) 1028system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55088 # number of UpgradeReq accesses(hits+misses) 1029system.cpu0.l2cache.UpgradeReq_accesses::total 55088 # number of UpgradeReq accesses(hits+misses) 1030system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19799 # number of SCUpgradeReq accesses(hits+misses) 1031system.cpu0.l2cache.SCUpgradeReq_accesses::total 19799 # number of SCUpgradeReq accesses(hits+misses) 1032system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) 1033system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) 1034system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269952 # number of ReadExReq accesses(hits+misses) 1035system.cpu0.l2cache.ReadExReq_accesses::total 269952 # number of ReadExReq accesses(hits+misses) 1036system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104402 # number of ReadCleanReq accesses(hits+misses) 1037system.cpu0.l2cache.ReadCleanReq_accesses::total 1104402 # number of ReadCleanReq accesses(hits+misses) 1038system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477846 # number of ReadSharedReq accesses(hits+misses) 1039system.cpu0.l2cache.ReadSharedReq_accesses::total 477846 # number of ReadSharedReq accesses(hits+misses) 1040system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10462 # number of demand (read+write) accesses 1041system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4713 # number of demand (read+write) accesses 1042system.cpu0.l2cache.demand_accesses::cpu0.inst 1104402 # number of demand (read+write) accesses 1043system.cpu0.l2cache.demand_accesses::cpu0.data 747798 # number of demand (read+write) accesses 1044system.cpu0.l2cache.demand_accesses::total 1867375 # number of demand (read+write) accesses 1045system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10462 # number of overall (read+write) accesses 1046system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4713 # number of overall (read+write) accesses 1047system.cpu0.l2cache.overall_accesses::cpu0.inst 1104402 # number of overall (read+write) accesses 1048system.cpu0.l2cache.overall_accesses::cpu0.data 747798 # number of overall (read+write) accesses 1049system.cpu0.l2cache.overall_accesses::total 1867375 # number of overall (read+write) accesses 1050system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for ReadReq accesses 1051system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029705 # miss rate for ReadReq accesses 1052system.cpu0.l2cache.ReadReq_miss_rate::total 0.024119 # miss rate for ReadReq accesses 1053system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1054system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1055system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1056system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1057system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1058system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1059system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.158584 # miss rate for ReadExReq accesses 1060system.cpu0.l2cache.ReadExReq_miss_rate::total 0.158584 # miss rate for ReadExReq accesses 1061system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041000 # miss rate for ReadCleanReq accesses 1062system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041000 # miss rate for ReadCleanReq accesses 1063system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.197066 # miss rate for ReadSharedReq accesses 1064system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.197066 # miss rate for ReadSharedReq accesses 1065system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for demand accesses 1066system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029705 # miss rate for demand accesses 1067system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041000 # miss rate for demand accesses 1068system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183174 # miss rate for demand accesses 1069system.cpu0.l2cache.demand_miss_rate::total 0.097797 # miss rate for demand accesses 1070system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for overall accesses 1071system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029705 # miss rate for overall accesses 1072system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041000 # miss rate for overall accesses 1073system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183174 # miss rate for overall accesses 1074system.cpu0.l2cache.overall_miss_rate::total 0.097797 # miss rate for overall accesses 1075system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average ReadReq miss latency 1076system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.142857 # average ReadReq miss latency 1077system.cpu0.l2cache.ReadReq_avg_miss_latency::total 24561.475410 # average ReadReq miss latency 1078system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1800.673468 # average UpgradeReq miss latency 1079system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1800.673468 # average UpgradeReq miss latency 1080system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1133.668367 # average SCUpgradeReq miss latency 1081system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1133.668367 # average SCUpgradeReq miss latency 1082system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 671749.500000 # average SCUpgradeFailReq miss latency 1083system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 671749.500000 # average SCUpgradeFailReq miss latency 1084system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 # average ReadExReq miss latency 1085system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency 1086system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency 1087system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency 1088system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency 1089system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency 1090system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency 1091system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency 1092system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency 1093system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency 1094system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency 1095system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency 1096system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency 1097system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency 1098system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency 1099system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency 1100system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1101system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1102system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1103system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1104system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1105system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1106system.cpu0.l2cache.unused_prefetches 10477 # number of HardPF blocks evicted w/o reference 1107system.cpu0.l2cache.writebacks::writebacks 227975 # number of writebacks 1108system.cpu0.l2cache.writebacks::total 227975 # number of writebacks 1109system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1162 # number of ReadExReq MSHR hits 1110system.cpu0.l2cache.ReadExReq_mshr_hits::total 1162 # number of ReadExReq MSHR hits 1111system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits 1112system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits 1113system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1192 # number of demand (read+write) MSHR hits 1114system.cpu0.l2cache.demand_mshr_hits::total 1192 # number of demand (read+write) MSHR hits 1115system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1192 # number of overall MSHR hits 1116system.cpu0.l2cache.overall_mshr_hits::total 1192 # number of overall MSHR hits 1117system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 226 # number of ReadReq MSHR misses 1118system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 140 # number of ReadReq MSHR misses 1119system.cpu0.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses 1120system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of HardPFReq MSHR misses 1121system.cpu0.l2cache.HardPFReq_mshr_misses::total 259577 # number of HardPFReq MSHR misses 1122system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55088 # number of UpgradeReq MSHR misses 1123system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55088 # number of UpgradeReq MSHR misses 1124system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19799 # number of SCUpgradeReq MSHR misses 1125system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19799 # number of SCUpgradeReq MSHR misses 1126system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses 1127system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses 1128system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41648 # number of ReadExReq MSHR misses 1129system.cpu0.l2cache.ReadExReq_mshr_misses::total 41648 # number of ReadExReq MSHR misses 1130system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 45280 # number of ReadCleanReq MSHR misses 1131system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 45280 # number of ReadCleanReq MSHR misses 1132system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94137 # number of ReadSharedReq MSHR misses 1133system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94137 # number of ReadSharedReq MSHR misses 1134system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 226 # number of demand (read+write) MSHR misses 1135system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 140 # number of demand (read+write) MSHR misses 1136system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 45280 # number of demand (read+write) MSHR misses 1137system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135785 # number of demand (read+write) MSHR misses 1138system.cpu0.l2cache.demand_mshr_misses::total 181431 # number of demand (read+write) MSHR misses 1139system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 226 # number of overall MSHR misses 1140system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 140 # number of overall MSHR misses 1141system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 45280 # number of overall MSHR misses 1142system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135785 # number of overall MSHR misses 1143system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of overall MSHR misses 1144system.cpu0.l2cache.overall_mshr_misses::total 441008 # number of overall MSHR misses 1145system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1146system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable 1147system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40814 # number of ReadReq MSHR uncacheable 1148system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 1149system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable 1150system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1151system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 1152system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 # number of overall MSHR uncacheable misses 1153system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles 1154system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles 1155system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles 1156system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles 1157system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles 1158system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles 1159system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles 1160system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles 1161system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304568000 # number of SCUpgradeReq MSHR miss cycles 1162system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097499 # number of SCUpgradeFailReq MSHR miss cycles 1163system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097499 # number of SCUpgradeFailReq MSHR miss cycles 1164system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500 # number of ReadExReq MSHR miss cycles 1165system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles 1166system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles 1167system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles 1168system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles 1169system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles 1170system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles 1171system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles 1172system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles 1173system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles 1174system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles 1175system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles 1176system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles 1177system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles 1178system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles 1179system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles 1180system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles 1181system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles 1182system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles 1183system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles 1184system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles 1185system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6374150500 # number of overall MSHR uncacheable cycles 1186system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117902000 # number of overall MSHR uncacheable cycles 1187system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for ReadReq accesses 1188system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for ReadReq accesses 1189system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024119 # mshr miss rate for ReadReq accesses 1190system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1191system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1192system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1193system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1194system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1195system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1196system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1197system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1198system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154279 # mshr miss rate for ReadExReq accesses 1199system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154279 # mshr miss rate for ReadExReq accesses 1200system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for ReadCleanReq accesses 1201system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041000 # mshr miss rate for ReadCleanReq accesses 1202system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197003 # mshr miss rate for ReadSharedReq accesses 1203system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197003 # mshr miss rate for ReadSharedReq accesses 1204system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for demand accesses 1205system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for demand accesses 1206system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for demand accesses 1207system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for demand accesses 1208system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097158 # mshr miss rate for demand accesses 1209system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for overall accesses 1210system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for overall accesses 1211system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for overall accesses 1212system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for overall accesses 1213system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1214system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 # mshr miss rate for overall accesses 1215system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency 1216system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency 1217system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency 1218system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency 1219system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency 1220system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency 1221system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency 1222system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency 1223system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15382.999141 # average SCUpgradeReq mshr miss latency 1224system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 548749.500000 # average SCUpgradeFailReq mshr miss latency 1225system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 548749.500000 # average SCUpgradeFailReq mshr miss latency 1226system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 # average ReadExReq mshr miss latency 1227system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency 1228system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency 1229system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency 1230system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency 1231system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency 1232system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency 1233system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency 1234system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency 1235system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency 1236system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency 1237system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency 1238system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency 1239system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency 1240system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency 1241system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency 1242system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency 1243system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency 1244system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency 1245system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency 1246system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency 1247system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency 1248system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency 1249system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter. 1250system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1251system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27957 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1252system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter. 1253system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1254system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1255system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1256system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution 1257system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution 1258system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution 1259system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution 1260system.cpu0.toL2Bus.trans_dist::WritebackDirty 705040 # Transaction distribution 1261system.cpu0.toL2Bus.trans_dist::WritebackClean 1319203 # Transaction distribution 1262system.cpu0.toL2Bus.trans_dist::CleanEvict 185302 # Transaction distribution 1263system.cpu0.toL2Bus.trans_dist::HardPFReq 307927 # Transaction distribution 1264system.cpu0.toL2Bus.trans_dist::UpgradeReq 87515 # Transaction distribution 1265system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42104 # Transaction distribution 1266system.cpu0.toL2Bus.trans_dist::UpgradeResp 112492 # Transaction distribution 1267system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution 1268system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution 1269system.cpu0.toL2Bus.trans_dist::ReadExReq 289204 # Transaction distribution 1270system.cpu0.toL2Bus.trans_dist::ReadExResp 285566 # Transaction distribution 1271system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104402 # Transaction distribution 1272system.cpu0.toL2Bus.trans_dist::ReadSharedReq 556293 # Transaction distribution 1273system.cpu0.toL2Bus.trans_dist::InvalidateReq 3323 # Transaction distribution 1274system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330729 # Packet count per connected master and slave (bytes) 1275system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2559536 # Packet count per connected master and slave (bytes) 1276system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11112 # Packet count per connected master and slave (bytes) 1277system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24847 # Packet count per connected master and slave (bytes) 1278system.cpu0.toL2Bus.pkt_count::total 5926224 # Packet count per connected master and slave (bytes) 1279system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141366200 # Cumulative packet size per connected master and slave (bytes) 1280system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96437860 # Cumulative packet size per connected master and slave (bytes) 1281system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18852 # Cumulative packet size per connected master and slave (bytes) 1282system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41848 # Cumulative packet size per connected master and slave (bytes) 1283system.cpu0.toL2Bus.pkt_size::total 237864760 # Cumulative packet size per connected master and slave (bytes) 1284system.cpu0.toL2Bus.snoops 984362 # Total snoops (count) 1285system.cpu0.toL2Bus.snoop_fanout::samples 2894410 # Request fanout histogram 1286system.cpu0.toL2Bus.snoop_fanout::mean 0.124539 # Request fanout histogram 1287system.cpu0.toL2Bus.snoop_fanout::stdev 0.334666 # Request fanout histogram 1288system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1289system.cpu0.toL2Bus.snoop_fanout::0 2538244 87.69% 87.69% # Request fanout histogram 1290system.cpu0.toL2Bus.snoop_fanout::1 351865 12.16% 99.85% # Request fanout histogram 1291system.cpu0.toL2Bus.snoop_fanout::2 4301 0.15% 100.00% # Request fanout histogram 1292system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1293system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1294system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1295system.cpu0.toL2Bus.snoop_fanout::total 2894410 # Request fanout histogram 1296system.cpu0.toL2Bus.reqLayer0.occupancy 3716866999 # Layer occupancy (ticks) 1297system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1298system.cpu0.toL2Bus.snoopLayer0.occupancy 114649584 # Layer occupancy (ticks) 1299system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1300system.cpu0.toL2Bus.respLayer0.occupancy 1665625000 # Layer occupancy (ticks) 1301system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1302system.cpu0.toL2Bus.respLayer1.occupancy 1205216982 # Layer occupancy (ticks) 1303system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1304system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) 1305system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1306system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks) 1307system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1308system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1309system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1310system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1311system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1312system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1313system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1314system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1315system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1316system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1317system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1318system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1319system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1320system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1321system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1322system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1323system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1324system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1325system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1326system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1327system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1328system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1329system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1330system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1331system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1332system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1333system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1334system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1335system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1336system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1337system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1338system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1339system.cpu1.dtb.walker.walks 3352 # Table walker walks requested 1340system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors 1341system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate 1342system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate 1343system.cpu1.dtb.walker.walkWaitTime::samples 3352 # Table walker wait (enqueue to first request) latency 1344system.cpu1.dtb.walker.walkWaitTime::0 3352 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1345system.cpu1.dtb.walker.walkWaitTime::total 3352 # Table walker wait (enqueue to first request) latency 1346system.cpu1.dtb.walker.walkCompletionTime::samples 2582 # Table walker service (enqueue to completion) latency 1347system.cpu1.dtb.walker.walkCompletionTime::mean 11816.227730 # Table walker service (enqueue to completion) latency 1348system.cpu1.dtb.walker.walkCompletionTime::gmean 11080.373538 # Table walker service (enqueue to completion) latency 1349system.cpu1.dtb.walker.walkCompletionTime::stdev 4768.875507 # Table walker service (enqueue to completion) latency 1350system.cpu1.dtb.walker.walkCompletionTime::0-4095 5 0.19% 0.19% # Table walker service (enqueue to completion) latency 1351system.cpu1.dtb.walker.walkCompletionTime::4096-8191 626 24.24% 24.44% # Table walker service (enqueue to completion) latency 1352system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1198 46.40% 70.84% # Table walker service (enqueue to completion) latency 1353system.cpu1.dtb.walker.walkCompletionTime::12288-16383 544 21.07% 91.91% # Table walker service (enqueue to completion) latency 1354system.cpu1.dtb.walker.walkCompletionTime::16384-20479 85 3.29% 95.20% # Table walker service (enqueue to completion) latency 1355system.cpu1.dtb.walker.walkCompletionTime::20480-24575 56 2.17% 97.37% # Table walker service (enqueue to completion) latency 1356system.cpu1.dtb.walker.walkCompletionTime::24576-28671 31 1.20% 98.57% # Table walker service (enqueue to completion) latency 1357system.cpu1.dtb.walker.walkCompletionTime::28672-32767 20 0.77% 99.34% # Table walker service (enqueue to completion) latency 1358system.cpu1.dtb.walker.walkCompletionTime::32768-36863 3 0.12% 99.46% # Table walker service (enqueue to completion) latency 1359system.cpu1.dtb.walker.walkCompletionTime::36864-40959 8 0.31% 99.77% # Table walker service (enqueue to completion) latency 1360system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency 1361system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.12% 100.00% # Table walker service (enqueue to completion) latency 1362system.cpu1.dtb.walker.walkCompletionTime::total 2582 # Table walker service (enqueue to completion) latency 1363system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution 1364system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution 1365system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution 1366system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.90% 74.90% # Table walker page sizes translated 1367system.cpu1.dtb.walker.walkPageSizes::1M 648 25.10% 100.00% # Table walker page sizes translated 1368system.cpu1.dtb.walker.walkPageSizes::total 2582 # Table walker page sizes translated 1369system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3352 # Table walker requests started/completed, data/inst 1370system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1371system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3352 # Table walker requests started/completed, data/inst 1372system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2582 # Table walker requests started/completed, data/inst 1373system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1374system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst 1375system.cpu1.dtb.walker.walkRequestOrigin::total 5934 # Table walker requests started/completed, data/inst 1376system.cpu1.dtb.inst_hits 0 # ITB inst hits 1377system.cpu1.dtb.inst_misses 0 # ITB inst misses 1378system.cpu1.dtb.read_hits 3941258 # DTB read hits 1379system.cpu1.dtb.read_misses 2845 # DTB read misses 1380system.cpu1.dtb.write_hits 3419362 # DTB write hits 1381system.cpu1.dtb.write_misses 507 # DTB write misses 1382system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1383system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1384system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1385system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1386system.cpu1.dtb.flush_entries 2044 # Number of entries that have been flushed from TLB	1386system.cpu1.dtb.flush_entries 1980 # Number of entries that have been flushed from TLB
1387system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1388system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch 1389system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1390system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1391system.cpu1.dtb.read_accesses 3944103 # DTB read accesses 1392system.cpu1.dtb.write_accesses 3419869 # DTB write accesses 1393system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1394system.cpu1.dtb.hits 7360620 # DTB hits 1395system.cpu1.dtb.misses 3352 # DTB misses 1396system.cpu1.dtb.accesses 7363972 # DTB accesses 1397system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1398system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1399system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1400system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1401system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1402system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1403system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1404system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1405system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1406system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1407system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1408system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1409system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1410system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1411system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1412system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1413system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1414system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1415system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1416system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1417system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1418system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1419system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1420system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1421system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1422system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1423system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1424system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1425system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1426system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1427system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1428system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1429system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1430system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1431system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1432system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1433system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1434system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1435system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1436system.cpu1.itb.walker.walkCompletionTime::mean 12335.140018 # Table walker service (enqueue to completion) latency 1437system.cpu1.itb.walker.walkCompletionTime::gmean 11518.936586 # Table walker service (enqueue to completion) latency 1438system.cpu1.itb.walker.walkCompletionTime::stdev 5605.729039 # Table walker service (enqueue to completion) latency 1439system.cpu1.itb.walker.walkCompletionTime::4096-8191 174 15.72% 15.72% # Table walker service (enqueue to completion) latency 1440system.cpu1.itb.walker.walkCompletionTime::8192-12287 657 59.35% 75.07% # Table walker service (enqueue to completion) latency 1441system.cpu1.itb.walker.walkCompletionTime::12288-16383 169 15.27% 90.33% # Table walker service (enqueue to completion) latency 1442system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 95.03% # Table walker service (enqueue to completion) latency 1443system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.12% # Table walker service (enqueue to completion) latency 1444system.cpu1.itb.walker.walkCompletionTime::24576-28671 20 1.81% 96.93% # Table walker service (enqueue to completion) latency 1445system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.37% # Table walker service (enqueue to completion) latency 1446system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 98.64% # Table walker service (enqueue to completion) latency 1447system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.90% 99.55% # Table walker service (enqueue to completion) latency 1448system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.73% # Table walker service (enqueue to completion) latency 1449system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 99.91% # Table walker service (enqueue to completion) latency 1450system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1451system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1452system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution 1453system.cpu1.itb.walker.walksPending::0 -2078939828 100.00% 100.00% # Table walker pending requests distribution 1454system.cpu1.itb.walker.walksPending::total -2078939828 # Table walker pending requests distribution 1455system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1456system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1457system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated 1458system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1459system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1460system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst 1461system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1462system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1463system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1464system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1465system.cpu1.itb.inst_hits 16556610 # ITB inst hits 1466system.cpu1.itb.inst_misses 1746 # ITB inst misses 1467system.cpu1.itb.read_hits 0 # DTB read hits 1468system.cpu1.itb.read_misses 0 # DTB read misses 1469system.cpu1.itb.write_hits 0 # DTB write hits 1470system.cpu1.itb.write_misses 0 # DTB write misses 1471system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1472system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1473system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1474system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	1387system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1388system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch 1389system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1390system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 1391system.cpu1.dtb.read_accesses 3944103 # DTB read accesses 1392system.cpu1.dtb.write_accesses 3419869 # DTB write accesses 1393system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1394system.cpu1.dtb.hits 7360620 # DTB hits 1395system.cpu1.dtb.misses 3352 # DTB misses 1396system.cpu1.dtb.accesses 7363972 # DTB accesses 1397system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1398system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1399system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1400system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1401system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1402system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1403system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1404system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1405system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1406system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1407system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1408system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1409system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1410system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1411system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1412system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1413system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1414system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1415system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1416system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1417system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1418system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1419system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1420system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1421system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1422system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1423system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1424system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1425system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1426system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1427system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1428system.cpu1.itb.walker.walks 1746 # Table walker walks requested 1429system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors 1430system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate 1431system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate 1432system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency 1433system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1434system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency 1435system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency 1436system.cpu1.itb.walker.walkCompletionTime::mean 12335.140018 # Table walker service (enqueue to completion) latency 1437system.cpu1.itb.walker.walkCompletionTime::gmean 11518.936586 # Table walker service (enqueue to completion) latency 1438system.cpu1.itb.walker.walkCompletionTime::stdev 5605.729039 # Table walker service (enqueue to completion) latency 1439system.cpu1.itb.walker.walkCompletionTime::4096-8191 174 15.72% 15.72% # Table walker service (enqueue to completion) latency 1440system.cpu1.itb.walker.walkCompletionTime::8192-12287 657 59.35% 75.07% # Table walker service (enqueue to completion) latency 1441system.cpu1.itb.walker.walkCompletionTime::12288-16383 169 15.27% 90.33% # Table walker service (enqueue to completion) latency 1442system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 95.03% # Table walker service (enqueue to completion) latency 1443system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.12% # Table walker service (enqueue to completion) latency 1444system.cpu1.itb.walker.walkCompletionTime::24576-28671 20 1.81% 96.93% # Table walker service (enqueue to completion) latency 1445system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.37% # Table walker service (enqueue to completion) latency 1446system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 98.64% # Table walker service (enqueue to completion) latency 1447system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.90% 99.55% # Table walker service (enqueue to completion) latency 1448system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.73% # Table walker service (enqueue to completion) latency 1449system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 99.91% # Table walker service (enqueue to completion) latency 1450system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency 1451system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency 1452system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution 1453system.cpu1.itb.walker.walksPending::0 -2078939828 100.00% 100.00% # Table walker pending requests distribution 1454system.cpu1.itb.walker.walksPending::total -2078939828 # Table walker pending requests distribution 1455system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated 1456system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated 1457system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated 1458system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1459system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst 1460system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst 1461system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1462system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst 1463system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst 1464system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst 1465system.cpu1.itb.inst_hits 16556610 # ITB inst hits 1466system.cpu1.itb.inst_misses 1746 # ITB inst misses 1467system.cpu1.itb.read_hits 0 # DTB read hits 1468system.cpu1.itb.read_misses 0 # DTB read misses 1469system.cpu1.itb.write_hits 0 # DTB write hits 1470system.cpu1.itb.write_misses 0 # DTB write misses 1471system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1472system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1473system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1474system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1475system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB	1475system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB
1476system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1477system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1478system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1479system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1480system.cpu1.itb.read_accesses 0 # DTB read accesses 1481system.cpu1.itb.write_accesses 0 # DTB write accesses 1482system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses 1483system.cpu1.itb.hits 16556610 # DTB hits 1484system.cpu1.itb.misses 1746 # DTB misses 1485system.cpu1.itb.accesses 16558356 # DTB accesses 1486system.cpu1.numPwrStateTransitions 5511 # Number of power state transitions 1487system.cpu1.pwrStateClkGateDist::samples 2756 # Distribution of time spent in the clock gated state 1488system.cpu1.pwrStateClkGateDist::mean 1031898407.856313 # Distribution of time spent in the clock gated state 1489system.cpu1.pwrStateClkGateDist::stdev 25737040202.524998 # Distribution of time spent in the clock gated state 1490system.cpu1.pwrStateClkGateDist::underflows 1964 71.26% 71.26% # Distribution of time spent in the clock gated state 1491system.cpu1.pwrStateClkGateDist::1000-5e+10 786 28.52% 99.78% # Distribution of time spent in the clock gated state 1492system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state 1493system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1494system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1495system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1496system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1497system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1498system.cpu1.pwrStateClkGateDist::max_value 929980631528 # Distribution of time spent in the clock gated state 1499system.cpu1.pwrStateClkGateDist::total 2756 # Distribution of time spent in the clock gated state 1500system.cpu1.pwrStateResidencyTicks::ON 25876957948 # Cumulative time (in ticks) in various power states 1501system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843912012052 # Cumulative time (in ticks) in various power states 1502system.cpu1.numCycles 5738649789 # number of cpu cycles simulated 1503system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1504system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1505system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1506system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed 1507system.cpu1.committedInsts 16201169 # Number of instructions committed 1508system.cpu1.committedOps 19741428 # Number of ops (including micro ops) committed 1509system.cpu1.num_int_alu_accesses 17804295 # Number of integer alu accesses 1510system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses 1511system.cpu1.num_func_calls 1029080 # number of times a function call or return occured 1512system.cpu1.num_conditional_control_insts 1813608 # number of instructions that are conditional controls 1513system.cpu1.num_int_insts 17804295 # number of integer instructions 1514system.cpu1.num_fp_insts 1857 # number of float instructions 1515system.cpu1.num_int_register_reads 32308777 # number of times the integer registers were read 1516system.cpu1.num_int_register_writes 12487661 # number of times the integer registers were written 1517system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read 1518system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1519system.cpu1.num_cc_register_reads 72166445 # number of times the CC registers were read 1520system.cpu1.num_cc_register_writes 6418557 # number of times the CC registers were written 1521system.cpu1.num_mem_refs 7593995 # number of memory refs 1522system.cpu1.num_load_insts 4052758 # Number of load instructions 1523system.cpu1.num_store_insts 3541237 # Number of store instructions 1524system.cpu1.num_idle_cycles 5686904242.264484 # Number of idle cycles 1525system.cpu1.num_busy_cycles 51745546.735515 # Number of busy cycles 1526system.cpu1.not_idle_fraction 0.009017 # Percentage of non-idle cycles 1527system.cpu1.idle_fraction 0.990983 # Percentage of idle cycles 1528system.cpu1.Branches 2921126 # Number of branches fetched 1529system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1530system.cpu1.op_class::IntAlu 12468405 62.06% 62.06% # Class of executed instruction 1531system.cpu1.op_class::IntMult 26465 0.13% 62.19% # Class of executed instruction 1532system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction 1533system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction 1534system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction 1535system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction 1536system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction 1537system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction 1538system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction 1539system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction 1540system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction 1541system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction 1542system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction 1543system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction 1544system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction 1545system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction 1546system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction 1547system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction 1548system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction 1549system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction 1550system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction 1551system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction 1552system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction 1553system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction 1554system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction 1555system.cpu1.op_class::SimdFloatMisc 3319 0.02% 62.20% # Class of executed instruction 1556system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction 1557system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction 1558system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction 1559system.cpu1.op_class::MemRead 4052758 20.17% 82.38% # Class of executed instruction 1560system.cpu1.op_class::MemWrite 3541237 17.62% 100.00% # Class of executed instruction 1561system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1562system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1563system.cpu1.op_class::total 20092250 # Class of executed instruction 1564system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1565system.cpu1.dcache.tags.replacements 186389 # number of replacements 1566system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use 1567system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks. 1568system.cpu1.dcache.tags.sampled_refs 186755 # Sample count of references to valid blocks. 1569system.cpu1.dcache.tags.avg_refs 37.984359 # Average number of references to valid blocks. 1570system.cpu1.dcache.tags.warmup_cycle 127433218000 # Cycle when the warmup percentage was hit. 1571system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.298921 # Average occupied blocks per requestor 1572system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916599 # Average percentage of cache occupancy 1573system.cpu1.dcache.tags.occ_percent::total 0.916599 # Average percentage of cache occupancy 1574system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id 1575system.cpu1.dcache.tags.age_task_id_blocks_1024::2 285 # Occupied blocks per task id 1576system.cpu1.dcache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id 1577system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id 1578system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses 1579system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses 1580system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1581system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits 1582system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits 1583system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits 1584system.cpu1.dcache.WriteReq_hits::total 3230955 # number of WriteReq hits 1585system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48929 # number of SoftPFReq hits 1586system.cpu1.dcache.SoftPFReq_hits::total 48929 # number of SoftPFReq hits 1587system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78822 # number of LoadLockedReq hits 1588system.cpu1.dcache.LoadLockedReq_hits::total 78822 # number of LoadLockedReq hits 1589system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70747 # number of StoreCondReq hits 1590system.cpu1.dcache.StoreCondReq_hits::total 70747 # number of StoreCondReq hits 1591system.cpu1.dcache.demand_hits::cpu1.data 6860355 # number of demand (read+write) hits 1592system.cpu1.dcache.demand_hits::total 6860355 # number of demand (read+write) hits 1593system.cpu1.dcache.overall_hits::cpu1.data 6909284 # number of overall hits 1594system.cpu1.dcache.overall_hits::total 6909284 # number of overall hits 1595system.cpu1.dcache.ReadReq_misses::cpu1.data 133654 # number of ReadReq misses 1596system.cpu1.dcache.ReadReq_misses::total 133654 # number of ReadReq misses 1597system.cpu1.dcache.WriteReq_misses::cpu1.data 91683 # number of WriteReq misses 1598system.cpu1.dcache.WriteReq_misses::total 91683 # number of WriteReq misses 1599system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30306 # number of SoftPFReq misses 1600system.cpu1.dcache.SoftPFReq_misses::total 30306 # number of SoftPFReq misses 1601system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17079 # number of LoadLockedReq misses 1602system.cpu1.dcache.LoadLockedReq_misses::total 17079 # number of LoadLockedReq misses 1603system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23334 # number of StoreCondReq misses 1604system.cpu1.dcache.StoreCondReq_misses::total 23334 # number of StoreCondReq misses 1605system.cpu1.dcache.demand_misses::cpu1.data 225337 # number of demand (read+write) misses 1606system.cpu1.dcache.demand_misses::total 225337 # number of demand (read+write) misses 1607system.cpu1.dcache.overall_misses::cpu1.data 255643 # number of overall misses 1608system.cpu1.dcache.overall_misses::total 255643 # number of overall misses 1609system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1974580500 # number of ReadReq miss cycles 1610system.cpu1.dcache.ReadReq_miss_latency::total 1974580500 # number of ReadReq miss cycles 1611system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2414638500 # number of WriteReq miss cycles 1612system.cpu1.dcache.WriteReq_miss_latency::total 2414638500 # number of WriteReq miss cycles 1613system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320455500 # number of LoadLockedReq miss cycles 1614system.cpu1.dcache.LoadLockedReq_miss_latency::total 320455500 # number of LoadLockedReq miss cycles 1615system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 569715000 # number of StoreCondReq miss cycles 1616system.cpu1.dcache.StoreCondReq_miss_latency::total 569715000 # number of StoreCondReq miss cycles 1617system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3416500 # number of StoreCondFailReq miss cycles 1618system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3416500 # number of StoreCondFailReq miss cycles 1619system.cpu1.dcache.demand_miss_latency::cpu1.data 4389219000 # number of demand (read+write) miss cycles 1620system.cpu1.dcache.demand_miss_latency::total 4389219000 # number of demand (read+write) miss cycles 1621system.cpu1.dcache.overall_miss_latency::cpu1.data 4389219000 # number of overall miss cycles 1622system.cpu1.dcache.overall_miss_latency::total 4389219000 # number of overall miss cycles 1623system.cpu1.dcache.ReadReq_accesses::cpu1.data 3763054 # number of ReadReq accesses(hits+misses) 1624system.cpu1.dcache.ReadReq_accesses::total 3763054 # number of ReadReq accesses(hits+misses) 1625system.cpu1.dcache.WriteReq_accesses::cpu1.data 3322638 # number of WriteReq accesses(hits+misses) 1626system.cpu1.dcache.WriteReq_accesses::total 3322638 # number of WriteReq accesses(hits+misses) 1627system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79235 # number of SoftPFReq accesses(hits+misses) 1628system.cpu1.dcache.SoftPFReq_accesses::total 79235 # number of SoftPFReq accesses(hits+misses) 1629system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95901 # number of LoadLockedReq accesses(hits+misses) 1630system.cpu1.dcache.LoadLockedReq_accesses::total 95901 # number of LoadLockedReq accesses(hits+misses) 1631system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94081 # number of StoreCondReq accesses(hits+misses) 1632system.cpu1.dcache.StoreCondReq_accesses::total 94081 # number of StoreCondReq accesses(hits+misses) 1633system.cpu1.dcache.demand_accesses::cpu1.data 7085692 # number of demand (read+write) accesses 1634system.cpu1.dcache.demand_accesses::total 7085692 # number of demand (read+write) accesses 1635system.cpu1.dcache.overall_accesses::cpu1.data 7164927 # number of overall (read+write) accesses 1636system.cpu1.dcache.overall_accesses::total 7164927 # number of overall (read+write) accesses 1637system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses 1638system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses 1639system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027593 # miss rate for WriteReq accesses 1640system.cpu1.dcache.WriteReq_miss_rate::total 0.027593 # miss rate for WriteReq accesses 1641system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382482 # miss rate for SoftPFReq accesses 1642system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382482 # miss rate for SoftPFReq accesses 1643system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178090 # miss rate for LoadLockedReq accesses 1644system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178090 # miss rate for LoadLockedReq accesses 1645system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248020 # miss rate for StoreCondReq accesses 1646system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248020 # miss rate for StoreCondReq accesses 1647system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031802 # miss rate for demand accesses 1648system.cpu1.dcache.demand_miss_rate::total 0.031802 # miss rate for demand accesses 1649system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035680 # miss rate for overall accesses 1650system.cpu1.dcache.overall_miss_rate::total 0.035680 # miss rate for overall accesses 1651system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.822706 # average ReadReq miss latency 1652system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.822706 # average ReadReq miss latency 1653system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26336.818167 # average WriteReq miss latency 1654system.cpu1.dcache.WriteReq_avg_miss_latency::total 26336.818167 # average WriteReq miss latency 1655system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18763.130160 # average LoadLockedReq miss latency 1656system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18763.130160 # average LoadLockedReq miss latency 1657system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24415.659553 # average StoreCondReq miss latency 1658system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24415.659553 # average StoreCondReq miss latency 1659system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1660system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1661system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19478.465587 # average overall miss latency 1662system.cpu1.dcache.demand_avg_miss_latency::total 19478.465587 # average overall miss latency 1663system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17169.329886 # average overall miss latency 1664system.cpu1.dcache.overall_avg_miss_latency::total 17169.329886 # average overall miss latency 1665system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1666system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1667system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1668system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1669system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1670system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1671system.cpu1.dcache.writebacks::writebacks 186389 # number of writebacks 1672system.cpu1.dcache.writebacks::total 186389 # number of writebacks 1673system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits 1674system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits 1675system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12013 # number of LoadLockedReq MSHR hits 1676system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12013 # number of LoadLockedReq MSHR hits 1677system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits 1678system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits 1679system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits 1680system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits 1681system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133371 # number of ReadReq MSHR misses 1682system.cpu1.dcache.ReadReq_mshr_misses::total 133371 # number of ReadReq MSHR misses 1683system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91683 # number of WriteReq MSHR misses 1684system.cpu1.dcache.WriteReq_mshr_misses::total 91683 # number of WriteReq MSHR misses 1685system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29541 # number of SoftPFReq MSHR misses 1686system.cpu1.dcache.SoftPFReq_mshr_misses::total 29541 # number of SoftPFReq MSHR misses 1687system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5066 # number of LoadLockedReq MSHR misses 1688system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5066 # number of LoadLockedReq MSHR misses 1689system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23334 # number of StoreCondReq MSHR misses 1690system.cpu1.dcache.StoreCondReq_mshr_misses::total 23334 # number of StoreCondReq MSHR misses 1691system.cpu1.dcache.demand_mshr_misses::cpu1.data 225054 # number of demand (read+write) MSHR misses 1692system.cpu1.dcache.demand_mshr_misses::total 225054 # number of demand (read+write) MSHR misses 1693system.cpu1.dcache.overall_mshr_misses::cpu1.data 254595 # number of overall MSHR misses 1694system.cpu1.dcache.overall_mshr_misses::total 254595 # number of overall MSHR misses 1695system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable 1696system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3095 # number of ReadReq MSHR uncacheable 1697system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable 1698system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable 1699system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses 1700system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5545 # number of overall MSHR uncacheable misses 1701system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1833975000 # number of ReadReq MSHR miss cycles 1702system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1833975000 # number of ReadReq MSHR miss cycles 1703system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2322955500 # number of WriteReq MSHR miss cycles 1704system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2322955500 # number of WriteReq MSHR miss cycles 1705system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 497374500 # number of SoftPFReq MSHR miss cycles 1706system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 497374500 # number of SoftPFReq MSHR miss cycles 1707system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87920500 # number of LoadLockedReq MSHR miss cycles 1708system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87920500 # number of LoadLockedReq MSHR miss cycles 1709system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 546440000 # number of StoreCondReq MSHR miss cycles 1710system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 546440000 # number of StoreCondReq MSHR miss cycles 1711system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3357500 # number of StoreCondFailReq MSHR miss cycles 1712system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3357500 # number of StoreCondFailReq MSHR miss cycles 1713system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4156930500 # number of demand (read+write) MSHR miss cycles 1714system.cpu1.dcache.demand_mshr_miss_latency::total 4156930500 # number of demand (read+write) MSHR miss cycles 1715system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4654305000 # number of overall MSHR miss cycles 1716system.cpu1.dcache.overall_mshr_miss_latency::total 4654305000 # number of overall MSHR miss cycles 1717system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443417000 # number of ReadReq MSHR uncacheable cycles 1718system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443417000 # number of ReadReq MSHR uncacheable cycles 1719system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443417000 # number of overall MSHR uncacheable cycles 1720system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443417000 # number of overall MSHR uncacheable cycles 1721system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses 1722system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses 1723system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027593 # mshr miss rate for WriteReq accesses 1724system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027593 # mshr miss rate for WriteReq accesses 1725system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372828 # mshr miss rate for SoftPFReq accesses 1726system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372828 # mshr miss rate for SoftPFReq accesses 1727system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052825 # mshr miss rate for LoadLockedReq accesses 1728system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052825 # mshr miss rate for LoadLockedReq accesses 1729system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248020 # mshr miss rate for StoreCondReq accesses 1730system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248020 # mshr miss rate for StoreCondReq accesses 1731system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for demand accesses 1732system.cpu1.dcache.demand_mshr_miss_rate::total 0.031762 # mshr miss rate for demand accesses 1733system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035534 # mshr miss rate for overall accesses 1734system.cpu1.dcache.overall_mshr_miss_rate::total 0.035534 # mshr miss rate for overall accesses 1735system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13750.927863 # average ReadReq mshr miss latency 1736system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13750.927863 # average ReadReq mshr miss latency 1737system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25336.818167 # average WriteReq mshr miss latency 1738system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25336.818167 # average WriteReq mshr miss latency 1739system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16836.752310 # average SoftPFReq mshr miss latency 1740system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16836.752310 # average SoftPFReq mshr miss latency 1741system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17355.013818 # average LoadLockedReq mshr miss latency 1742system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17355.013818 # average LoadLockedReq mshr miss latency 1743system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23418.188052 # average StoreCondReq mshr miss latency 1744system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23418.188052 # average StoreCondReq mshr miss latency 1745system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1746system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1747system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18470.813671 # average overall mshr miss latency 1748system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18470.813671 # average overall mshr miss latency 1749system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18281.211336 # average overall mshr miss latency 1750system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18281.211336 # average overall mshr miss latency 1751system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143268.820679 # average ReadReq mshr uncacheable latency 1752system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency 1753system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency 1754system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency 1755system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1756system.cpu1.icache.tags.replacements 505464 # number of replacements 1757system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use 1758system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks. 1759system.cpu1.icache.tags.sampled_refs 505976 # Sample count of references to valid blocks. 1760system.cpu1.icache.tags.avg_refs 31.722115 # Average number of references to valid blocks. 1761system.cpu1.icache.tags.warmup_cycle 85269924000 # Cycle when the warmup percentage was hit. 1762system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478732 # Average occupied blocks per requestor 1763system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy 1764system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy 1765system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1766system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id 1767system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id 1768system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1769system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1770system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses 1771system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses 1772system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1773system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits 1774system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits 1775system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits 1776system.cpu1.icache.demand_hits::total 16050629 # number of demand (read+write) hits 1777system.cpu1.icache.overall_hits::cpu1.inst 16050629 # number of overall hits 1778system.cpu1.icache.overall_hits::total 16050629 # number of overall hits 1779system.cpu1.icache.ReadReq_misses::cpu1.inst 505976 # number of ReadReq misses 1780system.cpu1.icache.ReadReq_misses::total 505976 # number of ReadReq misses 1781system.cpu1.icache.demand_misses::cpu1.inst 505976 # number of demand (read+write) misses 1782system.cpu1.icache.demand_misses::total 505976 # number of demand (read+write) misses 1783system.cpu1.icache.overall_misses::cpu1.inst 505976 # number of overall misses 1784system.cpu1.icache.overall_misses::total 505976 # number of overall misses 1785system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4528088500 # number of ReadReq miss cycles 1786system.cpu1.icache.ReadReq_miss_latency::total 4528088500 # number of ReadReq miss cycles 1787system.cpu1.icache.demand_miss_latency::cpu1.inst 4528088500 # number of demand (read+write) miss cycles 1788system.cpu1.icache.demand_miss_latency::total 4528088500 # number of demand (read+write) miss cycles 1789system.cpu1.icache.overall_miss_latency::cpu1.inst 4528088500 # number of overall miss cycles 1790system.cpu1.icache.overall_miss_latency::total 4528088500 # number of overall miss cycles 1791system.cpu1.icache.ReadReq_accesses::cpu1.inst 16556605 # number of ReadReq accesses(hits+misses) 1792system.cpu1.icache.ReadReq_accesses::total 16556605 # number of ReadReq accesses(hits+misses) 1793system.cpu1.icache.demand_accesses::cpu1.inst 16556605 # number of demand (read+write) accesses 1794system.cpu1.icache.demand_accesses::total 16556605 # number of demand (read+write) accesses 1795system.cpu1.icache.overall_accesses::cpu1.inst 16556605 # number of overall (read+write) accesses 1796system.cpu1.icache.overall_accesses::total 16556605 # number of overall (read+write) accesses 1797system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030560 # miss rate for ReadReq accesses 1798system.cpu1.icache.ReadReq_miss_rate::total 0.030560 # miss rate for ReadReq accesses 1799system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030560 # miss rate for demand accesses 1800system.cpu1.icache.demand_miss_rate::total 0.030560 # miss rate for demand accesses 1801system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030560 # miss rate for overall accesses 1802system.cpu1.icache.overall_miss_rate::total 0.030560 # miss rate for overall accesses 1803system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8949.215971 # average ReadReq miss latency 1804system.cpu1.icache.ReadReq_avg_miss_latency::total 8949.215971 # average ReadReq miss latency 1805system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency 1806system.cpu1.icache.demand_avg_miss_latency::total 8949.215971 # average overall miss latency 1807system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency 1808system.cpu1.icache.overall_avg_miss_latency::total 8949.215971 # average overall miss latency 1809system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1810system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1811system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1812system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1813system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1814system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1815system.cpu1.icache.writebacks::writebacks 505464 # number of writebacks 1816system.cpu1.icache.writebacks::total 505464 # number of writebacks 1817system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 505976 # number of ReadReq MSHR misses 1818system.cpu1.icache.ReadReq_mshr_misses::total 505976 # number of ReadReq MSHR misses 1819system.cpu1.icache.demand_mshr_misses::cpu1.inst 505976 # number of demand (read+write) MSHR misses 1820system.cpu1.icache.demand_mshr_misses::total 505976 # number of demand (read+write) MSHR misses 1821system.cpu1.icache.overall_mshr_misses::cpu1.inst 505976 # number of overall MSHR misses 1822system.cpu1.icache.overall_mshr_misses::total 505976 # number of overall MSHR misses 1823system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1824system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1825system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1826system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1827system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4275100500 # number of ReadReq MSHR miss cycles 1828system.cpu1.icache.ReadReq_mshr_miss_latency::total 4275100500 # number of ReadReq MSHR miss cycles 1829system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4275100500 # number of demand (read+write) MSHR miss cycles 1830system.cpu1.icache.demand_mshr_miss_latency::total 4275100500 # number of demand (read+write) MSHR miss cycles 1831system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4275100500 # number of overall MSHR miss cycles 1832system.cpu1.icache.overall_mshr_miss_latency::total 4275100500 # number of overall MSHR miss cycles 1833system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # number of ReadReq MSHR uncacheable cycles 1834system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15776500 # number of ReadReq MSHR uncacheable cycles 1835system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15776500 # number of overall MSHR uncacheable cycles 1836system.cpu1.icache.overall_mshr_uncacheable_latency::total 15776500 # number of overall MSHR uncacheable cycles 1837system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for ReadReq accesses 1838system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030560 # mshr miss rate for ReadReq accesses 1839system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for demand accesses 1840system.cpu1.icache.demand_mshr_miss_rate::total 0.030560 # mshr miss rate for demand accesses 1841system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for overall accesses 1842system.cpu1.icache.overall_mshr_miss_rate::total 0.030560 # mshr miss rate for overall accesses 1843system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average ReadReq mshr miss latency 1844system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8449.215971 # average ReadReq mshr miss latency 1845system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency 1846system.cpu1.icache.demand_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency 1847system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency 1848system.cpu1.icache.overall_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency 1849system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency 1850system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency 1851system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency 1852system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency 1853system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1854system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued 1855system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified 1856system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1857system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1858system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1859system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing 1860system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1861system.cpu1.l2cache.tags.replacements 44688 # number of replacements 1862system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use 1863system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks. 1864system.cpu1.l2cache.tags.sampled_refs 59377 # Sample count of references to valid blocks. 1865system.cpu1.l2cache.tags.avg_refs 19.563737 # Average number of references to valid blocks. 1866system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1867system.cpu1.l2cache.tags.occ_blocks::writebacks 14464.281457 # Average occupied blocks per requestor 1868system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.152749 # Average occupied blocks per requestor 1869system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.089726 # Average occupied blocks per requestor 1870system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 468.961320 # Average occupied blocks per requestor 1871system.cpu1.l2cache.tags.occ_percent::writebacks 0.882830 # Average percentage of cache occupancy 1872system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy 1873system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy 1874system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028623 # Average percentage of cache occupancy 1875system.cpu1.l2cache.tags.occ_percent::total 0.911773 # Average percentage of cache occupancy 1876system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id 1877system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 1878system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13646 # Occupied blocks per task id 1879system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 36 # Occupied blocks per task id 1880system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 993 # Occupied blocks per task id 1881system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1882system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 1883system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 1884system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id 1885system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11682 # Occupied blocks per task id 1886system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id 1887system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 1888system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832886 # Percentage of cache occupancy per task id 1889system.cpu1.l2cache.tags.tag_accesses 23775762 # Number of tag accesses 1890system.cpu1.l2cache.tags.data_accesses 23775762 # Number of data accesses 1891system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1892system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3761 # number of ReadReq hits 1893system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2010 # number of ReadReq hits 1894system.cpu1.l2cache.ReadReq_hits::total 5771 # number of ReadReq hits 1895system.cpu1.l2cache.WritebackDirty_hits::writebacks 113707 # number of WritebackDirty hits 1896system.cpu1.l2cache.WritebackDirty_hits::total 113707 # number of WritebackDirty hits 1897system.cpu1.l2cache.WritebackClean_hits::writebacks 567008 # number of WritebackClean hits 1898system.cpu1.l2cache.WritebackClean_hits::total 567008 # number of WritebackClean hits 1899system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27229 # number of ReadExReq hits 1900system.cpu1.l2cache.ReadExReq_hits::total 27229 # number of ReadExReq hits 1901system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 492726 # number of ReadCleanReq hits 1902system.cpu1.l2cache.ReadCleanReq_hits::total 492726 # number of ReadCleanReq hits 1903system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99930 # number of ReadSharedReq hits 1904system.cpu1.l2cache.ReadSharedReq_hits::total 99930 # number of ReadSharedReq hits 1905system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3761 # number of demand (read+write) hits 1906system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2010 # number of demand (read+write) hits 1907system.cpu1.l2cache.demand_hits::cpu1.inst 492726 # number of demand (read+write) hits 1908system.cpu1.l2cache.demand_hits::cpu1.data 127159 # number of demand (read+write) hits 1909system.cpu1.l2cache.demand_hits::total 625656 # number of demand (read+write) hits 1910system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3761 # number of overall hits 1911system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2010 # number of overall hits 1912system.cpu1.l2cache.overall_hits::cpu1.inst 492726 # number of overall hits 1913system.cpu1.l2cache.overall_hits::cpu1.data 127159 # number of overall hits 1914system.cpu1.l2cache.overall_hits::total 625656 # number of overall hits 1915system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 318 # number of ReadReq misses 1916system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses 1917system.cpu1.l2cache.ReadReq_misses::total 590 # number of ReadReq misses 1918system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29672 # number of UpgradeReq misses 1919system.cpu1.l2cache.UpgradeReq_misses::total 29672 # number of UpgradeReq misses 1920system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23330 # number of SCUpgradeReq misses 1921system.cpu1.l2cache.SCUpgradeReq_misses::total 23330 # number of SCUpgradeReq misses 1922system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 1923system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1924system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34782 # number of ReadExReq misses 1925system.cpu1.l2cache.ReadExReq_misses::total 34782 # number of ReadExReq misses 1926system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13250 # number of ReadCleanReq misses 1927system.cpu1.l2cache.ReadCleanReq_misses::total 13250 # number of ReadCleanReq misses 1928system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68048 # number of ReadSharedReq misses 1929system.cpu1.l2cache.ReadSharedReq_misses::total 68048 # number of ReadSharedReq misses 1930system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 318 # number of demand (read+write) misses 1931system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses 1932system.cpu1.l2cache.demand_misses::cpu1.inst 13250 # number of demand (read+write) misses 1933system.cpu1.l2cache.demand_misses::cpu1.data 102830 # number of demand (read+write) misses 1934system.cpu1.l2cache.demand_misses::total 116670 # number of demand (read+write) misses 1935system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 318 # number of overall misses 1936system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses 1937system.cpu1.l2cache.overall_misses::cpu1.inst 13250 # number of overall misses 1938system.cpu1.l2cache.overall_misses::cpu1.data 102830 # number of overall misses 1939system.cpu1.l2cache.overall_misses::total 116670 # number of overall misses 1940system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6473000 # number of ReadReq miss cycles 1941system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5557000 # number of ReadReq miss cycles 1942system.cpu1.l2cache.ReadReq_miss_latency::total 12030000 # number of ReadReq miss cycles 1943system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65067000 # number of UpgradeReq miss cycles 1944system.cpu1.l2cache.UpgradeReq_miss_latency::total 65067000 # number of UpgradeReq miss cycles 1945system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 32437500 # number of SCUpgradeReq miss cycles 1946system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 32437500 # number of SCUpgradeReq miss cycles 1947system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3268500 # number of SCUpgradeFailReq miss cycles 1948system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3268500 # number of SCUpgradeFailReq miss cycles 1949system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1333613500 # number of ReadExReq miss cycles 1950system.cpu1.l2cache.ReadExReq_miss_latency::total 1333613500 # number of ReadExReq miss cycles 1951system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 533576500 # number of ReadCleanReq miss cycles 1952system.cpu1.l2cache.ReadCleanReq_miss_latency::total 533576500 # number of ReadCleanReq miss cycles 1953system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1512816500 # number of ReadSharedReq miss cycles 1954system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1512816500 # number of ReadSharedReq miss cycles 1955system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6473000 # number of demand (read+write) miss cycles 1956system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5557000 # number of demand (read+write) miss cycles 1957system.cpu1.l2cache.demand_miss_latency::cpu1.inst 533576500 # number of demand (read+write) miss cycles 1958system.cpu1.l2cache.demand_miss_latency::cpu1.data 2846430000 # number of demand (read+write) miss cycles 1959system.cpu1.l2cache.demand_miss_latency::total 3392036500 # number of demand (read+write) miss cycles 1960system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6473000 # number of overall miss cycles 1961system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5557000 # number of overall miss cycles 1962system.cpu1.l2cache.overall_miss_latency::cpu1.inst 533576500 # number of overall miss cycles 1963system.cpu1.l2cache.overall_miss_latency::cpu1.data 2846430000 # number of overall miss cycles 1964system.cpu1.l2cache.overall_miss_latency::total 3392036500 # number of overall miss cycles 1965system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4079 # number of ReadReq accesses(hits+misses) 1966system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2282 # number of ReadReq accesses(hits+misses) 1967system.cpu1.l2cache.ReadReq_accesses::total 6361 # number of ReadReq accesses(hits+misses) 1968system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113707 # number of WritebackDirty accesses(hits+misses) 1969system.cpu1.l2cache.WritebackDirty_accesses::total 113707 # number of WritebackDirty accesses(hits+misses) 1970system.cpu1.l2cache.WritebackClean_accesses::writebacks 567008 # number of WritebackClean accesses(hits+misses) 1971system.cpu1.l2cache.WritebackClean_accesses::total 567008 # number of WritebackClean accesses(hits+misses) 1972system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29672 # number of UpgradeReq accesses(hits+misses) 1973system.cpu1.l2cache.UpgradeReq_accesses::total 29672 # number of UpgradeReq accesses(hits+misses) 1974system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23330 # number of SCUpgradeReq accesses(hits+misses) 1975system.cpu1.l2cache.SCUpgradeReq_accesses::total 23330 # number of SCUpgradeReq accesses(hits+misses) 1976system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1977system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1978system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62011 # number of ReadExReq accesses(hits+misses) 1979system.cpu1.l2cache.ReadExReq_accesses::total 62011 # number of ReadExReq accesses(hits+misses) 1980system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 505976 # number of ReadCleanReq accesses(hits+misses) 1981system.cpu1.l2cache.ReadCleanReq_accesses::total 505976 # number of ReadCleanReq accesses(hits+misses) 1982system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167978 # number of ReadSharedReq accesses(hits+misses) 1983system.cpu1.l2cache.ReadSharedReq_accesses::total 167978 # number of ReadSharedReq accesses(hits+misses) 1984system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4079 # number of demand (read+write) accesses 1985system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2282 # number of demand (read+write) accesses 1986system.cpu1.l2cache.demand_accesses::cpu1.inst 505976 # number of demand (read+write) accesses 1987system.cpu1.l2cache.demand_accesses::cpu1.data 229989 # number of demand (read+write) accesses 1988system.cpu1.l2cache.demand_accesses::total 742326 # number of demand (read+write) accesses 1989system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4079 # number of overall (read+write) accesses 1990system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2282 # number of overall (read+write) accesses 1991system.cpu1.l2cache.overall_accesses::cpu1.inst 505976 # number of overall (read+write) accesses 1992system.cpu1.l2cache.overall_accesses::cpu1.data 229989 # number of overall (read+write) accesses 1993system.cpu1.l2cache.overall_accesses::total 742326 # number of overall (read+write) accesses 1994system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for ReadReq accesses 1995system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.119194 # miss rate for ReadReq accesses 1996system.cpu1.l2cache.ReadReq_miss_rate::total 0.092753 # miss rate for ReadReq accesses 1997system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1998system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1999system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2000system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2001system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2002system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2003system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560900 # miss rate for ReadExReq accesses 2004system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560900 # miss rate for ReadExReq accesses 2005system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026187 # miss rate for ReadCleanReq accesses 2006system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026187 # miss rate for ReadCleanReq accesses 2007system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405101 # miss rate for ReadSharedReq accesses 2008system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405101 # miss rate for ReadSharedReq accesses 2009system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for demand accesses 2010system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.119194 # miss rate for demand accesses 2011system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026187 # miss rate for demand accesses 2012system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.447108 # miss rate for demand accesses 2013system.cpu1.l2cache.demand_miss_rate::total 0.157168 # miss rate for demand accesses 2014system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for overall accesses 2015system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.119194 # miss rate for overall accesses 2016system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026187 # miss rate for overall accesses 2017system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.447108 # miss rate for overall accesses 2018system.cpu1.l2cache.overall_miss_rate::total 0.157168 # miss rate for overall accesses 2019system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average ReadReq miss latency 2020system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20430.147059 # average ReadReq miss latency 2021system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20389.830508 # average ReadReq miss latency 2022system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2192.875438 # average UpgradeReq miss latency 2023system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2192.875438 # average UpgradeReq miss latency 2024system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1390.377197 # average SCUpgradeReq miss latency 2025system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1390.377197 # average SCUpgradeReq miss latency 2026system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 817125 # average SCUpgradeFailReq miss latency 2027system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 817125 # average SCUpgradeFailReq miss latency 2028system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38342.059111 # average ReadExReq miss latency 2029system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38342.059111 # average ReadExReq miss latency 2030system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40269.924528 # average ReadCleanReq miss latency 2031system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40269.924528 # average ReadCleanReq miss latency 2032system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22231.608570 # average ReadSharedReq miss latency 2033system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22231.608570 # average ReadSharedReq miss latency 2034system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency 2035system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency 2036system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency 2037system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency 2038system.cpu1.l2cache.demand_avg_miss_latency::total 29073.767892 # average overall miss latency 2039system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency 2040system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency 2041system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency 2042system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency 2043system.cpu1.l2cache.overall_avg_miss_latency::total 29073.767892 # average overall miss latency 2044system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2045system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2046system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2047system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2048system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2049system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2050system.cpu1.l2cache.unused_prefetches 790 # number of HardPF blocks evicted w/o reference 2051system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks 2052system.cpu1.l2cache.writebacks::total 33019 # number of writebacks 2053system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 57 # number of ReadExReq MSHR hits 2054system.cpu1.l2cache.ReadExReq_mshr_hits::total 57 # number of ReadExReq MSHR hits 2055system.cpu1.l2cache.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits 2056system.cpu1.l2cache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits 2057system.cpu1.l2cache.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits 2058system.cpu1.l2cache.overall_mshr_hits::total 57 # number of overall MSHR hits 2059system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 318 # number of ReadReq MSHR misses 2060system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 272 # number of ReadReq MSHR misses 2061system.cpu1.l2cache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses 2062system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of HardPFReq MSHR misses 2063system.cpu1.l2cache.HardPFReq_mshr_misses::total 24979 # number of HardPFReq MSHR misses 2064system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29672 # number of UpgradeReq MSHR misses 2065system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29672 # number of UpgradeReq MSHR misses 2066system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23330 # number of SCUpgradeReq MSHR misses 2067system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23330 # number of SCUpgradeReq MSHR misses 2068system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2069system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2070system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34725 # number of ReadExReq MSHR misses 2071system.cpu1.l2cache.ReadExReq_mshr_misses::total 34725 # number of ReadExReq MSHR misses 2072system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13250 # number of ReadCleanReq MSHR misses 2073system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13250 # number of ReadCleanReq MSHR misses 2074system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68048 # number of ReadSharedReq MSHR misses 2075system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68048 # number of ReadSharedReq MSHR misses 2076system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 318 # number of demand (read+write) MSHR misses 2077system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 272 # number of demand (read+write) MSHR misses 2078system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13250 # number of demand (read+write) MSHR misses 2079system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102773 # number of demand (read+write) MSHR misses 2080system.cpu1.l2cache.demand_mshr_misses::total 116613 # number of demand (read+write) MSHR misses 2081system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 318 # number of overall MSHR misses 2082system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 272 # number of overall MSHR misses 2083system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13250 # number of overall MSHR misses 2084system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102773 # number of overall MSHR misses 2085system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of overall MSHR misses 2086system.cpu1.l2cache.overall_mshr_misses::total 141592 # number of overall MSHR misses 2087system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2088system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable 2089system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3272 # number of ReadReq MSHR uncacheable 2090system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable 2091system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable 2092system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2093system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses 2094system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5722 # number of overall MSHR uncacheable misses 2095system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of ReadReq MSHR miss cycles 2096system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3925000 # number of ReadReq MSHR miss cycles 2097system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8490000 # number of ReadReq MSHR miss cycles 2098system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of HardPFReq MSHR miss cycles 2099system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 780424807 # number of HardPFReq MSHR miss cycles 2100system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 494079500 # number of UpgradeReq MSHR miss cycles 2101system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 494079500 # number of UpgradeReq MSHR miss cycles 2102system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 371536000 # number of SCUpgradeReq MSHR miss cycles 2103system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 371536000 # number of SCUpgradeReq MSHR miss cycles 2104system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2914500 # number of SCUpgradeFailReq MSHR miss cycles 2105system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2914500 # number of SCUpgradeFailReq MSHR miss cycles 2106system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1118604500 # number of ReadExReq MSHR miss cycles 2107system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1118604500 # number of ReadExReq MSHR miss cycles 2108system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 454076500 # number of ReadCleanReq MSHR miss cycles 2109system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 454076500 # number of ReadCleanReq MSHR miss cycles 2110system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1104528500 # number of ReadSharedReq MSHR miss cycles 2111system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1104528500 # number of ReadSharedReq MSHR miss cycles 2112system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of demand (read+write) MSHR miss cycles 2113system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3925000 # number of demand (read+write) MSHR miss cycles 2114system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454076500 # number of demand (read+write) MSHR miss cycles 2115system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2223133000 # number of demand (read+write) MSHR miss cycles 2116system.cpu1.l2cache.demand_mshr_miss_latency::total 2685699500 # number of demand (read+write) MSHR miss cycles 2117system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of overall MSHR miss cycles 2118system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3925000 # number of overall MSHR miss cycles 2119system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454076500 # number of overall MSHR miss cycles 2120system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2223133000 # number of overall MSHR miss cycles 2121system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of overall MSHR miss cycles 2122system.cpu1.l2cache.overall_mshr_miss_latency::total 3466124307 # number of overall MSHR miss cycles 2123system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14449000 # number of ReadReq MSHR uncacheable cycles 2124system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418310000 # number of ReadReq MSHR uncacheable cycles 2125system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432759000 # number of ReadReq MSHR uncacheable cycles 2126system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14449000 # number of overall MSHR uncacheable cycles 2127system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418310000 # number of overall MSHR uncacheable cycles 2128system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432759000 # number of overall MSHR uncacheable cycles 2129system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for ReadReq accesses 2130system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for ReadReq accesses 2131system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.092753 # mshr miss rate for ReadReq accesses 2132system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2133system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2134system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2135system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2136system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2137system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2138system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2139system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2140system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559981 # mshr miss rate for ReadExReq accesses 2141system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559981 # mshr miss rate for ReadExReq accesses 2142system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for ReadCleanReq accesses 2143system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadCleanReq accesses 2144system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.405101 # mshr miss rate for ReadSharedReq accesses 2145system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405101 # mshr miss rate for ReadSharedReq accesses 2146system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for demand accesses 2147system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for demand accesses 2148system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for demand accesses 2149system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for demand accesses 2150system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157091 # mshr miss rate for demand accesses 2151system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for overall accesses 2152system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for overall accesses 2153system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for overall accesses 2154system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for overall accesses 2155system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2156system.cpu1.l2cache.overall_mshr_miss_rate::total 0.190741 # mshr miss rate for overall accesses 2157system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average ReadReq mshr miss latency 2158system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average ReadReq mshr miss latency 2159system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14389.830508 # average ReadReq mshr miss latency 2160system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average HardPFReq mshr miss latency 2161system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31243.236599 # average HardPFReq mshr miss latency 2162system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16651.371664 # average UpgradeReq mshr miss latency 2163system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16651.371664 # average UpgradeReq mshr miss latency 2164system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15925.246464 # average SCUpgradeReq mshr miss latency 2165system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15925.246464 # average SCUpgradeReq mshr miss latency 2166system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 728625 # average SCUpgradeFailReq mshr miss latency 2167system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 728625 # average SCUpgradeFailReq mshr miss latency 2168system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32213.232541 # average ReadExReq mshr miss latency 2169system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32213.232541 # average ReadExReq mshr miss latency 2170system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average ReadCleanReq mshr miss latency 2171system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34269.924528 # average ReadCleanReq mshr miss latency 2172system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16231.608570 # average ReadSharedReq mshr miss latency 2173system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16231.608570 # average ReadSharedReq mshr miss latency 2174system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency 2175system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency 2176system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency 2177system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency 2178system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23030.875631 # average overall mshr miss latency 2179system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency 2180system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency 2181system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency 2182system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency 2183system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average overall mshr miss latency 2184system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24479.662036 # average overall mshr miss latency 2185system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency 2186system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135156.704362 # average ReadReq mshr uncacheable latency 2187system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132261.308068 # average ReadReq mshr uncacheable latency 2188system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency 2189system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75439.134355 # average overall mshr uncacheable latency 2190system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75630.723523 # average overall mshr uncacheable latency 2191system.cpu1.toL2Bus.snoop_filter.tot_requests 1487204 # Total number of requests made to the snoop filter. 2192system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751274 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2193system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2194system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter. 2195system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2196system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2197system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2198system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution 2199system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution 2200system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution 2201system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution 2202system.cpu1.toL2Bus.trans_dist::WritebackDirty 147816 # Transaction distribution 2203system.cpu1.toL2Bus.trans_dist::WritebackClean 578146 # Transaction distribution 2204system.cpu1.toL2Bus.trans_dist::CleanEvict 101473 # Transaction distribution 2205system.cpu1.toL2Bus.trans_dist::HardPFReq 30088 # Transaction distribution 2206system.cpu1.toL2Bus.trans_dist::UpgradeReq 71412 # Transaction distribution 2207system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41204 # Transaction distribution 2208system.cpu1.toL2Bus.trans_dist::UpgradeResp 85825 # Transaction distribution 2209system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 2210system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution 2211system.cpu1.toL2Bus.trans_dist::ReadExReq 69105 # Transaction distribution 2212system.cpu1.toL2Bus.trans_dist::ReadExResp 66696 # Transaction distribution 2213system.cpu1.toL2Bus.trans_dist::ReadCleanReq 505976 # Transaction distribution 2214system.cpu1.toL2Bus.trans_dist::ReadSharedReq 245752 # Transaction distribution 2215system.cpu1.toL2Bus.trans_dist::InvalidateReq 247 # Transaction distribution 2216system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1517770 # Packet count per connected master and slave (bytes) 2217system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838774 # Packet count per connected master and slave (bytes) 2218system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5606 # Packet count per connected master and slave (bytes) 2219system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10127 # Packet count per connected master and slave (bytes) 2220system.cpu1.toL2Bus.pkt_count::total 2372277 # Packet count per connected master and slave (bytes) 2221system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64732868 # Cumulative packet size per connected master and slave (bytes) 2222system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29385740 # Cumulative packet size per connected master and slave (bytes) 2223system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9128 # Cumulative packet size per connected master and slave (bytes) 2224system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16316 # Cumulative packet size per connected master and slave (bytes) 2225system.cpu1.toL2Bus.pkt_size::total 94144052 # Cumulative packet size per connected master and slave (bytes) 2226system.cpu1.toL2Bus.snoops 388756 # Total snoops (count) 2227system.cpu1.toL2Bus.snoop_fanout::samples 1114505 # Request fanout histogram 2228system.cpu1.toL2Bus.snoop_fanout::mean 0.179300 # Request fanout histogram 2229system.cpu1.toL2Bus.snoop_fanout::stdev 0.390891 # Request fanout histogram 2230system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2231system.cpu1.toL2Bus.snoop_fanout::0 917819 82.35% 82.35% # Request fanout histogram 2232system.cpu1.toL2Bus.snoop_fanout::1 193541 17.37% 99.72% # Request fanout histogram 2233system.cpu1.toL2Bus.snoop_fanout::2 3145 0.28% 100.00% # Request fanout histogram 2234system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2235system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2236system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2237system.cpu1.toL2Bus.snoop_fanout::total 1114505 # Request fanout histogram 2238system.cpu1.toL2Bus.reqLayer0.occupancy 1441037000 # Layer occupancy (ticks) 2239system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2240system.cpu1.toL2Bus.snoopLayer0.occupancy 80111937 # Layer occupancy (ticks) 2241system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2242system.cpu1.toL2Bus.respLayer0.occupancy 759141000 # Layer occupancy (ticks) 2243system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2244system.cpu1.toL2Bus.respLayer1.occupancy 375865500 # Layer occupancy (ticks) 2245system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2246system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2247system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2248system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks) 2249system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2250system.iobus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2251system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2252system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2253system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2254system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2255system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2256system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2257system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2258system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2259system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2260system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2261system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2262system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2263system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2264system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2265system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2266system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2267system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2268system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2269system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2270system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2271system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2272system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2273system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2274system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2275system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2276system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2277system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) 2278system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2279system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2280system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2281system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2282system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2283system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2284system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2285system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2286system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2287system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2288system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2289system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2290system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2291system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2292system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2293system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2294system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2295system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2296system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2297system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2298system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2299system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2300system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) 2301system.iobus.reqLayer0.occupancy 48726000 # Layer occupancy (ticks) 2302system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2303system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) 2304system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2305system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks) 2306system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2307system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) 2308system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2309system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) 2310system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2311system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) 2312system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2313system.iobus.reqLayer8.occupancy 601500 # Layer occupancy (ticks) 2314system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2315system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) 2316system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2317system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) 2318system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2319system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2320system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2321system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2322system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2323system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks) 2324system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2325system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 2326system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2327system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) 2328system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2329system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2330system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2331system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2332system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2333system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) 2334system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2335system.iobus.reqLayer23.occupancy 6164000 # Layer occupancy (ticks) 2336system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2337system.iobus.reqLayer24.occupancy 32044500 # Layer occupancy (ticks) 2338system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2339system.iobus.reqLayer25.occupancy 187734328 # Layer occupancy (ticks) 2340system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2341system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2342system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2343system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2344system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2345system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2346system.iocache.tags.replacements 36445 # number of replacements 2347system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use 2348system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2349system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2350system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2351system.iocache.tags.warmup_cycle 289174340000 # Cycle when the warmup percentage was hit. 2352system.iocache.tags.occ_blocks::realview.ide 14.386648 # Average occupied blocks per requestor 2353system.iocache.tags.occ_percent::realview.ide 0.899166 # Average percentage of cache occupancy 2354system.iocache.tags.occ_percent::total 0.899166 # Average percentage of cache occupancy 2355system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2356system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2357system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2358system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2359system.iocache.tags.data_accesses 328311 # Number of data accesses 2360system.iocache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2361system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2362system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2363system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2364system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2365system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses 2366system.iocache.demand_misses::total 36479 # number of demand (read+write) misses 2367system.iocache.overall_misses::realview.ide 36479 # number of overall misses 2368system.iocache.overall_misses::total 36479 # number of overall misses 2369system.iocache.ReadReq_miss_latency::realview.ide 36421877 # number of ReadReq miss cycles 2370system.iocache.ReadReq_miss_latency::total 36421877 # number of ReadReq miss cycles 2371system.iocache.WriteLineReq_miss_latency::realview.ide 4307524451 # number of WriteLineReq miss cycles 2372system.iocache.WriteLineReq_miss_latency::total 4307524451 # number of WriteLineReq miss cycles 2373system.iocache.demand_miss_latency::realview.ide 4343946328 # number of demand (read+write) miss cycles 2374system.iocache.demand_miss_latency::total 4343946328 # number of demand (read+write) miss cycles 2375system.iocache.overall_miss_latency::realview.ide 4343946328 # number of overall miss cycles 2376system.iocache.overall_miss_latency::total 4343946328 # number of overall miss cycles 2377system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2378system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2379system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2380system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2381system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses 2382system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses 2383system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses 2384system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses 2385system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2386system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2387system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2388system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2389system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2390system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2391system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2392system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2393system.iocache.ReadReq_avg_miss_latency::realview.ide 142830.890196 # average ReadReq miss latency 2394system.iocache.ReadReq_avg_miss_latency::total 142830.890196 # average ReadReq miss latency 2395system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118913.550436 # average WriteLineReq miss latency 2396system.iocache.WriteLineReq_avg_miss_latency::total 118913.550436 # average WriteLineReq miss latency 2397system.iocache.demand_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency 2398system.iocache.demand_avg_miss_latency::total 119080.740371 # average overall miss latency 2399system.iocache.overall_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency 2400system.iocache.overall_avg_miss_latency::total 119080.740371 # average overall miss latency 2401system.iocache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked 2402system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2403system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked 2404system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2405system.iocache.avg_blocked_cycles::no_mshrs 3.142857 # average number of cycles each access was blocked 2406system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2407system.iocache.writebacks::writebacks 36190 # number of writebacks 2408system.iocache.writebacks::total 36190 # number of writebacks 2409system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2410system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2411system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2412system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2413system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses 2414system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses 2415system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses 2416system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses 2417system.iocache.ReadReq_mshr_miss_latency::realview.ide 23671877 # number of ReadReq MSHR miss cycles 2418system.iocache.ReadReq_mshr_miss_latency::total 23671877 # number of ReadReq MSHR miss cycles 2419system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493982137 # number of WriteLineReq MSHR miss cycles 2420system.iocache.WriteLineReq_mshr_miss_latency::total 2493982137 # number of WriteLineReq MSHR miss cycles 2421system.iocache.demand_mshr_miss_latency::realview.ide 2517654014 # number of demand (read+write) MSHR miss cycles 2422system.iocache.demand_mshr_miss_latency::total 2517654014 # number of demand (read+write) MSHR miss cycles 2423system.iocache.overall_mshr_miss_latency::realview.ide 2517654014 # number of overall MSHR miss cycles 2424system.iocache.overall_mshr_miss_latency::total 2517654014 # number of overall MSHR miss cycles 2425system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2427system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2428system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2429system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2431system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2433system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 92830.890196 # average ReadReq mshr miss latency 2434system.iocache.ReadReq_avg_mshr_miss_latency::total 92830.890196 # average ReadReq mshr miss latency 2435system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68848.888499 # average WriteLineReq mshr miss latency 2436system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68848.888499 # average WriteLineReq mshr miss latency 2437system.iocache.demand_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency 2438system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency 2439system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency 2440system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency 2441system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2442system.l2c.tags.replacements 126308 # number of replacements 2443system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use 2444system.l2c.tags.total_refs 424315 # Total number of references to valid blocks. 2445system.l2c.tags.sampled_refs 190178 # Sample count of references to valid blocks. 2446system.l2c.tags.avg_refs 2.231147 # Average number of references to valid blocks. 2447system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2448system.l2c.tags.occ_blocks::writebacks 13637.426679 # Average occupied blocks per requestor 2449system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.018602 # Average occupied blocks per requestor 2450system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043991 # Average occupied blocks per requestor 2451system.l2c.tags.occ_blocks::cpu0.inst 7319.345128 # Average occupied blocks per requestor 2452system.l2c.tags.occ_blocks::cpu0.data 2841.087210 # Average occupied blocks per requestor 2453system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35552.012227 # Average occupied blocks per requestor 2454system.l2c.tags.occ_blocks::cpu1.inst 1437.607406 # Average occupied blocks per requestor 2455system.l2c.tags.occ_blocks::cpu1.data 447.669169 # Average occupied blocks per requestor 2456system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1777.834065 # Average occupied blocks per requestor 2457system.l2c.tags.occ_percent::writebacks 0.208091 # Average percentage of cache occupancy 2458system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy 2459system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2460system.l2c.tags.occ_percent::cpu0.inst 0.111684 # Average percentage of cache occupancy 2461system.l2c.tags.occ_percent::cpu0.data 0.043352 # Average percentage of cache occupancy 2462system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.542481 # Average percentage of cache occupancy 2463system.l2c.tags.occ_percent::cpu1.inst 0.021936 # Average percentage of cache occupancy 2464system.l2c.tags.occ_percent::cpu1.data 0.006831 # Average percentage of cache occupancy 2465system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027128 # Average percentage of cache occupancy 2466system.l2c.tags.occ_percent::total 0.961564 # Average percentage of cache occupancy 2467system.l2c.tags.occ_task_id_blocks::1022 30519 # Occupied blocks per task id 2468system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 2469system.l2c.tags.occ_task_id_blocks::1024 33346 # Occupied blocks per task id 2470system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 2471system.l2c.tags.age_task_id_blocks_1022::2 165 # Occupied blocks per task id 2472system.l2c.tags.age_task_id_blocks_1022::3 4688 # Occupied blocks per task id 2473system.l2c.tags.age_task_id_blocks_1022::4 25665 # Occupied blocks per task id 2474system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 2475system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2476system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 2477system.l2c.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id 2478system.l2c.tags.age_task_id_blocks_1024::3 2267 # Occupied blocks per task id 2479system.l2c.tags.age_task_id_blocks_1024::4 30712 # Occupied blocks per task id 2480system.l2c.tags.occ_task_id_percent::1022 0.465683 # Percentage of cache occupancy per task id 2481system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2482system.l2c.tags.occ_task_id_percent::1024 0.508820 # Percentage of cache occupancy per task id 2483system.l2c.tags.tag_accesses 5890164 # Number of tag accesses 2484system.l2c.tags.data_accesses 5890164 # Number of data accesses 2485system.l2c.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2486system.l2c.WritebackDirty_hits::writebacks 260994 # number of WritebackDirty hits 2487system.l2c.WritebackDirty_hits::total 260994 # number of WritebackDirty hits 2488system.l2c.UpgradeReq_hits::cpu0.data 31980 # number of UpgradeReq hits 2489system.l2c.UpgradeReq_hits::cpu1.data 2487 # number of UpgradeReq hits 2490system.l2c.UpgradeReq_hits::total 34467 # number of UpgradeReq hits 2491system.l2c.SCUpgradeReq_hits::cpu0.data 1985 # number of SCUpgradeReq hits 2492system.l2c.SCUpgradeReq_hits::cpu1.data 965 # number of SCUpgradeReq hits 2493system.l2c.SCUpgradeReq_hits::total 2950 # number of SCUpgradeReq hits 2494system.l2c.ReadExReq_hits::cpu0.data 3870 # number of ReadExReq hits 2495system.l2c.ReadExReq_hits::cpu1.data 1490 # number of ReadExReq hits 2496system.l2c.ReadExReq_hits::total 5360 # number of ReadExReq hits 2497system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 97 # number of ReadSharedReq hits 2498system.l2c.ReadSharedReq_hits::cpu0.itb.walker 76 # number of ReadSharedReq hits 2499system.l2c.ReadSharedReq_hits::cpu0.inst 27673 # number of ReadSharedReq hits 2500system.l2c.ReadSharedReq_hits::cpu0.data 45621 # number of ReadSharedReq hits 2501system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45892 # number of ReadSharedReq hits 2502system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 31 # number of ReadSharedReq hits 2503system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits 2504system.l2c.ReadSharedReq_hits::cpu1.inst 10962 # number of ReadSharedReq hits 2505system.l2c.ReadSharedReq_hits::cpu1.data 9208 # number of ReadSharedReq hits 2506system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5411 # number of ReadSharedReq hits 2507system.l2c.ReadSharedReq_hits::total 145008 # number of ReadSharedReq hits 2508system.l2c.demand_hits::cpu0.dtb.walker 97 # number of demand (read+write) hits 2509system.l2c.demand_hits::cpu0.itb.walker 76 # number of demand (read+write) hits 2510system.l2c.demand_hits::cpu0.inst 27673 # number of demand (read+write) hits 2511system.l2c.demand_hits::cpu0.data 49491 # number of demand (read+write) hits 2512system.l2c.demand_hits::cpu0.l2cache.prefetcher 45892 # number of demand (read+write) hits 2513system.l2c.demand_hits::cpu1.dtb.walker 31 # number of demand (read+write) hits 2514system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits 2515system.l2c.demand_hits::cpu1.inst 10962 # number of demand (read+write) hits 2516system.l2c.demand_hits::cpu1.data 10698 # number of demand (read+write) hits 2517system.l2c.demand_hits::cpu1.l2cache.prefetcher 5411 # number of demand (read+write) hits 2518system.l2c.demand_hits::total 150368 # number of demand (read+write) hits 2519system.l2c.overall_hits::cpu0.dtb.walker 97 # number of overall hits 2520system.l2c.overall_hits::cpu0.itb.walker 76 # number of overall hits 2521system.l2c.overall_hits::cpu0.inst 27673 # number of overall hits 2522system.l2c.overall_hits::cpu0.data 49491 # number of overall hits 2523system.l2c.overall_hits::cpu0.l2cache.prefetcher 45892 # number of overall hits 2524system.l2c.overall_hits::cpu1.dtb.walker 31 # number of overall hits 2525system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits 2526system.l2c.overall_hits::cpu1.inst 10962 # number of overall hits 2527system.l2c.overall_hits::cpu1.data 10698 # number of overall hits 2528system.l2c.overall_hits::cpu1.l2cache.prefetcher 5411 # number of overall hits 2529system.l2c.overall_hits::total 150368 # number of overall hits 2530system.l2c.UpgradeReq_misses::cpu0.data 8680 # number of UpgradeReq misses 2531system.l2c.UpgradeReq_misses::cpu1.data 2870 # number of UpgradeReq misses 2532system.l2c.UpgradeReq_misses::total 11550 # number of UpgradeReq misses 2533system.l2c.SCUpgradeReq_misses::cpu0.data 542 # number of SCUpgradeReq misses 2534system.l2c.SCUpgradeReq_misses::cpu1.data 1323 # number of SCUpgradeReq misses 2535system.l2c.SCUpgradeReq_misses::total 1865 # number of SCUpgradeReq misses 2536system.l2c.ReadExReq_misses::cpu0.data 11368 # number of ReadExReq misses 2537system.l2c.ReadExReq_misses::cpu1.data 8031 # number of ReadExReq misses 2538system.l2c.ReadExReq_misses::total 19399 # number of ReadExReq misses 2539system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 2540system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2541system.l2c.ReadSharedReq_misses::cpu0.inst 17607 # number of ReadSharedReq misses 2542system.l2c.ReadSharedReq_misses::cpu0.data 8862 # number of ReadSharedReq misses 2543system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq misses 2544system.l2c.ReadSharedReq_misses::cpu1.inst 2288 # number of ReadSharedReq misses 2545system.l2c.ReadSharedReq_misses::cpu1.data 856 # number of ReadSharedReq misses 2546system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq misses 2547system.l2c.ReadSharedReq_misses::total 169532 # number of ReadSharedReq misses 2548system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 2549system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2550system.l2c.demand_misses::cpu0.inst 17607 # number of demand (read+write) misses 2551system.l2c.demand_misses::cpu0.data 20230 # number of demand (read+write) misses 2552system.l2c.demand_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) misses 2553system.l2c.demand_misses::cpu1.inst 2288 # number of demand (read+write) misses 2554system.l2c.demand_misses::cpu1.data 8887 # number of demand (read+write) misses 2555system.l2c.demand_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) misses 2556system.l2c.demand_misses::total 188931 # number of demand (read+write) misses 2557system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 2558system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2559system.l2c.overall_misses::cpu0.inst 17607 # number of overall misses 2560system.l2c.overall_misses::cpu0.data 20230 # number of overall misses 2561system.l2c.overall_misses::cpu0.l2cache.prefetcher 133884 # number of overall misses 2562system.l2c.overall_misses::cpu1.inst 2288 # number of overall misses 2563system.l2c.overall_misses::cpu1.data 8887 # number of overall misses 2564system.l2c.overall_misses::cpu1.l2cache.prefetcher 6026 # number of overall misses 2565system.l2c.overall_misses::total 188931 # number of overall misses 2566system.l2c.UpgradeReq_miss_latency::cpu0.data 11274000 # number of UpgradeReq miss cycles 2567system.l2c.UpgradeReq_miss_latency::cpu1.data 4127500 # number of UpgradeReq miss cycles 2568system.l2c.UpgradeReq_miss_latency::total 15401500 # number of UpgradeReq miss cycles 2569system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1640500 # number of SCUpgradeReq miss cycles 2570system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1015500 # number of SCUpgradeReq miss cycles 2571system.l2c.SCUpgradeReq_miss_latency::total 2656000 # number of SCUpgradeReq miss cycles 2572system.l2c.ReadExReq_miss_latency::cpu0.data 1087660500 # number of ReadExReq miss cycles 2573system.l2c.ReadExReq_miss_latency::cpu1.data 661855000 # number of ReadExReq miss cycles 2574system.l2c.ReadExReq_miss_latency::total 1749515500 # number of ReadExReq miss cycles 2575system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles 2576system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles 2577system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles 2578system.l2c.ReadSharedReq_miss_latency::cpu0.data 776891500 # number of ReadSharedReq miss cycles 2579system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of ReadSharedReq miss cycles 2580system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles 2581system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles 2582system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles 2583system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles 2584system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles 2585system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles 2586system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles 2587system.l2c.demand_miss_latency::cpu0.data 1864552000 # number of demand (read+write) miss cycles 2588system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of demand (read+write) miss cycles 2589system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles 2590system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles 2591system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles 2592system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles 2593system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles 2594system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles 2595system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles 2596system.l2c.overall_miss_latency::cpu0.data 1864552000 # number of overall miss cycles 2597system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of overall miss cycles 2598system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles 2599system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles 2600system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles 2601system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles 2602system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses) 2603system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses) 2604system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses) 2605system.l2c.UpgradeReq_accesses::cpu1.data 5357 # number of UpgradeReq accesses(hits+misses) 2606system.l2c.UpgradeReq_accesses::total 46017 # number of UpgradeReq accesses(hits+misses) 2607system.l2c.SCUpgradeReq_accesses::cpu0.data 2527 # number of SCUpgradeReq accesses(hits+misses) 2608system.l2c.SCUpgradeReq_accesses::cpu1.data 2288 # number of SCUpgradeReq accesses(hits+misses) 2609system.l2c.SCUpgradeReq_accesses::total 4815 # number of SCUpgradeReq accesses(hits+misses) 2610system.l2c.ReadExReq_accesses::cpu0.data 15238 # number of ReadExReq accesses(hits+misses) 2611system.l2c.ReadExReq_accesses::cpu1.data 9521 # number of ReadExReq accesses(hits+misses) 2612system.l2c.ReadExReq_accesses::total 24759 # number of ReadExReq accesses(hits+misses) 2613system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 104 # number of ReadSharedReq accesses(hits+misses) 2614system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses) 2615system.l2c.ReadSharedReq_accesses::cpu0.inst 45280 # number of ReadSharedReq accesses(hits+misses) 2616system.l2c.ReadSharedReq_accesses::cpu0.data 54483 # number of ReadSharedReq accesses(hits+misses) 2617system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179776 # number of ReadSharedReq accesses(hits+misses) 2618system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 31 # number of ReadSharedReq accesses(hits+misses) 2619system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 37 # number of ReadSharedReq accesses(hits+misses) 2620system.l2c.ReadSharedReq_accesses::cpu1.inst 13250 # number of ReadSharedReq accesses(hits+misses) 2621system.l2c.ReadSharedReq_accesses::cpu1.data 10064 # number of ReadSharedReq accesses(hits+misses) 2622system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11437 # number of ReadSharedReq accesses(hits+misses) 2623system.l2c.ReadSharedReq_accesses::total 314540 # number of ReadSharedReq accesses(hits+misses) 2624system.l2c.demand_accesses::cpu0.dtb.walker 104 # number of demand (read+write) accesses 2625system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses 2626system.l2c.demand_accesses::cpu0.inst 45280 # number of demand (read+write) accesses 2627system.l2c.demand_accesses::cpu0.data 69721 # number of demand (read+write) accesses 2628system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179776 # number of demand (read+write) accesses 2629system.l2c.demand_accesses::cpu1.dtb.walker 31 # number of demand (read+write) accesses 2630system.l2c.demand_accesses::cpu1.itb.walker 37 # number of demand (read+write) accesses 2631system.l2c.demand_accesses::cpu1.inst 13250 # number of demand (read+write) accesses 2632system.l2c.demand_accesses::cpu1.data 19585 # number of demand (read+write) accesses 2633system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11437 # number of demand (read+write) accesses 2634system.l2c.demand_accesses::total 339299 # number of demand (read+write) accesses 2635system.l2c.overall_accesses::cpu0.dtb.walker 104 # number of overall (read+write) accesses 2636system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses 2637system.l2c.overall_accesses::cpu0.inst 45280 # number of overall (read+write) accesses 2638system.l2c.overall_accesses::cpu0.data 69721 # number of overall (read+write) accesses 2639system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179776 # number of overall (read+write) accesses 2640system.l2c.overall_accesses::cpu1.dtb.walker 31 # number of overall (read+write) accesses 2641system.l2c.overall_accesses::cpu1.itb.walker 37 # number of overall (read+write) accesses 2642system.l2c.overall_accesses::cpu1.inst 13250 # number of overall (read+write) accesses 2643system.l2c.overall_accesses::cpu1.data 19585 # number of overall (read+write) accesses 2644system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11437 # number of overall (read+write) accesses 2645system.l2c.overall_accesses::total 339299 # number of overall (read+write) accesses 2646system.l2c.UpgradeReq_miss_rate::cpu0.data 0.213478 # miss rate for UpgradeReq accesses 2647system.l2c.UpgradeReq_miss_rate::cpu1.data 0.535748 # miss rate for UpgradeReq accesses 2648system.l2c.UpgradeReq_miss_rate::total 0.250994 # miss rate for UpgradeReq accesses 2649system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.214484 # miss rate for SCUpgradeReq accesses 2650system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.578234 # miss rate for SCUpgradeReq accesses 2651system.l2c.SCUpgradeReq_miss_rate::total 0.387331 # miss rate for SCUpgradeReq accesses 2652system.l2c.ReadExReq_miss_rate::cpu0.data 0.746030 # miss rate for ReadExReq accesses 2653system.l2c.ReadExReq_miss_rate::cpu1.data 0.843504 # miss rate for ReadExReq accesses 2654system.l2c.ReadExReq_miss_rate::total 0.783513 # miss rate for ReadExReq accesses 2655system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for ReadSharedReq accesses 2656system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025641 # miss rate for ReadSharedReq accesses 2657system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.388847 # miss rate for ReadSharedReq accesses 2658system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162656 # miss rate for ReadSharedReq accesses 2659system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for ReadSharedReq accesses 2660system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.172679 # miss rate for ReadSharedReq accesses 2661system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.085056 # miss rate for ReadSharedReq accesses 2662system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for ReadSharedReq accesses 2663system.l2c.ReadSharedReq_miss_rate::total 0.538984 # miss rate for ReadSharedReq accesses 2664system.l2c.demand_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for demand accesses 2665system.l2c.demand_miss_rate::cpu0.itb.walker 0.025641 # miss rate for demand accesses 2666system.l2c.demand_miss_rate::cpu0.inst 0.388847 # miss rate for demand accesses 2667system.l2c.demand_miss_rate::cpu0.data 0.290156 # miss rate for demand accesses 2668system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for demand accesses 2669system.l2c.demand_miss_rate::cpu1.inst 0.172679 # miss rate for demand accesses 2670system.l2c.demand_miss_rate::cpu1.data 0.453766 # miss rate for demand accesses 2671system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for demand accesses 2672system.l2c.demand_miss_rate::total 0.556827 # miss rate for demand accesses 2673system.l2c.overall_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for overall accesses 2674system.l2c.overall_miss_rate::cpu0.itb.walker 0.025641 # miss rate for overall accesses 2675system.l2c.overall_miss_rate::cpu0.inst 0.388847 # miss rate for overall accesses 2676system.l2c.overall_miss_rate::cpu0.data 0.290156 # miss rate for overall accesses 2677system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for overall accesses 2678system.l2c.overall_miss_rate::cpu1.inst 0.172679 # miss rate for overall accesses 2679system.l2c.overall_miss_rate::cpu1.data 0.453766 # miss rate for overall accesses 2680system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for overall accesses 2681system.l2c.overall_miss_rate::total 0.556827 # miss rate for overall accesses 2682system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1298.847926 # average UpgradeReq miss latency 2683system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1438.153310 # average UpgradeReq miss latency 2684system.l2c.UpgradeReq_avg_miss_latency::total 1333.463203 # average UpgradeReq miss latency 2685system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3026.752768 # average SCUpgradeReq miss latency 2686system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 767.573696 # average SCUpgradeReq miss latency 2687system.l2c.SCUpgradeReq_avg_miss_latency::total 1424.128686 # average SCUpgradeReq miss latency 2688system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95677.383885 # average ReadExReq miss latency 2689system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82412.526460 # average ReadExReq miss latency 2690system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 # average ReadExReq miss latency 2691system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency 2692system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency 2693system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency 2694system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency 2695system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency 2696system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency 2697system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency 2698system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency 2699system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency 2700system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency 2701system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency 2702system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency 2703system.l2c.demand_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency 2704system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency 2705system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency 2706system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency 2707system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency 2708system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency 2709system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency 2710system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency 2711system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency 2712system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency 2713system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency 2714system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency 2715system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency 2716system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency 2717system.l2c.overall_avg_miss_latency::total 94581.324341 # average overall miss latency 2718system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2719system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2720system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2721system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2722system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2723system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2724system.l2c.writebacks::writebacks 98955 # number of writebacks 2725system.l2c.writebacks::total 98955 # number of writebacks 2726system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits 2727system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits 2728system.l2c.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 2729system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 2730system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits 2731system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 2732system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 2733system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits 2734system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits 2735system.l2c.CleanEvict_mshr_misses::writebacks 3251 # number of CleanEvict MSHR misses 2736system.l2c.CleanEvict_mshr_misses::total 3251 # number of CleanEvict MSHR misses 2737system.l2c.UpgradeReq_mshr_misses::cpu0.data 8680 # number of UpgradeReq MSHR misses 2738system.l2c.UpgradeReq_mshr_misses::cpu1.data 2870 # number of UpgradeReq MSHR misses 2739system.l2c.UpgradeReq_mshr_misses::total 11550 # number of UpgradeReq MSHR misses 2740system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 542 # number of SCUpgradeReq MSHR misses 2741system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1323 # number of SCUpgradeReq MSHR misses 2742system.l2c.SCUpgradeReq_mshr_misses::total 1865 # number of SCUpgradeReq MSHR misses 2743system.l2c.ReadExReq_mshr_misses::cpu0.data 11368 # number of ReadExReq MSHR misses 2744system.l2c.ReadExReq_mshr_misses::cpu1.data 8031 # number of ReadExReq MSHR misses 2745system.l2c.ReadExReq_mshr_misses::total 19399 # number of ReadExReq MSHR misses 2746system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses 2747system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2748system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17603 # number of ReadSharedReq MSHR misses 2749system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8862 # number of ReadSharedReq MSHR misses 2750system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq MSHR misses 2751system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2278 # number of ReadSharedReq MSHR misses 2752system.l2c.ReadSharedReq_mshr_misses::cpu1.data 856 # number of ReadSharedReq MSHR misses 2753system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq MSHR misses 2754system.l2c.ReadSharedReq_mshr_misses::total 169518 # number of ReadSharedReq MSHR misses 2755system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses 2756system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2757system.l2c.demand_mshr_misses::cpu0.inst 17603 # number of demand (read+write) MSHR misses 2758system.l2c.demand_mshr_misses::cpu0.data 20230 # number of demand (read+write) MSHR misses 2759system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) MSHR misses 2760system.l2c.demand_mshr_misses::cpu1.inst 2278 # number of demand (read+write) MSHR misses 2761system.l2c.demand_mshr_misses::cpu1.data 8887 # number of demand (read+write) MSHR misses 2762system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) MSHR misses 2763system.l2c.demand_mshr_misses::total 188917 # number of demand (read+write) MSHR misses 2764system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses 2765system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2766system.l2c.overall_mshr_misses::cpu0.inst 17603 # number of overall MSHR misses 2767system.l2c.overall_mshr_misses::cpu0.data 20230 # number of overall MSHR misses 2768system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of overall MSHR misses 2769system.l2c.overall_mshr_misses::cpu1.inst 2278 # number of overall MSHR misses 2770system.l2c.overall_mshr_misses::cpu1.data 8887 # number of overall MSHR misses 2771system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of overall MSHR misses 2772system.l2c.overall_mshr_misses::total 188917 # number of overall MSHR misses 2773system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 2774system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable 2775system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2776system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3092 # number of ReadReq MSHR uncacheable 2777system.l2c.ReadReq_mshr_uncacheable::total 44083 # number of ReadReq MSHR uncacheable 2778system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 2779system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable 2780system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable 2781system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 2782system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 2783system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2784system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5542 # number of overall MSHR uncacheable misses 2785system.l2c.overall_mshr_uncacheable_misses::total 74996 # number of overall MSHR uncacheable misses 2786system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 208012000 # number of UpgradeReq MSHR miss cycles 2787system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 65421000 # number of UpgradeReq MSHR miss cycles 2788system.l2c.UpgradeReq_mshr_miss_latency::total 273433000 # number of UpgradeReq MSHR miss cycles 2789system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 13993000 # number of SCUpgradeReq MSHR miss cycles 2790system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32976000 # number of SCUpgradeReq MSHR miss cycles 2791system.l2c.SCUpgradeReq_mshr_miss_latency::total 46969000 # number of SCUpgradeReq MSHR miss cycles 2792system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973980500 # number of ReadExReq MSHR miss cycles 2793system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 581545000 # number of ReadExReq MSHR miss cycles 2794system.l2c.ReadExReq_mshr_miss_latency::total 1555525500 # number of ReadExReq MSHR miss cycles 2795system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 633500 # number of ReadSharedReq MSHR miss cycles 2796system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles 2797system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles 2798system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688271500 # number of ReadSharedReq MSHR miss cycles 2799system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of ReadSharedReq MSHR miss cycles 2800system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 166489000 # number of ReadSharedReq MSHR miss cycles 2801system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68690501 # number of ReadSharedReq MSHR miss cycles 2802system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of ReadSharedReq MSHR miss cycles 2803system.l2c.ReadSharedReq_mshr_miss_latency::total 14423934199 # number of ReadSharedReq MSHR miss cycles 2804system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles 2805system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles 2806system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles 2807system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles 2808system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles 2809system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles 2810system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles 2811system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles 2812system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles 2813system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles 2814system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles 2815system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles 2816system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles 2817system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles 2818system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles 2819system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles 2820system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles 2821system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles 2822system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles 2823system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles 2824system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles 2825system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362609000 # number of ReadReq MSHR uncacheable cycles 2826system.l2c.ReadReq_mshr_uncacheable_latency::total 6757114500 # number of ReadReq MSHR uncacheable cycles 2827system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles 2828system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801887500 # number of overall MSHR uncacheable cycles 2829system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles 2830system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362609000 # number of overall MSHR uncacheable cycles 2831system.l2c.overall_mshr_uncacheable_latency::total 6757114500 # number of overall MSHR uncacheable cycles 2832system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2833system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2834system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.213478 # mshr miss rate for UpgradeReq accesses 2835system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.535748 # mshr miss rate for UpgradeReq accesses 2836system.l2c.UpgradeReq_mshr_miss_rate::total 0.250994 # mshr miss rate for UpgradeReq accesses 2837system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.214484 # mshr miss rate for SCUpgradeReq accesses 2838system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.578234 # mshr miss rate for SCUpgradeReq accesses 2839system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.387331 # mshr miss rate for SCUpgradeReq accesses 2840system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746030 # mshr miss rate for ReadExReq accesses 2841system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.843504 # mshr miss rate for ReadExReq accesses 2842system.l2c.ReadExReq_mshr_miss_rate::total 0.783513 # mshr miss rate for ReadExReq accesses 2843system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for ReadSharedReq accesses 2844system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses 2845system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for ReadSharedReq accesses 2846system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162656 # mshr miss rate for ReadSharedReq accesses 2847system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for ReadSharedReq accesses 2848system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for ReadSharedReq accesses 2849system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.085056 # mshr miss rate for ReadSharedReq accesses 2850system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for ReadSharedReq accesses 2851system.l2c.ReadSharedReq_mshr_miss_rate::total 0.538939 # mshr miss rate for ReadSharedReq accesses 2852system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for demand accesses 2853system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for demand accesses 2854system.l2c.demand_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for demand accesses 2855system.l2c.demand_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for demand accesses 2856system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for demand accesses 2857system.l2c.demand_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for demand accesses 2858system.l2c.demand_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for demand accesses 2859system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for demand accesses 2860system.l2c.demand_mshr_miss_rate::total 0.556786 # mshr miss rate for demand accesses 2861system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for overall accesses 2862system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for overall accesses 2863system.l2c.overall_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for overall accesses 2864system.l2c.overall_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for overall accesses 2865system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for overall accesses 2866system.l2c.overall_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for overall accesses 2867system.l2c.overall_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for overall accesses 2868system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for overall accesses 2869system.l2c.overall_mshr_miss_rate::total 0.556786 # mshr miss rate for overall accesses 2870system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23964.516129 # average UpgradeReq mshr miss latency 2871system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22794.773519 # average UpgradeReq mshr miss latency 2872system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23673.852814 # average UpgradeReq mshr miss latency 2873system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25817.343173 # average SCUpgradeReq mshr miss latency 2874system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24925.170068 # average SCUpgradeReq mshr miss latency 2875system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25184.450402 # average SCUpgradeReq mshr miss latency 2876system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85677.383885 # average ReadExReq mshr miss latency 2877system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72412.526460 # average ReadExReq mshr miss latency 2878system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 # average ReadExReq mshr miss latency 2879system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency 2880system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency 2881system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency 2882system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency 2883system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency 2884system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency 2885system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency 2886system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency 2887system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency 2888system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency 2889system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency 2890system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency 2891system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency 2892system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency 2893system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency 2894system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency 2895system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency 2896system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency 2897system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency 2898system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency 2899system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency 2900system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency 2901system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency 2902system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency 2903system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency 2904system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency 2905system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency 2906system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency 2907system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency 2908system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency 2909system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117273.285899 # average ReadReq mshr uncacheable latency 2910system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153281.639181 # average ReadReq mshr uncacheable latency 2911system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency 2912system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96288.897187 # average overall mshr uncacheable latency 2913system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency 2914system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.267412 # average overall mshr uncacheable latency 2915system.l2c.overall_avg_mshr_uncacheable_latency::total 90099.665315 # average overall mshr uncacheable latency 2916system.membus.snoop_filter.tot_requests 512702 # Total number of requests made to the snoop filter. 2917system.membus.snoop_filter.hit_single_requests 293222 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2918system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2919system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2920system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2921system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2922system.membus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2923system.membus.trans_dist::ReadReq 44083 # Transaction distribution 2924system.membus.trans_dist::ReadResp 213856 # Transaction distribution 2925system.membus.trans_dist::WriteReq 30913 # Transaction distribution 2926system.membus.trans_dist::WriteResp 30913 # Transaction distribution 2927system.membus.trans_dist::WritebackDirty 135145 # Transaction distribution 2928system.membus.trans_dist::CleanEvict 15700 # Transaction distribution 2929system.membus.trans_dist::UpgradeReq 75854 # Transaction distribution 2930system.membus.trans_dist::SCUpgradeReq 40085 # Transaction distribution 2931system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 2932system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2933system.membus.trans_dist::ReadExReq 39863 # Transaction distribution 2934system.membus.trans_dist::ReadExResp 19313 # Transaction distribution 2935system.membus.trans_dist::ReadSharedReq 169773 # Transaction distribution 2936system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2937system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2938system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2939system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes) 2940system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656506 # Packet count per connected master and slave (bytes) 2941system.membus.pkt_count_system.l2c.mem_side::total 778196 # Packet count per connected master and slave (bytes) 2942system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) 2943system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) 2944system.membus.pkt_count::total 851135 # Packet count per connected master and slave (bytes) 2945system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2946system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2947system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes) 2948system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18452748 # Cumulative packet size per connected master and slave (bytes) 2949system.membus.pkt_size_system.l2c.mem_side::total 18643092 # Cumulative packet size per connected master and slave (bytes) 2950system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2951system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2952system.membus.pkt_size::total 20960212 # Cumulative packet size per connected master and slave (bytes) 2953system.membus.snoops 123593 # Total snoops (count) 2954system.membus.snoop_fanout::samples 436796 # Request fanout histogram 2955system.membus.snoop_fanout::mean 0.011900 # Request fanout histogram 2956system.membus.snoop_fanout::stdev 0.108438 # Request fanout histogram 2957system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2958system.membus.snoop_fanout::0 431598 98.81% 98.81% # Request fanout histogram 2959system.membus.snoop_fanout::1 5198 1.19% 100.00% # Request fanout histogram 2960system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2961system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2962system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2963system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2964system.membus.snoop_fanout::total 436796 # Request fanout histogram 2965system.membus.reqLayer0.occupancy 88259500 # Layer occupancy (ticks) 2966system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2967system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2968system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2969system.membus.reqLayer2.occupancy 11350000 # Layer occupancy (ticks) 2970system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2971system.membus.reqLayer5.occupancy 980369236 # Layer occupancy (ticks) 2972system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2973system.membus.respLayer2.occupancy 1108695304 # Layer occupancy (ticks) 2974system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2975system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks) 2976system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2977system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2978system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2979system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2980system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2981system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2982system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2983system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2984system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2985system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2986system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2987system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2988system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2989system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 2990system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2991system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2992system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2993system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2994system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2995system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2996system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2997system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2998system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2999system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3000system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3001system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3002system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3003system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3004system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3005system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3006system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3007system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3008system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3009system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3010system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3011system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3012system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3013system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3014system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3015system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3016system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3017system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3018system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3019system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3020system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3021system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3022system.realview.ethernet.droppedPackets 0 # number of packets dropped 3023system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3024system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3025system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3026system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3027system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3028system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3029system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3030system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3031system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3032system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3033system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3034system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3035system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3036system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3037system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3038system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3039system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3040system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3041system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3042system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3043system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3044system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3045system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3046system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter. 3047system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3048system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3049system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter. 3050system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3051system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3052system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3053system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution 3054system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution 3055system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution 3056system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution 3057system.toL2Bus.trans_dist::WritebackDirty 359949 # Transaction distribution 3058system.toL2Bus.trans_dist::CleanEvict 109182 # Transaction distribution 3059system.toL2Bus.trans_dist::UpgradeReq 110235 # Transaction distribution 3060system.toL2Bus.trans_dist::SCUpgradeReq 43035 # Transaction distribution 3061system.toL2Bus.trans_dist::UpgradeResp 153270 # Transaction distribution 3062system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution 3063system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution 3064system.toL2Bus.trans_dist::ReadExReq 50915 # Transaction distribution 3065system.toL2Bus.trans_dist::ReadExResp 50915 # Transaction distribution 3066system.toL2Bus.trans_dist::ReadSharedReq 433367 # Transaction distribution 3067system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution 3068system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224504 # Packet count per connected master and slave (bytes) 3069system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 296079 # Packet count per connected master and slave (bytes) 3070system.toL2Bus.pkt_count::total 1520583 # Packet count per connected master and slave (bytes) 3071system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33710224 # Cumulative packet size per connected master and slave (bytes) 3072system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4970948 # Cumulative packet size per connected master and slave (bytes) 3073system.toL2Bus.pkt_size::total 38681172 # Cumulative packet size per connected master and slave (bytes) 3074system.toL2Bus.snoops 378680 # Total snoops (count) 3075system.toL2Bus.snoop_fanout::samples 843567 # Request fanout histogram 3076system.toL2Bus.snoop_fanout::mean 0.376795 # Request fanout histogram 3077system.toL2Bus.snoop_fanout::stdev 0.486500 # Request fanout histogram 3078system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3079system.toL2Bus.snoop_fanout::0 526500 62.41% 62.41% # Request fanout histogram 3080system.toL2Bus.snoop_fanout::1 316282 37.49% 99.91% # Request fanout histogram 3081system.toL2Bus.snoop_fanout::2 785 0.09% 100.00% # Request fanout histogram 3082system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3083system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3084system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3085system.toL2Bus.snoop_fanout::total 843567 # Request fanout histogram 3086system.toL2Bus.reqLayer0.occupancy 877207087 # Layer occupancy (ticks) 3087system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3088system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks) 3089system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3090system.toL2Bus.respLayer0.occupancy 640962681 # Layer occupancy (ticks) 3091system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3092system.toL2Bus.respLayer1.occupancy 223907403 # Layer occupancy (ticks) 3093system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3094 3095---------- End Simulation Statistics ----------	1476system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1477system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1478system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1479system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1480system.cpu1.itb.read_accesses 0 # DTB read accesses 1481system.cpu1.itb.write_accesses 0 # DTB write accesses 1482system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses 1483system.cpu1.itb.hits 16556610 # DTB hits 1484system.cpu1.itb.misses 1746 # DTB misses 1485system.cpu1.itb.accesses 16558356 # DTB accesses 1486system.cpu1.numPwrStateTransitions 5511 # Number of power state transitions 1487system.cpu1.pwrStateClkGateDist::samples 2756 # Distribution of time spent in the clock gated state 1488system.cpu1.pwrStateClkGateDist::mean 1031898407.856313 # Distribution of time spent in the clock gated state 1489system.cpu1.pwrStateClkGateDist::stdev 25737040202.524998 # Distribution of time spent in the clock gated state 1490system.cpu1.pwrStateClkGateDist::underflows 1964 71.26% 71.26% # Distribution of time spent in the clock gated state 1491system.cpu1.pwrStateClkGateDist::1000-5e+10 786 28.52% 99.78% # Distribution of time spent in the clock gated state 1492system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.85% # Distribution of time spent in the clock gated state 1493system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state 1494system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 1495system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 1496system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state 1497system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1498system.cpu1.pwrStateClkGateDist::max_value 929980631528 # Distribution of time spent in the clock gated state 1499system.cpu1.pwrStateClkGateDist::total 2756 # Distribution of time spent in the clock gated state 1500system.cpu1.pwrStateResidencyTicks::ON 25876957948 # Cumulative time (in ticks) in various power states 1501system.cpu1.pwrStateResidencyTicks::CLK_GATED 2843912012052 # Cumulative time (in ticks) in various power states 1502system.cpu1.numCycles 5738649789 # number of cpu cycles simulated 1503system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1504system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1505system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1506system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed 1507system.cpu1.committedInsts 16201169 # Number of instructions committed 1508system.cpu1.committedOps 19741428 # Number of ops (including micro ops) committed 1509system.cpu1.num_int_alu_accesses 17804295 # Number of integer alu accesses 1510system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses 1511system.cpu1.num_func_calls 1029080 # number of times a function call or return occured 1512system.cpu1.num_conditional_control_insts 1813608 # number of instructions that are conditional controls 1513system.cpu1.num_int_insts 17804295 # number of integer instructions 1514system.cpu1.num_fp_insts 1857 # number of float instructions 1515system.cpu1.num_int_register_reads 32308777 # number of times the integer registers were read 1516system.cpu1.num_int_register_writes 12487661 # number of times the integer registers were written 1517system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read 1518system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 1519system.cpu1.num_cc_register_reads 72166445 # number of times the CC registers were read 1520system.cpu1.num_cc_register_writes 6418557 # number of times the CC registers were written 1521system.cpu1.num_mem_refs 7593995 # number of memory refs 1522system.cpu1.num_load_insts 4052758 # Number of load instructions 1523system.cpu1.num_store_insts 3541237 # Number of store instructions 1524system.cpu1.num_idle_cycles 5686904242.264484 # Number of idle cycles 1525system.cpu1.num_busy_cycles 51745546.735515 # Number of busy cycles 1526system.cpu1.not_idle_fraction 0.009017 # Percentage of non-idle cycles 1527system.cpu1.idle_fraction 0.990983 # Percentage of idle cycles 1528system.cpu1.Branches 2921126 # Number of branches fetched 1529system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1530system.cpu1.op_class::IntAlu 12468405 62.06% 62.06% # Class of executed instruction 1531system.cpu1.op_class::IntMult 26465 0.13% 62.19% # Class of executed instruction 1532system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction 1533system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction 1534system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction 1535system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction 1536system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction 1537system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction 1538system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction 1539system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction 1540system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction 1541system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction 1542system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction 1543system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction 1544system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction 1545system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction 1546system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction 1547system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction 1548system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction 1549system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction 1550system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction 1551system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction 1552system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction 1553system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction 1554system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction 1555system.cpu1.op_class::SimdFloatMisc 3319 0.02% 62.20% # Class of executed instruction 1556system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction 1557system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction 1558system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction 1559system.cpu1.op_class::MemRead 4052758 20.17% 82.38% # Class of executed instruction 1560system.cpu1.op_class::MemWrite 3541237 17.62% 100.00% # Class of executed instruction 1561system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1562system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1563system.cpu1.op_class::total 20092250 # Class of executed instruction 1564system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1565system.cpu1.dcache.tags.replacements 186389 # number of replacements 1566system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use 1567system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks. 1568system.cpu1.dcache.tags.sampled_refs 186755 # Sample count of references to valid blocks. 1569system.cpu1.dcache.tags.avg_refs 37.984359 # Average number of references to valid blocks. 1570system.cpu1.dcache.tags.warmup_cycle 127433218000 # Cycle when the warmup percentage was hit. 1571system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.298921 # Average occupied blocks per requestor 1572system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916599 # Average percentage of cache occupancy 1573system.cpu1.dcache.tags.occ_percent::total 0.916599 # Average percentage of cache occupancy 1574system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id 1575system.cpu1.dcache.tags.age_task_id_blocks_1024::2 285 # Occupied blocks per task id 1576system.cpu1.dcache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id 1577system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id 1578system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses 1579system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses 1580system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1581system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits 1582system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits 1583system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits 1584system.cpu1.dcache.WriteReq_hits::total 3230955 # number of WriteReq hits 1585system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48929 # number of SoftPFReq hits 1586system.cpu1.dcache.SoftPFReq_hits::total 48929 # number of SoftPFReq hits 1587system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78822 # number of LoadLockedReq hits 1588system.cpu1.dcache.LoadLockedReq_hits::total 78822 # number of LoadLockedReq hits 1589system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70747 # number of StoreCondReq hits 1590system.cpu1.dcache.StoreCondReq_hits::total 70747 # number of StoreCondReq hits 1591system.cpu1.dcache.demand_hits::cpu1.data 6860355 # number of demand (read+write) hits 1592system.cpu1.dcache.demand_hits::total 6860355 # number of demand (read+write) hits 1593system.cpu1.dcache.overall_hits::cpu1.data 6909284 # number of overall hits 1594system.cpu1.dcache.overall_hits::total 6909284 # number of overall hits 1595system.cpu1.dcache.ReadReq_misses::cpu1.data 133654 # number of ReadReq misses 1596system.cpu1.dcache.ReadReq_misses::total 133654 # number of ReadReq misses 1597system.cpu1.dcache.WriteReq_misses::cpu1.data 91683 # number of WriteReq misses 1598system.cpu1.dcache.WriteReq_misses::total 91683 # number of WriteReq misses 1599system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30306 # number of SoftPFReq misses 1600system.cpu1.dcache.SoftPFReq_misses::total 30306 # number of SoftPFReq misses 1601system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17079 # number of LoadLockedReq misses 1602system.cpu1.dcache.LoadLockedReq_misses::total 17079 # number of LoadLockedReq misses 1603system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23334 # number of StoreCondReq misses 1604system.cpu1.dcache.StoreCondReq_misses::total 23334 # number of StoreCondReq misses 1605system.cpu1.dcache.demand_misses::cpu1.data 225337 # number of demand (read+write) misses 1606system.cpu1.dcache.demand_misses::total 225337 # number of demand (read+write) misses 1607system.cpu1.dcache.overall_misses::cpu1.data 255643 # number of overall misses 1608system.cpu1.dcache.overall_misses::total 255643 # number of overall misses 1609system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1974580500 # number of ReadReq miss cycles 1610system.cpu1.dcache.ReadReq_miss_latency::total 1974580500 # number of ReadReq miss cycles 1611system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2414638500 # number of WriteReq miss cycles 1612system.cpu1.dcache.WriteReq_miss_latency::total 2414638500 # number of WriteReq miss cycles 1613system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320455500 # number of LoadLockedReq miss cycles 1614system.cpu1.dcache.LoadLockedReq_miss_latency::total 320455500 # number of LoadLockedReq miss cycles 1615system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 569715000 # number of StoreCondReq miss cycles 1616system.cpu1.dcache.StoreCondReq_miss_latency::total 569715000 # number of StoreCondReq miss cycles 1617system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3416500 # number of StoreCondFailReq miss cycles 1618system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3416500 # number of StoreCondFailReq miss cycles 1619system.cpu1.dcache.demand_miss_latency::cpu1.data 4389219000 # number of demand (read+write) miss cycles 1620system.cpu1.dcache.demand_miss_latency::total 4389219000 # number of demand (read+write) miss cycles 1621system.cpu1.dcache.overall_miss_latency::cpu1.data 4389219000 # number of overall miss cycles 1622system.cpu1.dcache.overall_miss_latency::total 4389219000 # number of overall miss cycles 1623system.cpu1.dcache.ReadReq_accesses::cpu1.data 3763054 # number of ReadReq accesses(hits+misses) 1624system.cpu1.dcache.ReadReq_accesses::total 3763054 # number of ReadReq accesses(hits+misses) 1625system.cpu1.dcache.WriteReq_accesses::cpu1.data 3322638 # number of WriteReq accesses(hits+misses) 1626system.cpu1.dcache.WriteReq_accesses::total 3322638 # number of WriteReq accesses(hits+misses) 1627system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79235 # number of SoftPFReq accesses(hits+misses) 1628system.cpu1.dcache.SoftPFReq_accesses::total 79235 # number of SoftPFReq accesses(hits+misses) 1629system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95901 # number of LoadLockedReq accesses(hits+misses) 1630system.cpu1.dcache.LoadLockedReq_accesses::total 95901 # number of LoadLockedReq accesses(hits+misses) 1631system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94081 # number of StoreCondReq accesses(hits+misses) 1632system.cpu1.dcache.StoreCondReq_accesses::total 94081 # number of StoreCondReq accesses(hits+misses) 1633system.cpu1.dcache.demand_accesses::cpu1.data 7085692 # number of demand (read+write) accesses 1634system.cpu1.dcache.demand_accesses::total 7085692 # number of demand (read+write) accesses 1635system.cpu1.dcache.overall_accesses::cpu1.data 7164927 # number of overall (read+write) accesses 1636system.cpu1.dcache.overall_accesses::total 7164927 # number of overall (read+write) accesses 1637system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses 1638system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses 1639system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027593 # miss rate for WriteReq accesses 1640system.cpu1.dcache.WriteReq_miss_rate::total 0.027593 # miss rate for WriteReq accesses 1641system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382482 # miss rate for SoftPFReq accesses 1642system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382482 # miss rate for SoftPFReq accesses 1643system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178090 # miss rate for LoadLockedReq accesses 1644system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178090 # miss rate for LoadLockedReq accesses 1645system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248020 # miss rate for StoreCondReq accesses 1646system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248020 # miss rate for StoreCondReq accesses 1647system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031802 # miss rate for demand accesses 1648system.cpu1.dcache.demand_miss_rate::total 0.031802 # miss rate for demand accesses 1649system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035680 # miss rate for overall accesses 1650system.cpu1.dcache.overall_miss_rate::total 0.035680 # miss rate for overall accesses 1651system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.822706 # average ReadReq miss latency 1652system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.822706 # average ReadReq miss latency 1653system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26336.818167 # average WriteReq miss latency 1654system.cpu1.dcache.WriteReq_avg_miss_latency::total 26336.818167 # average WriteReq miss latency 1655system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18763.130160 # average LoadLockedReq miss latency 1656system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18763.130160 # average LoadLockedReq miss latency 1657system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24415.659553 # average StoreCondReq miss latency 1658system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24415.659553 # average StoreCondReq miss latency 1659system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1660system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1661system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19478.465587 # average overall miss latency 1662system.cpu1.dcache.demand_avg_miss_latency::total 19478.465587 # average overall miss latency 1663system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17169.329886 # average overall miss latency 1664system.cpu1.dcache.overall_avg_miss_latency::total 17169.329886 # average overall miss latency 1665system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1666system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1667system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1668system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1669system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1670system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1671system.cpu1.dcache.writebacks::writebacks 186389 # number of writebacks 1672system.cpu1.dcache.writebacks::total 186389 # number of writebacks 1673system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits 1674system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits 1675system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12013 # number of LoadLockedReq MSHR hits 1676system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12013 # number of LoadLockedReq MSHR hits 1677system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits 1678system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits 1679system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits 1680system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits 1681system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133371 # number of ReadReq MSHR misses 1682system.cpu1.dcache.ReadReq_mshr_misses::total 133371 # number of ReadReq MSHR misses 1683system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91683 # number of WriteReq MSHR misses 1684system.cpu1.dcache.WriteReq_mshr_misses::total 91683 # number of WriteReq MSHR misses 1685system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29541 # number of SoftPFReq MSHR misses 1686system.cpu1.dcache.SoftPFReq_mshr_misses::total 29541 # number of SoftPFReq MSHR misses 1687system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5066 # number of LoadLockedReq MSHR misses 1688system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5066 # number of LoadLockedReq MSHR misses 1689system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23334 # number of StoreCondReq MSHR misses 1690system.cpu1.dcache.StoreCondReq_mshr_misses::total 23334 # number of StoreCondReq MSHR misses 1691system.cpu1.dcache.demand_mshr_misses::cpu1.data 225054 # number of demand (read+write) MSHR misses 1692system.cpu1.dcache.demand_mshr_misses::total 225054 # number of demand (read+write) MSHR misses 1693system.cpu1.dcache.overall_mshr_misses::cpu1.data 254595 # number of overall MSHR misses 1694system.cpu1.dcache.overall_mshr_misses::total 254595 # number of overall MSHR misses 1695system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable 1696system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3095 # number of ReadReq MSHR uncacheable 1697system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable 1698system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable 1699system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses 1700system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5545 # number of overall MSHR uncacheable misses 1701system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1833975000 # number of ReadReq MSHR miss cycles 1702system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1833975000 # number of ReadReq MSHR miss cycles 1703system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2322955500 # number of WriteReq MSHR miss cycles 1704system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2322955500 # number of WriteReq MSHR miss cycles 1705system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 497374500 # number of SoftPFReq MSHR miss cycles 1706system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 497374500 # number of SoftPFReq MSHR miss cycles 1707system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87920500 # number of LoadLockedReq MSHR miss cycles 1708system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87920500 # number of LoadLockedReq MSHR miss cycles 1709system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 546440000 # number of StoreCondReq MSHR miss cycles 1710system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 546440000 # number of StoreCondReq MSHR miss cycles 1711system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3357500 # number of StoreCondFailReq MSHR miss cycles 1712system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3357500 # number of StoreCondFailReq MSHR miss cycles 1713system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4156930500 # number of demand (read+write) MSHR miss cycles 1714system.cpu1.dcache.demand_mshr_miss_latency::total 4156930500 # number of demand (read+write) MSHR miss cycles 1715system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4654305000 # number of overall MSHR miss cycles 1716system.cpu1.dcache.overall_mshr_miss_latency::total 4654305000 # number of overall MSHR miss cycles 1717system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443417000 # number of ReadReq MSHR uncacheable cycles 1718system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443417000 # number of ReadReq MSHR uncacheable cycles 1719system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443417000 # number of overall MSHR uncacheable cycles 1720system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443417000 # number of overall MSHR uncacheable cycles 1721system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses 1722system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses 1723system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027593 # mshr miss rate for WriteReq accesses 1724system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027593 # mshr miss rate for WriteReq accesses 1725system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372828 # mshr miss rate for SoftPFReq accesses 1726system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372828 # mshr miss rate for SoftPFReq accesses 1727system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052825 # mshr miss rate for LoadLockedReq accesses 1728system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052825 # mshr miss rate for LoadLockedReq accesses 1729system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248020 # mshr miss rate for StoreCondReq accesses 1730system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248020 # mshr miss rate for StoreCondReq accesses 1731system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for demand accesses 1732system.cpu1.dcache.demand_mshr_miss_rate::total 0.031762 # mshr miss rate for demand accesses 1733system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035534 # mshr miss rate for overall accesses 1734system.cpu1.dcache.overall_mshr_miss_rate::total 0.035534 # mshr miss rate for overall accesses 1735system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13750.927863 # average ReadReq mshr miss latency 1736system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13750.927863 # average ReadReq mshr miss latency 1737system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25336.818167 # average WriteReq mshr miss latency 1738system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25336.818167 # average WriteReq mshr miss latency 1739system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16836.752310 # average SoftPFReq mshr miss latency 1740system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16836.752310 # average SoftPFReq mshr miss latency 1741system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17355.013818 # average LoadLockedReq mshr miss latency 1742system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17355.013818 # average LoadLockedReq mshr miss latency 1743system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23418.188052 # average StoreCondReq mshr miss latency 1744system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23418.188052 # average StoreCondReq mshr miss latency 1745system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1746system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1747system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18470.813671 # average overall mshr miss latency 1748system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18470.813671 # average overall mshr miss latency 1749system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18281.211336 # average overall mshr miss latency 1750system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18281.211336 # average overall mshr miss latency 1751system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143268.820679 # average ReadReq mshr uncacheable latency 1752system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency 1753system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency 1754system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency 1755system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1756system.cpu1.icache.tags.replacements 505464 # number of replacements 1757system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use 1758system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks. 1759system.cpu1.icache.tags.sampled_refs 505976 # Sample count of references to valid blocks. 1760system.cpu1.icache.tags.avg_refs 31.722115 # Average number of references to valid blocks. 1761system.cpu1.icache.tags.warmup_cycle 85269924000 # Cycle when the warmup percentage was hit. 1762system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478732 # Average occupied blocks per requestor 1763system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy 1764system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy 1765system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1766system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id 1767system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id 1768system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id 1769system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1770system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses 1771system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses 1772system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1773system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits 1774system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits 1775system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits 1776system.cpu1.icache.demand_hits::total 16050629 # number of demand (read+write) hits 1777system.cpu1.icache.overall_hits::cpu1.inst 16050629 # number of overall hits 1778system.cpu1.icache.overall_hits::total 16050629 # number of overall hits 1779system.cpu1.icache.ReadReq_misses::cpu1.inst 505976 # number of ReadReq misses 1780system.cpu1.icache.ReadReq_misses::total 505976 # number of ReadReq misses 1781system.cpu1.icache.demand_misses::cpu1.inst 505976 # number of demand (read+write) misses 1782system.cpu1.icache.demand_misses::total 505976 # number of demand (read+write) misses 1783system.cpu1.icache.overall_misses::cpu1.inst 505976 # number of overall misses 1784system.cpu1.icache.overall_misses::total 505976 # number of overall misses 1785system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4528088500 # number of ReadReq miss cycles 1786system.cpu1.icache.ReadReq_miss_latency::total 4528088500 # number of ReadReq miss cycles 1787system.cpu1.icache.demand_miss_latency::cpu1.inst 4528088500 # number of demand (read+write) miss cycles 1788system.cpu1.icache.demand_miss_latency::total 4528088500 # number of demand (read+write) miss cycles 1789system.cpu1.icache.overall_miss_latency::cpu1.inst 4528088500 # number of overall miss cycles 1790system.cpu1.icache.overall_miss_latency::total 4528088500 # number of overall miss cycles 1791system.cpu1.icache.ReadReq_accesses::cpu1.inst 16556605 # number of ReadReq accesses(hits+misses) 1792system.cpu1.icache.ReadReq_accesses::total 16556605 # number of ReadReq accesses(hits+misses) 1793system.cpu1.icache.demand_accesses::cpu1.inst 16556605 # number of demand (read+write) accesses 1794system.cpu1.icache.demand_accesses::total 16556605 # number of demand (read+write) accesses 1795system.cpu1.icache.overall_accesses::cpu1.inst 16556605 # number of overall (read+write) accesses 1796system.cpu1.icache.overall_accesses::total 16556605 # number of overall (read+write) accesses 1797system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030560 # miss rate for ReadReq accesses 1798system.cpu1.icache.ReadReq_miss_rate::total 0.030560 # miss rate for ReadReq accesses 1799system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030560 # miss rate for demand accesses 1800system.cpu1.icache.demand_miss_rate::total 0.030560 # miss rate for demand accesses 1801system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030560 # miss rate for overall accesses 1802system.cpu1.icache.overall_miss_rate::total 0.030560 # miss rate for overall accesses 1803system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8949.215971 # average ReadReq miss latency 1804system.cpu1.icache.ReadReq_avg_miss_latency::total 8949.215971 # average ReadReq miss latency 1805system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency 1806system.cpu1.icache.demand_avg_miss_latency::total 8949.215971 # average overall miss latency 1807system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency 1808system.cpu1.icache.overall_avg_miss_latency::total 8949.215971 # average overall miss latency 1809system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1810system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1811system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1812system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1813system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1814system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1815system.cpu1.icache.writebacks::writebacks 505464 # number of writebacks 1816system.cpu1.icache.writebacks::total 505464 # number of writebacks 1817system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 505976 # number of ReadReq MSHR misses 1818system.cpu1.icache.ReadReq_mshr_misses::total 505976 # number of ReadReq MSHR misses 1819system.cpu1.icache.demand_mshr_misses::cpu1.inst 505976 # number of demand (read+write) MSHR misses 1820system.cpu1.icache.demand_mshr_misses::total 505976 # number of demand (read+write) MSHR misses 1821system.cpu1.icache.overall_mshr_misses::cpu1.inst 505976 # number of overall MSHR misses 1822system.cpu1.icache.overall_mshr_misses::total 505976 # number of overall MSHR misses 1823system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1824system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1825system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1826system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1827system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4275100500 # number of ReadReq MSHR miss cycles 1828system.cpu1.icache.ReadReq_mshr_miss_latency::total 4275100500 # number of ReadReq MSHR miss cycles 1829system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4275100500 # number of demand (read+write) MSHR miss cycles 1830system.cpu1.icache.demand_mshr_miss_latency::total 4275100500 # number of demand (read+write) MSHR miss cycles 1831system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4275100500 # number of overall MSHR miss cycles 1832system.cpu1.icache.overall_mshr_miss_latency::total 4275100500 # number of overall MSHR miss cycles 1833system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # number of ReadReq MSHR uncacheable cycles 1834system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15776500 # number of ReadReq MSHR uncacheable cycles 1835system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15776500 # number of overall MSHR uncacheable cycles 1836system.cpu1.icache.overall_mshr_uncacheable_latency::total 15776500 # number of overall MSHR uncacheable cycles 1837system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for ReadReq accesses 1838system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030560 # mshr miss rate for ReadReq accesses 1839system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for demand accesses 1840system.cpu1.icache.demand_mshr_miss_rate::total 0.030560 # mshr miss rate for demand accesses 1841system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for overall accesses 1842system.cpu1.icache.overall_mshr_miss_rate::total 0.030560 # mshr miss rate for overall accesses 1843system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average ReadReq mshr miss latency 1844system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8449.215971 # average ReadReq mshr miss latency 1845system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency 1846system.cpu1.icache.demand_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency 1847system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency 1848system.cpu1.icache.overall_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency 1849system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency 1850system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency 1851system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency 1852system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency 1853system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1854system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued 1855system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified 1856system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 1857system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1858system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1859system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing 1860system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1861system.cpu1.l2cache.tags.replacements 44688 # number of replacements 1862system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use 1863system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks. 1864system.cpu1.l2cache.tags.sampled_refs 59377 # Sample count of references to valid blocks. 1865system.cpu1.l2cache.tags.avg_refs 19.563737 # Average number of references to valid blocks. 1866system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1867system.cpu1.l2cache.tags.occ_blocks::writebacks 14464.281457 # Average occupied blocks per requestor 1868system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.152749 # Average occupied blocks per requestor 1869system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.089726 # Average occupied blocks per requestor 1870system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 468.961320 # Average occupied blocks per requestor 1871system.cpu1.l2cache.tags.occ_percent::writebacks 0.882830 # Average percentage of cache occupancy 1872system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy 1873system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy 1874system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028623 # Average percentage of cache occupancy 1875system.cpu1.l2cache.tags.occ_percent::total 0.911773 # Average percentage of cache occupancy 1876system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id 1877system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id 1878system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13646 # Occupied blocks per task id 1879system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 36 # Occupied blocks per task id 1880system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 993 # Occupied blocks per task id 1881system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 1882system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 1883system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id 1884system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id 1885system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11682 # Occupied blocks per task id 1886system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id 1887system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id 1888system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832886 # Percentage of cache occupancy per task id 1889system.cpu1.l2cache.tags.tag_accesses 23775762 # Number of tag accesses 1890system.cpu1.l2cache.tags.data_accesses 23775762 # Number of data accesses 1891system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 1892system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3761 # number of ReadReq hits 1893system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2010 # number of ReadReq hits 1894system.cpu1.l2cache.ReadReq_hits::total 5771 # number of ReadReq hits 1895system.cpu1.l2cache.WritebackDirty_hits::writebacks 113707 # number of WritebackDirty hits 1896system.cpu1.l2cache.WritebackDirty_hits::total 113707 # number of WritebackDirty hits 1897system.cpu1.l2cache.WritebackClean_hits::writebacks 567008 # number of WritebackClean hits 1898system.cpu1.l2cache.WritebackClean_hits::total 567008 # number of WritebackClean hits 1899system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27229 # number of ReadExReq hits 1900system.cpu1.l2cache.ReadExReq_hits::total 27229 # number of ReadExReq hits 1901system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 492726 # number of ReadCleanReq hits 1902system.cpu1.l2cache.ReadCleanReq_hits::total 492726 # number of ReadCleanReq hits 1903system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99930 # number of ReadSharedReq hits 1904system.cpu1.l2cache.ReadSharedReq_hits::total 99930 # number of ReadSharedReq hits 1905system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3761 # number of demand (read+write) hits 1906system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2010 # number of demand (read+write) hits 1907system.cpu1.l2cache.demand_hits::cpu1.inst 492726 # number of demand (read+write) hits 1908system.cpu1.l2cache.demand_hits::cpu1.data 127159 # number of demand (read+write) hits 1909system.cpu1.l2cache.demand_hits::total 625656 # number of demand (read+write) hits 1910system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3761 # number of overall hits 1911system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2010 # number of overall hits 1912system.cpu1.l2cache.overall_hits::cpu1.inst 492726 # number of overall hits 1913system.cpu1.l2cache.overall_hits::cpu1.data 127159 # number of overall hits 1914system.cpu1.l2cache.overall_hits::total 625656 # number of overall hits 1915system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 318 # number of ReadReq misses 1916system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses 1917system.cpu1.l2cache.ReadReq_misses::total 590 # number of ReadReq misses 1918system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29672 # number of UpgradeReq misses 1919system.cpu1.l2cache.UpgradeReq_misses::total 29672 # number of UpgradeReq misses 1920system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23330 # number of SCUpgradeReq misses 1921system.cpu1.l2cache.SCUpgradeReq_misses::total 23330 # number of SCUpgradeReq misses 1922system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 1923system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1924system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34782 # number of ReadExReq misses 1925system.cpu1.l2cache.ReadExReq_misses::total 34782 # number of ReadExReq misses 1926system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13250 # number of ReadCleanReq misses 1927system.cpu1.l2cache.ReadCleanReq_misses::total 13250 # number of ReadCleanReq misses 1928system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68048 # number of ReadSharedReq misses 1929system.cpu1.l2cache.ReadSharedReq_misses::total 68048 # number of ReadSharedReq misses 1930system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 318 # number of demand (read+write) misses 1931system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses 1932system.cpu1.l2cache.demand_misses::cpu1.inst 13250 # number of demand (read+write) misses 1933system.cpu1.l2cache.demand_misses::cpu1.data 102830 # number of demand (read+write) misses 1934system.cpu1.l2cache.demand_misses::total 116670 # number of demand (read+write) misses 1935system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 318 # number of overall misses 1936system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses 1937system.cpu1.l2cache.overall_misses::cpu1.inst 13250 # number of overall misses 1938system.cpu1.l2cache.overall_misses::cpu1.data 102830 # number of overall misses 1939system.cpu1.l2cache.overall_misses::total 116670 # number of overall misses 1940system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6473000 # number of ReadReq miss cycles 1941system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5557000 # number of ReadReq miss cycles 1942system.cpu1.l2cache.ReadReq_miss_latency::total 12030000 # number of ReadReq miss cycles 1943system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65067000 # number of UpgradeReq miss cycles 1944system.cpu1.l2cache.UpgradeReq_miss_latency::total 65067000 # number of UpgradeReq miss cycles 1945system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 32437500 # number of SCUpgradeReq miss cycles 1946system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 32437500 # number of SCUpgradeReq miss cycles 1947system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3268500 # number of SCUpgradeFailReq miss cycles 1948system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3268500 # number of SCUpgradeFailReq miss cycles 1949system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1333613500 # number of ReadExReq miss cycles 1950system.cpu1.l2cache.ReadExReq_miss_latency::total 1333613500 # number of ReadExReq miss cycles 1951system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 533576500 # number of ReadCleanReq miss cycles 1952system.cpu1.l2cache.ReadCleanReq_miss_latency::total 533576500 # number of ReadCleanReq miss cycles 1953system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1512816500 # number of ReadSharedReq miss cycles 1954system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1512816500 # number of ReadSharedReq miss cycles 1955system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6473000 # number of demand (read+write) miss cycles 1956system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5557000 # number of demand (read+write) miss cycles 1957system.cpu1.l2cache.demand_miss_latency::cpu1.inst 533576500 # number of demand (read+write) miss cycles 1958system.cpu1.l2cache.demand_miss_latency::cpu1.data 2846430000 # number of demand (read+write) miss cycles 1959system.cpu1.l2cache.demand_miss_latency::total 3392036500 # number of demand (read+write) miss cycles 1960system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6473000 # number of overall miss cycles 1961system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5557000 # number of overall miss cycles 1962system.cpu1.l2cache.overall_miss_latency::cpu1.inst 533576500 # number of overall miss cycles 1963system.cpu1.l2cache.overall_miss_latency::cpu1.data 2846430000 # number of overall miss cycles 1964system.cpu1.l2cache.overall_miss_latency::total 3392036500 # number of overall miss cycles 1965system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4079 # number of ReadReq accesses(hits+misses) 1966system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2282 # number of ReadReq accesses(hits+misses) 1967system.cpu1.l2cache.ReadReq_accesses::total 6361 # number of ReadReq accesses(hits+misses) 1968system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113707 # number of WritebackDirty accesses(hits+misses) 1969system.cpu1.l2cache.WritebackDirty_accesses::total 113707 # number of WritebackDirty accesses(hits+misses) 1970system.cpu1.l2cache.WritebackClean_accesses::writebacks 567008 # number of WritebackClean accesses(hits+misses) 1971system.cpu1.l2cache.WritebackClean_accesses::total 567008 # number of WritebackClean accesses(hits+misses) 1972system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29672 # number of UpgradeReq accesses(hits+misses) 1973system.cpu1.l2cache.UpgradeReq_accesses::total 29672 # number of UpgradeReq accesses(hits+misses) 1974system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23330 # number of SCUpgradeReq accesses(hits+misses) 1975system.cpu1.l2cache.SCUpgradeReq_accesses::total 23330 # number of SCUpgradeReq accesses(hits+misses) 1976system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1977system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1978system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62011 # number of ReadExReq accesses(hits+misses) 1979system.cpu1.l2cache.ReadExReq_accesses::total 62011 # number of ReadExReq accesses(hits+misses) 1980system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 505976 # number of ReadCleanReq accesses(hits+misses) 1981system.cpu1.l2cache.ReadCleanReq_accesses::total 505976 # number of ReadCleanReq accesses(hits+misses) 1982system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167978 # number of ReadSharedReq accesses(hits+misses) 1983system.cpu1.l2cache.ReadSharedReq_accesses::total 167978 # number of ReadSharedReq accesses(hits+misses) 1984system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4079 # number of demand (read+write) accesses 1985system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2282 # number of demand (read+write) accesses 1986system.cpu1.l2cache.demand_accesses::cpu1.inst 505976 # number of demand (read+write) accesses 1987system.cpu1.l2cache.demand_accesses::cpu1.data 229989 # number of demand (read+write) accesses 1988system.cpu1.l2cache.demand_accesses::total 742326 # number of demand (read+write) accesses 1989system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4079 # number of overall (read+write) accesses 1990system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2282 # number of overall (read+write) accesses 1991system.cpu1.l2cache.overall_accesses::cpu1.inst 505976 # number of overall (read+write) accesses 1992system.cpu1.l2cache.overall_accesses::cpu1.data 229989 # number of overall (read+write) accesses 1993system.cpu1.l2cache.overall_accesses::total 742326 # number of overall (read+write) accesses 1994system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for ReadReq accesses 1995system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.119194 # miss rate for ReadReq accesses 1996system.cpu1.l2cache.ReadReq_miss_rate::total 0.092753 # miss rate for ReadReq accesses 1997system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1998system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1999system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2000system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2001system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2002system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2003system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560900 # miss rate for ReadExReq accesses 2004system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560900 # miss rate for ReadExReq accesses 2005system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026187 # miss rate for ReadCleanReq accesses 2006system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026187 # miss rate for ReadCleanReq accesses 2007system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405101 # miss rate for ReadSharedReq accesses 2008system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405101 # miss rate for ReadSharedReq accesses 2009system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for demand accesses 2010system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.119194 # miss rate for demand accesses 2011system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026187 # miss rate for demand accesses 2012system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.447108 # miss rate for demand accesses 2013system.cpu1.l2cache.demand_miss_rate::total 0.157168 # miss rate for demand accesses 2014system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for overall accesses 2015system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.119194 # miss rate for overall accesses 2016system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026187 # miss rate for overall accesses 2017system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.447108 # miss rate for overall accesses 2018system.cpu1.l2cache.overall_miss_rate::total 0.157168 # miss rate for overall accesses 2019system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average ReadReq miss latency 2020system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20430.147059 # average ReadReq miss latency 2021system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20389.830508 # average ReadReq miss latency 2022system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2192.875438 # average UpgradeReq miss latency 2023system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2192.875438 # average UpgradeReq miss latency 2024system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1390.377197 # average SCUpgradeReq miss latency 2025system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1390.377197 # average SCUpgradeReq miss latency 2026system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 817125 # average SCUpgradeFailReq miss latency 2027system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 817125 # average SCUpgradeFailReq miss latency 2028system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38342.059111 # average ReadExReq miss latency 2029system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38342.059111 # average ReadExReq miss latency 2030system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40269.924528 # average ReadCleanReq miss latency 2031system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40269.924528 # average ReadCleanReq miss latency 2032system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22231.608570 # average ReadSharedReq miss latency 2033system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22231.608570 # average ReadSharedReq miss latency 2034system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency 2035system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency 2036system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency 2037system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency 2038system.cpu1.l2cache.demand_avg_miss_latency::total 29073.767892 # average overall miss latency 2039system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency 2040system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency 2041system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency 2042system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency 2043system.cpu1.l2cache.overall_avg_miss_latency::total 29073.767892 # average overall miss latency 2044system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2045system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2046system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2047system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2048system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2049system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2050system.cpu1.l2cache.unused_prefetches 790 # number of HardPF blocks evicted w/o reference 2051system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks 2052system.cpu1.l2cache.writebacks::total 33019 # number of writebacks 2053system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 57 # number of ReadExReq MSHR hits 2054system.cpu1.l2cache.ReadExReq_mshr_hits::total 57 # number of ReadExReq MSHR hits 2055system.cpu1.l2cache.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits 2056system.cpu1.l2cache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits 2057system.cpu1.l2cache.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits 2058system.cpu1.l2cache.overall_mshr_hits::total 57 # number of overall MSHR hits 2059system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 318 # number of ReadReq MSHR misses 2060system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 272 # number of ReadReq MSHR misses 2061system.cpu1.l2cache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses 2062system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of HardPFReq MSHR misses 2063system.cpu1.l2cache.HardPFReq_mshr_misses::total 24979 # number of HardPFReq MSHR misses 2064system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29672 # number of UpgradeReq MSHR misses 2065system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29672 # number of UpgradeReq MSHR misses 2066system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23330 # number of SCUpgradeReq MSHR misses 2067system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23330 # number of SCUpgradeReq MSHR misses 2068system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2069system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2070system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34725 # number of ReadExReq MSHR misses 2071system.cpu1.l2cache.ReadExReq_mshr_misses::total 34725 # number of ReadExReq MSHR misses 2072system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13250 # number of ReadCleanReq MSHR misses 2073system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13250 # number of ReadCleanReq MSHR misses 2074system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68048 # number of ReadSharedReq MSHR misses 2075system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68048 # number of ReadSharedReq MSHR misses 2076system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 318 # number of demand (read+write) MSHR misses 2077system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 272 # number of demand (read+write) MSHR misses 2078system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13250 # number of demand (read+write) MSHR misses 2079system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102773 # number of demand (read+write) MSHR misses 2080system.cpu1.l2cache.demand_mshr_misses::total 116613 # number of demand (read+write) MSHR misses 2081system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 318 # number of overall MSHR misses 2082system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 272 # number of overall MSHR misses 2083system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13250 # number of overall MSHR misses 2084system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102773 # number of overall MSHR misses 2085system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of overall MSHR misses 2086system.cpu1.l2cache.overall_mshr_misses::total 141592 # number of overall MSHR misses 2087system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2088system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable 2089system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3272 # number of ReadReq MSHR uncacheable 2090system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable 2091system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable 2092system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2093system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses 2094system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5722 # number of overall MSHR uncacheable misses 2095system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of ReadReq MSHR miss cycles 2096system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3925000 # number of ReadReq MSHR miss cycles 2097system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8490000 # number of ReadReq MSHR miss cycles 2098system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of HardPFReq MSHR miss cycles 2099system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 780424807 # number of HardPFReq MSHR miss cycles 2100system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 494079500 # number of UpgradeReq MSHR miss cycles 2101system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 494079500 # number of UpgradeReq MSHR miss cycles 2102system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 371536000 # number of SCUpgradeReq MSHR miss cycles 2103system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 371536000 # number of SCUpgradeReq MSHR miss cycles 2104system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2914500 # number of SCUpgradeFailReq MSHR miss cycles 2105system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2914500 # number of SCUpgradeFailReq MSHR miss cycles 2106system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1118604500 # number of ReadExReq MSHR miss cycles 2107system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1118604500 # number of ReadExReq MSHR miss cycles 2108system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 454076500 # number of ReadCleanReq MSHR miss cycles 2109system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 454076500 # number of ReadCleanReq MSHR miss cycles 2110system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1104528500 # number of ReadSharedReq MSHR miss cycles 2111system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1104528500 # number of ReadSharedReq MSHR miss cycles 2112system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of demand (read+write) MSHR miss cycles 2113system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3925000 # number of demand (read+write) MSHR miss cycles 2114system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454076500 # number of demand (read+write) MSHR miss cycles 2115system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2223133000 # number of demand (read+write) MSHR miss cycles 2116system.cpu1.l2cache.demand_mshr_miss_latency::total 2685699500 # number of demand (read+write) MSHR miss cycles 2117system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of overall MSHR miss cycles 2118system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3925000 # number of overall MSHR miss cycles 2119system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454076500 # number of overall MSHR miss cycles 2120system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2223133000 # number of overall MSHR miss cycles 2121system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of overall MSHR miss cycles 2122system.cpu1.l2cache.overall_mshr_miss_latency::total 3466124307 # number of overall MSHR miss cycles 2123system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14449000 # number of ReadReq MSHR uncacheable cycles 2124system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418310000 # number of ReadReq MSHR uncacheable cycles 2125system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432759000 # number of ReadReq MSHR uncacheable cycles 2126system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14449000 # number of overall MSHR uncacheable cycles 2127system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418310000 # number of overall MSHR uncacheable cycles 2128system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432759000 # number of overall MSHR uncacheable cycles 2129system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for ReadReq accesses 2130system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for ReadReq accesses 2131system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.092753 # mshr miss rate for ReadReq accesses 2132system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2133system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2134system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2135system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2136system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2137system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2138system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2139system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2140system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559981 # mshr miss rate for ReadExReq accesses 2141system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559981 # mshr miss rate for ReadExReq accesses 2142system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for ReadCleanReq accesses 2143system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadCleanReq accesses 2144system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.405101 # mshr miss rate for ReadSharedReq accesses 2145system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405101 # mshr miss rate for ReadSharedReq accesses 2146system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for demand accesses 2147system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for demand accesses 2148system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for demand accesses 2149system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for demand accesses 2150system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157091 # mshr miss rate for demand accesses 2151system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for overall accesses 2152system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for overall accesses 2153system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for overall accesses 2154system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for overall accesses 2155system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2156system.cpu1.l2cache.overall_mshr_miss_rate::total 0.190741 # mshr miss rate for overall accesses 2157system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average ReadReq mshr miss latency 2158system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average ReadReq mshr miss latency 2159system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14389.830508 # average ReadReq mshr miss latency 2160system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average HardPFReq mshr miss latency 2161system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31243.236599 # average HardPFReq mshr miss latency 2162system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16651.371664 # average UpgradeReq mshr miss latency 2163system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16651.371664 # average UpgradeReq mshr miss latency 2164system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15925.246464 # average SCUpgradeReq mshr miss latency 2165system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15925.246464 # average SCUpgradeReq mshr miss latency 2166system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 728625 # average SCUpgradeFailReq mshr miss latency 2167system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 728625 # average SCUpgradeFailReq mshr miss latency 2168system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32213.232541 # average ReadExReq mshr miss latency 2169system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32213.232541 # average ReadExReq mshr miss latency 2170system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average ReadCleanReq mshr miss latency 2171system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34269.924528 # average ReadCleanReq mshr miss latency 2172system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16231.608570 # average ReadSharedReq mshr miss latency 2173system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16231.608570 # average ReadSharedReq mshr miss latency 2174system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency 2175system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency 2176system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency 2177system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency 2178system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23030.875631 # average overall mshr miss latency 2179system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency 2180system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency 2181system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency 2182system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency 2183system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average overall mshr miss latency 2184system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24479.662036 # average overall mshr miss latency 2185system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency 2186system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135156.704362 # average ReadReq mshr uncacheable latency 2187system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132261.308068 # average ReadReq mshr uncacheable latency 2188system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency 2189system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75439.134355 # average overall mshr uncacheable latency 2190system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75630.723523 # average overall mshr uncacheable latency 2191system.cpu1.toL2Bus.snoop_filter.tot_requests 1487204 # Total number of requests made to the snoop filter. 2192system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751274 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2193system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2194system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter. 2195system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2196system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2197system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2198system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution 2199system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution 2200system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution 2201system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution 2202system.cpu1.toL2Bus.trans_dist::WritebackDirty 147816 # Transaction distribution 2203system.cpu1.toL2Bus.trans_dist::WritebackClean 578146 # Transaction distribution 2204system.cpu1.toL2Bus.trans_dist::CleanEvict 101473 # Transaction distribution 2205system.cpu1.toL2Bus.trans_dist::HardPFReq 30088 # Transaction distribution 2206system.cpu1.toL2Bus.trans_dist::UpgradeReq 71412 # Transaction distribution 2207system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41204 # Transaction distribution 2208system.cpu1.toL2Bus.trans_dist::UpgradeResp 85825 # Transaction distribution 2209system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 2210system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution 2211system.cpu1.toL2Bus.trans_dist::ReadExReq 69105 # Transaction distribution 2212system.cpu1.toL2Bus.trans_dist::ReadExResp 66696 # Transaction distribution 2213system.cpu1.toL2Bus.trans_dist::ReadCleanReq 505976 # Transaction distribution 2214system.cpu1.toL2Bus.trans_dist::ReadSharedReq 245752 # Transaction distribution 2215system.cpu1.toL2Bus.trans_dist::InvalidateReq 247 # Transaction distribution 2216system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1517770 # Packet count per connected master and slave (bytes) 2217system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838774 # Packet count per connected master and slave (bytes) 2218system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5606 # Packet count per connected master and slave (bytes) 2219system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10127 # Packet count per connected master and slave (bytes) 2220system.cpu1.toL2Bus.pkt_count::total 2372277 # Packet count per connected master and slave (bytes) 2221system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64732868 # Cumulative packet size per connected master and slave (bytes) 2222system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29385740 # Cumulative packet size per connected master and slave (bytes) 2223system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9128 # Cumulative packet size per connected master and slave (bytes) 2224system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16316 # Cumulative packet size per connected master and slave (bytes) 2225system.cpu1.toL2Bus.pkt_size::total 94144052 # Cumulative packet size per connected master and slave (bytes) 2226system.cpu1.toL2Bus.snoops 388756 # Total snoops (count) 2227system.cpu1.toL2Bus.snoop_fanout::samples 1114505 # Request fanout histogram 2228system.cpu1.toL2Bus.snoop_fanout::mean 0.179300 # Request fanout histogram 2229system.cpu1.toL2Bus.snoop_fanout::stdev 0.390891 # Request fanout histogram 2230system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2231system.cpu1.toL2Bus.snoop_fanout::0 917819 82.35% 82.35% # Request fanout histogram 2232system.cpu1.toL2Bus.snoop_fanout::1 193541 17.37% 99.72% # Request fanout histogram 2233system.cpu1.toL2Bus.snoop_fanout::2 3145 0.28% 100.00% # Request fanout histogram 2234system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2235system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2236system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2237system.cpu1.toL2Bus.snoop_fanout::total 1114505 # Request fanout histogram 2238system.cpu1.toL2Bus.reqLayer0.occupancy 1441037000 # Layer occupancy (ticks) 2239system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2240system.cpu1.toL2Bus.snoopLayer0.occupancy 80111937 # Layer occupancy (ticks) 2241system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2242system.cpu1.toL2Bus.respLayer0.occupancy 759141000 # Layer occupancy (ticks) 2243system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2244system.cpu1.toL2Bus.respLayer1.occupancy 375865500 # Layer occupancy (ticks) 2245system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2246system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) 2247system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2248system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks) 2249system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2250system.iobus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2251system.iobus.trans_dist::ReadReq 31015 # Transaction distribution 2252system.iobus.trans_dist::ReadResp 31015 # Transaction distribution 2253system.iobus.trans_dist::WriteReq 59422 # Transaction distribution 2254system.iobus.trans_dist::WriteResp 59422 # Transaction distribution 2255system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) 2256system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2257system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2258system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2259system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2260system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2261system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2262system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2263system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2264system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2265system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2266system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2267system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2268system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2269system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2270system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2271system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2272system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2273system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2274system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) 2275system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) 2276system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) 2277system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) 2278system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) 2279system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2280system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2281system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2282system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2283system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2284system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2285system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2286system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2287system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2288system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2289system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2290system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2291system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2292system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2293system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2294system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2295system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2296system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2297system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) 2298system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) 2299system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) 2300system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) 2301system.iobus.reqLayer0.occupancy 48726000 # Layer occupancy (ticks) 2302system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2303system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) 2304system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2305system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks) 2306system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2307system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) 2308system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2309system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) 2310system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2311system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) 2312system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2313system.iobus.reqLayer8.occupancy 601500 # Layer occupancy (ticks) 2314system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2315system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) 2316system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2317system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) 2318system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2319system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2320system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2321system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2322system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2323system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks) 2324system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2325system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 2326system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2327system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) 2328system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2329system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2330system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2331system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2332system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2333system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) 2334system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2335system.iobus.reqLayer23.occupancy 6164000 # Layer occupancy (ticks) 2336system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2337system.iobus.reqLayer24.occupancy 32044500 # Layer occupancy (ticks) 2338system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2339system.iobus.reqLayer25.occupancy 187734328 # Layer occupancy (ticks) 2340system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2341system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) 2342system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2343system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) 2344system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2345system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2346system.iocache.tags.replacements 36445 # number of replacements 2347system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use 2348system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2349system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. 2350system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2351system.iocache.tags.warmup_cycle 289174340000 # Cycle when the warmup percentage was hit. 2352system.iocache.tags.occ_blocks::realview.ide 14.386648 # Average occupied blocks per requestor 2353system.iocache.tags.occ_percent::realview.ide 0.899166 # Average percentage of cache occupancy 2354system.iocache.tags.occ_percent::total 0.899166 # Average percentage of cache occupancy 2355system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2356system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2357system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2358system.iocache.tags.tag_accesses 328311 # Number of tag accesses 2359system.iocache.tags.data_accesses 328311 # Number of data accesses 2360system.iocache.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2361system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses 2362system.iocache.ReadReq_misses::total 255 # number of ReadReq misses 2363system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2364system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2365system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses 2366system.iocache.demand_misses::total 36479 # number of demand (read+write) misses 2367system.iocache.overall_misses::realview.ide 36479 # number of overall misses 2368system.iocache.overall_misses::total 36479 # number of overall misses 2369system.iocache.ReadReq_miss_latency::realview.ide 36421877 # number of ReadReq miss cycles 2370system.iocache.ReadReq_miss_latency::total 36421877 # number of ReadReq miss cycles 2371system.iocache.WriteLineReq_miss_latency::realview.ide 4307524451 # number of WriteLineReq miss cycles 2372system.iocache.WriteLineReq_miss_latency::total 4307524451 # number of WriteLineReq miss cycles 2373system.iocache.demand_miss_latency::realview.ide 4343946328 # number of demand (read+write) miss cycles 2374system.iocache.demand_miss_latency::total 4343946328 # number of demand (read+write) miss cycles 2375system.iocache.overall_miss_latency::realview.ide 4343946328 # number of overall miss cycles 2376system.iocache.overall_miss_latency::total 4343946328 # number of overall miss cycles 2377system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) 2378system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) 2379system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2380system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2381system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses 2382system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses 2383system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses 2384system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses 2385system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2386system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2387system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2388system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2389system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2390system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2391system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2392system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2393system.iocache.ReadReq_avg_miss_latency::realview.ide 142830.890196 # average ReadReq miss latency 2394system.iocache.ReadReq_avg_miss_latency::total 142830.890196 # average ReadReq miss latency 2395system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118913.550436 # average WriteLineReq miss latency 2396system.iocache.WriteLineReq_avg_miss_latency::total 118913.550436 # average WriteLineReq miss latency 2397system.iocache.demand_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency 2398system.iocache.demand_avg_miss_latency::total 119080.740371 # average overall miss latency 2399system.iocache.overall_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency 2400system.iocache.overall_avg_miss_latency::total 119080.740371 # average overall miss latency 2401system.iocache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked 2402system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2403system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked 2404system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2405system.iocache.avg_blocked_cycles::no_mshrs 3.142857 # average number of cycles each access was blocked 2406system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2407system.iocache.writebacks::writebacks 36190 # number of writebacks 2408system.iocache.writebacks::total 36190 # number of writebacks 2409system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses 2410system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses 2411system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2412system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2413system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses 2414system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses 2415system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses 2416system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses 2417system.iocache.ReadReq_mshr_miss_latency::realview.ide 23671877 # number of ReadReq MSHR miss cycles 2418system.iocache.ReadReq_mshr_miss_latency::total 23671877 # number of ReadReq MSHR miss cycles 2419system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493982137 # number of WriteLineReq MSHR miss cycles 2420system.iocache.WriteLineReq_mshr_miss_latency::total 2493982137 # number of WriteLineReq MSHR miss cycles 2421system.iocache.demand_mshr_miss_latency::realview.ide 2517654014 # number of demand (read+write) MSHR miss cycles 2422system.iocache.demand_mshr_miss_latency::total 2517654014 # number of demand (read+write) MSHR miss cycles 2423system.iocache.overall_mshr_miss_latency::realview.ide 2517654014 # number of overall MSHR miss cycles 2424system.iocache.overall_mshr_miss_latency::total 2517654014 # number of overall MSHR miss cycles 2425system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2426system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2427system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2428system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2429system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2430system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2431system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2432system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2433system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 92830.890196 # average ReadReq mshr miss latency 2434system.iocache.ReadReq_avg_mshr_miss_latency::total 92830.890196 # average ReadReq mshr miss latency 2435system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68848.888499 # average WriteLineReq mshr miss latency 2436system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68848.888499 # average WriteLineReq mshr miss latency 2437system.iocache.demand_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency 2438system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency 2439system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency 2440system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency 2441system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2442system.l2c.tags.replacements 126308 # number of replacements 2443system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use 2444system.l2c.tags.total_refs 424315 # Total number of references to valid blocks. 2445system.l2c.tags.sampled_refs 190178 # Sample count of references to valid blocks. 2446system.l2c.tags.avg_refs 2.231147 # Average number of references to valid blocks. 2447system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2448system.l2c.tags.occ_blocks::writebacks 13637.426679 # Average occupied blocks per requestor 2449system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.018602 # Average occupied blocks per requestor 2450system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043991 # Average occupied blocks per requestor 2451system.l2c.tags.occ_blocks::cpu0.inst 7319.345128 # Average occupied blocks per requestor 2452system.l2c.tags.occ_blocks::cpu0.data 2841.087210 # Average occupied blocks per requestor 2453system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35552.012227 # Average occupied blocks per requestor 2454system.l2c.tags.occ_blocks::cpu1.inst 1437.607406 # Average occupied blocks per requestor 2455system.l2c.tags.occ_blocks::cpu1.data 447.669169 # Average occupied blocks per requestor 2456system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1777.834065 # Average occupied blocks per requestor 2457system.l2c.tags.occ_percent::writebacks 0.208091 # Average percentage of cache occupancy 2458system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy 2459system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 2460system.l2c.tags.occ_percent::cpu0.inst 0.111684 # Average percentage of cache occupancy 2461system.l2c.tags.occ_percent::cpu0.data 0.043352 # Average percentage of cache occupancy 2462system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.542481 # Average percentage of cache occupancy 2463system.l2c.tags.occ_percent::cpu1.inst 0.021936 # Average percentage of cache occupancy 2464system.l2c.tags.occ_percent::cpu1.data 0.006831 # Average percentage of cache occupancy 2465system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027128 # Average percentage of cache occupancy 2466system.l2c.tags.occ_percent::total 0.961564 # Average percentage of cache occupancy 2467system.l2c.tags.occ_task_id_blocks::1022 30519 # Occupied blocks per task id 2468system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 2469system.l2c.tags.occ_task_id_blocks::1024 33346 # Occupied blocks per task id 2470system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 2471system.l2c.tags.age_task_id_blocks_1022::2 165 # Occupied blocks per task id 2472system.l2c.tags.age_task_id_blocks_1022::3 4688 # Occupied blocks per task id 2473system.l2c.tags.age_task_id_blocks_1022::4 25665 # Occupied blocks per task id 2474system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 2475system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2476system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id 2477system.l2c.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id 2478system.l2c.tags.age_task_id_blocks_1024::3 2267 # Occupied blocks per task id 2479system.l2c.tags.age_task_id_blocks_1024::4 30712 # Occupied blocks per task id 2480system.l2c.tags.occ_task_id_percent::1022 0.465683 # Percentage of cache occupancy per task id 2481system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2482system.l2c.tags.occ_task_id_percent::1024 0.508820 # Percentage of cache occupancy per task id 2483system.l2c.tags.tag_accesses 5890164 # Number of tag accesses 2484system.l2c.tags.data_accesses 5890164 # Number of data accesses 2485system.l2c.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2486system.l2c.WritebackDirty_hits::writebacks 260994 # number of WritebackDirty hits 2487system.l2c.WritebackDirty_hits::total 260994 # number of WritebackDirty hits 2488system.l2c.UpgradeReq_hits::cpu0.data 31980 # number of UpgradeReq hits 2489system.l2c.UpgradeReq_hits::cpu1.data 2487 # number of UpgradeReq hits 2490system.l2c.UpgradeReq_hits::total 34467 # number of UpgradeReq hits 2491system.l2c.SCUpgradeReq_hits::cpu0.data 1985 # number of SCUpgradeReq hits 2492system.l2c.SCUpgradeReq_hits::cpu1.data 965 # number of SCUpgradeReq hits 2493system.l2c.SCUpgradeReq_hits::total 2950 # number of SCUpgradeReq hits 2494system.l2c.ReadExReq_hits::cpu0.data 3870 # number of ReadExReq hits 2495system.l2c.ReadExReq_hits::cpu1.data 1490 # number of ReadExReq hits 2496system.l2c.ReadExReq_hits::total 5360 # number of ReadExReq hits 2497system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 97 # number of ReadSharedReq hits 2498system.l2c.ReadSharedReq_hits::cpu0.itb.walker 76 # number of ReadSharedReq hits 2499system.l2c.ReadSharedReq_hits::cpu0.inst 27673 # number of ReadSharedReq hits 2500system.l2c.ReadSharedReq_hits::cpu0.data 45621 # number of ReadSharedReq hits 2501system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45892 # number of ReadSharedReq hits 2502system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 31 # number of ReadSharedReq hits 2503system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits 2504system.l2c.ReadSharedReq_hits::cpu1.inst 10962 # number of ReadSharedReq hits 2505system.l2c.ReadSharedReq_hits::cpu1.data 9208 # number of ReadSharedReq hits 2506system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5411 # number of ReadSharedReq hits 2507system.l2c.ReadSharedReq_hits::total 145008 # number of ReadSharedReq hits 2508system.l2c.demand_hits::cpu0.dtb.walker 97 # number of demand (read+write) hits 2509system.l2c.demand_hits::cpu0.itb.walker 76 # number of demand (read+write) hits 2510system.l2c.demand_hits::cpu0.inst 27673 # number of demand (read+write) hits 2511system.l2c.demand_hits::cpu0.data 49491 # number of demand (read+write) hits 2512system.l2c.demand_hits::cpu0.l2cache.prefetcher 45892 # number of demand (read+write) hits 2513system.l2c.demand_hits::cpu1.dtb.walker 31 # number of demand (read+write) hits 2514system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits 2515system.l2c.demand_hits::cpu1.inst 10962 # number of demand (read+write) hits 2516system.l2c.demand_hits::cpu1.data 10698 # number of demand (read+write) hits 2517system.l2c.demand_hits::cpu1.l2cache.prefetcher 5411 # number of demand (read+write) hits 2518system.l2c.demand_hits::total 150368 # number of demand (read+write) hits 2519system.l2c.overall_hits::cpu0.dtb.walker 97 # number of overall hits 2520system.l2c.overall_hits::cpu0.itb.walker 76 # number of overall hits 2521system.l2c.overall_hits::cpu0.inst 27673 # number of overall hits 2522system.l2c.overall_hits::cpu0.data 49491 # number of overall hits 2523system.l2c.overall_hits::cpu0.l2cache.prefetcher 45892 # number of overall hits 2524system.l2c.overall_hits::cpu1.dtb.walker 31 # number of overall hits 2525system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits 2526system.l2c.overall_hits::cpu1.inst 10962 # number of overall hits 2527system.l2c.overall_hits::cpu1.data 10698 # number of overall hits 2528system.l2c.overall_hits::cpu1.l2cache.prefetcher 5411 # number of overall hits 2529system.l2c.overall_hits::total 150368 # number of overall hits 2530system.l2c.UpgradeReq_misses::cpu0.data 8680 # number of UpgradeReq misses 2531system.l2c.UpgradeReq_misses::cpu1.data 2870 # number of UpgradeReq misses 2532system.l2c.UpgradeReq_misses::total 11550 # number of UpgradeReq misses 2533system.l2c.SCUpgradeReq_misses::cpu0.data 542 # number of SCUpgradeReq misses 2534system.l2c.SCUpgradeReq_misses::cpu1.data 1323 # number of SCUpgradeReq misses 2535system.l2c.SCUpgradeReq_misses::total 1865 # number of SCUpgradeReq misses 2536system.l2c.ReadExReq_misses::cpu0.data 11368 # number of ReadExReq misses 2537system.l2c.ReadExReq_misses::cpu1.data 8031 # number of ReadExReq misses 2538system.l2c.ReadExReq_misses::total 19399 # number of ReadExReq misses 2539system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 2540system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2541system.l2c.ReadSharedReq_misses::cpu0.inst 17607 # number of ReadSharedReq misses 2542system.l2c.ReadSharedReq_misses::cpu0.data 8862 # number of ReadSharedReq misses 2543system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq misses 2544system.l2c.ReadSharedReq_misses::cpu1.inst 2288 # number of ReadSharedReq misses 2545system.l2c.ReadSharedReq_misses::cpu1.data 856 # number of ReadSharedReq misses 2546system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq misses 2547system.l2c.ReadSharedReq_misses::total 169532 # number of ReadSharedReq misses 2548system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 2549system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2550system.l2c.demand_misses::cpu0.inst 17607 # number of demand (read+write) misses 2551system.l2c.demand_misses::cpu0.data 20230 # number of demand (read+write) misses 2552system.l2c.demand_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) misses 2553system.l2c.demand_misses::cpu1.inst 2288 # number of demand (read+write) misses 2554system.l2c.demand_misses::cpu1.data 8887 # number of demand (read+write) misses 2555system.l2c.demand_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) misses 2556system.l2c.demand_misses::total 188931 # number of demand (read+write) misses 2557system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 2558system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2559system.l2c.overall_misses::cpu0.inst 17607 # number of overall misses 2560system.l2c.overall_misses::cpu0.data 20230 # number of overall misses 2561system.l2c.overall_misses::cpu0.l2cache.prefetcher 133884 # number of overall misses 2562system.l2c.overall_misses::cpu1.inst 2288 # number of overall misses 2563system.l2c.overall_misses::cpu1.data 8887 # number of overall misses 2564system.l2c.overall_misses::cpu1.l2cache.prefetcher 6026 # number of overall misses 2565system.l2c.overall_misses::total 188931 # number of overall misses 2566system.l2c.UpgradeReq_miss_latency::cpu0.data 11274000 # number of UpgradeReq miss cycles 2567system.l2c.UpgradeReq_miss_latency::cpu1.data 4127500 # number of UpgradeReq miss cycles 2568system.l2c.UpgradeReq_miss_latency::total 15401500 # number of UpgradeReq miss cycles 2569system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1640500 # number of SCUpgradeReq miss cycles 2570system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1015500 # number of SCUpgradeReq miss cycles 2571system.l2c.SCUpgradeReq_miss_latency::total 2656000 # number of SCUpgradeReq miss cycles 2572system.l2c.ReadExReq_miss_latency::cpu0.data 1087660500 # number of ReadExReq miss cycles 2573system.l2c.ReadExReq_miss_latency::cpu1.data 661855000 # number of ReadExReq miss cycles 2574system.l2c.ReadExReq_miss_latency::total 1749515500 # number of ReadExReq miss cycles 2575system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles 2576system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles 2577system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles 2578system.l2c.ReadSharedReq_miss_latency::cpu0.data 776891500 # number of ReadSharedReq miss cycles 2579system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of ReadSharedReq miss cycles 2580system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles 2581system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles 2582system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles 2583system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles 2584system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles 2585system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles 2586system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles 2587system.l2c.demand_miss_latency::cpu0.data 1864552000 # number of demand (read+write) miss cycles 2588system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of demand (read+write) miss cycles 2589system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles 2590system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles 2591system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles 2592system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles 2593system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles 2594system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles 2595system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles 2596system.l2c.overall_miss_latency::cpu0.data 1864552000 # number of overall miss cycles 2597system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of overall miss cycles 2598system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles 2599system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles 2600system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles 2601system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles 2602system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses) 2603system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses) 2604system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses) 2605system.l2c.UpgradeReq_accesses::cpu1.data 5357 # number of UpgradeReq accesses(hits+misses) 2606system.l2c.UpgradeReq_accesses::total 46017 # number of UpgradeReq accesses(hits+misses) 2607system.l2c.SCUpgradeReq_accesses::cpu0.data 2527 # number of SCUpgradeReq accesses(hits+misses) 2608system.l2c.SCUpgradeReq_accesses::cpu1.data 2288 # number of SCUpgradeReq accesses(hits+misses) 2609system.l2c.SCUpgradeReq_accesses::total 4815 # number of SCUpgradeReq accesses(hits+misses) 2610system.l2c.ReadExReq_accesses::cpu0.data 15238 # number of ReadExReq accesses(hits+misses) 2611system.l2c.ReadExReq_accesses::cpu1.data 9521 # number of ReadExReq accesses(hits+misses) 2612system.l2c.ReadExReq_accesses::total 24759 # number of ReadExReq accesses(hits+misses) 2613system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 104 # number of ReadSharedReq accesses(hits+misses) 2614system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses) 2615system.l2c.ReadSharedReq_accesses::cpu0.inst 45280 # number of ReadSharedReq accesses(hits+misses) 2616system.l2c.ReadSharedReq_accesses::cpu0.data 54483 # number of ReadSharedReq accesses(hits+misses) 2617system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179776 # number of ReadSharedReq accesses(hits+misses) 2618system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 31 # number of ReadSharedReq accesses(hits+misses) 2619system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 37 # number of ReadSharedReq accesses(hits+misses) 2620system.l2c.ReadSharedReq_accesses::cpu1.inst 13250 # number of ReadSharedReq accesses(hits+misses) 2621system.l2c.ReadSharedReq_accesses::cpu1.data 10064 # number of ReadSharedReq accesses(hits+misses) 2622system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11437 # number of ReadSharedReq accesses(hits+misses) 2623system.l2c.ReadSharedReq_accesses::total 314540 # number of ReadSharedReq accesses(hits+misses) 2624system.l2c.demand_accesses::cpu0.dtb.walker 104 # number of demand (read+write) accesses 2625system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses 2626system.l2c.demand_accesses::cpu0.inst 45280 # number of demand (read+write) accesses 2627system.l2c.demand_accesses::cpu0.data 69721 # number of demand (read+write) accesses 2628system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179776 # number of demand (read+write) accesses 2629system.l2c.demand_accesses::cpu1.dtb.walker 31 # number of demand (read+write) accesses 2630system.l2c.demand_accesses::cpu1.itb.walker 37 # number of demand (read+write) accesses 2631system.l2c.demand_accesses::cpu1.inst 13250 # number of demand (read+write) accesses 2632system.l2c.demand_accesses::cpu1.data 19585 # number of demand (read+write) accesses 2633system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11437 # number of demand (read+write) accesses 2634system.l2c.demand_accesses::total 339299 # number of demand (read+write) accesses 2635system.l2c.overall_accesses::cpu0.dtb.walker 104 # number of overall (read+write) accesses 2636system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses 2637system.l2c.overall_accesses::cpu0.inst 45280 # number of overall (read+write) accesses 2638system.l2c.overall_accesses::cpu0.data 69721 # number of overall (read+write) accesses 2639system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179776 # number of overall (read+write) accesses 2640system.l2c.overall_accesses::cpu1.dtb.walker 31 # number of overall (read+write) accesses 2641system.l2c.overall_accesses::cpu1.itb.walker 37 # number of overall (read+write) accesses 2642system.l2c.overall_accesses::cpu1.inst 13250 # number of overall (read+write) accesses 2643system.l2c.overall_accesses::cpu1.data 19585 # number of overall (read+write) accesses 2644system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11437 # number of overall (read+write) accesses 2645system.l2c.overall_accesses::total 339299 # number of overall (read+write) accesses 2646system.l2c.UpgradeReq_miss_rate::cpu0.data 0.213478 # miss rate for UpgradeReq accesses 2647system.l2c.UpgradeReq_miss_rate::cpu1.data 0.535748 # miss rate for UpgradeReq accesses 2648system.l2c.UpgradeReq_miss_rate::total 0.250994 # miss rate for UpgradeReq accesses 2649system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.214484 # miss rate for SCUpgradeReq accesses 2650system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.578234 # miss rate for SCUpgradeReq accesses 2651system.l2c.SCUpgradeReq_miss_rate::total 0.387331 # miss rate for SCUpgradeReq accesses 2652system.l2c.ReadExReq_miss_rate::cpu0.data 0.746030 # miss rate for ReadExReq accesses 2653system.l2c.ReadExReq_miss_rate::cpu1.data 0.843504 # miss rate for ReadExReq accesses 2654system.l2c.ReadExReq_miss_rate::total 0.783513 # miss rate for ReadExReq accesses 2655system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for ReadSharedReq accesses 2656system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025641 # miss rate for ReadSharedReq accesses 2657system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.388847 # miss rate for ReadSharedReq accesses 2658system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162656 # miss rate for ReadSharedReq accesses 2659system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for ReadSharedReq accesses 2660system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.172679 # miss rate for ReadSharedReq accesses 2661system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.085056 # miss rate for ReadSharedReq accesses 2662system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for ReadSharedReq accesses 2663system.l2c.ReadSharedReq_miss_rate::total 0.538984 # miss rate for ReadSharedReq accesses 2664system.l2c.demand_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for demand accesses 2665system.l2c.demand_miss_rate::cpu0.itb.walker 0.025641 # miss rate for demand accesses 2666system.l2c.demand_miss_rate::cpu0.inst 0.388847 # miss rate for demand accesses 2667system.l2c.demand_miss_rate::cpu0.data 0.290156 # miss rate for demand accesses 2668system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for demand accesses 2669system.l2c.demand_miss_rate::cpu1.inst 0.172679 # miss rate for demand accesses 2670system.l2c.demand_miss_rate::cpu1.data 0.453766 # miss rate for demand accesses 2671system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for demand accesses 2672system.l2c.demand_miss_rate::total 0.556827 # miss rate for demand accesses 2673system.l2c.overall_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for overall accesses 2674system.l2c.overall_miss_rate::cpu0.itb.walker 0.025641 # miss rate for overall accesses 2675system.l2c.overall_miss_rate::cpu0.inst 0.388847 # miss rate for overall accesses 2676system.l2c.overall_miss_rate::cpu0.data 0.290156 # miss rate for overall accesses 2677system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for overall accesses 2678system.l2c.overall_miss_rate::cpu1.inst 0.172679 # miss rate for overall accesses 2679system.l2c.overall_miss_rate::cpu1.data 0.453766 # miss rate for overall accesses 2680system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for overall accesses 2681system.l2c.overall_miss_rate::total 0.556827 # miss rate for overall accesses 2682system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1298.847926 # average UpgradeReq miss latency 2683system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1438.153310 # average UpgradeReq miss latency 2684system.l2c.UpgradeReq_avg_miss_latency::total 1333.463203 # average UpgradeReq miss latency 2685system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3026.752768 # average SCUpgradeReq miss latency 2686system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 767.573696 # average SCUpgradeReq miss latency 2687system.l2c.SCUpgradeReq_avg_miss_latency::total 1424.128686 # average SCUpgradeReq miss latency 2688system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95677.383885 # average ReadExReq miss latency 2689system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82412.526460 # average ReadExReq miss latency 2690system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 # average ReadExReq miss latency 2691system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency 2692system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency 2693system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency 2694system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency 2695system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency 2696system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency 2697system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency 2698system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency 2699system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency 2700system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency 2701system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency 2702system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency 2703system.l2c.demand_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency 2704system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency 2705system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency 2706system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency 2707system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency 2708system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency 2709system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency 2710system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency 2711system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency 2712system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency 2713system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency 2714system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency 2715system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency 2716system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency 2717system.l2c.overall_avg_miss_latency::total 94581.324341 # average overall miss latency 2718system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2719system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2720system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2721system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2722system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2723system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2724system.l2c.writebacks::writebacks 98955 # number of writebacks 2725system.l2c.writebacks::total 98955 # number of writebacks 2726system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits 2727system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits 2728system.l2c.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 2729system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 2730system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits 2731system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 2732system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 2733system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits 2734system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits 2735system.l2c.CleanEvict_mshr_misses::writebacks 3251 # number of CleanEvict MSHR misses 2736system.l2c.CleanEvict_mshr_misses::total 3251 # number of CleanEvict MSHR misses 2737system.l2c.UpgradeReq_mshr_misses::cpu0.data 8680 # number of UpgradeReq MSHR misses 2738system.l2c.UpgradeReq_mshr_misses::cpu1.data 2870 # number of UpgradeReq MSHR misses 2739system.l2c.UpgradeReq_mshr_misses::total 11550 # number of UpgradeReq MSHR misses 2740system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 542 # number of SCUpgradeReq MSHR misses 2741system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1323 # number of SCUpgradeReq MSHR misses 2742system.l2c.SCUpgradeReq_mshr_misses::total 1865 # number of SCUpgradeReq MSHR misses 2743system.l2c.ReadExReq_mshr_misses::cpu0.data 11368 # number of ReadExReq MSHR misses 2744system.l2c.ReadExReq_mshr_misses::cpu1.data 8031 # number of ReadExReq MSHR misses 2745system.l2c.ReadExReq_mshr_misses::total 19399 # number of ReadExReq MSHR misses 2746system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses 2747system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2748system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17603 # number of ReadSharedReq MSHR misses 2749system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8862 # number of ReadSharedReq MSHR misses 2750system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq MSHR misses 2751system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2278 # number of ReadSharedReq MSHR misses 2752system.l2c.ReadSharedReq_mshr_misses::cpu1.data 856 # number of ReadSharedReq MSHR misses 2753system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq MSHR misses 2754system.l2c.ReadSharedReq_mshr_misses::total 169518 # number of ReadSharedReq MSHR misses 2755system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses 2756system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2757system.l2c.demand_mshr_misses::cpu0.inst 17603 # number of demand (read+write) MSHR misses 2758system.l2c.demand_mshr_misses::cpu0.data 20230 # number of demand (read+write) MSHR misses 2759system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) MSHR misses 2760system.l2c.demand_mshr_misses::cpu1.inst 2278 # number of demand (read+write) MSHR misses 2761system.l2c.demand_mshr_misses::cpu1.data 8887 # number of demand (read+write) MSHR misses 2762system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) MSHR misses 2763system.l2c.demand_mshr_misses::total 188917 # number of demand (read+write) MSHR misses 2764system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses 2765system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2766system.l2c.overall_mshr_misses::cpu0.inst 17603 # number of overall MSHR misses 2767system.l2c.overall_mshr_misses::cpu0.data 20230 # number of overall MSHR misses 2768system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 133884 # number of overall MSHR misses 2769system.l2c.overall_mshr_misses::cpu1.inst 2278 # number of overall MSHR misses 2770system.l2c.overall_mshr_misses::cpu1.data 8887 # number of overall MSHR misses 2771system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6026 # number of overall MSHR misses 2772system.l2c.overall_mshr_misses::total 188917 # number of overall MSHR misses 2773system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 2774system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable 2775system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2776system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3092 # number of ReadReq MSHR uncacheable 2777system.l2c.ReadReq_mshr_uncacheable::total 44083 # number of ReadReq MSHR uncacheable 2778system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable 2779system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable 2780system.l2c.WriteReq_mshr_uncacheable::total 30913 # number of WriteReq MSHR uncacheable 2781system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 2782system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses 2783system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2784system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5542 # number of overall MSHR uncacheable misses 2785system.l2c.overall_mshr_uncacheable_misses::total 74996 # number of overall MSHR uncacheable misses 2786system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 208012000 # number of UpgradeReq MSHR miss cycles 2787system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 65421000 # number of UpgradeReq MSHR miss cycles 2788system.l2c.UpgradeReq_mshr_miss_latency::total 273433000 # number of UpgradeReq MSHR miss cycles 2789system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 13993000 # number of SCUpgradeReq MSHR miss cycles 2790system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 32976000 # number of SCUpgradeReq MSHR miss cycles 2791system.l2c.SCUpgradeReq_mshr_miss_latency::total 46969000 # number of SCUpgradeReq MSHR miss cycles 2792system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973980500 # number of ReadExReq MSHR miss cycles 2793system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 581545000 # number of ReadExReq MSHR miss cycles 2794system.l2c.ReadExReq_mshr_miss_latency::total 1555525500 # number of ReadExReq MSHR miss cycles 2795system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 633500 # number of ReadSharedReq MSHR miss cycles 2796system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles 2797system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles 2798system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688271500 # number of ReadSharedReq MSHR miss cycles 2799system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of ReadSharedReq MSHR miss cycles 2800system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 166489000 # number of ReadSharedReq MSHR miss cycles 2801system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68690501 # number of ReadSharedReq MSHR miss cycles 2802system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of ReadSharedReq MSHR miss cycles 2803system.l2c.ReadSharedReq_mshr_miss_latency::total 14423934199 # number of ReadSharedReq MSHR miss cycles 2804system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles 2805system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles 2806system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles 2807system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles 2808system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles 2809system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles 2810system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles 2811system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles 2812system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles 2813system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles 2814system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles 2815system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles 2816system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles 2817system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles 2818system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles 2819system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles 2820system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles 2821system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles 2822system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles 2823system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles 2824system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles 2825system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362609000 # number of ReadReq MSHR uncacheable cycles 2826system.l2c.ReadReq_mshr_uncacheable_latency::total 6757114500 # number of ReadReq MSHR uncacheable cycles 2827system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles 2828system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801887500 # number of overall MSHR uncacheable cycles 2829system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles 2830system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362609000 # number of overall MSHR uncacheable cycles 2831system.l2c.overall_mshr_uncacheable_latency::total 6757114500 # number of overall MSHR uncacheable cycles 2832system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2833system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2834system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.213478 # mshr miss rate for UpgradeReq accesses 2835system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.535748 # mshr miss rate for UpgradeReq accesses 2836system.l2c.UpgradeReq_mshr_miss_rate::total 0.250994 # mshr miss rate for UpgradeReq accesses 2837system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.214484 # mshr miss rate for SCUpgradeReq accesses 2838system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.578234 # mshr miss rate for SCUpgradeReq accesses 2839system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.387331 # mshr miss rate for SCUpgradeReq accesses 2840system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746030 # mshr miss rate for ReadExReq accesses 2841system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.843504 # mshr miss rate for ReadExReq accesses 2842system.l2c.ReadExReq_mshr_miss_rate::total 0.783513 # mshr miss rate for ReadExReq accesses 2843system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for ReadSharedReq accesses 2844system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses 2845system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for ReadSharedReq accesses 2846system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162656 # mshr miss rate for ReadSharedReq accesses 2847system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for ReadSharedReq accesses 2848system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for ReadSharedReq accesses 2849system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.085056 # mshr miss rate for ReadSharedReq accesses 2850system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for ReadSharedReq accesses 2851system.l2c.ReadSharedReq_mshr_miss_rate::total 0.538939 # mshr miss rate for ReadSharedReq accesses 2852system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for demand accesses 2853system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for demand accesses 2854system.l2c.demand_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for demand accesses 2855system.l2c.demand_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for demand accesses 2856system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for demand accesses 2857system.l2c.demand_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for demand accesses 2858system.l2c.demand_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for demand accesses 2859system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for demand accesses 2860system.l2c.demand_mshr_miss_rate::total 0.556786 # mshr miss rate for demand accesses 2861system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for overall accesses 2862system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for overall accesses 2863system.l2c.overall_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for overall accesses 2864system.l2c.overall_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for overall accesses 2865system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for overall accesses 2866system.l2c.overall_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for overall accesses 2867system.l2c.overall_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for overall accesses 2868system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for overall accesses 2869system.l2c.overall_mshr_miss_rate::total 0.556786 # mshr miss rate for overall accesses 2870system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23964.516129 # average UpgradeReq mshr miss latency 2871system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22794.773519 # average UpgradeReq mshr miss latency 2872system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23673.852814 # average UpgradeReq mshr miss latency 2873system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25817.343173 # average SCUpgradeReq mshr miss latency 2874system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24925.170068 # average SCUpgradeReq mshr miss latency 2875system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25184.450402 # average SCUpgradeReq mshr miss latency 2876system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85677.383885 # average ReadExReq mshr miss latency 2877system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72412.526460 # average ReadExReq mshr miss latency 2878system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 # average ReadExReq mshr miss latency 2879system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency 2880system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency 2881system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency 2882system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency 2883system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency 2884system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency 2885system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency 2886system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency 2887system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency 2888system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency 2889system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency 2890system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency 2891system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency 2892system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency 2893system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency 2894system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency 2895system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency 2896system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency 2897system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency 2898system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency 2899system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency 2900system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency 2901system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency 2902system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency 2903system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency 2904system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency 2905system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency 2906system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency 2907system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency 2908system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency 2909system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117273.285899 # average ReadReq mshr uncacheable latency 2910system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153281.639181 # average ReadReq mshr uncacheable latency 2911system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency 2912system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96288.897187 # average overall mshr uncacheable latency 2913system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency 2914system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.267412 # average overall mshr uncacheable latency 2915system.l2c.overall_avg_mshr_uncacheable_latency::total 90099.665315 # average overall mshr uncacheable latency 2916system.membus.snoop_filter.tot_requests 512702 # Total number of requests made to the snoop filter. 2917system.membus.snoop_filter.hit_single_requests 293222 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2918system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2919system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 2920system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2921system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2922system.membus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2923system.membus.trans_dist::ReadReq 44083 # Transaction distribution 2924system.membus.trans_dist::ReadResp 213856 # Transaction distribution 2925system.membus.trans_dist::WriteReq 30913 # Transaction distribution 2926system.membus.trans_dist::WriteResp 30913 # Transaction distribution 2927system.membus.trans_dist::WritebackDirty 135145 # Transaction distribution 2928system.membus.trans_dist::CleanEvict 15700 # Transaction distribution 2929system.membus.trans_dist::UpgradeReq 75854 # Transaction distribution 2930system.membus.trans_dist::SCUpgradeReq 40085 # Transaction distribution 2931system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 2932system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 2933system.membus.trans_dist::ReadExReq 39863 # Transaction distribution 2934system.membus.trans_dist::ReadExResp 19313 # Transaction distribution 2935system.membus.trans_dist::ReadSharedReq 169773 # Transaction distribution 2936system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2937system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) 2938system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2939system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes) 2940system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656506 # Packet count per connected master and slave (bytes) 2941system.membus.pkt_count_system.l2c.mem_side::total 778196 # Packet count per connected master and slave (bytes) 2942system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) 2943system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) 2944system.membus.pkt_count::total 851135 # Packet count per connected master and slave (bytes) 2945system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) 2946system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2947system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes) 2948system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18452748 # Cumulative packet size per connected master and slave (bytes) 2949system.membus.pkt_size_system.l2c.mem_side::total 18643092 # Cumulative packet size per connected master and slave (bytes) 2950system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2951system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2952system.membus.pkt_size::total 20960212 # Cumulative packet size per connected master and slave (bytes) 2953system.membus.snoops 123593 # Total snoops (count) 2954system.membus.snoop_fanout::samples 436796 # Request fanout histogram 2955system.membus.snoop_fanout::mean 0.011900 # Request fanout histogram 2956system.membus.snoop_fanout::stdev 0.108438 # Request fanout histogram 2957system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2958system.membus.snoop_fanout::0 431598 98.81% 98.81% # Request fanout histogram 2959system.membus.snoop_fanout::1 5198 1.19% 100.00% # Request fanout histogram 2960system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2961system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2962system.membus.snoop_fanout::min_value 0 # Request fanout histogram 2963system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2964system.membus.snoop_fanout::total 436796 # Request fanout histogram 2965system.membus.reqLayer0.occupancy 88259500 # Layer occupancy (ticks) 2966system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2967system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2968system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2969system.membus.reqLayer2.occupancy 11350000 # Layer occupancy (ticks) 2970system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2971system.membus.reqLayer5.occupancy 980369236 # Layer occupancy (ticks) 2972system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2973system.membus.respLayer2.occupancy 1108695304 # Layer occupancy (ticks) 2974system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2975system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks) 2976system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2977system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2978system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2979system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2980system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2981system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2982system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2983system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2984system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2985system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2986system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2987system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2988system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2989system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 2990system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2991system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 2992system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2993system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2994system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2995system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2996system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2997system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2998system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2999system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3000system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3001system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3002system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3003system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3004system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3005system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3006system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3007system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3008system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3009system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3010system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3011system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3012system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3013system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3014system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3015system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3016system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3017system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3018system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3019system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3020system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3021system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 3022system.realview.ethernet.droppedPackets 0 # number of packets dropped 3023system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3024system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3025system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3026system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3027system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3028system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3029system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3030system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3031system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3032system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3033system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3034system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3035system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3036system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3037system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3038system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3039system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3040system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3041system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3042system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3043system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3044system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3045system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3046system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter. 3047system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3048system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3049system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter. 3050system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3051system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3052system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869788970000 # Cumulative time (in ticks) in various power states 3053system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution 3054system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution 3055system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution 3056system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution 3057system.toL2Bus.trans_dist::WritebackDirty 359949 # Transaction distribution 3058system.toL2Bus.trans_dist::CleanEvict 109182 # Transaction distribution 3059system.toL2Bus.trans_dist::UpgradeReq 110235 # Transaction distribution 3060system.toL2Bus.trans_dist::SCUpgradeReq 43035 # Transaction distribution 3061system.toL2Bus.trans_dist::UpgradeResp 153270 # Transaction distribution 3062system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution 3063system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution 3064system.toL2Bus.trans_dist::ReadExReq 50915 # Transaction distribution 3065system.toL2Bus.trans_dist::ReadExResp 50915 # Transaction distribution 3066system.toL2Bus.trans_dist::ReadSharedReq 433367 # Transaction distribution 3067system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution 3068system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224504 # Packet count per connected master and slave (bytes) 3069system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 296079 # Packet count per connected master and slave (bytes) 3070system.toL2Bus.pkt_count::total 1520583 # Packet count per connected master and slave (bytes) 3071system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33710224 # Cumulative packet size per connected master and slave (bytes) 3072system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4970948 # Cumulative packet size per connected master and slave (bytes) 3073system.toL2Bus.pkt_size::total 38681172 # Cumulative packet size per connected master and slave (bytes) 3074system.toL2Bus.snoops 378680 # Total snoops (count) 3075system.toL2Bus.snoop_fanout::samples 843567 # Request fanout histogram 3076system.toL2Bus.snoop_fanout::mean 0.376795 # Request fanout histogram 3077system.toL2Bus.snoop_fanout::stdev 0.486500 # Request fanout histogram 3078system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3079system.toL2Bus.snoop_fanout::0 526500 62.41% 62.41% # Request fanout histogram 3080system.toL2Bus.snoop_fanout::1 316282 37.49% 99.91% # Request fanout histogram 3081system.toL2Bus.snoop_fanout::2 785 0.09% 100.00% # Request fanout histogram 3082system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3083system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3084system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3085system.toL2Bus.snoop_fanout::total 843567 # Request fanout histogram 3086system.toL2Bus.reqLayer0.occupancy 877207087 # Layer occupancy (ticks) 3087system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3088system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks) 3089system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3090system.toL2Bus.respLayer0.occupancy 640962681 # Layer occupancy (ticks) 3091system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3092system.toL2Bus.respLayer1.occupancy 223907403 # Layer occupancy (ticks) 3093system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3094 3095---------- End Simulation Statistics ----------