1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.869789 # Number of seconds simulated
4sim_ticks 2869788970000 # Number of ticks simulated
5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.869789 # Number of seconds simulated
4sim_ticks 2869788970000 # Number of ticks simulated
5final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 543935 # Simulator instruction rate (inst/s)
8host_op_rate 657921 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 11865725522 # Simulator tick rate (ticks/s)
10host_mem_usage 611884 # Number of bytes of host memory used
11host_seconds 241.86 # Real time elapsed on the host
12sim_insts 131553572 # Number of instructions simulated
13sim_ops 159121620 # Number of ops (including micro ops) simulated
| 7host_inst_rate 480288 # Simulator instruction rate (inst/s)
8host_op_rate 580935 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 10477281069 # Simulator tick rate (ticks/s)
10host_mem_usage 611892 # Number of bytes of host memory used
11host_seconds 273.91 # Real time elapsed on the host
12sim_insts 131553574 # Number of instructions simulated
13sim_ops 159121622 # Number of ops (including micro ops) simulated
|
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.data 567572 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.l2cache.prefetcher 385664 # Number of bytes read from this memory
24system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
25system.physmem.bytes_read::total 12103024 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 1162532 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 146452 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::total 1308984 # Number of instructions bytes read from this memory
29system.physmem.bytes_written::writebacks 8649280 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
32system.physmem.bytes_written::total 8666844 # Number of bytes written to this memory
33system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.inst 26618 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.data 20544 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.l2cache.prefetcher 133714 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.inst 2443 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.data 8889 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.l2cache.prefetcher 6026 # Number of read requests responded to by this memory
41system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 198258 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 135145 # Number of write requests responded to by this memory
44system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
45system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
46system.physmem.num_writes::total 139536 # Number of write requests responded to by this memory
47system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.inst 405093 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.data 446574 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.l2cache.prefetcher 2981995 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.inst 51032 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.data 197775 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.l2cache.prefetcher 134388 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::total 4217392 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_inst_read::cpu0.inst 405093 # Instruction read bandwidth from this memory (bytes/s)
58system.physmem.bw_inst_read::cpu1.inst 51032 # Instruction read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::total 456126 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_write::writebacks 3013908 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::total 3020028 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_total::writebacks 3013908 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.inst 405093 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.data 452680 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.l2cache.prefetcher 2981995 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.inst 51032 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.data 197789 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu1.l2cache.prefetcher 134388 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::total 7237420 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.readReqs 198258 # Number of read requests accepted
76system.physmem.writeReqs 139536 # Number of write requests accepted
77system.physmem.readBursts 198258 # Number of DRAM read bursts, including those serviced by the write queue
78system.physmem.writeBursts 139536 # Number of DRAM write bursts, including those merged in the write queue
79system.physmem.bytesReadDRAM 12678976 # Total number of bytes read from DRAM
80system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue
81system.physmem.bytesWritten 8679232 # Total number of bytes written to DRAM
82system.physmem.bytesReadSys 12103024 # Total read bytes from the system interface side
83system.physmem.bytesWrittenSys 8666844 # Total written bytes from the system interface side
84system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue
85system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
86system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
87system.physmem.perBankRdBursts::0 11529 # Per bank write bursts
88system.physmem.perBankRdBursts::1 11853 # Per bank write bursts
89system.physmem.perBankRdBursts::2 12105 # Per bank write bursts
90system.physmem.perBankRdBursts::3 12154 # Per bank write bursts
91system.physmem.perBankRdBursts::4 20931 # Per bank write bursts
92system.physmem.perBankRdBursts::5 12788 # Per bank write bursts
93system.physmem.perBankRdBursts::6 12012 # Per bank write bursts
94system.physmem.perBankRdBursts::7 12170 # Per bank write bursts
95system.physmem.perBankRdBursts::8 12327 # Per bank write bursts
96system.physmem.perBankRdBursts::9 12530 # Per bank write bursts
97system.physmem.perBankRdBursts::10 11492 # Per bank write bursts
98system.physmem.perBankRdBursts::11 10989 # Per bank write bursts
99system.physmem.perBankRdBursts::12 11634 # Per bank write bursts
100system.physmem.perBankRdBursts::13 11866 # Per bank write bursts
101system.physmem.perBankRdBursts::14 10750 # Per bank write bursts
102system.physmem.perBankRdBursts::15 10979 # Per bank write bursts
103system.physmem.perBankWrBursts::0 8343 # Per bank write bursts
104system.physmem.perBankWrBursts::1 8774 # Per bank write bursts
105system.physmem.perBankWrBursts::2 9050 # Per bank write bursts
106system.physmem.perBankWrBursts::3 8765 # Per bank write bursts
107system.physmem.perBankWrBursts::4 8633 # Per bank write bursts
108system.physmem.perBankWrBursts::5 9228 # Per bank write bursts
109system.physmem.perBankWrBursts::6 8690 # Per bank write bursts
110system.physmem.perBankWrBursts::7 8516 # Per bank write bursts
111system.physmem.perBankWrBursts::8 8766 # Per bank write bursts
112system.physmem.perBankWrBursts::9 8956 # Per bank write bursts
113system.physmem.perBankWrBursts::10 8280 # Per bank write bursts
114system.physmem.perBankWrBursts::11 8060 # Per bank write bursts
115system.physmem.perBankWrBursts::12 8431 # Per bank write bursts
116system.physmem.perBankWrBursts::13 8106 # Per bank write bursts
117system.physmem.perBankWrBursts::14 7529 # Per bank write bursts
118system.physmem.perBankWrBursts::15 7486 # Per bank write bursts
119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
120system.physmem.numWrRetry 45 # Number of times write queue was full causing retry
121system.physmem.totGap 2869788469000 # Total gap between requests
122system.physmem.readPktSize::0 0 # Read request sizes (log2)
123system.physmem.readPktSize::1 0 # Read request sizes (log2)
124system.physmem.readPktSize::2 9732 # Read request sizes (log2)
125system.physmem.readPktSize::3 28 # Read request sizes (log2)
126system.physmem.readPktSize::4 0 # Read request sizes (log2)
127system.physmem.readPktSize::5 0 # Read request sizes (log2)
128system.physmem.readPktSize::6 188498 # Read request sizes (log2)
129system.physmem.writePktSize::0 0 # Write request sizes (log2)
130system.physmem.writePktSize::1 0 # Write request sizes (log2)
131system.physmem.writePktSize::2 4391 # Write request sizes (log2)
132system.physmem.writePktSize::3 0 # Write request sizes (log2)
133system.physmem.writePktSize::4 0 # Write request sizes (log2)
134system.physmem.writePktSize::5 0 # Write request sizes (log2)
135system.physmem.writePktSize::6 135145 # Write request sizes (log2)
136system.physmem.rdQLenPdf::0 138706 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::1 15839 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::2 10261 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::3 8725 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::4 6930 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::5 5461 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::6 4641 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::7 3898 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::8 3401 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::9 95 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::10 62 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::11 46 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::13 12 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
168system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::15 2819 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::16 3840 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::18 5706 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::19 6587 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::20 6581 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::21 7205 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::22 7662 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::23 8640 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::24 8482 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::25 9948 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::26 10382 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::28 8458 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::29 9785 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::30 8058 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::31 7351 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::32 7133 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::36 141 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::42 177 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::46 192 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::47 145 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::48 96 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::50 116 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::52 72 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::53 55 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see
232system.physmem.bytesPerActivate::samples 89189 # Bytes accessed per row activation
233system.physmem.bytesPerActivate::mean 239.470607 # Bytes accessed per row activation
234system.physmem.bytesPerActivate::gmean 135.176312 # Bytes accessed per row activation
235system.physmem.bytesPerActivate::stdev 302.792926 # Bytes accessed per row activation
236system.physmem.bytesPerActivate::0-127 47900 53.71% 53.71% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::128-255 17682 19.83% 73.53% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::256-383 5838 6.55% 80.08% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::384-511 3495 3.92% 84.00% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::512-639 2471 2.77% 86.77% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::640-767 1457 1.63% 88.40% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::896-1023 998 1.12% 90.69% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::1024-1151 8300 9.31% 100.00% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::total 89189 # Bytes accessed per row activation
246system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes
247system.physmem.rdPerTurnAround::mean 29.638989 # Reads before turning the bus around for writes
248system.physmem.rdPerTurnAround::stdev 578.089254 # Reads before turning the bus around for writes
249system.physmem.rdPerTurnAround::0-2047 6683 99.99% 99.99% # Reads before turning the bus around for writes
250system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes
252system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::mean 20.289198 # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::gmean 18.751921 # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::stdev 12.518584 # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::16-19 5662 84.71% 84.71% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::20-23 280 4.19% 88.90% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::24-27 70 1.05% 89.95% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::28-31 44 0.66% 90.60% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::32-35 285 4.26% 94.87% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::36-39 29 0.43% 95.30% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::40-43 28 0.42% 95.72% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::44-47 27 0.40% 96.13% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::48-51 17 0.25% 96.38% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::52-55 10 0.15% 96.53% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::56-59 5 0.07% 96.60% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::60-63 9 0.13% 96.74% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::64-67 159 2.38% 99.12% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::68-71 2 0.03% 99.15% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::72-75 11 0.16% 99.31% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::76-79 1 0.01% 99.33% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::80-83 9 0.13% 99.46% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::100-103 1 0.01% 99.54% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::120-123 2 0.03% 99.66% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::128-131 8 0.12% 99.78% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::132-135 5 0.07% 99.85% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::140-143 1 0.01% 99.87% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::148-151 2 0.03% 99.90% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads
| 14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.data 567572 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.l2cache.prefetcher 385664 # Number of bytes read from this memory
24system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
25system.physmem.bytes_read::total 12103024 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 1162532 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 146452 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::total 1308984 # Number of instructions bytes read from this memory
29system.physmem.bytes_written::writebacks 8649280 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
32system.physmem.bytes_written::total 8666844 # Number of bytes written to this memory
33system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.inst 26618 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.data 20544 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.l2cache.prefetcher 133714 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.inst 2443 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.data 8889 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.l2cache.prefetcher 6026 # Number of read requests responded to by this memory
41system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 198258 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 135145 # Number of write requests responded to by this memory
44system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
45system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
46system.physmem.num_writes::total 139536 # Number of write requests responded to by this memory
47system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.inst 405093 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.data 446574 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.l2cache.prefetcher 2981995 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.inst 51032 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.data 197775 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.l2cache.prefetcher 134388 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::total 4217392 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_inst_read::cpu0.inst 405093 # Instruction read bandwidth from this memory (bytes/s)
58system.physmem.bw_inst_read::cpu1.inst 51032 # Instruction read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::total 456126 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_write::writebacks 3013908 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::total 3020028 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_total::writebacks 3013908 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.inst 405093 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.data 452680 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.l2cache.prefetcher 2981995 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.inst 51032 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.data 197789 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu1.l2cache.prefetcher 134388 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::total 7237420 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.readReqs 198258 # Number of read requests accepted
76system.physmem.writeReqs 139536 # Number of write requests accepted
77system.physmem.readBursts 198258 # Number of DRAM read bursts, including those serviced by the write queue
78system.physmem.writeBursts 139536 # Number of DRAM write bursts, including those merged in the write queue
79system.physmem.bytesReadDRAM 12678976 # Total number of bytes read from DRAM
80system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue
81system.physmem.bytesWritten 8679232 # Total number of bytes written to DRAM
82system.physmem.bytesReadSys 12103024 # Total read bytes from the system interface side
83system.physmem.bytesWrittenSys 8666844 # Total written bytes from the system interface side
84system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue
85system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
86system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
87system.physmem.perBankRdBursts::0 11529 # Per bank write bursts
88system.physmem.perBankRdBursts::1 11853 # Per bank write bursts
89system.physmem.perBankRdBursts::2 12105 # Per bank write bursts
90system.physmem.perBankRdBursts::3 12154 # Per bank write bursts
91system.physmem.perBankRdBursts::4 20931 # Per bank write bursts
92system.physmem.perBankRdBursts::5 12788 # Per bank write bursts
93system.physmem.perBankRdBursts::6 12012 # Per bank write bursts
94system.physmem.perBankRdBursts::7 12170 # Per bank write bursts
95system.physmem.perBankRdBursts::8 12327 # Per bank write bursts
96system.physmem.perBankRdBursts::9 12530 # Per bank write bursts
97system.physmem.perBankRdBursts::10 11492 # Per bank write bursts
98system.physmem.perBankRdBursts::11 10989 # Per bank write bursts
99system.physmem.perBankRdBursts::12 11634 # Per bank write bursts
100system.physmem.perBankRdBursts::13 11866 # Per bank write bursts
101system.physmem.perBankRdBursts::14 10750 # Per bank write bursts
102system.physmem.perBankRdBursts::15 10979 # Per bank write bursts
103system.physmem.perBankWrBursts::0 8343 # Per bank write bursts
104system.physmem.perBankWrBursts::1 8774 # Per bank write bursts
105system.physmem.perBankWrBursts::2 9050 # Per bank write bursts
106system.physmem.perBankWrBursts::3 8765 # Per bank write bursts
107system.physmem.perBankWrBursts::4 8633 # Per bank write bursts
108system.physmem.perBankWrBursts::5 9228 # Per bank write bursts
109system.physmem.perBankWrBursts::6 8690 # Per bank write bursts
110system.physmem.perBankWrBursts::7 8516 # Per bank write bursts
111system.physmem.perBankWrBursts::8 8766 # Per bank write bursts
112system.physmem.perBankWrBursts::9 8956 # Per bank write bursts
113system.physmem.perBankWrBursts::10 8280 # Per bank write bursts
114system.physmem.perBankWrBursts::11 8060 # Per bank write bursts
115system.physmem.perBankWrBursts::12 8431 # Per bank write bursts
116system.physmem.perBankWrBursts::13 8106 # Per bank write bursts
117system.physmem.perBankWrBursts::14 7529 # Per bank write bursts
118system.physmem.perBankWrBursts::15 7486 # Per bank write bursts
119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
120system.physmem.numWrRetry 45 # Number of times write queue was full causing retry
121system.physmem.totGap 2869788469000 # Total gap between requests
122system.physmem.readPktSize::0 0 # Read request sizes (log2)
123system.physmem.readPktSize::1 0 # Read request sizes (log2)
124system.physmem.readPktSize::2 9732 # Read request sizes (log2)
125system.physmem.readPktSize::3 28 # Read request sizes (log2)
126system.physmem.readPktSize::4 0 # Read request sizes (log2)
127system.physmem.readPktSize::5 0 # Read request sizes (log2)
128system.physmem.readPktSize::6 188498 # Read request sizes (log2)
129system.physmem.writePktSize::0 0 # Write request sizes (log2)
130system.physmem.writePktSize::1 0 # Write request sizes (log2)
131system.physmem.writePktSize::2 4391 # Write request sizes (log2)
132system.physmem.writePktSize::3 0 # Write request sizes (log2)
133system.physmem.writePktSize::4 0 # Write request sizes (log2)
134system.physmem.writePktSize::5 0 # Write request sizes (log2)
135system.physmem.writePktSize::6 135145 # Write request sizes (log2)
136system.physmem.rdQLenPdf::0 138706 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::1 15839 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::2 10261 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::3 8725 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::4 6930 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::5 5461 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::6 4641 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::7 3898 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::8 3401 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::9 95 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::10 62 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::11 46 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::13 12 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
168system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::15 2819 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::16 3840 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::18 5706 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::19 6587 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::20 6581 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::21 7205 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::22 7662 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::23 8640 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::24 8482 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::25 9948 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::26 10382 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::27 8582 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::28 8458 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::29 9785 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::30 8058 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::31 7351 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::32 7133 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::34 227 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::36 141 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::38 150 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::42 177 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::46 192 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::47 145 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::48 96 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::50 116 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::52 72 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::53 55 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see
232system.physmem.bytesPerActivate::samples 89189 # Bytes accessed per row activation
233system.physmem.bytesPerActivate::mean 239.470607 # Bytes accessed per row activation
234system.physmem.bytesPerActivate::gmean 135.176312 # Bytes accessed per row activation
235system.physmem.bytesPerActivate::stdev 302.792926 # Bytes accessed per row activation
236system.physmem.bytesPerActivate::0-127 47900 53.71% 53.71% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::128-255 17682 19.83% 73.53% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::256-383 5838 6.55% 80.08% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::384-511 3495 3.92% 84.00% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::512-639 2471 2.77% 86.77% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::640-767 1457 1.63% 88.40% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::896-1023 998 1.12% 90.69% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::1024-1151 8300 9.31% 100.00% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::total 89189 # Bytes accessed per row activation
246system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes
247system.physmem.rdPerTurnAround::mean 29.638989 # Reads before turning the bus around for writes
248system.physmem.rdPerTurnAround::stdev 578.089254 # Reads before turning the bus around for writes
249system.physmem.rdPerTurnAround::0-2047 6683 99.99% 99.99% # Reads before turning the bus around for writes
250system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes
252system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::mean 20.289198 # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::gmean 18.751921 # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::stdev 12.518584 # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::16-19 5662 84.71% 84.71% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::20-23 280 4.19% 88.90% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::24-27 70 1.05% 89.95% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::28-31 44 0.66% 90.60% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::32-35 285 4.26% 94.87% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::36-39 29 0.43% 95.30% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::40-43 28 0.42% 95.72% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::44-47 27 0.40% 96.13% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::48-51 17 0.25% 96.38% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::52-55 10 0.15% 96.53% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::56-59 5 0.07% 96.60% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::60-63 9 0.13% 96.74% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::64-67 159 2.38% 99.12% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::68-71 2 0.03% 99.15% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::72-75 11 0.16% 99.31% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::76-79 1 0.01% 99.33% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::80-83 9 0.13% 99.46% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::100-103 1 0.01% 99.54% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::120-123 2 0.03% 99.66% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::128-131 8 0.12% 99.78% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::132-135 5 0.07% 99.85% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::140-143 1 0.01% 99.87% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::148-151 2 0.03% 99.90% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads
|
289system.physmem.totQLat 4572923146 # Total ticks spent queuing
290system.physmem.totMemAccLat 8287466896 # Total ticks spent from burst creation until serviced by the DRAM
| 289system.physmem.totQLat 4572903146 # Total ticks spent queuing
290system.physmem.totMemAccLat 8287446896 # Total ticks spent from burst creation until serviced by the DRAM
|
291system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers
| 291system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers
|
292system.physmem.avgQLat 23082.86 # Average queueing delay per DRAM burst
| 292system.physmem.avgQLat 23082.76 # Average queueing delay per DRAM burst
|
293system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
| 293system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
294system.physmem.avgMemAccLat 41832.86 # Average memory access latency per DRAM burst
| 294system.physmem.avgMemAccLat 41832.76 # Average memory access latency per DRAM burst
|
295system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s
296system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s
297system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s
298system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s
299system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
300system.physmem.busUtil 0.06 # Data bus utilization in percentage
301system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
302system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
303system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
304system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing
305system.physmem.readRowHits 165757 # Number of row buffer hits during reads
306system.physmem.writeRowHits 78775 # Number of row buffer hits during writes
307system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads
308system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes
309system.physmem.avgGap 8495676.27 # Average gap between requests
310system.physmem.pageHitRate 73.27 # Row buffer hit rate, read and write combined
311system.physmem_0.actEnergy 348221160 # Energy for activate commands per rank (pJ)
312system.physmem_0.preEnergy 190001625 # Energy for precharge commands per rank (pJ)
313system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ)
314system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ)
315system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ)
| 295system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s
296system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s
297system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s
298system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s
299system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
300system.physmem.busUtil 0.06 # Data bus utilization in percentage
301system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
302system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
303system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
304system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing
305system.physmem.readRowHits 165757 # Number of row buffer hits during reads
306system.physmem.writeRowHits 78775 # Number of row buffer hits during writes
307system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads
308system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes
309system.physmem.avgGap 8495676.27 # Average gap between requests
310system.physmem.pageHitRate 73.27 # Row buffer hit rate, read and write combined
311system.physmem_0.actEnergy 348221160 # Energy for activate commands per rank (pJ)
312system.physmem_0.preEnergy 190001625 # Energy for precharge commands per rank (pJ)
313system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ)
314system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ)
315system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ)
|
316system.physmem_0.actBackEnergy 84729045645 # Energy for active background per rank (pJ)
317system.physmem_0.preBackEnergy 1647547992750 # Energy for precharge background per rank (pJ)
318system.physmem_0.totalEnergy 1921532542260 # Total energy per rank (pJ)
| 316system.physmem_0.actBackEnergy 84729042225 # Energy for active background per rank (pJ)
317system.physmem_0.preBackEnergy 1647547995750 # Energy for precharge background per rank (pJ)
318system.physmem_0.totalEnergy 1921532541840 # Total energy per rank (pJ)
|
319system.physmem_0.averagePower 669.573415 # Core power per rank (mW)
| 319system.physmem_0.averagePower 669.573415 # Core power per rank (mW)
|
320system.physmem_0.memoryStateTime::IDLE 2740710561422 # Time in different power states
| 320system.physmem_0.memoryStateTime::IDLE 2740710565422 # Time in different power states
|
321system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states
322system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
| 321system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states
322system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
323system.physmem_0.memoryStateTime::ACT 33249852578 # Time in different power states
| 323system.physmem_0.memoryStateTime::ACT 33249848578 # Time in different power states
|
324system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
325system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ)
326system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ)
327system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ)
328system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ)
329system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ)
| 324system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
325system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ)
326system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ)
327system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ)
328system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ)
329system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ)
|
330system.physmem_1.actBackEnergy 84061532610 # Energy for active background per rank (pJ)
331system.physmem_1.preBackEnergy 1648133530500 # Energy for precharge background per rank (pJ)
332system.physmem_1.totalEnergy 1921286682870 # Total energy per rank (pJ)
| 330system.physmem_1.actBackEnergy 84061530045 # Energy for active background per rank (pJ)
331system.physmem_1.preBackEnergy 1648133532750 # Energy for precharge background per rank (pJ)
332system.physmem_1.totalEnergy 1921286682555 # Total energy per rank (pJ)
|
333system.physmem_1.averagePower 669.487743 # Core power per rank (mW)
| 333system.physmem_1.averagePower 669.487743 # Core power per rank (mW)
|
334system.physmem_1.memoryStateTime::IDLE 2741691176386 # Time in different power states
| 334system.physmem_1.memoryStateTime::IDLE 2741691180386 # Time in different power states
|
335system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states
336system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
| 335system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states
336system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
337system.physmem_1.memoryStateTime::ACT 32266572364 # Time in different power states
| 337system.physmem_1.memoryStateTime::ACT 32266568364 # Time in different power states
|
338system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
339system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
340system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
341system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
342system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
343system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
344system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
345system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
346system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
347system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
348system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
349system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
350system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
351system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
352system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
353system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
354system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
355system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
356system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
357system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
358system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
359system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
360system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
361system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
362system.cf0.dma_write_txs 631 # Number of DMA write transactions.
363system.cpu_clk_domain.clock 500 # Clock period in ticks
364system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
365system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
366system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
367system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
372system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
373system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
374system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
375system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
376system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
377system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
378system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
379system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
380system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
381system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
382system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
383system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
384system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
385system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
386system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
387system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
388system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
389system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
390system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
391system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
392system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
393system.cpu0.dtb.walker.walks 7943 # Table walker walks requested
394system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors
395system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate
396system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6442 # Level at which table walker walks with short descriptors terminate
397system.cpu0.dtb.walker.walkWaitTime::samples 7943 # Table walker wait (enqueue to first request) latency
398system.cpu0.dtb.walker.walkWaitTime::0 7943 100.00% 100.00% # Table walker wait (enqueue to first request) latency
399system.cpu0.dtb.walker.walkWaitTime::total 7943 # Table walker wait (enqueue to first request) latency
400system.cpu0.dtb.walker.walkCompletionTime::samples 6549 # Table walker service (enqueue to completion) latency
401system.cpu0.dtb.walker.walkCompletionTime::mean 12300.885631 # Table walker service (enqueue to completion) latency
402system.cpu0.dtb.walker.walkCompletionTime::gmean 11415.801761 # Table walker service (enqueue to completion) latency
403system.cpu0.dtb.walker.walkCompletionTime::stdev 5728.954139 # Table walker service (enqueue to completion) latency
404system.cpu0.dtb.walker.walkCompletionTime::0-16383 6064 92.59% 92.59% # Table walker service (enqueue to completion) latency
405system.cpu0.dtb.walker.walkCompletionTime::16384-32767 441 6.73% 99.33% # Table walker service (enqueue to completion) latency
406system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.85% # Table walker service (enqueue to completion) latency
407system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.91% # Table walker service (enqueue to completion) latency
408system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency
409system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
410system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
411system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
412system.cpu0.dtb.walker.walkCompletionTime::total 6549 # Table walker service (enqueue to completion) latency
413system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution
414system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution
415system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution
416system.cpu0.dtb.walker.walkPageSizes::4K 5087 77.68% 77.68% # Table walker page sizes translated
417system.cpu0.dtb.walker.walkPageSizes::1M 1462 22.32% 100.00% # Table walker page sizes translated
418system.cpu0.dtb.walker.walkPageSizes::total 6549 # Table walker page sizes translated
419system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7943 # Table walker requests started/completed, data/inst
420system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
421system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7943 # Table walker requests started/completed, data/inst
422system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6549 # Table walker requests started/completed, data/inst
423system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
424system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 # Table walker requests started/completed, data/inst
425system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst
426system.cpu0.dtb.inst_hits 0 # ITB inst hits
427system.cpu0.dtb.inst_misses 0 # ITB inst misses
| 338system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
339system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
340system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
341system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
342system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
343system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
344system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
345system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
346system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
347system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
348system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
349system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
350system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
351system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
352system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
353system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
354system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
355system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
356system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
357system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
358system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
359system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
360system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
361system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
362system.cf0.dma_write_txs 631 # Number of DMA write transactions.
363system.cpu_clk_domain.clock 500 # Clock period in ticks
364system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
365system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
366system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
367system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
372system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
373system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
374system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
375system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
376system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
377system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
378system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
379system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
380system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
381system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
382system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
383system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
384system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
385system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
386system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
387system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
388system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
389system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
390system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
391system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
392system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
393system.cpu0.dtb.walker.walks 7943 # Table walker walks requested
394system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors
395system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate
396system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6442 # Level at which table walker walks with short descriptors terminate
397system.cpu0.dtb.walker.walkWaitTime::samples 7943 # Table walker wait (enqueue to first request) latency
398system.cpu0.dtb.walker.walkWaitTime::0 7943 100.00% 100.00% # Table walker wait (enqueue to first request) latency
399system.cpu0.dtb.walker.walkWaitTime::total 7943 # Table walker wait (enqueue to first request) latency
400system.cpu0.dtb.walker.walkCompletionTime::samples 6549 # Table walker service (enqueue to completion) latency
401system.cpu0.dtb.walker.walkCompletionTime::mean 12300.885631 # Table walker service (enqueue to completion) latency
402system.cpu0.dtb.walker.walkCompletionTime::gmean 11415.801761 # Table walker service (enqueue to completion) latency
403system.cpu0.dtb.walker.walkCompletionTime::stdev 5728.954139 # Table walker service (enqueue to completion) latency
404system.cpu0.dtb.walker.walkCompletionTime::0-16383 6064 92.59% 92.59% # Table walker service (enqueue to completion) latency
405system.cpu0.dtb.walker.walkCompletionTime::16384-32767 441 6.73% 99.33% # Table walker service (enqueue to completion) latency
406system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.85% # Table walker service (enqueue to completion) latency
407system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.91% # Table walker service (enqueue to completion) latency
408system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency
409system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
410system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency
411system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
412system.cpu0.dtb.walker.walkCompletionTime::total 6549 # Table walker service (enqueue to completion) latency
413system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution
414system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution
415system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution
416system.cpu0.dtb.walker.walkPageSizes::4K 5087 77.68% 77.68% # Table walker page sizes translated
417system.cpu0.dtb.walker.walkPageSizes::1M 1462 22.32% 100.00% # Table walker page sizes translated
418system.cpu0.dtb.walker.walkPageSizes::total 6549 # Table walker page sizes translated
419system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7943 # Table walker requests started/completed, data/inst
420system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
421system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7943 # Table walker requests started/completed, data/inst
422system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6549 # Table walker requests started/completed, data/inst
423system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
424system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 # Table walker requests started/completed, data/inst
425system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst
426system.cpu0.dtb.inst_hits 0 # ITB inst hits
427system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
428system.cpu0.dtb.read_hits 25156507 # DTB read hits
| 428system.cpu0.dtb.read_hits 25156508 # DTB read hits
|
429system.cpu0.dtb.read_misses 6829 # DTB read misses
| 429system.cpu0.dtb.read_misses 6829 # DTB read misses
|
430system.cpu0.dtb.write_hits 18749940 # DTB write hits
| 430system.cpu0.dtb.write_hits 18749941 # DTB write hits
|
431system.cpu0.dtb.write_misses 1114 # DTB write misses
432system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
433system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
434system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
435system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
436system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB
437system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
438system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch
439system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
440system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
| 431system.cpu0.dtb.write_misses 1114 # DTB write misses
432system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
433system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
434system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
435system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
436system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB
437system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
438system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch
439system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
440system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
|
441system.cpu0.dtb.read_accesses 25163336 # DTB read accesses
442system.cpu0.dtb.write_accesses 18751054 # DTB write accesses
| 441system.cpu0.dtb.read_accesses 25163337 # DTB read accesses
442system.cpu0.dtb.write_accesses 18751055 # DTB write accesses
|
443system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
| 443system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
444system.cpu0.dtb.hits 43906447 # DTB hits
| 444system.cpu0.dtb.hits 43906449 # DTB hits
|
445system.cpu0.dtb.misses 7943 # DTB misses
| 445system.cpu0.dtb.misses 7943 # DTB misses
|
446system.cpu0.dtb.accesses 43914390 # DTB accesses
| 446system.cpu0.dtb.accesses 43914392 # DTB accesses
|
447system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
451system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
455system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
456system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
457system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
458system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
459system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
460system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
461system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
462system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
463system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
464system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
465system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
466system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
467system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
468system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
469system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
470system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
471system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
472system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
473system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
474system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
475system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
476system.cpu0.itb.walker.walks 3349 # Table walker walks requested
477system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors
478system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate
479system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate
480system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency
481system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency
482system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency
483system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency
484system.cpu0.itb.walker.walkCompletionTime::mean 12856.622375 # Table walker service (enqueue to completion) latency
485system.cpu0.itb.walker.walkCompletionTime::gmean 12024.130170 # Table walker service (enqueue to completion) latency
486system.cpu0.itb.walker.walkCompletionTime::stdev 5718.443506 # Table walker service (enqueue to completion) latency
487system.cpu0.itb.walker.walkCompletionTime::0-8191 360 15.43% 15.43% # Table walker service (enqueue to completion) latency
488system.cpu0.itb.walker.walkCompletionTime::8192-16383 1695 72.65% 88.08% # Table walker service (enqueue to completion) latency
489system.cpu0.itb.walker.walkCompletionTime::16384-24575 216 9.26% 97.34% # Table walker service (enqueue to completion) latency
490system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.24% 98.59% # Table walker service (enqueue to completion) latency
491system.cpu0.itb.walker.walkCompletionTime::32768-40959 29 1.24% 99.83% # Table walker service (enqueue to completion) latency
492system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency
493system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency
494system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
495system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
496system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency
497system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution
498system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution
499system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution
500system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated
501system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated
502system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated
503system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
504system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst
505system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst
506system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
507system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst
508system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst
509system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst
510system.cpu0.itb.inst_hits 119016789 # ITB inst hits
511system.cpu0.itb.inst_misses 3349 # ITB inst misses
512system.cpu0.itb.read_hits 0 # DTB read hits
513system.cpu0.itb.read_misses 0 # DTB read misses
514system.cpu0.itb.write_hits 0 # DTB write hits
515system.cpu0.itb.write_misses 0 # DTB write misses
516system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
517system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
518system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
519system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
520system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB
521system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
522system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
523system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
524system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
525system.cpu0.itb.read_accesses 0 # DTB read accesses
526system.cpu0.itb.write_accesses 0 # DTB write accesses
527system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses
528system.cpu0.itb.hits 119016789 # DTB hits
529system.cpu0.itb.misses 3349 # DTB misses
530system.cpu0.itb.accesses 119020138 # DTB accesses
531system.cpu0.numCycles 5739577940 # number of cpu cycles simulated
532system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
533system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
534system.cpu0.kern.inst.arm 0 # number of arm instructions executed
535system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed
| 447system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
451system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
455system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
456system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
457system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
458system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
459system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
460system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
461system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
462system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
463system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
464system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
465system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
466system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
467system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
468system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
469system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
470system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
471system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
472system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
473system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
474system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
475system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
476system.cpu0.itb.walker.walks 3349 # Table walker walks requested
477system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors
478system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate
479system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate
480system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency
481system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency
482system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency
483system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency
484system.cpu0.itb.walker.walkCompletionTime::mean 12856.622375 # Table walker service (enqueue to completion) latency
485system.cpu0.itb.walker.walkCompletionTime::gmean 12024.130170 # Table walker service (enqueue to completion) latency
486system.cpu0.itb.walker.walkCompletionTime::stdev 5718.443506 # Table walker service (enqueue to completion) latency
487system.cpu0.itb.walker.walkCompletionTime::0-8191 360 15.43% 15.43% # Table walker service (enqueue to completion) latency
488system.cpu0.itb.walker.walkCompletionTime::8192-16383 1695 72.65% 88.08% # Table walker service (enqueue to completion) latency
489system.cpu0.itb.walker.walkCompletionTime::16384-24575 216 9.26% 97.34% # Table walker service (enqueue to completion) latency
490system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.24% 98.59% # Table walker service (enqueue to completion) latency
491system.cpu0.itb.walker.walkCompletionTime::32768-40959 29 1.24% 99.83% # Table walker service (enqueue to completion) latency
492system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency
493system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency
494system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
495system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
496system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency
497system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution
498system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution
499system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution
500system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated
501system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated
502system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated
503system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
504system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst
505system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst
506system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
507system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst
508system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst
509system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst
510system.cpu0.itb.inst_hits 119016789 # ITB inst hits
511system.cpu0.itb.inst_misses 3349 # ITB inst misses
512system.cpu0.itb.read_hits 0 # DTB read hits
513system.cpu0.itb.read_misses 0 # DTB read misses
514system.cpu0.itb.write_hits 0 # DTB write hits
515system.cpu0.itb.write_misses 0 # DTB write misses
516system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
517system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
518system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
519system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
520system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB
521system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
522system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
523system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
524system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
525system.cpu0.itb.read_accesses 0 # DTB read accesses
526system.cpu0.itb.write_accesses 0 # DTB write accesses
527system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses
528system.cpu0.itb.hits 119016789 # DTB hits
529system.cpu0.itb.misses 3349 # DTB misses
530system.cpu0.itb.accesses 119020138 # DTB accesses
531system.cpu0.numCycles 5739577940 # number of cpu cycles simulated
532system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
533system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
534system.cpu0.kern.inst.arm 0 # number of arm instructions executed
535system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed
|
536system.cpu0.committedInsts 115352403 # Number of instructions committed
537system.cpu0.committedOps 139380192 # Number of ops (including micro ops) committed
| 536system.cpu0.committedInsts 115352405 # Number of instructions committed
537system.cpu0.committedOps 139380194 # Number of ops (including micro ops) committed
|
538system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses
539system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses
540system.cpu0.num_func_calls 12675179 # number of times a function call or return occured
541system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls
542system.cpu0.num_int_insts 123360698 # number of integer instructions
543system.cpu0.num_fp_insts 9756 # number of float instructions
| 538system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses
539system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses
540system.cpu0.num_func_calls 12675179 # number of times a function call or return occured
541system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls
542system.cpu0.num_int_insts 123360698 # number of integer instructions
543system.cpu0.num_fp_insts 9756 # number of float instructions
|
544system.cpu0.num_int_register_reads 227087076 # number of times the integer registers were read
545system.cpu0.num_int_register_writes 85717148 # number of times the integer registers were written
| 544system.cpu0.num_int_register_reads 227087077 # number of times the integer registers were read
545system.cpu0.num_int_register_writes 85717152 # number of times the integer registers were written
|
546system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read
547system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
| 546system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read
547system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
|
548system.cpu0.num_cc_register_reads 504942673 # number of times the CC registers were read
| 548system.cpu0.num_cc_register_reads 504942676 # number of times the CC registers were read
|
549system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written
550system.cpu0.num_mem_refs 45042977 # number of memory refs
551system.cpu0.num_load_insts 25408336 # Number of load instructions
552system.cpu0.num_store_insts 19634641 # Number of store instructions
553system.cpu0.num_idle_cycles 5464040817.996096 # Number of idle cycles
554system.cpu0.num_busy_cycles 275537122.003904 # Number of busy cycles
555system.cpu0.not_idle_fraction 0.048007 # Percentage of non-idle cycles
556system.cpu0.idle_fraction 0.951993 # Percentage of idle cycles
557system.cpu0.Branches 29113703 # Number of branches fetched
558system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
559system.cpu0.op_class::IntAlu 97981864 68.45% 68.45% # Class of executed instruction
560system.cpu0.op_class::IntMult 109763 0.08% 68.53% # Class of executed instruction
561system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction
562system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction
563system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction
564system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction
565system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
566system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction
567system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction
568system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction
569system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction
570system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction
571system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction
572system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction
573system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction
574system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction
575system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction
576system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction
577system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction
578system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction
579system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction
580system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction
581system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction
582system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction
583system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction
584system.cpu0.op_class::SimdFloatMisc 8197 0.01% 68.53% # Class of executed instruction
585system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction
586system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction
587system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction
588system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction
589system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction
590system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
591system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
592system.cpu0.op_class::total 143145074 # Class of executed instruction
593system.cpu0.dcache.tags.replacements 692159 # number of replacements
594system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use
| 549system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written
550system.cpu0.num_mem_refs 45042977 # number of memory refs
551system.cpu0.num_load_insts 25408336 # Number of load instructions
552system.cpu0.num_store_insts 19634641 # Number of store instructions
553system.cpu0.num_idle_cycles 5464040817.996096 # Number of idle cycles
554system.cpu0.num_busy_cycles 275537122.003904 # Number of busy cycles
555system.cpu0.not_idle_fraction 0.048007 # Percentage of non-idle cycles
556system.cpu0.idle_fraction 0.951993 # Percentage of idle cycles
557system.cpu0.Branches 29113703 # Number of branches fetched
558system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
559system.cpu0.op_class::IntAlu 97981864 68.45% 68.45% # Class of executed instruction
560system.cpu0.op_class::IntMult 109763 0.08% 68.53% # Class of executed instruction
561system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction
562system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction
563system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction
564system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction
565system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
566system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction
567system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction
568system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction
569system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction
570system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction
571system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction
572system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction
573system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction
574system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction
575system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction
576system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction
577system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction
578system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction
579system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction
580system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction
581system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction
582system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction
583system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction
584system.cpu0.op_class::SimdFloatMisc 8197 0.01% 68.53% # Class of executed instruction
585system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction
586system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction
587system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction
588system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction
589system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction
590system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
591system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
592system.cpu0.op_class::total 143145074 # Class of executed instruction
593system.cpu0.dcache.tags.replacements 692159 # number of replacements
594system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use
|
595system.cpu0.dcache.tags.total_refs 43035504 # Total number of references to valid blocks.
| 595system.cpu0.dcache.tags.total_refs 43035506 # Total number of references to valid blocks.
|
596system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks.
| 596system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks.
|
597system.cpu0.dcache.tags.avg_refs 62.129790 # Average number of references to valid blocks.
| 597system.cpu0.dcache.tags.avg_refs 62.129793 # Average number of references to valid blocks.
|
598system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit.
599system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor
600system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy
601system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy
602system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
603system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
604system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
605system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
606system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
| 598system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit.
599system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor
600system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy
601system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy
602system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
603system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
604system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id
605system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
606system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
607system.cpu0.dcache.tags.tag_accesses 88449495 # Number of tag accesses
608system.cpu0.dcache.tags.data_accesses 88449495 # Number of data accesses
609system.cpu0.dcache.ReadReq_hits::cpu0.data 23895287 # number of ReadReq hits
610system.cpu0.dcache.ReadReq_hits::total 23895287 # number of ReadReq hits
611system.cpu0.dcache.WriteReq_hits::cpu0.data 18018355 # number of WriteReq hits
612system.cpu0.dcache.WriteReq_hits::total 18018355 # number of WriteReq hits
| 607system.cpu0.dcache.tags.tag_accesses 88449499 # Number of tag accesses
608system.cpu0.dcache.tags.data_accesses 88449499 # Number of data accesses
609system.cpu0.dcache.ReadReq_hits::cpu0.data 23895288 # number of ReadReq hits
610system.cpu0.dcache.ReadReq_hits::total 23895288 # number of ReadReq hits
611system.cpu0.dcache.WriteReq_hits::cpu0.data 18018356 # number of WriteReq hits
612system.cpu0.dcache.WriteReq_hits::total 18018356 # number of WriteReq hits
|
613system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits
614system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits
615system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits
616system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits
617system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits
618system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits
| 613system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits
614system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits
615system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits
616system.cpu0.dcache.LoadLockedReq_hits::total 365501 # number of LoadLockedReq hits
617system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362365 # number of StoreCondReq hits
618system.cpu0.dcache.StoreCondReq_hits::total 362365 # number of StoreCondReq hits
|
619system.cpu0.dcache.demand_hits::cpu0.data 41913642 # number of demand (read+write) hits
620system.cpu0.dcache.demand_hits::total 41913642 # number of demand (read+write) hits
621system.cpu0.dcache.overall_hits::cpu0.data 42232748 # number of overall hits
622system.cpu0.dcache.overall_hits::total 42232748 # number of overall hits
| 619system.cpu0.dcache.demand_hits::cpu0.data 41913644 # number of demand (read+write) hits
620system.cpu0.dcache.demand_hits::total 41913644 # number of demand (read+write) hits
621system.cpu0.dcache.overall_hits::cpu0.data 42232750 # number of overall hits
622system.cpu0.dcache.overall_hits::total 42232750 # number of overall hits
|
623system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses
624system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses
625system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses
626system.cpu0.dcache.WriteReq_misses::total 325040 # number of WriteReq misses
627system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127692 # number of SoftPFReq misses
628system.cpu0.dcache.SoftPFReq_misses::total 127692 # number of SoftPFReq misses
629system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21584 # number of LoadLockedReq misses
630system.cpu0.dcache.LoadLockedReq_misses::total 21584 # number of LoadLockedReq misses
631system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19801 # number of StoreCondReq misses
632system.cpu0.dcache.StoreCondReq_misses::total 19801 # number of StoreCondReq misses
633system.cpu0.dcache.demand_misses::cpu0.data 721136 # number of demand (read+write) misses
634system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses
635system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses
636system.cpu0.dcache.overall_misses::total 848828 # number of overall misses
| 623system.cpu0.dcache.ReadReq_misses::cpu0.data 396096 # number of ReadReq misses
624system.cpu0.dcache.ReadReq_misses::total 396096 # number of ReadReq misses
625system.cpu0.dcache.WriteReq_misses::cpu0.data 325040 # number of WriteReq misses
626system.cpu0.dcache.WriteReq_misses::total 325040 # number of WriteReq misses
627system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127692 # number of SoftPFReq misses
628system.cpu0.dcache.SoftPFReq_misses::total 127692 # number of SoftPFReq misses
629system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21584 # number of LoadLockedReq misses
630system.cpu0.dcache.LoadLockedReq_misses::total 21584 # number of LoadLockedReq misses
631system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19801 # number of StoreCondReq misses
632system.cpu0.dcache.StoreCondReq_misses::total 19801 # number of StoreCondReq misses
633system.cpu0.dcache.demand_misses::cpu0.data 721136 # number of demand (read+write) misses
634system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses
635system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses
636system.cpu0.dcache.overall_misses::total 848828 # number of overall misses
|
637system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078700000 # number of ReadReq miss cycles
638system.cpu0.dcache.ReadReq_miss_latency::total 5078700000 # number of ReadReq miss cycles
| 637system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078698000 # number of ReadReq miss cycles
638system.cpu0.dcache.ReadReq_miss_latency::total 5078698000 # number of ReadReq miss cycles
|
639system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles
640system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles
641system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles
642system.cpu0.dcache.LoadLockedReq_miss_latency::total 329182500 # number of LoadLockedReq miss cycles
643system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 # number of StoreCondReq miss cycles
644system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles
645system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles
646system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles
| 639system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles
640system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles
641system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles
642system.cpu0.dcache.LoadLockedReq_miss_latency::total 329182500 # number of LoadLockedReq miss cycles
643system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 # number of StoreCondReq miss cycles
644system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles
645system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles
646system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles
|
647system.cpu0.dcache.demand_miss_latency::cpu0.data 10808062000 # number of demand (read+write) miss cycles
648system.cpu0.dcache.demand_miss_latency::total 10808062000 # number of demand (read+write) miss cycles
649system.cpu0.dcache.overall_miss_latency::cpu0.data 10808062000 # number of overall miss cycles
650system.cpu0.dcache.overall_miss_latency::total 10808062000 # number of overall miss cycles
651system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291383 # number of ReadReq accesses(hits+misses)
652system.cpu0.dcache.ReadReq_accesses::total 24291383 # number of ReadReq accesses(hits+misses)
653system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343395 # number of WriteReq accesses(hits+misses)
654system.cpu0.dcache.WriteReq_accesses::total 18343395 # number of WriteReq accesses(hits+misses)
| 647system.cpu0.dcache.demand_miss_latency::cpu0.data 10808060000 # number of demand (read+write) miss cycles
648system.cpu0.dcache.demand_miss_latency::total 10808060000 # number of demand (read+write) miss cycles
649system.cpu0.dcache.overall_miss_latency::cpu0.data 10808060000 # number of overall miss cycles
650system.cpu0.dcache.overall_miss_latency::total 10808060000 # number of overall miss cycles
651system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291384 # number of ReadReq accesses(hits+misses)
652system.cpu0.dcache.ReadReq_accesses::total 24291384 # number of ReadReq accesses(hits+misses)
653system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343396 # number of WriteReq accesses(hits+misses)
654system.cpu0.dcache.WriteReq_accesses::total 18343396 # number of WriteReq accesses(hits+misses)
|
655system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses)
656system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses)
657system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses)
658system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses)
659system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses)
660system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses)
| 655system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses)
656system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses)
657system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses)
658system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses)
659system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses)
660system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses)
|
661system.cpu0.dcache.demand_accesses::cpu0.data 42634778 # number of demand (read+write) accesses
662system.cpu0.dcache.demand_accesses::total 42634778 # number of demand (read+write) accesses
663system.cpu0.dcache.overall_accesses::cpu0.data 43081576 # number of overall (read+write) accesses
664system.cpu0.dcache.overall_accesses::total 43081576 # number of overall (read+write) accesses
| 661system.cpu0.dcache.demand_accesses::cpu0.data 42634780 # number of demand (read+write) accesses
662system.cpu0.dcache.demand_accesses::total 42634780 # number of demand (read+write) accesses
663system.cpu0.dcache.overall_accesses::cpu0.data 43081578 # number of overall (read+write) accesses
664system.cpu0.dcache.overall_accesses::total 43081578 # number of overall (read+write) accesses
|
665system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses
666system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses
667system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses
668system.cpu0.dcache.WriteReq_miss_rate::total 0.017720 # miss rate for WriteReq accesses
669system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285794 # miss rate for SoftPFReq accesses
670system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285794 # miss rate for SoftPFReq accesses
671system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055760 # miss rate for LoadLockedReq accesses
672system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055760 # miss rate for LoadLockedReq accesses
673system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051813 # miss rate for StoreCondReq accesses
674system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051813 # miss rate for StoreCondReq accesses
675system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 # miss rate for demand accesses
676system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses
677system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses
678system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses
| 665system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses
666system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses
667system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses
668system.cpu0.dcache.WriteReq_miss_rate::total 0.017720 # miss rate for WriteReq accesses
669system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285794 # miss rate for SoftPFReq accesses
670system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285794 # miss rate for SoftPFReq accesses
671system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055760 # miss rate for LoadLockedReq accesses
672system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055760 # miss rate for LoadLockedReq accesses
673system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051813 # miss rate for StoreCondReq accesses
674system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051813 # miss rate for StoreCondReq accesses
675system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 # miss rate for demand accesses
676system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses
677system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses
678system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses
|
679system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.891663 # average ReadReq miss latency
680system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.891663 # average ReadReq miss latency
| 679system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.886613 # average ReadReq miss latency
680system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.886613 # average ReadReq miss latency
|
681system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency
682system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency
683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency
684system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15251.227761 # average LoadLockedReq miss latency
685system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 # average StoreCondReq miss latency
686system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency
687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
688system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
| 681system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency
682system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency
683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency
684system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15251.227761 # average LoadLockedReq miss latency
685system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 # average StoreCondReq miss latency
686system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency
687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
688system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
|
689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.550199 # average overall miss latency
690system.cpu0.dcache.demand_avg_miss_latency::total 14987.550199 # average overall miss latency
691system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.923513 # average overall miss latency
692system.cpu0.dcache.overall_avg_miss_latency::total 12732.923513 # average overall miss latency
| 689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.547425 # average overall miss latency
690system.cpu0.dcache.demand_avg_miss_latency::total 14987.547425 # average overall miss latency
691system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.921157 # average overall miss latency
692system.cpu0.dcache.overall_avg_miss_latency::total 12732.921157 # average overall miss latency
|
693system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
696system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
697system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
698system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
699system.cpu0.dcache.writebacks::writebacks 692159 # number of writebacks
700system.cpu0.dcache.writebacks::total 692159 # number of writebacks
701system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25284 # number of ReadReq MSHR hits
702system.cpu0.dcache.ReadReq_mshr_hits::total 25284 # number of ReadReq MSHR hits
703system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15032 # number of LoadLockedReq MSHR hits
704system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15032 # number of LoadLockedReq MSHR hits
705system.cpu0.dcache.demand_mshr_hits::cpu0.data 25284 # number of demand (read+write) MSHR hits
706system.cpu0.dcache.demand_mshr_hits::total 25284 # number of demand (read+write) MSHR hits
707system.cpu0.dcache.overall_mshr_hits::cpu0.data 25284 # number of overall MSHR hits
708system.cpu0.dcache.overall_mshr_hits::total 25284 # number of overall MSHR hits
709system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370812 # number of ReadReq MSHR misses
710system.cpu0.dcache.ReadReq_mshr_misses::total 370812 # number of ReadReq MSHR misses
711system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325040 # number of WriteReq MSHR misses
712system.cpu0.dcache.WriteReq_mshr_misses::total 325040 # number of WriteReq MSHR misses
713system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100482 # number of SoftPFReq MSHR misses
714system.cpu0.dcache.SoftPFReq_mshr_misses::total 100482 # number of SoftPFReq MSHR misses
715system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6552 # number of LoadLockedReq MSHR misses
716system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6552 # number of LoadLockedReq MSHR misses
717system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19801 # number of StoreCondReq MSHR misses
718system.cpu0.dcache.StoreCondReq_mshr_misses::total 19801 # number of StoreCondReq MSHR misses
719system.cpu0.dcache.demand_mshr_misses::cpu0.data 695852 # number of demand (read+write) MSHR misses
720system.cpu0.dcache.demand_mshr_misses::total 695852 # number of demand (read+write) MSHR misses
721system.cpu0.dcache.overall_mshr_misses::cpu0.data 796334 # number of overall MSHR misses
722system.cpu0.dcache.overall_mshr_misses::total 796334 # number of overall MSHR misses
723system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable
724system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31792 # number of ReadReq MSHR uncacheable
725system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable
726system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable
727system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses
728system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses
| 693system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
696system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
697system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
698system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
699system.cpu0.dcache.writebacks::writebacks 692159 # number of writebacks
700system.cpu0.dcache.writebacks::total 692159 # number of writebacks
701system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25284 # number of ReadReq MSHR hits
702system.cpu0.dcache.ReadReq_mshr_hits::total 25284 # number of ReadReq MSHR hits
703system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15032 # number of LoadLockedReq MSHR hits
704system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15032 # number of LoadLockedReq MSHR hits
705system.cpu0.dcache.demand_mshr_hits::cpu0.data 25284 # number of demand (read+write) MSHR hits
706system.cpu0.dcache.demand_mshr_hits::total 25284 # number of demand (read+write) MSHR hits
707system.cpu0.dcache.overall_mshr_hits::cpu0.data 25284 # number of overall MSHR hits
708system.cpu0.dcache.overall_mshr_hits::total 25284 # number of overall MSHR hits
709system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370812 # number of ReadReq MSHR misses
710system.cpu0.dcache.ReadReq_mshr_misses::total 370812 # number of ReadReq MSHR misses
711system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325040 # number of WriteReq MSHR misses
712system.cpu0.dcache.WriteReq_mshr_misses::total 325040 # number of WriteReq MSHR misses
713system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100482 # number of SoftPFReq MSHR misses
714system.cpu0.dcache.SoftPFReq_mshr_misses::total 100482 # number of SoftPFReq MSHR misses
715system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6552 # number of LoadLockedReq MSHR misses
716system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6552 # number of LoadLockedReq MSHR misses
717system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19801 # number of StoreCondReq MSHR misses
718system.cpu0.dcache.StoreCondReq_mshr_misses::total 19801 # number of StoreCondReq MSHR misses
719system.cpu0.dcache.demand_mshr_misses::cpu0.data 695852 # number of demand (read+write) MSHR misses
720system.cpu0.dcache.demand_mshr_misses::total 695852 # number of demand (read+write) MSHR misses
721system.cpu0.dcache.overall_mshr_misses::cpu0.data 796334 # number of overall MSHR misses
722system.cpu0.dcache.overall_mshr_misses::total 796334 # number of overall MSHR misses
723system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable
724system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31792 # number of ReadReq MSHR uncacheable
725system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable
726system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable
727system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses
728system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60255 # number of overall MSHR uncacheable misses
|
729system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312933000 # number of ReadReq MSHR miss cycles
730system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312933000 # number of ReadReq MSHR miss cycles
| 729system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4312931000 # number of ReadReq MSHR miss cycles
730system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4312931000 # number of ReadReq MSHR miss cycles
|
731system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles
732system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles
733system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles
734system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615427000 # number of SoftPFReq MSHR miss cycles
735system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98795500 # number of LoadLockedReq MSHR miss cycles
736system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98795500 # number of LoadLockedReq MSHR miss cycles
737system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 # number of StoreCondReq MSHR miss cycles
738system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles
739system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles
740system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles
| 731system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5404322000 # number of WriteReq MSHR miss cycles
732system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5404322000 # number of WriteReq MSHR miss cycles
733system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1615427000 # number of SoftPFReq MSHR miss cycles
734system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1615427000 # number of SoftPFReq MSHR miss cycles
735system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98795500 # number of LoadLockedReq MSHR miss cycles
736system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98795500 # number of LoadLockedReq MSHR miss cycles
737system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452825500 # number of StoreCondReq MSHR miss cycles
738system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452825500 # number of StoreCondReq MSHR miss cycles
739system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1405500 # number of StoreCondFailReq MSHR miss cycles
740system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1405500 # number of StoreCondFailReq MSHR miss cycles
|
741system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717255000 # number of demand (read+write) MSHR miss cycles
742system.cpu0.dcache.demand_mshr_miss_latency::total 9717255000 # number of demand (read+write) MSHR miss cycles
743system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332682000 # number of overall MSHR miss cycles
744system.cpu0.dcache.overall_mshr_miss_latency::total 11332682000 # number of overall MSHR miss cycles
| 741system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717253000 # number of demand (read+write) MSHR miss cycles
742system.cpu0.dcache.demand_mshr_miss_latency::total 9717253000 # number of demand (read+write) MSHR miss cycles
743system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332680000 # number of overall MSHR miss cycles
744system.cpu0.dcache.overall_mshr_miss_latency::total 11332680000 # number of overall MSHR miss cycles
|
745system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles
746system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles
747system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles
748system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628901000 # number of overall MSHR uncacheable cycles
749system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015265 # mshr miss rate for ReadReq accesses
750system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015265 # mshr miss rate for ReadReq accesses
751system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017720 # mshr miss rate for WriteReq accesses
752system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses
753system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224894 # mshr miss rate for SoftPFReq accesses
754system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224894 # mshr miss rate for SoftPFReq accesses
755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016927 # mshr miss rate for LoadLockedReq accesses
756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016927 # mshr miss rate for LoadLockedReq accesses
757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051813 # mshr miss rate for StoreCondReq accesses
758system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051813 # mshr miss rate for StoreCondReq accesses
759system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 # mshr miss rate for demand accesses
760system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses
761system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses
762system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses
| 745system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles
746system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles
747system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles
748system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628901000 # number of overall MSHR uncacheable cycles
749system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015265 # mshr miss rate for ReadReq accesses
750system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015265 # mshr miss rate for ReadReq accesses
751system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017720 # mshr miss rate for WriteReq accesses
752system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses
753system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224894 # mshr miss rate for SoftPFReq accesses
754system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224894 # mshr miss rate for SoftPFReq accesses
755system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016927 # mshr miss rate for LoadLockedReq accesses
756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016927 # mshr miss rate for LoadLockedReq accesses
757system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051813 # mshr miss rate for StoreCondReq accesses
758system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051813 # mshr miss rate for StoreCondReq accesses
759system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 # mshr miss rate for demand accesses
760system.cpu0.dcache.demand_mshr_miss_rate::total 0.016321 # mshr miss rate for demand accesses
761system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018484 # mshr miss rate for overall accesses
762system.cpu0.dcache.overall_mshr_miss_rate::total 0.018484 # mshr miss rate for overall accesses
|
763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.050236 # average ReadReq mshr miss latency
764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.050236 # average ReadReq mshr miss latency
| 763system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11631.044842 # average ReadReq mshr miss latency
764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11631.044842 # average ReadReq mshr miss latency
|
765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency
766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency
767system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency
768system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.779921 # average SoftPFReq mshr miss latency
769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15078.678266 # average LoadLockedReq mshr miss latency
770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15078.678266 # average LoadLockedReq mshr miss latency
771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 # average StoreCondReq mshr miss latency
772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency
773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
| 765system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16626.636722 # average WriteReq mshr miss latency
766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16626.636722 # average WriteReq mshr miss latency
767system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16076.779921 # average SoftPFReq mshr miss latency
768system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.779921 # average SoftPFReq mshr miss latency
769system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15078.678266 # average LoadLockedReq mshr miss latency
770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15078.678266 # average LoadLockedReq mshr miss latency
771system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 # average StoreCondReq mshr miss latency
772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency
773system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
|
775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.542748 # average overall mshr miss latency
776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.542748 # average overall mshr miss latency
777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.066362 # average overall mshr miss latency
778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.066362 # average overall mshr miss latency
| 775system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13964.539873 # average overall mshr miss latency
776system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13964.539873 # average overall mshr miss latency
777system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14231.063850 # average overall mshr miss latency
778system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14231.063850 # average overall mshr miss latency
|
779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency
780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency
781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency
782system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency
783system.cpu0.icache.tags.replacements 1103881 # number of replacements
784system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use
785system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks.
786system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks.
787system.cpu0.icache.tags.avg_refs 106.766692 # Average number of references to valid blocks.
788system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit.
789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor
790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy
791system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy
792system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
793system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
794system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
795system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id
796system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
797system.cpu0.icache.tags.tag_accesses 239137980 # Number of tag accesses
798system.cpu0.icache.tags.data_accesses 239137980 # Number of data accesses
799system.cpu0.icache.ReadReq_hits::cpu0.inst 117912387 # number of ReadReq hits
800system.cpu0.icache.ReadReq_hits::total 117912387 # number of ReadReq hits
801system.cpu0.icache.demand_hits::cpu0.inst 117912387 # number of demand (read+write) hits
802system.cpu0.icache.demand_hits::total 117912387 # number of demand (read+write) hits
803system.cpu0.icache.overall_hits::cpu0.inst 117912387 # number of overall hits
804system.cpu0.icache.overall_hits::total 117912387 # number of overall hits
805system.cpu0.icache.ReadReq_misses::cpu0.inst 1104402 # number of ReadReq misses
806system.cpu0.icache.ReadReq_misses::total 1104402 # number of ReadReq misses
807system.cpu0.icache.demand_misses::cpu0.inst 1104402 # number of demand (read+write) misses
808system.cpu0.icache.demand_misses::total 1104402 # number of demand (read+write) misses
809system.cpu0.icache.overall_misses::cpu0.inst 1104402 # number of overall misses
810system.cpu0.icache.overall_misses::total 1104402 # number of overall misses
811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11028665000 # number of ReadReq miss cycles
812system.cpu0.icache.ReadReq_miss_latency::total 11028665000 # number of ReadReq miss cycles
813system.cpu0.icache.demand_miss_latency::cpu0.inst 11028665000 # number of demand (read+write) miss cycles
814system.cpu0.icache.demand_miss_latency::total 11028665000 # number of demand (read+write) miss cycles
815system.cpu0.icache.overall_miss_latency::cpu0.inst 11028665000 # number of overall miss cycles
816system.cpu0.icache.overall_miss_latency::total 11028665000 # number of overall miss cycles
817system.cpu0.icache.ReadReq_accesses::cpu0.inst 119016789 # number of ReadReq accesses(hits+misses)
818system.cpu0.icache.ReadReq_accesses::total 119016789 # number of ReadReq accesses(hits+misses)
819system.cpu0.icache.demand_accesses::cpu0.inst 119016789 # number of demand (read+write) accesses
820system.cpu0.icache.demand_accesses::total 119016789 # number of demand (read+write) accesses
821system.cpu0.icache.overall_accesses::cpu0.inst 119016789 # number of overall (read+write) accesses
822system.cpu0.icache.overall_accesses::total 119016789 # number of overall (read+write) accesses
823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009279 # miss rate for ReadReq accesses
824system.cpu0.icache.ReadReq_miss_rate::total 0.009279 # miss rate for ReadReq accesses
825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009279 # miss rate for demand accesses
826system.cpu0.icache.demand_miss_rate::total 0.009279 # miss rate for demand accesses
827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009279 # miss rate for overall accesses
828system.cpu0.icache.overall_miss_rate::total 0.009279 # miss rate for overall accesses
829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9986.096548 # average ReadReq miss latency
830system.cpu0.icache.ReadReq_avg_miss_latency::total 9986.096548 # average ReadReq miss latency
831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency
832system.cpu0.icache.demand_avg_miss_latency::total 9986.096548 # average overall miss latency
833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency
834system.cpu0.icache.overall_avg_miss_latency::total 9986.096548 # average overall miss latency
835system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
839system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
841system.cpu0.icache.writebacks::writebacks 1103881 # number of writebacks
842system.cpu0.icache.writebacks::total 1103881 # number of writebacks
843system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104402 # number of ReadReq MSHR misses
844system.cpu0.icache.ReadReq_mshr_misses::total 1104402 # number of ReadReq MSHR misses
845system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104402 # number of demand (read+write) MSHR misses
846system.cpu0.icache.demand_mshr_misses::total 1104402 # number of demand (read+write) MSHR misses
847system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104402 # number of overall MSHR misses
848system.cpu0.icache.overall_mshr_misses::total 1104402 # number of overall MSHR misses
849system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
850system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
851system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
852system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
853system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10476464000 # number of ReadReq MSHR miss cycles
854system.cpu0.icache.ReadReq_mshr_miss_latency::total 10476464000 # number of ReadReq MSHR miss cycles
855system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10476464000 # number of demand (read+write) MSHR miss cycles
856system.cpu0.icache.demand_mshr_miss_latency::total 10476464000 # number of demand (read+write) MSHR miss cycles
857system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10476464000 # number of overall MSHR miss cycles
858system.cpu0.icache.overall_mshr_miss_latency::total 10476464000 # number of overall MSHR miss cycles
859system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles
860system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles
861system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles
862system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles
863system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for ReadReq accesses
864system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009279 # mshr miss rate for ReadReq accesses
865system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for demand accesses
866system.cpu0.icache.demand_mshr_miss_rate::total 0.009279 # mshr miss rate for demand accesses
867system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for overall accesses
868system.cpu0.icache.overall_mshr_miss_rate::total 0.009279 # mshr miss rate for overall accesses
869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average ReadReq mshr miss latency
870system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9486.096548 # average ReadReq mshr miss latency
871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency
872system.cpu0.icache.demand_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency
873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency
874system.cpu0.icache.overall_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency
875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency
876system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency
877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency
878system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency
879system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued
880system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified
881system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue
882system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
883system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
884system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing
885system.cpu0.l2cache.tags.replacements 266444 # number of replacements
886system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use
887system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks.
888system.cpu0.l2cache.tags.sampled_refs 282538 # Sample count of references to valid blocks.
889system.cpu0.l2cache.tags.avg_refs 10.354310 # Average number of references to valid blocks.
890system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
891system.cpu0.l2cache.tags.occ_blocks::writebacks 14606.769244 # Average occupied blocks per requestor
892system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.268403 # Average occupied blocks per requestor
893system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.133561 # Average occupied blocks per requestor
894system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1470.339456 # Average occupied blocks per requestor
895system.cpu0.l2cache.tags.occ_percent::writebacks 0.891526 # Average percentage of cache occupancy
896system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000138 # Average percentage of cache occupancy
897system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
898system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.089742 # Average percentage of cache occupancy
899system.cpu0.l2cache.tags.occ_percent::total 0.981415 # Average percentage of cache occupancy
900system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id
901system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
902system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id
903system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
904system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 289 # Occupied blocks per task id
905system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 351 # Occupied blocks per task id
906system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 399 # Occupied blocks per task id
907system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
908system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
909system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
910system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
911system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id
912system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7676 # Occupied blocks per task id
913system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3752 # Occupied blocks per task id
914system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id
915system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
916system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id
917system.cpu0.l2cache.tags.tag_accesses 60110945 # Number of tag accesses
918system.cpu0.l2cache.tags.data_accesses 60110945 # Number of data accesses
919system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10236 # number of ReadReq hits
920system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4573 # number of ReadReq hits
921system.cpu0.l2cache.ReadReq_hits::total 14809 # number of ReadReq hits
922system.cpu0.l2cache.WritebackDirty_hits::writebacks 476837 # number of WritebackDirty hits
923system.cpu0.l2cache.WritebackDirty_hits::total 476837 # number of WritebackDirty hits
924system.cpu0.l2cache.WritebackClean_hits::writebacks 1291246 # number of WritebackClean hits
925system.cpu0.l2cache.WritebackClean_hits::total 1291246 # number of WritebackClean hits
926system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227142 # number of ReadExReq hits
927system.cpu0.l2cache.ReadExReq_hits::total 227142 # number of ReadExReq hits
928system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1059122 # number of ReadCleanReq hits
929system.cpu0.l2cache.ReadCleanReq_hits::total 1059122 # number of ReadCleanReq hits
930system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 383679 # number of ReadSharedReq hits
931system.cpu0.l2cache.ReadSharedReq_hits::total 383679 # number of ReadSharedReq hits
932system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10236 # number of demand (read+write) hits
933system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4573 # number of demand (read+write) hits
934system.cpu0.l2cache.demand_hits::cpu0.inst 1059122 # number of demand (read+write) hits
935system.cpu0.l2cache.demand_hits::cpu0.data 610821 # number of demand (read+write) hits
936system.cpu0.l2cache.demand_hits::total 1684752 # number of demand (read+write) hits
937system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10236 # number of overall hits
938system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4573 # number of overall hits
939system.cpu0.l2cache.overall_hits::cpu0.inst 1059122 # number of overall hits
940system.cpu0.l2cache.overall_hits::cpu0.data 610821 # number of overall hits
941system.cpu0.l2cache.overall_hits::total 1684752 # number of overall hits
942system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 226 # number of ReadReq misses
943system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses
944system.cpu0.l2cache.ReadReq_misses::total 366 # number of ReadReq misses
945system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55088 # number of UpgradeReq misses
946system.cpu0.l2cache.UpgradeReq_misses::total 55088 # number of UpgradeReq misses
947system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses
948system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses
949system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
950system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
951system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42810 # number of ReadExReq misses
952system.cpu0.l2cache.ReadExReq_misses::total 42810 # number of ReadExReq misses
953system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 45280 # number of ReadCleanReq misses
954system.cpu0.l2cache.ReadCleanReq_misses::total 45280 # number of ReadCleanReq misses
955system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94167 # number of ReadSharedReq misses
956system.cpu0.l2cache.ReadSharedReq_misses::total 94167 # number of ReadSharedReq misses
957system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 226 # number of demand (read+write) misses
958system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses
959system.cpu0.l2cache.demand_misses::cpu0.inst 45280 # number of demand (read+write) misses
960system.cpu0.l2cache.demand_misses::cpu0.data 136977 # number of demand (read+write) misses
961system.cpu0.l2cache.demand_misses::total 182623 # number of demand (read+write) misses
962system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 226 # number of overall misses
963system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses
964system.cpu0.l2cache.overall_misses::cpu0.inst 45280 # number of overall misses
965system.cpu0.l2cache.overall_misses::cpu0.data 136977 # number of overall misses
966system.cpu0.l2cache.overall_misses::total 182623 # number of overall misses
967system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5649500 # number of ReadReq miss cycles
968system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3340000 # number of ReadReq miss cycles
969system.cpu0.l2cache.ReadReq_miss_latency::total 8989500 # number of ReadReq miss cycles
970system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 99195500 # number of UpgradeReq miss cycles
971system.cpu0.l2cache.UpgradeReq_miss_latency::total 99195500 # number of UpgradeReq miss cycles
972system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22445500 # number of SCUpgradeReq miss cycles
973system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22445500 # number of SCUpgradeReq miss cycles
974system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1343499 # number of SCUpgradeFailReq miss cycles
975system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1343499 # number of SCUpgradeFailReq miss cycles
976system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 # number of ReadExReq miss cycles
977system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles
978system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles
979system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles
| 779system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208508.461248 # average ReadReq mshr uncacheable latency
780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208508.461248 # average ReadReq mshr uncacheable latency
781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 110014.123309 # average overall mshr uncacheable latency
782system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 110014.123309 # average overall mshr uncacheable latency
783system.cpu0.icache.tags.replacements 1103881 # number of replacements
784system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use
785system.cpu0.icache.tags.total_refs 117912387 # Total number of references to valid blocks.
786system.cpu0.icache.tags.sampled_refs 1104393 # Sample count of references to valid blocks.
787system.cpu0.icache.tags.avg_refs 106.766692 # Average number of references to valid blocks.
788system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit.
789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor
790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy
791system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy
792system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
793system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
794system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
795system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id
796system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
797system.cpu0.icache.tags.tag_accesses 239137980 # Number of tag accesses
798system.cpu0.icache.tags.data_accesses 239137980 # Number of data accesses
799system.cpu0.icache.ReadReq_hits::cpu0.inst 117912387 # number of ReadReq hits
800system.cpu0.icache.ReadReq_hits::total 117912387 # number of ReadReq hits
801system.cpu0.icache.demand_hits::cpu0.inst 117912387 # number of demand (read+write) hits
802system.cpu0.icache.demand_hits::total 117912387 # number of demand (read+write) hits
803system.cpu0.icache.overall_hits::cpu0.inst 117912387 # number of overall hits
804system.cpu0.icache.overall_hits::total 117912387 # number of overall hits
805system.cpu0.icache.ReadReq_misses::cpu0.inst 1104402 # number of ReadReq misses
806system.cpu0.icache.ReadReq_misses::total 1104402 # number of ReadReq misses
807system.cpu0.icache.demand_misses::cpu0.inst 1104402 # number of demand (read+write) misses
808system.cpu0.icache.demand_misses::total 1104402 # number of demand (read+write) misses
809system.cpu0.icache.overall_misses::cpu0.inst 1104402 # number of overall misses
810system.cpu0.icache.overall_misses::total 1104402 # number of overall misses
811system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11028665000 # number of ReadReq miss cycles
812system.cpu0.icache.ReadReq_miss_latency::total 11028665000 # number of ReadReq miss cycles
813system.cpu0.icache.demand_miss_latency::cpu0.inst 11028665000 # number of demand (read+write) miss cycles
814system.cpu0.icache.demand_miss_latency::total 11028665000 # number of demand (read+write) miss cycles
815system.cpu0.icache.overall_miss_latency::cpu0.inst 11028665000 # number of overall miss cycles
816system.cpu0.icache.overall_miss_latency::total 11028665000 # number of overall miss cycles
817system.cpu0.icache.ReadReq_accesses::cpu0.inst 119016789 # number of ReadReq accesses(hits+misses)
818system.cpu0.icache.ReadReq_accesses::total 119016789 # number of ReadReq accesses(hits+misses)
819system.cpu0.icache.demand_accesses::cpu0.inst 119016789 # number of demand (read+write) accesses
820system.cpu0.icache.demand_accesses::total 119016789 # number of demand (read+write) accesses
821system.cpu0.icache.overall_accesses::cpu0.inst 119016789 # number of overall (read+write) accesses
822system.cpu0.icache.overall_accesses::total 119016789 # number of overall (read+write) accesses
823system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009279 # miss rate for ReadReq accesses
824system.cpu0.icache.ReadReq_miss_rate::total 0.009279 # miss rate for ReadReq accesses
825system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009279 # miss rate for demand accesses
826system.cpu0.icache.demand_miss_rate::total 0.009279 # miss rate for demand accesses
827system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009279 # miss rate for overall accesses
828system.cpu0.icache.overall_miss_rate::total 0.009279 # miss rate for overall accesses
829system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9986.096548 # average ReadReq miss latency
830system.cpu0.icache.ReadReq_avg_miss_latency::total 9986.096548 # average ReadReq miss latency
831system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency
832system.cpu0.icache.demand_avg_miss_latency::total 9986.096548 # average overall miss latency
833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9986.096548 # average overall miss latency
834system.cpu0.icache.overall_avg_miss_latency::total 9986.096548 # average overall miss latency
835system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
839system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
841system.cpu0.icache.writebacks::writebacks 1103881 # number of writebacks
842system.cpu0.icache.writebacks::total 1103881 # number of writebacks
843system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1104402 # number of ReadReq MSHR misses
844system.cpu0.icache.ReadReq_mshr_misses::total 1104402 # number of ReadReq MSHR misses
845system.cpu0.icache.demand_mshr_misses::cpu0.inst 1104402 # number of demand (read+write) MSHR misses
846system.cpu0.icache.demand_mshr_misses::total 1104402 # number of demand (read+write) MSHR misses
847system.cpu0.icache.overall_mshr_misses::cpu0.inst 1104402 # number of overall MSHR misses
848system.cpu0.icache.overall_mshr_misses::total 1104402 # number of overall MSHR misses
849system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
850system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
851system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
852system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
853system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10476464000 # number of ReadReq MSHR miss cycles
854system.cpu0.icache.ReadReq_mshr_miss_latency::total 10476464000 # number of ReadReq MSHR miss cycles
855system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10476464000 # number of demand (read+write) MSHR miss cycles
856system.cpu0.icache.demand_mshr_miss_latency::total 10476464000 # number of demand (read+write) MSHR miss cycles
857system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10476464000 # number of overall MSHR miss cycles
858system.cpu0.icache.overall_mshr_miss_latency::total 10476464000 # number of overall MSHR miss cycles
859system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles
860system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles
861system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles
862system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles
863system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for ReadReq accesses
864system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009279 # mshr miss rate for ReadReq accesses
865system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for demand accesses
866system.cpu0.icache.demand_mshr_miss_rate::total 0.009279 # mshr miss rate for demand accesses
867system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for overall accesses
868system.cpu0.icache.overall_mshr_miss_rate::total 0.009279 # mshr miss rate for overall accesses
869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average ReadReq mshr miss latency
870system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9486.096548 # average ReadReq mshr miss latency
871system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency
872system.cpu0.icache.demand_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency
873system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency
874system.cpu0.icache.overall_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency
875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency
876system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency
877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency
878system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency
879system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued
880system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified
881system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue
882system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
883system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
884system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing
885system.cpu0.l2cache.tags.replacements 266444 # number of replacements
886system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use
887system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks.
888system.cpu0.l2cache.tags.sampled_refs 282538 # Sample count of references to valid blocks.
889system.cpu0.l2cache.tags.avg_refs 10.354310 # Average number of references to valid blocks.
890system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
891system.cpu0.l2cache.tags.occ_blocks::writebacks 14606.769244 # Average occupied blocks per requestor
892system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.268403 # Average occupied blocks per requestor
893system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.133561 # Average occupied blocks per requestor
894system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1470.339456 # Average occupied blocks per requestor
895system.cpu0.l2cache.tags.occ_percent::writebacks 0.891526 # Average percentage of cache occupancy
896system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000138 # Average percentage of cache occupancy
897system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
898system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.089742 # Average percentage of cache occupancy
899system.cpu0.l2cache.tags.occ_percent::total 0.981415 # Average percentage of cache occupancy
900system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id
901system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
902system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id
903system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
904system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 289 # Occupied blocks per task id
905system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 351 # Occupied blocks per task id
906system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 399 # Occupied blocks per task id
907system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
908system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
909system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id
910system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
911system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id
912system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7676 # Occupied blocks per task id
913system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3752 # Occupied blocks per task id
914system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063904 # Percentage of cache occupancy per task id
915system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
916system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id
917system.cpu0.l2cache.tags.tag_accesses 60110945 # Number of tag accesses
918system.cpu0.l2cache.tags.data_accesses 60110945 # Number of data accesses
919system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10236 # number of ReadReq hits
920system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4573 # number of ReadReq hits
921system.cpu0.l2cache.ReadReq_hits::total 14809 # number of ReadReq hits
922system.cpu0.l2cache.WritebackDirty_hits::writebacks 476837 # number of WritebackDirty hits
923system.cpu0.l2cache.WritebackDirty_hits::total 476837 # number of WritebackDirty hits
924system.cpu0.l2cache.WritebackClean_hits::writebacks 1291246 # number of WritebackClean hits
925system.cpu0.l2cache.WritebackClean_hits::total 1291246 # number of WritebackClean hits
926system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227142 # number of ReadExReq hits
927system.cpu0.l2cache.ReadExReq_hits::total 227142 # number of ReadExReq hits
928system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1059122 # number of ReadCleanReq hits
929system.cpu0.l2cache.ReadCleanReq_hits::total 1059122 # number of ReadCleanReq hits
930system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 383679 # number of ReadSharedReq hits
931system.cpu0.l2cache.ReadSharedReq_hits::total 383679 # number of ReadSharedReq hits
932system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10236 # number of demand (read+write) hits
933system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4573 # number of demand (read+write) hits
934system.cpu0.l2cache.demand_hits::cpu0.inst 1059122 # number of demand (read+write) hits
935system.cpu0.l2cache.demand_hits::cpu0.data 610821 # number of demand (read+write) hits
936system.cpu0.l2cache.demand_hits::total 1684752 # number of demand (read+write) hits
937system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10236 # number of overall hits
938system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4573 # number of overall hits
939system.cpu0.l2cache.overall_hits::cpu0.inst 1059122 # number of overall hits
940system.cpu0.l2cache.overall_hits::cpu0.data 610821 # number of overall hits
941system.cpu0.l2cache.overall_hits::total 1684752 # number of overall hits
942system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 226 # number of ReadReq misses
943system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses
944system.cpu0.l2cache.ReadReq_misses::total 366 # number of ReadReq misses
945system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55088 # number of UpgradeReq misses
946system.cpu0.l2cache.UpgradeReq_misses::total 55088 # number of UpgradeReq misses
947system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses
948system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses
949system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
950system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
951system.cpu0.l2cache.ReadExReq_misses::cpu0.data 42810 # number of ReadExReq misses
952system.cpu0.l2cache.ReadExReq_misses::total 42810 # number of ReadExReq misses
953system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 45280 # number of ReadCleanReq misses
954system.cpu0.l2cache.ReadCleanReq_misses::total 45280 # number of ReadCleanReq misses
955system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94167 # number of ReadSharedReq misses
956system.cpu0.l2cache.ReadSharedReq_misses::total 94167 # number of ReadSharedReq misses
957system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 226 # number of demand (read+write) misses
958system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses
959system.cpu0.l2cache.demand_misses::cpu0.inst 45280 # number of demand (read+write) misses
960system.cpu0.l2cache.demand_misses::cpu0.data 136977 # number of demand (read+write) misses
961system.cpu0.l2cache.demand_misses::total 182623 # number of demand (read+write) misses
962system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 226 # number of overall misses
963system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses
964system.cpu0.l2cache.overall_misses::cpu0.inst 45280 # number of overall misses
965system.cpu0.l2cache.overall_misses::cpu0.data 136977 # number of overall misses
966system.cpu0.l2cache.overall_misses::total 182623 # number of overall misses
967system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5649500 # number of ReadReq miss cycles
968system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3340000 # number of ReadReq miss cycles
969system.cpu0.l2cache.ReadReq_miss_latency::total 8989500 # number of ReadReq miss cycles
970system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 99195500 # number of UpgradeReq miss cycles
971system.cpu0.l2cache.UpgradeReq_miss_latency::total 99195500 # number of UpgradeReq miss cycles
972system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22445500 # number of SCUpgradeReq miss cycles
973system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22445500 # number of SCUpgradeReq miss cycles
974system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1343499 # number of SCUpgradeFailReq miss cycles
975system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1343499 # number of SCUpgradeFailReq miss cycles
976system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047795000 # number of ReadExReq miss cycles
977system.cpu0.l2cache.ReadExReq_miss_latency::total 2047795000 # number of ReadExReq miss cycles
978system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2416123000 # number of ReadCleanReq miss cycles
979system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2416123000 # number of ReadCleanReq miss cycles
|
980system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805930000 # number of ReadSharedReq miss cycles
981system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805930000 # number of ReadSharedReq miss cycles
| 980system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2805928000 # number of ReadSharedReq miss cycles
981system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2805928000 # number of ReadSharedReq miss cycles
|
982system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles
983system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles
984system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles
| 982system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5649500 # number of demand (read+write) miss cycles
983system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3340000 # number of demand (read+write) miss cycles
984system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2416123000 # number of demand (read+write) miss cycles
|
985system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853725000 # number of demand (read+write) miss cycles
986system.cpu0.l2cache.demand_miss_latency::total 7278837500 # number of demand (read+write) miss cycles
| 985system.cpu0.l2cache.demand_miss_latency::cpu0.data 4853723000 # number of demand (read+write) miss cycles
986system.cpu0.l2cache.demand_miss_latency::total 7278835500 # number of demand (read+write) miss cycles
|
987system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles
988system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles
989system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles
| 987system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5649500 # number of overall miss cycles
988system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3340000 # number of overall miss cycles
989system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2416123000 # number of overall miss cycles
|
990system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853725000 # number of overall miss cycles
991system.cpu0.l2cache.overall_miss_latency::total 7278837500 # number of overall miss cycles
| 990system.cpu0.l2cache.overall_miss_latency::cpu0.data 4853723000 # number of overall miss cycles
991system.cpu0.l2cache.overall_miss_latency::total 7278835500 # number of overall miss cycles
|
992system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses)
993system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses)
994system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses)
995system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476837 # number of WritebackDirty accesses(hits+misses)
996system.cpu0.l2cache.WritebackDirty_accesses::total 476837 # number of WritebackDirty accesses(hits+misses)
997system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291246 # number of WritebackClean accesses(hits+misses)
998system.cpu0.l2cache.WritebackClean_accesses::total 1291246 # number of WritebackClean accesses(hits+misses)
999system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55088 # number of UpgradeReq accesses(hits+misses)
1000system.cpu0.l2cache.UpgradeReq_accesses::total 55088 # number of UpgradeReq accesses(hits+misses)
1001system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19799 # number of SCUpgradeReq accesses(hits+misses)
1002system.cpu0.l2cache.SCUpgradeReq_accesses::total 19799 # number of SCUpgradeReq accesses(hits+misses)
1003system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1004system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1005system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269952 # number of ReadExReq accesses(hits+misses)
1006system.cpu0.l2cache.ReadExReq_accesses::total 269952 # number of ReadExReq accesses(hits+misses)
1007system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104402 # number of ReadCleanReq accesses(hits+misses)
1008system.cpu0.l2cache.ReadCleanReq_accesses::total 1104402 # number of ReadCleanReq accesses(hits+misses)
1009system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477846 # number of ReadSharedReq accesses(hits+misses)
1010system.cpu0.l2cache.ReadSharedReq_accesses::total 477846 # number of ReadSharedReq accesses(hits+misses)
1011system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10462 # number of demand (read+write) accesses
1012system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4713 # number of demand (read+write) accesses
1013system.cpu0.l2cache.demand_accesses::cpu0.inst 1104402 # number of demand (read+write) accesses
1014system.cpu0.l2cache.demand_accesses::cpu0.data 747798 # number of demand (read+write) accesses
1015system.cpu0.l2cache.demand_accesses::total 1867375 # number of demand (read+write) accesses
1016system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10462 # number of overall (read+write) accesses
1017system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4713 # number of overall (read+write) accesses
1018system.cpu0.l2cache.overall_accesses::cpu0.inst 1104402 # number of overall (read+write) accesses
1019system.cpu0.l2cache.overall_accesses::cpu0.data 747798 # number of overall (read+write) accesses
1020system.cpu0.l2cache.overall_accesses::total 1867375 # number of overall (read+write) accesses
1021system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for ReadReq accesses
1022system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029705 # miss rate for ReadReq accesses
1023system.cpu0.l2cache.ReadReq_miss_rate::total 0.024119 # miss rate for ReadReq accesses
1024system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1025system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1026system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1027system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1028system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1029system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1030system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.158584 # miss rate for ReadExReq accesses
1031system.cpu0.l2cache.ReadExReq_miss_rate::total 0.158584 # miss rate for ReadExReq accesses
1032system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041000 # miss rate for ReadCleanReq accesses
1033system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041000 # miss rate for ReadCleanReq accesses
1034system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.197066 # miss rate for ReadSharedReq accesses
1035system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.197066 # miss rate for ReadSharedReq accesses
1036system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for demand accesses
1037system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029705 # miss rate for demand accesses
1038system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041000 # miss rate for demand accesses
1039system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183174 # miss rate for demand accesses
1040system.cpu0.l2cache.demand_miss_rate::total 0.097797 # miss rate for demand accesses
1041system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for overall accesses
1042system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029705 # miss rate for overall accesses
1043system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041000 # miss rate for overall accesses
1044system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183174 # miss rate for overall accesses
1045system.cpu0.l2cache.overall_miss_rate::total 0.097797 # miss rate for overall accesses
1046system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average ReadReq miss latency
1047system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.142857 # average ReadReq miss latency
1048system.cpu0.l2cache.ReadReq_avg_miss_latency::total 24561.475410 # average ReadReq miss latency
1049system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1800.673468 # average UpgradeReq miss latency
1050system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1800.673468 # average UpgradeReq miss latency
1051system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1133.668367 # average SCUpgradeReq miss latency
1052system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1133.668367 # average SCUpgradeReq miss latency
1053system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 671749.500000 # average SCUpgradeFailReq miss latency
1054system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 671749.500000 # average SCUpgradeFailReq miss latency
1055system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 # average ReadExReq miss latency
1056system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency
1057system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency
1058system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency
| 992system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10462 # number of ReadReq accesses(hits+misses)
993system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4713 # number of ReadReq accesses(hits+misses)
994system.cpu0.l2cache.ReadReq_accesses::total 15175 # number of ReadReq accesses(hits+misses)
995system.cpu0.l2cache.WritebackDirty_accesses::writebacks 476837 # number of WritebackDirty accesses(hits+misses)
996system.cpu0.l2cache.WritebackDirty_accesses::total 476837 # number of WritebackDirty accesses(hits+misses)
997system.cpu0.l2cache.WritebackClean_accesses::writebacks 1291246 # number of WritebackClean accesses(hits+misses)
998system.cpu0.l2cache.WritebackClean_accesses::total 1291246 # number of WritebackClean accesses(hits+misses)
999system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55088 # number of UpgradeReq accesses(hits+misses)
1000system.cpu0.l2cache.UpgradeReq_accesses::total 55088 # number of UpgradeReq accesses(hits+misses)
1001system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19799 # number of SCUpgradeReq accesses(hits+misses)
1002system.cpu0.l2cache.SCUpgradeReq_accesses::total 19799 # number of SCUpgradeReq accesses(hits+misses)
1003system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1004system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1005system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269952 # number of ReadExReq accesses(hits+misses)
1006system.cpu0.l2cache.ReadExReq_accesses::total 269952 # number of ReadExReq accesses(hits+misses)
1007system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1104402 # number of ReadCleanReq accesses(hits+misses)
1008system.cpu0.l2cache.ReadCleanReq_accesses::total 1104402 # number of ReadCleanReq accesses(hits+misses)
1009system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 477846 # number of ReadSharedReq accesses(hits+misses)
1010system.cpu0.l2cache.ReadSharedReq_accesses::total 477846 # number of ReadSharedReq accesses(hits+misses)
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1012system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4713 # number of demand (read+write) accesses
1013system.cpu0.l2cache.demand_accesses::cpu0.inst 1104402 # number of demand (read+write) accesses
1014system.cpu0.l2cache.demand_accesses::cpu0.data 747798 # number of demand (read+write) accesses
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1016system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10462 # number of overall (read+write) accesses
1017system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4713 # number of overall (read+write) accesses
1018system.cpu0.l2cache.overall_accesses::cpu0.inst 1104402 # number of overall (read+write) accesses
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1020system.cpu0.l2cache.overall_accesses::total 1867375 # number of overall (read+write) accesses
1021system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for ReadReq accesses
1022system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029705 # miss rate for ReadReq accesses
1023system.cpu0.l2cache.ReadReq_miss_rate::total 0.024119 # miss rate for ReadReq accesses
1024system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1025system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1026system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1027system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1028system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1029system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1030system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.158584 # miss rate for ReadExReq accesses
1031system.cpu0.l2cache.ReadExReq_miss_rate::total 0.158584 # miss rate for ReadExReq accesses
1032system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041000 # miss rate for ReadCleanReq accesses
1033system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041000 # miss rate for ReadCleanReq accesses
1034system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.197066 # miss rate for ReadSharedReq accesses
1035system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.197066 # miss rate for ReadSharedReq accesses
1036system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for demand accesses
1037system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029705 # miss rate for demand accesses
1038system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041000 # miss rate for demand accesses
1039system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183174 # miss rate for demand accesses
1040system.cpu0.l2cache.demand_miss_rate::total 0.097797 # miss rate for demand accesses
1041system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021602 # miss rate for overall accesses
1042system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029705 # miss rate for overall accesses
1043system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041000 # miss rate for overall accesses
1044system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183174 # miss rate for overall accesses
1045system.cpu0.l2cache.overall_miss_rate::total 0.097797 # miss rate for overall accesses
1046system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average ReadReq miss latency
1047system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23857.142857 # average ReadReq miss latency
1048system.cpu0.l2cache.ReadReq_avg_miss_latency::total 24561.475410 # average ReadReq miss latency
1049system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1800.673468 # average UpgradeReq miss latency
1050system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1800.673468 # average UpgradeReq miss latency
1051system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1133.668367 # average SCUpgradeReq miss latency
1052system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1133.668367 # average SCUpgradeReq miss latency
1053system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 671749.500000 # average SCUpgradeFailReq miss latency
1054system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 671749.500000 # average SCUpgradeFailReq miss latency
1055system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47834.501285 # average ReadExReq miss latency
1056system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47834.501285 # average ReadExReq miss latency
1057system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53359.606890 # average ReadCleanReq miss latency
1058system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53359.606890 # average ReadCleanReq miss latency
|
1059system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.381248 # average ReadSharedReq miss latency
1060system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.381248 # average ReadSharedReq miss latency
| 1059system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29797.360009 # average ReadSharedReq miss latency
1060system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29797.360009 # average ReadSharedReq miss latency
|
1061system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency
1062system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency
1063system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency
| 1061system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency
1062system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency
1063system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency
|
1064system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency
1065system.cpu0.l2cache.demand_avg_miss_latency::total 39857.178450 # average overall miss latency
| 1064system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency
1065system.cpu0.l2cache.demand_avg_miss_latency::total 39857.167498 # average overall miss latency
|
1066system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency
1067system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency
1068system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency
| 1066system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24997.787611 # average overall miss latency
1067system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23857.142857 # average overall miss latency
1068system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53359.606890 # average overall miss latency
|
1069system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.598509 # average overall miss latency
1070system.cpu0.l2cache.overall_avg_miss_latency::total 39857.178450 # average overall miss latency
| 1069system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35434.583908 # average overall miss latency
1070system.cpu0.l2cache.overall_avg_miss_latency::total 39857.167498 # average overall miss latency
|
1071system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1072system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1073system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1074system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1075system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1076system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1077system.cpu0.l2cache.unused_prefetches 10477 # number of HardPF blocks evicted w/o reference
1078system.cpu0.l2cache.writebacks::writebacks 227975 # number of writebacks
1079system.cpu0.l2cache.writebacks::total 227975 # number of writebacks
1080system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1162 # number of ReadExReq MSHR hits
1081system.cpu0.l2cache.ReadExReq_mshr_hits::total 1162 # number of ReadExReq MSHR hits
1082system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits
1083system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits
1084system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1192 # number of demand (read+write) MSHR hits
1085system.cpu0.l2cache.demand_mshr_hits::total 1192 # number of demand (read+write) MSHR hits
1086system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1192 # number of overall MSHR hits
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1089system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 140 # number of ReadReq MSHR misses
1090system.cpu0.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
1091system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of HardPFReq MSHR misses
1092system.cpu0.l2cache.HardPFReq_mshr_misses::total 259577 # number of HardPFReq MSHR misses
1093system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55088 # number of UpgradeReq MSHR misses
1094system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55088 # number of UpgradeReq MSHR misses
1095system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19799 # number of SCUpgradeReq MSHR misses
1096system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19799 # number of SCUpgradeReq MSHR misses
1097system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
1098system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
1099system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41648 # number of ReadExReq MSHR misses
1100system.cpu0.l2cache.ReadExReq_mshr_misses::total 41648 # number of ReadExReq MSHR misses
1101system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 45280 # number of ReadCleanReq MSHR misses
1102system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 45280 # number of ReadCleanReq MSHR misses
1103system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94137 # number of ReadSharedReq MSHR misses
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1105system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 226 # number of demand (read+write) MSHR misses
1106system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 140 # number of demand (read+write) MSHR misses
1107system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 45280 # number of demand (read+write) MSHR misses
1108system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135785 # number of demand (read+write) MSHR misses
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1111system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 140 # number of overall MSHR misses
1112system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 45280 # number of overall MSHR misses
1113system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135785 # number of overall MSHR misses
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1115system.cpu0.l2cache.overall_mshr_misses::total 441008 # number of overall MSHR misses
1116system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
1117system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable
1118system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40814 # number of ReadReq MSHR uncacheable
1119system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable
1120system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable
1121system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
1122system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses
1123system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 # number of overall MSHR uncacheable misses
1124system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles
1125system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles
1126system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles
| 1071system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1072system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1073system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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1075system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1076system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1077system.cpu0.l2cache.unused_prefetches 10477 # number of HardPF blocks evicted w/o reference
1078system.cpu0.l2cache.writebacks::writebacks 227975 # number of writebacks
1079system.cpu0.l2cache.writebacks::total 227975 # number of writebacks
1080system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1162 # number of ReadExReq MSHR hits
1081system.cpu0.l2cache.ReadExReq_mshr_hits::total 1162 # number of ReadExReq MSHR hits
1082system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 30 # number of ReadSharedReq MSHR hits
1083system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 30 # number of ReadSharedReq MSHR hits
1084system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1192 # number of demand (read+write) MSHR hits
1085system.cpu0.l2cache.demand_mshr_hits::total 1192 # number of demand (read+write) MSHR hits
1086system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1192 # number of overall MSHR hits
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1090system.cpu0.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses
1091system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 259577 # number of HardPFReq MSHR misses
1092system.cpu0.l2cache.HardPFReq_mshr_misses::total 259577 # number of HardPFReq MSHR misses
1093system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55088 # number of UpgradeReq MSHR misses
1094system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55088 # number of UpgradeReq MSHR misses
1095system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19799 # number of SCUpgradeReq MSHR misses
1096system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19799 # number of SCUpgradeReq MSHR misses
1097system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
1098system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
1099system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41648 # number of ReadExReq MSHR misses
1100system.cpu0.l2cache.ReadExReq_mshr_misses::total 41648 # number of ReadExReq MSHR misses
1101system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 45280 # number of ReadCleanReq MSHR misses
1102system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 45280 # number of ReadCleanReq MSHR misses
1103system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94137 # number of ReadSharedReq MSHR misses
1104system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94137 # number of ReadSharedReq MSHR misses
1105system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 226 # number of demand (read+write) MSHR misses
1106system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 140 # number of demand (read+write) MSHR misses
1107system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 45280 # number of demand (read+write) MSHR misses
1108system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135785 # number of demand (read+write) MSHR misses
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1110system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 226 # number of overall MSHR misses
1111system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 140 # number of overall MSHR misses
1112system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 45280 # number of overall MSHR misses
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1115system.cpu0.l2cache.overall_mshr_misses::total 441008 # number of overall MSHR misses
1116system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
1117system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31792 # number of ReadReq MSHR uncacheable
1118system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40814 # number of ReadReq MSHR uncacheable
1119system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28463 # number of WriteReq MSHR uncacheable
1120system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28463 # number of WriteReq MSHR uncacheable
1121system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
1122system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60255 # number of overall MSHR uncacheable misses
1123system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69277 # number of overall MSHR uncacheable misses
1124system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of ReadReq MSHR miss cycles
1125system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2500000 # number of ReadReq MSHR miss cycles
1126system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6793500 # number of ReadReq MSHR miss cycles
|
1127system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of HardPFReq MSHR miss cycles
1128system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785840950 # number of HardPFReq MSHR miss cycles
| 1127system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of HardPFReq MSHR miss cycles
1128system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13785822950 # number of HardPFReq MSHR miss cycles
|
1129system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1059758500 # number of UpgradeReq MSHR miss cycles
1130system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles
1131system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles
1132system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304568000 # number of SCUpgradeReq MSHR miss cycles
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1134system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097499 # number of SCUpgradeFailReq MSHR miss cycles
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1136system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles
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1138system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles
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1130system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1059758500 # number of UpgradeReq MSHR miss cycles
1131system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 304568000 # number of SCUpgradeReq MSHR miss cycles
1132system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 304568000 # number of SCUpgradeReq MSHR miss cycles
1133system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097499 # number of SCUpgradeFailReq MSHR miss cycles
1134system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097499 # number of SCUpgradeFailReq MSHR miss cycles
1135system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1683019500 # number of ReadExReq MSHR miss cycles
1136system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1683019500 # number of ReadExReq MSHR miss cycles
1137system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2144443000 # number of ReadCleanReq MSHR miss cycles
1138system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2144443000 # number of ReadCleanReq MSHR miss cycles
|
1139system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236277000 # number of ReadSharedReq MSHR miss cycles
1140system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236277000 # number of ReadSharedReq MSHR miss cycles
| 1139system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2236275000 # number of ReadSharedReq MSHR miss cycles
1140system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2236275000 # number of ReadSharedReq MSHR miss cycles
|
1141system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles
1142system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles
1143system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles
| 1141system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of demand (read+write) MSHR miss cycles
1142system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2500000 # number of demand (read+write) MSHR miss cycles
1143system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2144443000 # number of demand (read+write) MSHR miss cycles
|
1144system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919296500 # number of demand (read+write) MSHR miss cycles
1145system.cpu0.l2cache.demand_mshr_miss_latency::total 6070533000 # number of demand (read+write) MSHR miss cycles
| 1144system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3919294500 # number of demand (read+write) MSHR miss cycles
1145system.cpu0.l2cache.demand_mshr_miss_latency::total 6070531000 # number of demand (read+write) MSHR miss cycles
|
1146system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles
1147system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles
1148system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles
| 1146system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4293500 # number of overall MSHR miss cycles
1147system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2500000 # number of overall MSHR miss cycles
1148system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2144443000 # number of overall MSHR miss cycles
|
1149system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919296500 # number of overall MSHR miss cycles
1150system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785840950 # number of overall MSHR miss cycles
1151system.cpu0.l2cache.overall_mshr_miss_latency::total 19856373950 # number of overall MSHR miss cycles
| 1149system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3919294500 # number of overall MSHR miss cycles
1150system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13785822950 # number of overall MSHR miss cycles
1151system.cpu0.l2cache.overall_mshr_miss_latency::total 19856353950 # number of overall MSHR miss cycles
|
1152system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles
1153system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles
1154system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles
1155system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles
1156system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6374150500 # number of overall MSHR uncacheable cycles
1157system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117902000 # number of overall MSHR uncacheable cycles
1158system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for ReadReq accesses
1159system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for ReadReq accesses
1160system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024119 # mshr miss rate for ReadReq accesses
1161system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1162system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1163system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1164system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1165system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1166system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1167system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1168system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1169system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154279 # mshr miss rate for ReadExReq accesses
1170system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154279 # mshr miss rate for ReadExReq accesses
1171system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for ReadCleanReq accesses
1172system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041000 # mshr miss rate for ReadCleanReq accesses
1173system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197003 # mshr miss rate for ReadSharedReq accesses
1174system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197003 # mshr miss rate for ReadSharedReq accesses
1175system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for demand accesses
1176system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for demand accesses
1177system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for demand accesses
1178system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for demand accesses
1179system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097158 # mshr miss rate for demand accesses
1180system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for overall accesses
1181system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for overall accesses
1182system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for overall accesses
1183system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for overall accesses
1184system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1185system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 # mshr miss rate for overall accesses
1186system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency
1187system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency
1188system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency
| 1152system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles
1153system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374150500 # number of ReadReq MSHR uncacheable cycles
1154system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7117902000 # number of ReadReq MSHR uncacheable cycles
1155system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles
1156system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6374150500 # number of overall MSHR uncacheable cycles
1157system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7117902000 # number of overall MSHR uncacheable cycles
1158system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for ReadReq accesses
1159system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for ReadReq accesses
1160system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024119 # mshr miss rate for ReadReq accesses
1161system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1162system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1163system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1164system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1165system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1166system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1167system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1168system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1169system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154279 # mshr miss rate for ReadExReq accesses
1170system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154279 # mshr miss rate for ReadExReq accesses
1171system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for ReadCleanReq accesses
1172system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041000 # mshr miss rate for ReadCleanReq accesses
1173system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197003 # mshr miss rate for ReadSharedReq accesses
1174system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197003 # mshr miss rate for ReadSharedReq accesses
1175system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for demand accesses
1176system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for demand accesses
1177system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for demand accesses
1178system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for demand accesses
1179system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097158 # mshr miss rate for demand accesses
1180system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021602 # mshr miss rate for overall accesses
1181system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.029705 # mshr miss rate for overall accesses
1182system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041000 # mshr miss rate for overall accesses
1183system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for overall accesses
1184system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1185system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 # mshr miss rate for overall accesses
1186system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency
1187system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency
1188system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency
|
1189system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average HardPFReq mshr miss latency
1190system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.869237 # average HardPFReq mshr miss latency
| 1189system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average HardPFReq mshr miss latency
1190system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.799894 # average HardPFReq mshr miss latency
|
1191system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency
1192system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency
1193system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency
1194system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15382.999141 # average SCUpgradeReq mshr miss latency
1195system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 548749.500000 # average SCUpgradeFailReq mshr miss latency
1196system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 548749.500000 # average SCUpgradeFailReq mshr miss latency
1197system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 # average ReadExReq mshr miss latency
1198system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency
1199system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency
1200system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency
| 1191system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency
1192system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency
1193system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency
1194system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15382.999141 # average SCUpgradeReq mshr miss latency
1195system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 548749.500000 # average SCUpgradeFailReq mshr miss latency
1196system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 548749.500000 # average SCUpgradeFailReq mshr miss latency
1197system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 # average ReadExReq mshr miss latency
1198system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency
1199system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency
1200system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency
|
1201system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.558388 # average ReadSharedReq mshr miss latency
1202system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.558388 # average ReadSharedReq mshr miss latency
| 1201system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.537143 # average ReadSharedReq mshr miss latency
1202system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.537143 # average ReadSharedReq mshr miss latency
|
1203system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency
1204system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency
1205system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency
| 1203system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency
1204system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency
1205system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency
|
1206system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency
1207system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.182830 # average overall mshr miss latency
| 1206system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency
1207system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.171806 # average overall mshr miss latency
|
1208system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency
1209system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency
1210system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency
| 1208system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency
1209system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency
1210system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency
|
1211system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency
1212system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average overall mshr miss latency
1213system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.974490 # average overall mshr miss latency
| 1211system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.972456 # average overall mshr miss latency
1212system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.799894 # average overall mshr miss latency
1213system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.929140 # average overall mshr miss latency
|
1214system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency
1215system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency
1216system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency
1217system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency
1218system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency
1219system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency
1220system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter.
1221system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1222system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27957 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1223system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter.
1224system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1225system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1226system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution
1227system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution
1228system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution
1229system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution
1230system.cpu0.toL2Bus.trans_dist::WritebackDirty 705040 # Transaction distribution
1231system.cpu0.toL2Bus.trans_dist::WritebackClean 1319203 # Transaction distribution
1232system.cpu0.toL2Bus.trans_dist::CleanEvict 185302 # Transaction distribution
1233system.cpu0.toL2Bus.trans_dist::HardPFReq 307927 # Transaction distribution
1234system.cpu0.toL2Bus.trans_dist::UpgradeReq 87515 # Transaction distribution
1235system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42104 # Transaction distribution
1236system.cpu0.toL2Bus.trans_dist::UpgradeResp 112492 # Transaction distribution
1237system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
1238system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution
1239system.cpu0.toL2Bus.trans_dist::ReadExReq 289204 # Transaction distribution
1240system.cpu0.toL2Bus.trans_dist::ReadExResp 285566 # Transaction distribution
1241system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104402 # Transaction distribution
1242system.cpu0.toL2Bus.trans_dist::ReadSharedReq 556293 # Transaction distribution
1243system.cpu0.toL2Bus.trans_dist::InvalidateReq 3323 # Transaction distribution
1244system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330729 # Packet count per connected master and slave (bytes)
1245system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2559536 # Packet count per connected master and slave (bytes)
1246system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11112 # Packet count per connected master and slave (bytes)
1247system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24847 # Packet count per connected master and slave (bytes)
1248system.cpu0.toL2Bus.pkt_count::total 5926224 # Packet count per connected master and slave (bytes)
1249system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141366200 # Cumulative packet size per connected master and slave (bytes)
1250system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96437860 # Cumulative packet size per connected master and slave (bytes)
1251system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18852 # Cumulative packet size per connected master and slave (bytes)
1252system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41848 # Cumulative packet size per connected master and slave (bytes)
1253system.cpu0.toL2Bus.pkt_size::total 237864760 # Cumulative packet size per connected master and slave (bytes)
1254system.cpu0.toL2Bus.snoops 984362 # Total snoops (count)
1255system.cpu0.toL2Bus.snoop_fanout::samples 2894410 # Request fanout histogram
1256system.cpu0.toL2Bus.snoop_fanout::mean 0.124539 # Request fanout histogram
1257system.cpu0.toL2Bus.snoop_fanout::stdev 0.334666 # Request fanout histogram
1258system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1259system.cpu0.toL2Bus.snoop_fanout::0 2538244 87.69% 87.69% # Request fanout histogram
1260system.cpu0.toL2Bus.snoop_fanout::1 351865 12.16% 99.85% # Request fanout histogram
1261system.cpu0.toL2Bus.snoop_fanout::2 4301 0.15% 100.00% # Request fanout histogram
1262system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1263system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1264system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1265system.cpu0.toL2Bus.snoop_fanout::total 2894410 # Request fanout histogram
1266system.cpu0.toL2Bus.reqLayer0.occupancy 3716866999 # Layer occupancy (ticks)
1267system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1268system.cpu0.toL2Bus.snoopLayer0.occupancy 114649584 # Layer occupancy (ticks)
1269system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1270system.cpu0.toL2Bus.respLayer0.occupancy 1665625000 # Layer occupancy (ticks)
1271system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1272system.cpu0.toL2Bus.respLayer1.occupancy 1205216982 # Layer occupancy (ticks)
1273system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1274system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
1275system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1276system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks)
1277system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1278system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1279system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1280system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1281system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1282system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1283system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1284system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1285system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1286system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1287system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1288system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1289system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1290system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1291system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1292system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1293system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1294system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1295system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1296system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1297system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1298system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1299system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1300system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1301system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1302system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1303system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1304system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1305system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1306system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1307system.cpu1.dtb.walker.walks 3352 # Table walker walks requested
1308system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors
1309system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate
1310system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate
1311system.cpu1.dtb.walker.walkWaitTime::samples 3352 # Table walker wait (enqueue to first request) latency
1312system.cpu1.dtb.walker.walkWaitTime::0 3352 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1313system.cpu1.dtb.walker.walkWaitTime::total 3352 # Table walker wait (enqueue to first request) latency
1314system.cpu1.dtb.walker.walkCompletionTime::samples 2582 # Table walker service (enqueue to completion) latency
1315system.cpu1.dtb.walker.walkCompletionTime::mean 11816.227730 # Table walker service (enqueue to completion) latency
1316system.cpu1.dtb.walker.walkCompletionTime::gmean 11080.373538 # Table walker service (enqueue to completion) latency
1317system.cpu1.dtb.walker.walkCompletionTime::stdev 4768.875507 # Table walker service (enqueue to completion) latency
1318system.cpu1.dtb.walker.walkCompletionTime::0-4095 5 0.19% 0.19% # Table walker service (enqueue to completion) latency
1319system.cpu1.dtb.walker.walkCompletionTime::4096-8191 626 24.24% 24.44% # Table walker service (enqueue to completion) latency
1320system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1198 46.40% 70.84% # Table walker service (enqueue to completion) latency
1321system.cpu1.dtb.walker.walkCompletionTime::12288-16383 544 21.07% 91.91% # Table walker service (enqueue to completion) latency
1322system.cpu1.dtb.walker.walkCompletionTime::16384-20479 85 3.29% 95.20% # Table walker service (enqueue to completion) latency
1323system.cpu1.dtb.walker.walkCompletionTime::20480-24575 56 2.17% 97.37% # Table walker service (enqueue to completion) latency
1324system.cpu1.dtb.walker.walkCompletionTime::24576-28671 31 1.20% 98.57% # Table walker service (enqueue to completion) latency
1325system.cpu1.dtb.walker.walkCompletionTime::28672-32767 20 0.77% 99.34% # Table walker service (enqueue to completion) latency
1326system.cpu1.dtb.walker.walkCompletionTime::32768-36863 3 0.12% 99.46% # Table walker service (enqueue to completion) latency
1327system.cpu1.dtb.walker.walkCompletionTime::36864-40959 8 0.31% 99.77% # Table walker service (enqueue to completion) latency
1328system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency
1329system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.12% 100.00% # Table walker service (enqueue to completion) latency
1330system.cpu1.dtb.walker.walkCompletionTime::total 2582 # Table walker service (enqueue to completion) latency
1331system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution
1332system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution
1333system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution
1334system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.90% 74.90% # Table walker page sizes translated
1335system.cpu1.dtb.walker.walkPageSizes::1M 648 25.10% 100.00% # Table walker page sizes translated
1336system.cpu1.dtb.walker.walkPageSizes::total 2582 # Table walker page sizes translated
1337system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3352 # Table walker requests started/completed, data/inst
1338system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1339system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3352 # Table walker requests started/completed, data/inst
1340system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2582 # Table walker requests started/completed, data/inst
1341system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1342system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst
1343system.cpu1.dtb.walker.walkRequestOrigin::total 5934 # Table walker requests started/completed, data/inst
1344system.cpu1.dtb.inst_hits 0 # ITB inst hits
1345system.cpu1.dtb.inst_misses 0 # ITB inst misses
1346system.cpu1.dtb.read_hits 3941258 # DTB read hits
1347system.cpu1.dtb.read_misses 2845 # DTB read misses
1348system.cpu1.dtb.write_hits 3419362 # DTB write hits
1349system.cpu1.dtb.write_misses 507 # DTB write misses
1350system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1351system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1352system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1353system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1354system.cpu1.dtb.flush_entries 2044 # Number of entries that have been flushed from TLB
1355system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1356system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch
1357system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1358system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
1359system.cpu1.dtb.read_accesses 3944103 # DTB read accesses
1360system.cpu1.dtb.write_accesses 3419869 # DTB write accesses
1361system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1362system.cpu1.dtb.hits 7360620 # DTB hits
1363system.cpu1.dtb.misses 3352 # DTB misses
1364system.cpu1.dtb.accesses 7363972 # DTB accesses
1365system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1366system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1367system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1368system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1369system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1370system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1371system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1372system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1373system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1374system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1375system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1376system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1377system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1378system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1379system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1380system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1381system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1382system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1383system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1384system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1385system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1386system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1387system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1388system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1389system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1390system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1391system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1392system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1393system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1394system.cpu1.itb.walker.walks 1746 # Table walker walks requested
1395system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors
1396system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate
1397system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate
1398system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency
1399system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1400system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency
1401system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency
1402system.cpu1.itb.walker.walkCompletionTime::mean 12335.140018 # Table walker service (enqueue to completion) latency
1403system.cpu1.itb.walker.walkCompletionTime::gmean 11518.936586 # Table walker service (enqueue to completion) latency
1404system.cpu1.itb.walker.walkCompletionTime::stdev 5605.729039 # Table walker service (enqueue to completion) latency
1405system.cpu1.itb.walker.walkCompletionTime::4096-8191 174 15.72% 15.72% # Table walker service (enqueue to completion) latency
1406system.cpu1.itb.walker.walkCompletionTime::8192-12287 657 59.35% 75.07% # Table walker service (enqueue to completion) latency
1407system.cpu1.itb.walker.walkCompletionTime::12288-16383 169 15.27% 90.33% # Table walker service (enqueue to completion) latency
1408system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 95.03% # Table walker service (enqueue to completion) latency
1409system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.12% # Table walker service (enqueue to completion) latency
1410system.cpu1.itb.walker.walkCompletionTime::24576-28671 20 1.81% 96.93% # Table walker service (enqueue to completion) latency
1411system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.37% # Table walker service (enqueue to completion) latency
1412system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 98.64% # Table walker service (enqueue to completion) latency
1413system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.90% 99.55% # Table walker service (enqueue to completion) latency
1414system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.73% # Table walker service (enqueue to completion) latency
1415system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 99.91% # Table walker service (enqueue to completion) latency
1416system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
1417system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency
1418system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution
1419system.cpu1.itb.walker.walksPending::0 -2078939828 100.00% 100.00% # Table walker pending requests distribution
1420system.cpu1.itb.walker.walksPending::total -2078939828 # Table walker pending requests distribution
1421system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated
1422system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated
1423system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated
1424system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1425system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst
1426system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst
1427system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1428system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst
1429system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst
1430system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst
1431system.cpu1.itb.inst_hits 16556610 # ITB inst hits
1432system.cpu1.itb.inst_misses 1746 # ITB inst misses
1433system.cpu1.itb.read_hits 0 # DTB read hits
1434system.cpu1.itb.read_misses 0 # DTB read misses
1435system.cpu1.itb.write_hits 0 # DTB write hits
1436system.cpu1.itb.write_misses 0 # DTB write misses
1437system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1438system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1439system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1440system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1441system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB
1442system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1443system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1444system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1445system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1446system.cpu1.itb.read_accesses 0 # DTB read accesses
1447system.cpu1.itb.write_accesses 0 # DTB write accesses
1448system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses
1449system.cpu1.itb.hits 16556610 # DTB hits
1450system.cpu1.itb.misses 1746 # DTB misses
1451system.cpu1.itb.accesses 16558356 # DTB accesses
1452system.cpu1.numCycles 5738649789 # number of cpu cycles simulated
1453system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1454system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1455system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1456system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed
1457system.cpu1.committedInsts 16201169 # Number of instructions committed
1458system.cpu1.committedOps 19741428 # Number of ops (including micro ops) committed
1459system.cpu1.num_int_alu_accesses 17804295 # Number of integer alu accesses
1460system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses
1461system.cpu1.num_func_calls 1029080 # number of times a function call or return occured
1462system.cpu1.num_conditional_control_insts 1813608 # number of instructions that are conditional controls
1463system.cpu1.num_int_insts 17804295 # number of integer instructions
1464system.cpu1.num_fp_insts 1857 # number of float instructions
1465system.cpu1.num_int_register_reads 32314180 # number of times the integer registers were read
1466system.cpu1.num_int_register_writes 12487661 # number of times the integer registers were written
1467system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read
1468system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
1469system.cpu1.num_cc_register_reads 72166445 # number of times the CC registers were read
1470system.cpu1.num_cc_register_writes 6418557 # number of times the CC registers were written
1471system.cpu1.num_mem_refs 7593995 # number of memory refs
1472system.cpu1.num_load_insts 4052758 # Number of load instructions
1473system.cpu1.num_store_insts 3541237 # Number of store instructions
1474system.cpu1.num_idle_cycles 5686904242.264484 # Number of idle cycles
1475system.cpu1.num_busy_cycles 51745546.735515 # Number of busy cycles
1476system.cpu1.not_idle_fraction 0.009017 # Percentage of non-idle cycles
1477system.cpu1.idle_fraction 0.990983 # Percentage of idle cycles
1478system.cpu1.Branches 2921126 # Number of branches fetched
1479system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
1480system.cpu1.op_class::IntAlu 12468405 62.06% 62.06% # Class of executed instruction
1481system.cpu1.op_class::IntMult 26465 0.13% 62.19% # Class of executed instruction
1482system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction
1483system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction
1484system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction
1485system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction
1486system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction
1487system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction
1488system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction
1489system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction
1490system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction
1491system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction
1492system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction
1493system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction
1494system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction
1495system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction
1496system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction
1497system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction
1498system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction
1499system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction
1500system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction
1501system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction
1502system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction
1503system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction
1504system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction
1505system.cpu1.op_class::SimdFloatMisc 3319 0.02% 62.20% # Class of executed instruction
1506system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction
1507system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction
1508system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction
1509system.cpu1.op_class::MemRead 4052758 20.17% 82.38% # Class of executed instruction
1510system.cpu1.op_class::MemWrite 3541237 17.62% 100.00% # Class of executed instruction
1511system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1512system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1513system.cpu1.op_class::total 20092250 # Class of executed instruction
1514system.cpu1.dcache.tags.replacements 186389 # number of replacements
1515system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use
1516system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks.
1517system.cpu1.dcache.tags.sampled_refs 186755 # Sample count of references to valid blocks.
1518system.cpu1.dcache.tags.avg_refs 37.984359 # Average number of references to valid blocks.
1519system.cpu1.dcache.tags.warmup_cycle 127433218000 # Cycle when the warmup percentage was hit.
1520system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.298921 # Average occupied blocks per requestor
1521system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916599 # Average percentage of cache occupancy
1522system.cpu1.dcache.tags.occ_percent::total 0.916599 # Average percentage of cache occupancy
1523system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id
1524system.cpu1.dcache.tags.age_task_id_blocks_1024::2 285 # Occupied blocks per task id
1525system.cpu1.dcache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id
1526system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id
1527system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses
1528system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses
1529system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits
1530system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits
1531system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits
1532system.cpu1.dcache.WriteReq_hits::total 3230955 # number of WriteReq hits
1533system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48929 # number of SoftPFReq hits
1534system.cpu1.dcache.SoftPFReq_hits::total 48929 # number of SoftPFReq hits
1535system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78822 # number of LoadLockedReq hits
1536system.cpu1.dcache.LoadLockedReq_hits::total 78822 # number of LoadLockedReq hits
1537system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70747 # number of StoreCondReq hits
1538system.cpu1.dcache.StoreCondReq_hits::total 70747 # number of StoreCondReq hits
1539system.cpu1.dcache.demand_hits::cpu1.data 6860355 # number of demand (read+write) hits
1540system.cpu1.dcache.demand_hits::total 6860355 # number of demand (read+write) hits
1541system.cpu1.dcache.overall_hits::cpu1.data 6909284 # number of overall hits
1542system.cpu1.dcache.overall_hits::total 6909284 # number of overall hits
1543system.cpu1.dcache.ReadReq_misses::cpu1.data 133654 # number of ReadReq misses
1544system.cpu1.dcache.ReadReq_misses::total 133654 # number of ReadReq misses
1545system.cpu1.dcache.WriteReq_misses::cpu1.data 91683 # number of WriteReq misses
1546system.cpu1.dcache.WriteReq_misses::total 91683 # number of WriteReq misses
1547system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30306 # number of SoftPFReq misses
1548system.cpu1.dcache.SoftPFReq_misses::total 30306 # number of SoftPFReq misses
1549system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17079 # number of LoadLockedReq misses
1550system.cpu1.dcache.LoadLockedReq_misses::total 17079 # number of LoadLockedReq misses
1551system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23334 # number of StoreCondReq misses
1552system.cpu1.dcache.StoreCondReq_misses::total 23334 # number of StoreCondReq misses
1553system.cpu1.dcache.demand_misses::cpu1.data 225337 # number of demand (read+write) misses
1554system.cpu1.dcache.demand_misses::total 225337 # number of demand (read+write) misses
1555system.cpu1.dcache.overall_misses::cpu1.data 255643 # number of overall misses
1556system.cpu1.dcache.overall_misses::total 255643 # number of overall misses
1557system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1974580500 # number of ReadReq miss cycles
1558system.cpu1.dcache.ReadReq_miss_latency::total 1974580500 # number of ReadReq miss cycles
1559system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2414638500 # number of WriteReq miss cycles
1560system.cpu1.dcache.WriteReq_miss_latency::total 2414638500 # number of WriteReq miss cycles
1561system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320455500 # number of LoadLockedReq miss cycles
1562system.cpu1.dcache.LoadLockedReq_miss_latency::total 320455500 # number of LoadLockedReq miss cycles
1563system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 569715000 # number of StoreCondReq miss cycles
1564system.cpu1.dcache.StoreCondReq_miss_latency::total 569715000 # number of StoreCondReq miss cycles
1565system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3416500 # number of StoreCondFailReq miss cycles
1566system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3416500 # number of StoreCondFailReq miss cycles
1567system.cpu1.dcache.demand_miss_latency::cpu1.data 4389219000 # number of demand (read+write) miss cycles
1568system.cpu1.dcache.demand_miss_latency::total 4389219000 # number of demand (read+write) miss cycles
1569system.cpu1.dcache.overall_miss_latency::cpu1.data 4389219000 # number of overall miss cycles
1570system.cpu1.dcache.overall_miss_latency::total 4389219000 # number of overall miss cycles
1571system.cpu1.dcache.ReadReq_accesses::cpu1.data 3763054 # number of ReadReq accesses(hits+misses)
1572system.cpu1.dcache.ReadReq_accesses::total 3763054 # number of ReadReq accesses(hits+misses)
1573system.cpu1.dcache.WriteReq_accesses::cpu1.data 3322638 # number of WriteReq accesses(hits+misses)
1574system.cpu1.dcache.WriteReq_accesses::total 3322638 # number of WriteReq accesses(hits+misses)
1575system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79235 # number of SoftPFReq accesses(hits+misses)
1576system.cpu1.dcache.SoftPFReq_accesses::total 79235 # number of SoftPFReq accesses(hits+misses)
1577system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95901 # number of LoadLockedReq accesses(hits+misses)
1578system.cpu1.dcache.LoadLockedReq_accesses::total 95901 # number of LoadLockedReq accesses(hits+misses)
1579system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94081 # number of StoreCondReq accesses(hits+misses)
1580system.cpu1.dcache.StoreCondReq_accesses::total 94081 # number of StoreCondReq accesses(hits+misses)
1581system.cpu1.dcache.demand_accesses::cpu1.data 7085692 # number of demand (read+write) accesses
1582system.cpu1.dcache.demand_accesses::total 7085692 # number of demand (read+write) accesses
1583system.cpu1.dcache.overall_accesses::cpu1.data 7164927 # number of overall (read+write) accesses
1584system.cpu1.dcache.overall_accesses::total 7164927 # number of overall (read+write) accesses
1585system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses
1586system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses
1587system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027593 # miss rate for WriteReq accesses
1588system.cpu1.dcache.WriteReq_miss_rate::total 0.027593 # miss rate for WriteReq accesses
1589system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382482 # miss rate for SoftPFReq accesses
1590system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382482 # miss rate for SoftPFReq accesses
1591system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178090 # miss rate for LoadLockedReq accesses
1592system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178090 # miss rate for LoadLockedReq accesses
1593system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248020 # miss rate for StoreCondReq accesses
1594system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248020 # miss rate for StoreCondReq accesses
1595system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031802 # miss rate for demand accesses
1596system.cpu1.dcache.demand_miss_rate::total 0.031802 # miss rate for demand accesses
1597system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035680 # miss rate for overall accesses
1598system.cpu1.dcache.overall_miss_rate::total 0.035680 # miss rate for overall accesses
1599system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.822706 # average ReadReq miss latency
1600system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.822706 # average ReadReq miss latency
1601system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26336.818167 # average WriteReq miss latency
1602system.cpu1.dcache.WriteReq_avg_miss_latency::total 26336.818167 # average WriteReq miss latency
1603system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18763.130160 # average LoadLockedReq miss latency
1604system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18763.130160 # average LoadLockedReq miss latency
1605system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24415.659553 # average StoreCondReq miss latency
1606system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24415.659553 # average StoreCondReq miss latency
1607system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1608system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1609system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19478.465587 # average overall miss latency
1610system.cpu1.dcache.demand_avg_miss_latency::total 19478.465587 # average overall miss latency
1611system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17169.329886 # average overall miss latency
1612system.cpu1.dcache.overall_avg_miss_latency::total 17169.329886 # average overall miss latency
1613system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1614system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1615system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1616system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1617system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1618system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1619system.cpu1.dcache.writebacks::writebacks 186389 # number of writebacks
1620system.cpu1.dcache.writebacks::total 186389 # number of writebacks
1621system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits
1622system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits
1623system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12013 # number of LoadLockedReq MSHR hits
1624system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12013 # number of LoadLockedReq MSHR hits
1625system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits
1626system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits
1627system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits
1628system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits
1629system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133371 # number of ReadReq MSHR misses
1630system.cpu1.dcache.ReadReq_mshr_misses::total 133371 # number of ReadReq MSHR misses
1631system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91683 # number of WriteReq MSHR misses
1632system.cpu1.dcache.WriteReq_mshr_misses::total 91683 # number of WriteReq MSHR misses
1633system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29541 # number of SoftPFReq MSHR misses
1634system.cpu1.dcache.SoftPFReq_mshr_misses::total 29541 # number of SoftPFReq MSHR misses
1635system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5066 # number of LoadLockedReq MSHR misses
1636system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5066 # number of LoadLockedReq MSHR misses
1637system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23334 # number of StoreCondReq MSHR misses
1638system.cpu1.dcache.StoreCondReq_mshr_misses::total 23334 # number of StoreCondReq MSHR misses
1639system.cpu1.dcache.demand_mshr_misses::cpu1.data 225054 # number of demand (read+write) MSHR misses
1640system.cpu1.dcache.demand_mshr_misses::total 225054 # number of demand (read+write) MSHR misses
1641system.cpu1.dcache.overall_mshr_misses::cpu1.data 254595 # number of overall MSHR misses
1642system.cpu1.dcache.overall_mshr_misses::total 254595 # number of overall MSHR misses
1643system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable
1644system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3095 # number of ReadReq MSHR uncacheable
1645system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
1646system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable
1647system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses
1648system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5545 # number of overall MSHR uncacheable misses
1649system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1833975000 # number of ReadReq MSHR miss cycles
1650system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1833975000 # number of ReadReq MSHR miss cycles
1651system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2322955500 # number of WriteReq MSHR miss cycles
1652system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2322955500 # number of WriteReq MSHR miss cycles
1653system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 497374500 # number of SoftPFReq MSHR miss cycles
1654system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 497374500 # number of SoftPFReq MSHR miss cycles
1655system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87920500 # number of LoadLockedReq MSHR miss cycles
1656system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87920500 # number of LoadLockedReq MSHR miss cycles
1657system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 546440000 # number of StoreCondReq MSHR miss cycles
1658system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 546440000 # number of StoreCondReq MSHR miss cycles
1659system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3357500 # number of StoreCondFailReq MSHR miss cycles
1660system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3357500 # number of StoreCondFailReq MSHR miss cycles
1661system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4156930500 # number of demand (read+write) MSHR miss cycles
1662system.cpu1.dcache.demand_mshr_miss_latency::total 4156930500 # number of demand (read+write) MSHR miss cycles
1663system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4654305000 # number of overall MSHR miss cycles
1664system.cpu1.dcache.overall_mshr_miss_latency::total 4654305000 # number of overall MSHR miss cycles
1665system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443417000 # number of ReadReq MSHR uncacheable cycles
1666system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443417000 # number of ReadReq MSHR uncacheable cycles
1667system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443417000 # number of overall MSHR uncacheable cycles
1668system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443417000 # number of overall MSHR uncacheable cycles
1669system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses
1670system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses
1671system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027593 # mshr miss rate for WriteReq accesses
1672system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027593 # mshr miss rate for WriteReq accesses
1673system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372828 # mshr miss rate for SoftPFReq accesses
1674system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372828 # mshr miss rate for SoftPFReq accesses
1675system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052825 # mshr miss rate for LoadLockedReq accesses
1676system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052825 # mshr miss rate for LoadLockedReq accesses
1677system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248020 # mshr miss rate for StoreCondReq accesses
1678system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248020 # mshr miss rate for StoreCondReq accesses
1679system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for demand accesses
1680system.cpu1.dcache.demand_mshr_miss_rate::total 0.031762 # mshr miss rate for demand accesses
1681system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035534 # mshr miss rate for overall accesses
1682system.cpu1.dcache.overall_mshr_miss_rate::total 0.035534 # mshr miss rate for overall accesses
1683system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13750.927863 # average ReadReq mshr miss latency
1684system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13750.927863 # average ReadReq mshr miss latency
1685system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25336.818167 # average WriteReq mshr miss latency
1686system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25336.818167 # average WriteReq mshr miss latency
1687system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16836.752310 # average SoftPFReq mshr miss latency
1688system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16836.752310 # average SoftPFReq mshr miss latency
1689system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17355.013818 # average LoadLockedReq mshr miss latency
1690system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17355.013818 # average LoadLockedReq mshr miss latency
1691system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23418.188052 # average StoreCondReq mshr miss latency
1692system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23418.188052 # average StoreCondReq mshr miss latency
1693system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1694system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1695system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18470.813671 # average overall mshr miss latency
1696system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18470.813671 # average overall mshr miss latency
1697system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18281.211336 # average overall mshr miss latency
1698system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18281.211336 # average overall mshr miss latency
1699system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143268.820679 # average ReadReq mshr uncacheable latency
1700system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency
1701system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency
1702system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency
1703system.cpu1.icache.tags.replacements 505464 # number of replacements
1704system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use
1705system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks.
1706system.cpu1.icache.tags.sampled_refs 505976 # Sample count of references to valid blocks.
1707system.cpu1.icache.tags.avg_refs 31.722115 # Average number of references to valid blocks.
1708system.cpu1.icache.tags.warmup_cycle 85269924000 # Cycle when the warmup percentage was hit.
1709system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478732 # Average occupied blocks per requestor
1710system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy
1711system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy
1712system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1713system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
1714system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id
1715system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
1716system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1717system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses
1718system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses
1719system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits
1720system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits
1721system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits
1722system.cpu1.icache.demand_hits::total 16050629 # number of demand (read+write) hits
1723system.cpu1.icache.overall_hits::cpu1.inst 16050629 # number of overall hits
1724system.cpu1.icache.overall_hits::total 16050629 # number of overall hits
1725system.cpu1.icache.ReadReq_misses::cpu1.inst 505976 # number of ReadReq misses
1726system.cpu1.icache.ReadReq_misses::total 505976 # number of ReadReq misses
1727system.cpu1.icache.demand_misses::cpu1.inst 505976 # number of demand (read+write) misses
1728system.cpu1.icache.demand_misses::total 505976 # number of demand (read+write) misses
1729system.cpu1.icache.overall_misses::cpu1.inst 505976 # number of overall misses
1730system.cpu1.icache.overall_misses::total 505976 # number of overall misses
1731system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4528088500 # number of ReadReq miss cycles
1732system.cpu1.icache.ReadReq_miss_latency::total 4528088500 # number of ReadReq miss cycles
1733system.cpu1.icache.demand_miss_latency::cpu1.inst 4528088500 # number of demand (read+write) miss cycles
1734system.cpu1.icache.demand_miss_latency::total 4528088500 # number of demand (read+write) miss cycles
1735system.cpu1.icache.overall_miss_latency::cpu1.inst 4528088500 # number of overall miss cycles
1736system.cpu1.icache.overall_miss_latency::total 4528088500 # number of overall miss cycles
1737system.cpu1.icache.ReadReq_accesses::cpu1.inst 16556605 # number of ReadReq accesses(hits+misses)
1738system.cpu1.icache.ReadReq_accesses::total 16556605 # number of ReadReq accesses(hits+misses)
1739system.cpu1.icache.demand_accesses::cpu1.inst 16556605 # number of demand (read+write) accesses
1740system.cpu1.icache.demand_accesses::total 16556605 # number of demand (read+write) accesses
1741system.cpu1.icache.overall_accesses::cpu1.inst 16556605 # number of overall (read+write) accesses
1742system.cpu1.icache.overall_accesses::total 16556605 # number of overall (read+write) accesses
1743system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030560 # miss rate for ReadReq accesses
1744system.cpu1.icache.ReadReq_miss_rate::total 0.030560 # miss rate for ReadReq accesses
1745system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030560 # miss rate for demand accesses
1746system.cpu1.icache.demand_miss_rate::total 0.030560 # miss rate for demand accesses
1747system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030560 # miss rate for overall accesses
1748system.cpu1.icache.overall_miss_rate::total 0.030560 # miss rate for overall accesses
1749system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8949.215971 # average ReadReq miss latency
1750system.cpu1.icache.ReadReq_avg_miss_latency::total 8949.215971 # average ReadReq miss latency
1751system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency
1752system.cpu1.icache.demand_avg_miss_latency::total 8949.215971 # average overall miss latency
1753system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency
1754system.cpu1.icache.overall_avg_miss_latency::total 8949.215971 # average overall miss latency
1755system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1756system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1757system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1758system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1759system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1760system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1761system.cpu1.icache.writebacks::writebacks 505464 # number of writebacks
1762system.cpu1.icache.writebacks::total 505464 # number of writebacks
1763system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 505976 # number of ReadReq MSHR misses
1764system.cpu1.icache.ReadReq_mshr_misses::total 505976 # number of ReadReq MSHR misses
1765system.cpu1.icache.demand_mshr_misses::cpu1.inst 505976 # number of demand (read+write) MSHR misses
1766system.cpu1.icache.demand_mshr_misses::total 505976 # number of demand (read+write) MSHR misses
1767system.cpu1.icache.overall_mshr_misses::cpu1.inst 505976 # number of overall MSHR misses
1768system.cpu1.icache.overall_mshr_misses::total 505976 # number of overall MSHR misses
1769system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
1770system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
1771system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
1772system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
1773system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4275100500 # number of ReadReq MSHR miss cycles
1774system.cpu1.icache.ReadReq_mshr_miss_latency::total 4275100500 # number of ReadReq MSHR miss cycles
1775system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4275100500 # number of demand (read+write) MSHR miss cycles
1776system.cpu1.icache.demand_mshr_miss_latency::total 4275100500 # number of demand (read+write) MSHR miss cycles
1777system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4275100500 # number of overall MSHR miss cycles
1778system.cpu1.icache.overall_mshr_miss_latency::total 4275100500 # number of overall MSHR miss cycles
1779system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # number of ReadReq MSHR uncacheable cycles
1780system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15776500 # number of ReadReq MSHR uncacheable cycles
1781system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15776500 # number of overall MSHR uncacheable cycles
1782system.cpu1.icache.overall_mshr_uncacheable_latency::total 15776500 # number of overall MSHR uncacheable cycles
1783system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for ReadReq accesses
1784system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030560 # mshr miss rate for ReadReq accesses
1785system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for demand accesses
1786system.cpu1.icache.demand_mshr_miss_rate::total 0.030560 # mshr miss rate for demand accesses
1787system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for overall accesses
1788system.cpu1.icache.overall_mshr_miss_rate::total 0.030560 # mshr miss rate for overall accesses
1789system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average ReadReq mshr miss latency
1790system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8449.215971 # average ReadReq mshr miss latency
1791system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency
1792system.cpu1.icache.demand_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency
1793system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency
1794system.cpu1.icache.overall_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency
1795system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency
1796system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency
1797system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency
1798system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency
1799system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued
1800system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified
1801system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
1802system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1803system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1804system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing
1805system.cpu1.l2cache.tags.replacements 44688 # number of replacements
1806system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use
1807system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks.
1808system.cpu1.l2cache.tags.sampled_refs 59377 # Sample count of references to valid blocks.
1809system.cpu1.l2cache.tags.avg_refs 19.563737 # Average number of references to valid blocks.
1810system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1811system.cpu1.l2cache.tags.occ_blocks::writebacks 14464.281457 # Average occupied blocks per requestor
1812system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.152749 # Average occupied blocks per requestor
1813system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.089726 # Average occupied blocks per requestor
1814system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 468.961320 # Average occupied blocks per requestor
1815system.cpu1.l2cache.tags.occ_percent::writebacks 0.882830 # Average percentage of cache occupancy
1816system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy
1817system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy
1818system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028623 # Average percentage of cache occupancy
1819system.cpu1.l2cache.tags.occ_percent::total 0.911773 # Average percentage of cache occupancy
1820system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id
1821system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
1822system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13646 # Occupied blocks per task id
1823system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 36 # Occupied blocks per task id
1824system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 993 # Occupied blocks per task id
1825system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
1826system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
1827system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id
1828system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id
1829system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11682 # Occupied blocks per task id
1830system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id
1831system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
1832system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832886 # Percentage of cache occupancy per task id
1833system.cpu1.l2cache.tags.tag_accesses 23775762 # Number of tag accesses
1834system.cpu1.l2cache.tags.data_accesses 23775762 # Number of data accesses
1835system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3761 # number of ReadReq hits
1836system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2010 # number of ReadReq hits
1837system.cpu1.l2cache.ReadReq_hits::total 5771 # number of ReadReq hits
1838system.cpu1.l2cache.WritebackDirty_hits::writebacks 113707 # number of WritebackDirty hits
1839system.cpu1.l2cache.WritebackDirty_hits::total 113707 # number of WritebackDirty hits
1840system.cpu1.l2cache.WritebackClean_hits::writebacks 567008 # number of WritebackClean hits
1841system.cpu1.l2cache.WritebackClean_hits::total 567008 # number of WritebackClean hits
1842system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27229 # number of ReadExReq hits
1843system.cpu1.l2cache.ReadExReq_hits::total 27229 # number of ReadExReq hits
1844system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 492726 # number of ReadCleanReq hits
1845system.cpu1.l2cache.ReadCleanReq_hits::total 492726 # number of ReadCleanReq hits
1846system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99930 # number of ReadSharedReq hits
1847system.cpu1.l2cache.ReadSharedReq_hits::total 99930 # number of ReadSharedReq hits
1848system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3761 # number of demand (read+write) hits
1849system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2010 # number of demand (read+write) hits
1850system.cpu1.l2cache.demand_hits::cpu1.inst 492726 # number of demand (read+write) hits
1851system.cpu1.l2cache.demand_hits::cpu1.data 127159 # number of demand (read+write) hits
1852system.cpu1.l2cache.demand_hits::total 625656 # number of demand (read+write) hits
1853system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3761 # number of overall hits
1854system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2010 # number of overall hits
1855system.cpu1.l2cache.overall_hits::cpu1.inst 492726 # number of overall hits
1856system.cpu1.l2cache.overall_hits::cpu1.data 127159 # number of overall hits
1857system.cpu1.l2cache.overall_hits::total 625656 # number of overall hits
1858system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 318 # number of ReadReq misses
1859system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses
1860system.cpu1.l2cache.ReadReq_misses::total 590 # number of ReadReq misses
1861system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29672 # number of UpgradeReq misses
1862system.cpu1.l2cache.UpgradeReq_misses::total 29672 # number of UpgradeReq misses
1863system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23330 # number of SCUpgradeReq misses
1864system.cpu1.l2cache.SCUpgradeReq_misses::total 23330 # number of SCUpgradeReq misses
1865system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses
1866system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
1867system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34782 # number of ReadExReq misses
1868system.cpu1.l2cache.ReadExReq_misses::total 34782 # number of ReadExReq misses
1869system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13250 # number of ReadCleanReq misses
1870system.cpu1.l2cache.ReadCleanReq_misses::total 13250 # number of ReadCleanReq misses
1871system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68048 # number of ReadSharedReq misses
1872system.cpu1.l2cache.ReadSharedReq_misses::total 68048 # number of ReadSharedReq misses
1873system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 318 # number of demand (read+write) misses
1874system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses
1875system.cpu1.l2cache.demand_misses::cpu1.inst 13250 # number of demand (read+write) misses
1876system.cpu1.l2cache.demand_misses::cpu1.data 102830 # number of demand (read+write) misses
1877system.cpu1.l2cache.demand_misses::total 116670 # number of demand (read+write) misses
1878system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 318 # number of overall misses
1879system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses
1880system.cpu1.l2cache.overall_misses::cpu1.inst 13250 # number of overall misses
1881system.cpu1.l2cache.overall_misses::cpu1.data 102830 # number of overall misses
1882system.cpu1.l2cache.overall_misses::total 116670 # number of overall misses
1883system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6473000 # number of ReadReq miss cycles
1884system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5557000 # number of ReadReq miss cycles
1885system.cpu1.l2cache.ReadReq_miss_latency::total 12030000 # number of ReadReq miss cycles
1886system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65067000 # number of UpgradeReq miss cycles
1887system.cpu1.l2cache.UpgradeReq_miss_latency::total 65067000 # number of UpgradeReq miss cycles
1888system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 32437500 # number of SCUpgradeReq miss cycles
1889system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 32437500 # number of SCUpgradeReq miss cycles
1890system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3268500 # number of SCUpgradeFailReq miss cycles
1891system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3268500 # number of SCUpgradeFailReq miss cycles
1892system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1333613500 # number of ReadExReq miss cycles
1893system.cpu1.l2cache.ReadExReq_miss_latency::total 1333613500 # number of ReadExReq miss cycles
1894system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 533576500 # number of ReadCleanReq miss cycles
1895system.cpu1.l2cache.ReadCleanReq_miss_latency::total 533576500 # number of ReadCleanReq miss cycles
1896system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1512816500 # number of ReadSharedReq miss cycles
1897system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1512816500 # number of ReadSharedReq miss cycles
1898system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6473000 # number of demand (read+write) miss cycles
1899system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5557000 # number of demand (read+write) miss cycles
1900system.cpu1.l2cache.demand_miss_latency::cpu1.inst 533576500 # number of demand (read+write) miss cycles
1901system.cpu1.l2cache.demand_miss_latency::cpu1.data 2846430000 # number of demand (read+write) miss cycles
1902system.cpu1.l2cache.demand_miss_latency::total 3392036500 # number of demand (read+write) miss cycles
1903system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6473000 # number of overall miss cycles
1904system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5557000 # number of overall miss cycles
1905system.cpu1.l2cache.overall_miss_latency::cpu1.inst 533576500 # number of overall miss cycles
1906system.cpu1.l2cache.overall_miss_latency::cpu1.data 2846430000 # number of overall miss cycles
1907system.cpu1.l2cache.overall_miss_latency::total 3392036500 # number of overall miss cycles
1908system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4079 # number of ReadReq accesses(hits+misses)
1909system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2282 # number of ReadReq accesses(hits+misses)
1910system.cpu1.l2cache.ReadReq_accesses::total 6361 # number of ReadReq accesses(hits+misses)
1911system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113707 # number of WritebackDirty accesses(hits+misses)
1912system.cpu1.l2cache.WritebackDirty_accesses::total 113707 # number of WritebackDirty accesses(hits+misses)
1913system.cpu1.l2cache.WritebackClean_accesses::writebacks 567008 # number of WritebackClean accesses(hits+misses)
1914system.cpu1.l2cache.WritebackClean_accesses::total 567008 # number of WritebackClean accesses(hits+misses)
1915system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29672 # number of UpgradeReq accesses(hits+misses)
1916system.cpu1.l2cache.UpgradeReq_accesses::total 29672 # number of UpgradeReq accesses(hits+misses)
1917system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23330 # number of SCUpgradeReq accesses(hits+misses)
1918system.cpu1.l2cache.SCUpgradeReq_accesses::total 23330 # number of SCUpgradeReq accesses(hits+misses)
1919system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
1920system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
1921system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62011 # number of ReadExReq accesses(hits+misses)
1922system.cpu1.l2cache.ReadExReq_accesses::total 62011 # number of ReadExReq accesses(hits+misses)
1923system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 505976 # number of ReadCleanReq accesses(hits+misses)
1924system.cpu1.l2cache.ReadCleanReq_accesses::total 505976 # number of ReadCleanReq accesses(hits+misses)
1925system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167978 # number of ReadSharedReq accesses(hits+misses)
1926system.cpu1.l2cache.ReadSharedReq_accesses::total 167978 # number of ReadSharedReq accesses(hits+misses)
1927system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4079 # number of demand (read+write) accesses
1928system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2282 # number of demand (read+write) accesses
1929system.cpu1.l2cache.demand_accesses::cpu1.inst 505976 # number of demand (read+write) accesses
1930system.cpu1.l2cache.demand_accesses::cpu1.data 229989 # number of demand (read+write) accesses
1931system.cpu1.l2cache.demand_accesses::total 742326 # number of demand (read+write) accesses
1932system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4079 # number of overall (read+write) accesses
1933system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2282 # number of overall (read+write) accesses
1934system.cpu1.l2cache.overall_accesses::cpu1.inst 505976 # number of overall (read+write) accesses
1935system.cpu1.l2cache.overall_accesses::cpu1.data 229989 # number of overall (read+write) accesses
1936system.cpu1.l2cache.overall_accesses::total 742326 # number of overall (read+write) accesses
1937system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for ReadReq accesses
1938system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.119194 # miss rate for ReadReq accesses
1939system.cpu1.l2cache.ReadReq_miss_rate::total 0.092753 # miss rate for ReadReq accesses
1940system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1941system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1942system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1943system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1944system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1945system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1946system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560900 # miss rate for ReadExReq accesses
1947system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560900 # miss rate for ReadExReq accesses
1948system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026187 # miss rate for ReadCleanReq accesses
1949system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026187 # miss rate for ReadCleanReq accesses
1950system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405101 # miss rate for ReadSharedReq accesses
1951system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405101 # miss rate for ReadSharedReq accesses
1952system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for demand accesses
1953system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.119194 # miss rate for demand accesses
1954system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026187 # miss rate for demand accesses
1955system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.447108 # miss rate for demand accesses
1956system.cpu1.l2cache.demand_miss_rate::total 0.157168 # miss rate for demand accesses
1957system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for overall accesses
1958system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.119194 # miss rate for overall accesses
1959system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026187 # miss rate for overall accesses
1960system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.447108 # miss rate for overall accesses
1961system.cpu1.l2cache.overall_miss_rate::total 0.157168 # miss rate for overall accesses
1962system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average ReadReq miss latency
1963system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20430.147059 # average ReadReq miss latency
1964system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20389.830508 # average ReadReq miss latency
1965system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2192.875438 # average UpgradeReq miss latency
1966system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2192.875438 # average UpgradeReq miss latency
1967system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1390.377197 # average SCUpgradeReq miss latency
1968system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1390.377197 # average SCUpgradeReq miss latency
1969system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 817125 # average SCUpgradeFailReq miss latency
1970system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 817125 # average SCUpgradeFailReq miss latency
1971system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38342.059111 # average ReadExReq miss latency
1972system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38342.059111 # average ReadExReq miss latency
1973system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40269.924528 # average ReadCleanReq miss latency
1974system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40269.924528 # average ReadCleanReq miss latency
1975system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22231.608570 # average ReadSharedReq miss latency
1976system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22231.608570 # average ReadSharedReq miss latency
1977system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency
1978system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency
1979system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency
1980system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency
1981system.cpu1.l2cache.demand_avg_miss_latency::total 29073.767892 # average overall miss latency
1982system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency
1983system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency
1984system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency
1985system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency
1986system.cpu1.l2cache.overall_avg_miss_latency::total 29073.767892 # average overall miss latency
1987system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1988system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1989system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1990system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1991system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1992system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1993system.cpu1.l2cache.unused_prefetches 790 # number of HardPF blocks evicted w/o reference
1994system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks
1995system.cpu1.l2cache.writebacks::total 33019 # number of writebacks
1996system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 57 # number of ReadExReq MSHR hits
1997system.cpu1.l2cache.ReadExReq_mshr_hits::total 57 # number of ReadExReq MSHR hits
1998system.cpu1.l2cache.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits
1999system.cpu1.l2cache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits
2000system.cpu1.l2cache.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits
2001system.cpu1.l2cache.overall_mshr_hits::total 57 # number of overall MSHR hits
2002system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 318 # number of ReadReq MSHR misses
2003system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 272 # number of ReadReq MSHR misses
2004system.cpu1.l2cache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses
2005system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of HardPFReq MSHR misses
2006system.cpu1.l2cache.HardPFReq_mshr_misses::total 24979 # number of HardPFReq MSHR misses
2007system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29672 # number of UpgradeReq MSHR misses
2008system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29672 # number of UpgradeReq MSHR misses
2009system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23330 # number of SCUpgradeReq MSHR misses
2010system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23330 # number of SCUpgradeReq MSHR misses
2011system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses
2012system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
2013system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34725 # number of ReadExReq MSHR misses
2014system.cpu1.l2cache.ReadExReq_mshr_misses::total 34725 # number of ReadExReq MSHR misses
2015system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13250 # number of ReadCleanReq MSHR misses
2016system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13250 # number of ReadCleanReq MSHR misses
2017system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68048 # number of ReadSharedReq MSHR misses
2018system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68048 # number of ReadSharedReq MSHR misses
2019system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 318 # number of demand (read+write) MSHR misses
2020system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 272 # number of demand (read+write) MSHR misses
2021system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13250 # number of demand (read+write) MSHR misses
2022system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102773 # number of demand (read+write) MSHR misses
2023system.cpu1.l2cache.demand_mshr_misses::total 116613 # number of demand (read+write) MSHR misses
2024system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 318 # number of overall MSHR misses
2025system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 272 # number of overall MSHR misses
2026system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13250 # number of overall MSHR misses
2027system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102773 # number of overall MSHR misses
2028system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of overall MSHR misses
2029system.cpu1.l2cache.overall_mshr_misses::total 141592 # number of overall MSHR misses
2030system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2031system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable
2032system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3272 # number of ReadReq MSHR uncacheable
2033system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
2034system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable
2035system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2036system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses
2037system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5722 # number of overall MSHR uncacheable misses
2038system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of ReadReq MSHR miss cycles
2039system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3925000 # number of ReadReq MSHR miss cycles
2040system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8490000 # number of ReadReq MSHR miss cycles
2041system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of HardPFReq MSHR miss cycles
2042system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 780424807 # number of HardPFReq MSHR miss cycles
2043system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 494079500 # number of UpgradeReq MSHR miss cycles
2044system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 494079500 # number of UpgradeReq MSHR miss cycles
2045system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 371536000 # number of SCUpgradeReq MSHR miss cycles
2046system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 371536000 # number of SCUpgradeReq MSHR miss cycles
2047system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2914500 # number of SCUpgradeFailReq MSHR miss cycles
2048system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2914500 # number of SCUpgradeFailReq MSHR miss cycles
2049system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1118604500 # number of ReadExReq MSHR miss cycles
2050system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1118604500 # number of ReadExReq MSHR miss cycles
2051system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 454076500 # number of ReadCleanReq MSHR miss cycles
2052system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 454076500 # number of ReadCleanReq MSHR miss cycles
2053system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1104528500 # number of ReadSharedReq MSHR miss cycles
2054system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1104528500 # number of ReadSharedReq MSHR miss cycles
2055system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of demand (read+write) MSHR miss cycles
2056system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3925000 # number of demand (read+write) MSHR miss cycles
2057system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454076500 # number of demand (read+write) MSHR miss cycles
2058system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2223133000 # number of demand (read+write) MSHR miss cycles
2059system.cpu1.l2cache.demand_mshr_miss_latency::total 2685699500 # number of demand (read+write) MSHR miss cycles
2060system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of overall MSHR miss cycles
2061system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3925000 # number of overall MSHR miss cycles
2062system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454076500 # number of overall MSHR miss cycles
2063system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2223133000 # number of overall MSHR miss cycles
2064system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of overall MSHR miss cycles
2065system.cpu1.l2cache.overall_mshr_miss_latency::total 3466124307 # number of overall MSHR miss cycles
2066system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14449000 # number of ReadReq MSHR uncacheable cycles
2067system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418310000 # number of ReadReq MSHR uncacheable cycles
2068system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432759000 # number of ReadReq MSHR uncacheable cycles
2069system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14449000 # number of overall MSHR uncacheable cycles
2070system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418310000 # number of overall MSHR uncacheable cycles
2071system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432759000 # number of overall MSHR uncacheable cycles
2072system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for ReadReq accesses
2073system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for ReadReq accesses
2074system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.092753 # mshr miss rate for ReadReq accesses
2075system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2076system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2077system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2078system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2079system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2080system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2081system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2082system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2083system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559981 # mshr miss rate for ReadExReq accesses
2084system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559981 # mshr miss rate for ReadExReq accesses
2085system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for ReadCleanReq accesses
2086system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadCleanReq accesses
2087system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.405101 # mshr miss rate for ReadSharedReq accesses
2088system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405101 # mshr miss rate for ReadSharedReq accesses
2089system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for demand accesses
2090system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for demand accesses
2091system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for demand accesses
2092system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for demand accesses
2093system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157091 # mshr miss rate for demand accesses
2094system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for overall accesses
2095system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for overall accesses
2096system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for overall accesses
2097system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for overall accesses
2098system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2099system.cpu1.l2cache.overall_mshr_miss_rate::total 0.190741 # mshr miss rate for overall accesses
2100system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average ReadReq mshr miss latency
2101system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average ReadReq mshr miss latency
2102system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14389.830508 # average ReadReq mshr miss latency
2103system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average HardPFReq mshr miss latency
2104system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31243.236599 # average HardPFReq mshr miss latency
2105system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16651.371664 # average UpgradeReq mshr miss latency
2106system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16651.371664 # average UpgradeReq mshr miss latency
2107system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15925.246464 # average SCUpgradeReq mshr miss latency
2108system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15925.246464 # average SCUpgradeReq mshr miss latency
2109system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 728625 # average SCUpgradeFailReq mshr miss latency
2110system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 728625 # average SCUpgradeFailReq mshr miss latency
2111system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32213.232541 # average ReadExReq mshr miss latency
2112system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32213.232541 # average ReadExReq mshr miss latency
2113system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average ReadCleanReq mshr miss latency
2114system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34269.924528 # average ReadCleanReq mshr miss latency
2115system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16231.608570 # average ReadSharedReq mshr miss latency
2116system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16231.608570 # average ReadSharedReq mshr miss latency
2117system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency
2118system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency
2119system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency
2120system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency
2121system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23030.875631 # average overall mshr miss latency
2122system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency
2123system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency
2124system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency
2125system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency
2126system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average overall mshr miss latency
2127system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24479.662036 # average overall mshr miss latency
2128system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency
2129system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135156.704362 # average ReadReq mshr uncacheable latency
2130system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132261.308068 # average ReadReq mshr uncacheable latency
2131system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency
2132system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75439.134355 # average overall mshr uncacheable latency
2133system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75630.723523 # average overall mshr uncacheable latency
2134system.cpu1.toL2Bus.snoop_filter.tot_requests 1487204 # Total number of requests made to the snoop filter.
2135system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751274 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2136system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2137system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter.
2138system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2139system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2140system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution
2141system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution
2142system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution
2143system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution
2144system.cpu1.toL2Bus.trans_dist::WritebackDirty 147816 # Transaction distribution
2145system.cpu1.toL2Bus.trans_dist::WritebackClean 578146 # Transaction distribution
2146system.cpu1.toL2Bus.trans_dist::CleanEvict 101473 # Transaction distribution
2147system.cpu1.toL2Bus.trans_dist::HardPFReq 30088 # Transaction distribution
2148system.cpu1.toL2Bus.trans_dist::UpgradeReq 71412 # Transaction distribution
2149system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41204 # Transaction distribution
2150system.cpu1.toL2Bus.trans_dist::UpgradeResp 85825 # Transaction distribution
2151system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
2152system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution
2153system.cpu1.toL2Bus.trans_dist::ReadExReq 69105 # Transaction distribution
2154system.cpu1.toL2Bus.trans_dist::ReadExResp 66696 # Transaction distribution
2155system.cpu1.toL2Bus.trans_dist::ReadCleanReq 505976 # Transaction distribution
2156system.cpu1.toL2Bus.trans_dist::ReadSharedReq 245752 # Transaction distribution
2157system.cpu1.toL2Bus.trans_dist::InvalidateReq 247 # Transaction distribution
2158system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1517770 # Packet count per connected master and slave (bytes)
2159system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838774 # Packet count per connected master and slave (bytes)
2160system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5606 # Packet count per connected master and slave (bytes)
2161system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10127 # Packet count per connected master and slave (bytes)
2162system.cpu1.toL2Bus.pkt_count::total 2372277 # Packet count per connected master and slave (bytes)
2163system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64732868 # Cumulative packet size per connected master and slave (bytes)
2164system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29385740 # Cumulative packet size per connected master and slave (bytes)
2165system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9128 # Cumulative packet size per connected master and slave (bytes)
2166system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16316 # Cumulative packet size per connected master and slave (bytes)
2167system.cpu1.toL2Bus.pkt_size::total 94144052 # Cumulative packet size per connected master and slave (bytes)
2168system.cpu1.toL2Bus.snoops 388756 # Total snoops (count)
2169system.cpu1.toL2Bus.snoop_fanout::samples 1114505 # Request fanout histogram
2170system.cpu1.toL2Bus.snoop_fanout::mean 0.179300 # Request fanout histogram
2171system.cpu1.toL2Bus.snoop_fanout::stdev 0.390891 # Request fanout histogram
2172system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2173system.cpu1.toL2Bus.snoop_fanout::0 917819 82.35% 82.35% # Request fanout histogram
2174system.cpu1.toL2Bus.snoop_fanout::1 193541 17.37% 99.72% # Request fanout histogram
2175system.cpu1.toL2Bus.snoop_fanout::2 3145 0.28% 100.00% # Request fanout histogram
2176system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2177system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2178system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2179system.cpu1.toL2Bus.snoop_fanout::total 1114505 # Request fanout histogram
2180system.cpu1.toL2Bus.reqLayer0.occupancy 1441037000 # Layer occupancy (ticks)
2181system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2182system.cpu1.toL2Bus.snoopLayer0.occupancy 80111937 # Layer occupancy (ticks)
2183system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2184system.cpu1.toL2Bus.respLayer0.occupancy 759141000 # Layer occupancy (ticks)
2185system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2186system.cpu1.toL2Bus.respLayer1.occupancy 375865500 # Layer occupancy (ticks)
2187system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2188system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks)
2189system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2190system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks)
2191system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2192system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
2193system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
2194system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
2195system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
2196system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
2197system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2198system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2199system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2200system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2201system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2202system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2203system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2204system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2205system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2206system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2207system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2208system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2209system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2210system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2211system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2212system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2213system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2214system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2215system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
2216system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
2217system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
2218system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes)
2219system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
2220system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2221system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2222system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2223system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2224system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2225system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2226system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2227system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2228system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2229system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2230system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2231system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2232system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2233system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2234system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2235system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2236system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2237system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2238system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
2239system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
2240system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
2241system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes)
2242system.iobus.reqLayer0.occupancy 48726000 # Layer occupancy (ticks)
2243system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2244system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks)
2245system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2246system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks)
2247system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2248system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks)
2249system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2250system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
2251system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2252system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks)
2253system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2254system.iobus.reqLayer8.occupancy 601500 # Layer occupancy (ticks)
2255system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2256system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks)
2257system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2258system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2259system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2260system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
2261system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2262system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
2263system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2264system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks)
2265system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2266system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
2267system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2268system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks)
2269system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2270system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2271system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2272system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2273system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2274system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2275system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2276system.iobus.reqLayer23.occupancy 6164000 # Layer occupancy (ticks)
2277system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2278system.iobus.reqLayer24.occupancy 32044500 # Layer occupancy (ticks)
2279system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2280system.iobus.reqLayer25.occupancy 187734328 # Layer occupancy (ticks)
2281system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2282system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
2283system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2284system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
2285system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2286system.iocache.tags.replacements 36445 # number of replacements
2287system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use
2288system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2289system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
2290system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2291system.iocache.tags.warmup_cycle 289174340000 # Cycle when the warmup percentage was hit.
2292system.iocache.tags.occ_blocks::realview.ide 14.386648 # Average occupied blocks per requestor
2293system.iocache.tags.occ_percent::realview.ide 0.899166 # Average percentage of cache occupancy
2294system.iocache.tags.occ_percent::total 0.899166 # Average percentage of cache occupancy
2295system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2296system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2297system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2298system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2299system.iocache.tags.data_accesses 328311 # Number of data accesses
2300system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2301system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2302system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2303system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2304system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
2305system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
2306system.iocache.overall_misses::realview.ide 36479 # number of overall misses
2307system.iocache.overall_misses::total 36479 # number of overall misses
2308system.iocache.ReadReq_miss_latency::realview.ide 36421877 # number of ReadReq miss cycles
2309system.iocache.ReadReq_miss_latency::total 36421877 # number of ReadReq miss cycles
2310system.iocache.WriteLineReq_miss_latency::realview.ide 4307524451 # number of WriteLineReq miss cycles
2311system.iocache.WriteLineReq_miss_latency::total 4307524451 # number of WriteLineReq miss cycles
2312system.iocache.demand_miss_latency::realview.ide 4343946328 # number of demand (read+write) miss cycles
2313system.iocache.demand_miss_latency::total 4343946328 # number of demand (read+write) miss cycles
2314system.iocache.overall_miss_latency::realview.ide 4343946328 # number of overall miss cycles
2315system.iocache.overall_miss_latency::total 4343946328 # number of overall miss cycles
2316system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2317system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2318system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2319system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2320system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
2321system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
2322system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
2323system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
2324system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2325system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2326system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2327system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2328system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2329system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2330system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2331system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2332system.iocache.ReadReq_avg_miss_latency::realview.ide 142830.890196 # average ReadReq miss latency
2333system.iocache.ReadReq_avg_miss_latency::total 142830.890196 # average ReadReq miss latency
2334system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118913.550436 # average WriteLineReq miss latency
2335system.iocache.WriteLineReq_avg_miss_latency::total 118913.550436 # average WriteLineReq miss latency
2336system.iocache.demand_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency
2337system.iocache.demand_avg_miss_latency::total 119080.740371 # average overall miss latency
2338system.iocache.overall_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency
2339system.iocache.overall_avg_miss_latency::total 119080.740371 # average overall miss latency
2340system.iocache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked
2341system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2342system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked
2343system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2344system.iocache.avg_blocked_cycles::no_mshrs 3.142857 # average number of cycles each access was blocked
2345system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2346system.iocache.writebacks::writebacks 36190 # number of writebacks
2347system.iocache.writebacks::total 36190 # number of writebacks
2348system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2349system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2350system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2351system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2352system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
2353system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
2354system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
2355system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
2356system.iocache.ReadReq_mshr_miss_latency::realview.ide 23671877 # number of ReadReq MSHR miss cycles
2357system.iocache.ReadReq_mshr_miss_latency::total 23671877 # number of ReadReq MSHR miss cycles
2358system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493982137 # number of WriteLineReq MSHR miss cycles
2359system.iocache.WriteLineReq_mshr_miss_latency::total 2493982137 # number of WriteLineReq MSHR miss cycles
2360system.iocache.demand_mshr_miss_latency::realview.ide 2517654014 # number of demand (read+write) MSHR miss cycles
2361system.iocache.demand_mshr_miss_latency::total 2517654014 # number of demand (read+write) MSHR miss cycles
2362system.iocache.overall_mshr_miss_latency::realview.ide 2517654014 # number of overall MSHR miss cycles
2363system.iocache.overall_mshr_miss_latency::total 2517654014 # number of overall MSHR miss cycles
2364system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2365system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2366system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2367system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2368system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2369system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2370system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2371system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2372system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 92830.890196 # average ReadReq mshr miss latency
2373system.iocache.ReadReq_avg_mshr_miss_latency::total 92830.890196 # average ReadReq mshr miss latency
2374system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68848.888499 # average WriteLineReq mshr miss latency
2375system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68848.888499 # average WriteLineReq mshr miss latency
2376system.iocache.demand_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency
2377system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency
2378system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency
2379system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency
2380system.l2c.tags.replacements 126308 # number of replacements
2381system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use
2382system.l2c.tags.total_refs 424315 # Total number of references to valid blocks.
2383system.l2c.tags.sampled_refs 190178 # Sample count of references to valid blocks.
2384system.l2c.tags.avg_refs 2.231147 # Average number of references to valid blocks.
2385system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2386system.l2c.tags.occ_blocks::writebacks 13637.426679 # Average occupied blocks per requestor
2387system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.018602 # Average occupied blocks per requestor
2388system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043991 # Average occupied blocks per requestor
2389system.l2c.tags.occ_blocks::cpu0.inst 7319.345128 # Average occupied blocks per requestor
2390system.l2c.tags.occ_blocks::cpu0.data 2841.087210 # Average occupied blocks per requestor
2391system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35552.012227 # Average occupied blocks per requestor
2392system.l2c.tags.occ_blocks::cpu1.inst 1437.607406 # Average occupied blocks per requestor
2393system.l2c.tags.occ_blocks::cpu1.data 447.669169 # Average occupied blocks per requestor
2394system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1777.834065 # Average occupied blocks per requestor
2395system.l2c.tags.occ_percent::writebacks 0.208091 # Average percentage of cache occupancy
2396system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy
2397system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2398system.l2c.tags.occ_percent::cpu0.inst 0.111684 # Average percentage of cache occupancy
2399system.l2c.tags.occ_percent::cpu0.data 0.043352 # Average percentage of cache occupancy
2400system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.542481 # Average percentage of cache occupancy
2401system.l2c.tags.occ_percent::cpu1.inst 0.021936 # Average percentage of cache occupancy
2402system.l2c.tags.occ_percent::cpu1.data 0.006831 # Average percentage of cache occupancy
2403system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027128 # Average percentage of cache occupancy
2404system.l2c.tags.occ_percent::total 0.961564 # Average percentage of cache occupancy
2405system.l2c.tags.occ_task_id_blocks::1022 30519 # Occupied blocks per task id
2406system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
2407system.l2c.tags.occ_task_id_blocks::1024 33346 # Occupied blocks per task id
2408system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
2409system.l2c.tags.age_task_id_blocks_1022::2 165 # Occupied blocks per task id
2410system.l2c.tags.age_task_id_blocks_1022::3 4688 # Occupied blocks per task id
2411system.l2c.tags.age_task_id_blocks_1022::4 25665 # Occupied blocks per task id
2412system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
2413system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
2414system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
2415system.l2c.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id
2416system.l2c.tags.age_task_id_blocks_1024::3 2267 # Occupied blocks per task id
2417system.l2c.tags.age_task_id_blocks_1024::4 30712 # Occupied blocks per task id
2418system.l2c.tags.occ_task_id_percent::1022 0.465683 # Percentage of cache occupancy per task id
2419system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
2420system.l2c.tags.occ_task_id_percent::1024 0.508820 # Percentage of cache occupancy per task id
2421system.l2c.tags.tag_accesses 5890164 # Number of tag accesses
2422system.l2c.tags.data_accesses 5890164 # Number of data accesses
2423system.l2c.WritebackDirty_hits::writebacks 260994 # number of WritebackDirty hits
2424system.l2c.WritebackDirty_hits::total 260994 # number of WritebackDirty hits
2425system.l2c.UpgradeReq_hits::cpu0.data 31980 # number of UpgradeReq hits
2426system.l2c.UpgradeReq_hits::cpu1.data 2487 # number of UpgradeReq hits
2427system.l2c.UpgradeReq_hits::total 34467 # number of UpgradeReq hits
2428system.l2c.SCUpgradeReq_hits::cpu0.data 1985 # number of SCUpgradeReq hits
2429system.l2c.SCUpgradeReq_hits::cpu1.data 965 # number of SCUpgradeReq hits
2430system.l2c.SCUpgradeReq_hits::total 2950 # number of SCUpgradeReq hits
2431system.l2c.ReadExReq_hits::cpu0.data 3870 # number of ReadExReq hits
2432system.l2c.ReadExReq_hits::cpu1.data 1490 # number of ReadExReq hits
2433system.l2c.ReadExReq_hits::total 5360 # number of ReadExReq hits
2434system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 97 # number of ReadSharedReq hits
2435system.l2c.ReadSharedReq_hits::cpu0.itb.walker 76 # number of ReadSharedReq hits
2436system.l2c.ReadSharedReq_hits::cpu0.inst 27673 # number of ReadSharedReq hits
2437system.l2c.ReadSharedReq_hits::cpu0.data 45621 # number of ReadSharedReq hits
2438system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45892 # number of ReadSharedReq hits
2439system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 31 # number of ReadSharedReq hits
2440system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits
2441system.l2c.ReadSharedReq_hits::cpu1.inst 10962 # number of ReadSharedReq hits
2442system.l2c.ReadSharedReq_hits::cpu1.data 9208 # number of ReadSharedReq hits
2443system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5411 # number of ReadSharedReq hits
2444system.l2c.ReadSharedReq_hits::total 145008 # number of ReadSharedReq hits
2445system.l2c.demand_hits::cpu0.dtb.walker 97 # number of demand (read+write) hits
2446system.l2c.demand_hits::cpu0.itb.walker 76 # number of demand (read+write) hits
2447system.l2c.demand_hits::cpu0.inst 27673 # number of demand (read+write) hits
2448system.l2c.demand_hits::cpu0.data 49491 # number of demand (read+write) hits
2449system.l2c.demand_hits::cpu0.l2cache.prefetcher 45892 # number of demand (read+write) hits
2450system.l2c.demand_hits::cpu1.dtb.walker 31 # number of demand (read+write) hits
2451system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits
2452system.l2c.demand_hits::cpu1.inst 10962 # number of demand (read+write) hits
2453system.l2c.demand_hits::cpu1.data 10698 # number of demand (read+write) hits
2454system.l2c.demand_hits::cpu1.l2cache.prefetcher 5411 # number of demand (read+write) hits
2455system.l2c.demand_hits::total 150368 # number of demand (read+write) hits
2456system.l2c.overall_hits::cpu0.dtb.walker 97 # number of overall hits
2457system.l2c.overall_hits::cpu0.itb.walker 76 # number of overall hits
2458system.l2c.overall_hits::cpu0.inst 27673 # number of overall hits
2459system.l2c.overall_hits::cpu0.data 49491 # number of overall hits
2460system.l2c.overall_hits::cpu0.l2cache.prefetcher 45892 # number of overall hits
2461system.l2c.overall_hits::cpu1.dtb.walker 31 # number of overall hits
2462system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits
2463system.l2c.overall_hits::cpu1.inst 10962 # number of overall hits
2464system.l2c.overall_hits::cpu1.data 10698 # number of overall hits
2465system.l2c.overall_hits::cpu1.l2cache.prefetcher 5411 # number of overall hits
2466system.l2c.overall_hits::total 150368 # number of overall hits
2467system.l2c.UpgradeReq_misses::cpu0.data 8680 # number of UpgradeReq misses
2468system.l2c.UpgradeReq_misses::cpu1.data 2870 # number of UpgradeReq misses
2469system.l2c.UpgradeReq_misses::total 11550 # number of UpgradeReq misses
2470system.l2c.SCUpgradeReq_misses::cpu0.data 542 # number of SCUpgradeReq misses
2471system.l2c.SCUpgradeReq_misses::cpu1.data 1323 # number of SCUpgradeReq misses
2472system.l2c.SCUpgradeReq_misses::total 1865 # number of SCUpgradeReq misses
2473system.l2c.ReadExReq_misses::cpu0.data 11368 # number of ReadExReq misses
2474system.l2c.ReadExReq_misses::cpu1.data 8031 # number of ReadExReq misses
2475system.l2c.ReadExReq_misses::total 19399 # number of ReadExReq misses
2476system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses
2477system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
2478system.l2c.ReadSharedReq_misses::cpu0.inst 17607 # number of ReadSharedReq misses
2479system.l2c.ReadSharedReq_misses::cpu0.data 8862 # number of ReadSharedReq misses
2480system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq misses
2481system.l2c.ReadSharedReq_misses::cpu1.inst 2288 # number of ReadSharedReq misses
2482system.l2c.ReadSharedReq_misses::cpu1.data 856 # number of ReadSharedReq misses
2483system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq misses
2484system.l2c.ReadSharedReq_misses::total 169532 # number of ReadSharedReq misses
2485system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
2486system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
2487system.l2c.demand_misses::cpu0.inst 17607 # number of demand (read+write) misses
2488system.l2c.demand_misses::cpu0.data 20230 # number of demand (read+write) misses
2489system.l2c.demand_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) misses
2490system.l2c.demand_misses::cpu1.inst 2288 # number of demand (read+write) misses
2491system.l2c.demand_misses::cpu1.data 8887 # number of demand (read+write) misses
2492system.l2c.demand_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) misses
2493system.l2c.demand_misses::total 188931 # number of demand (read+write) misses
2494system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
2495system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
2496system.l2c.overall_misses::cpu0.inst 17607 # number of overall misses
2497system.l2c.overall_misses::cpu0.data 20230 # number of overall misses
2498system.l2c.overall_misses::cpu0.l2cache.prefetcher 133884 # number of overall misses
2499system.l2c.overall_misses::cpu1.inst 2288 # number of overall misses
2500system.l2c.overall_misses::cpu1.data 8887 # number of overall misses
2501system.l2c.overall_misses::cpu1.l2cache.prefetcher 6026 # number of overall misses
2502system.l2c.overall_misses::total 188931 # number of overall misses
2503system.l2c.UpgradeReq_miss_latency::cpu0.data 11274000 # number of UpgradeReq miss cycles
2504system.l2c.UpgradeReq_miss_latency::cpu1.data 4127500 # number of UpgradeReq miss cycles
2505system.l2c.UpgradeReq_miss_latency::total 15401500 # number of UpgradeReq miss cycles
2506system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1640500 # number of SCUpgradeReq miss cycles
2507system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1015500 # number of SCUpgradeReq miss cycles
2508system.l2c.SCUpgradeReq_miss_latency::total 2656000 # number of SCUpgradeReq miss cycles
2509system.l2c.ReadExReq_miss_latency::cpu0.data 1087660500 # number of ReadExReq miss cycles
2510system.l2c.ReadExReq_miss_latency::cpu1.data 661855000 # number of ReadExReq miss cycles
2511system.l2c.ReadExReq_miss_latency::total 1749515500 # number of ReadExReq miss cycles
2512system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles
2513system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles
2514system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles
| 1214system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency
1215system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency
1216system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency
1217system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency
1218system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency
1219system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency
1220system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter.
1221system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1222system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27957 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1223system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter.
1224system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1225system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1226system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution
1227system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution
1228system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution
1229system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution
1230system.cpu0.toL2Bus.trans_dist::WritebackDirty 705040 # Transaction distribution
1231system.cpu0.toL2Bus.trans_dist::WritebackClean 1319203 # Transaction distribution
1232system.cpu0.toL2Bus.trans_dist::CleanEvict 185302 # Transaction distribution
1233system.cpu0.toL2Bus.trans_dist::HardPFReq 307927 # Transaction distribution
1234system.cpu0.toL2Bus.trans_dist::UpgradeReq 87515 # Transaction distribution
1235system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42104 # Transaction distribution
1236system.cpu0.toL2Bus.trans_dist::UpgradeResp 112492 # Transaction distribution
1237system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
1238system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution
1239system.cpu0.toL2Bus.trans_dist::ReadExReq 289204 # Transaction distribution
1240system.cpu0.toL2Bus.trans_dist::ReadExResp 285566 # Transaction distribution
1241system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104402 # Transaction distribution
1242system.cpu0.toL2Bus.trans_dist::ReadSharedReq 556293 # Transaction distribution
1243system.cpu0.toL2Bus.trans_dist::InvalidateReq 3323 # Transaction distribution
1244system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330729 # Packet count per connected master and slave (bytes)
1245system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2559536 # Packet count per connected master and slave (bytes)
1246system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11112 # Packet count per connected master and slave (bytes)
1247system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24847 # Packet count per connected master and slave (bytes)
1248system.cpu0.toL2Bus.pkt_count::total 5926224 # Packet count per connected master and slave (bytes)
1249system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141366200 # Cumulative packet size per connected master and slave (bytes)
1250system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96437860 # Cumulative packet size per connected master and slave (bytes)
1251system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18852 # Cumulative packet size per connected master and slave (bytes)
1252system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41848 # Cumulative packet size per connected master and slave (bytes)
1253system.cpu0.toL2Bus.pkt_size::total 237864760 # Cumulative packet size per connected master and slave (bytes)
1254system.cpu0.toL2Bus.snoops 984362 # Total snoops (count)
1255system.cpu0.toL2Bus.snoop_fanout::samples 2894410 # Request fanout histogram
1256system.cpu0.toL2Bus.snoop_fanout::mean 0.124539 # Request fanout histogram
1257system.cpu0.toL2Bus.snoop_fanout::stdev 0.334666 # Request fanout histogram
1258system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1259system.cpu0.toL2Bus.snoop_fanout::0 2538244 87.69% 87.69% # Request fanout histogram
1260system.cpu0.toL2Bus.snoop_fanout::1 351865 12.16% 99.85% # Request fanout histogram
1261system.cpu0.toL2Bus.snoop_fanout::2 4301 0.15% 100.00% # Request fanout histogram
1262system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1263system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1264system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1265system.cpu0.toL2Bus.snoop_fanout::total 2894410 # Request fanout histogram
1266system.cpu0.toL2Bus.reqLayer0.occupancy 3716866999 # Layer occupancy (ticks)
1267system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1268system.cpu0.toL2Bus.snoopLayer0.occupancy 114649584 # Layer occupancy (ticks)
1269system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1270system.cpu0.toL2Bus.respLayer0.occupancy 1665625000 # Layer occupancy (ticks)
1271system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1272system.cpu0.toL2Bus.respLayer1.occupancy 1205216982 # Layer occupancy (ticks)
1273system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1274system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
1275system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1276system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks)
1277system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1278system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1279system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1280system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1281system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1282system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1283system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1284system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1285system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1286system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1287system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1288system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1289system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1290system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1291system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1292system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1293system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1294system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1295system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1296system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1297system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1298system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1299system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1300system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1301system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1302system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1303system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1304system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1305system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1306system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1307system.cpu1.dtb.walker.walks 3352 # Table walker walks requested
1308system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors
1309system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate
1310system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate
1311system.cpu1.dtb.walker.walkWaitTime::samples 3352 # Table walker wait (enqueue to first request) latency
1312system.cpu1.dtb.walker.walkWaitTime::0 3352 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1313system.cpu1.dtb.walker.walkWaitTime::total 3352 # Table walker wait (enqueue to first request) latency
1314system.cpu1.dtb.walker.walkCompletionTime::samples 2582 # Table walker service (enqueue to completion) latency
1315system.cpu1.dtb.walker.walkCompletionTime::mean 11816.227730 # Table walker service (enqueue to completion) latency
1316system.cpu1.dtb.walker.walkCompletionTime::gmean 11080.373538 # Table walker service (enqueue to completion) latency
1317system.cpu1.dtb.walker.walkCompletionTime::stdev 4768.875507 # Table walker service (enqueue to completion) latency
1318system.cpu1.dtb.walker.walkCompletionTime::0-4095 5 0.19% 0.19% # Table walker service (enqueue to completion) latency
1319system.cpu1.dtb.walker.walkCompletionTime::4096-8191 626 24.24% 24.44% # Table walker service (enqueue to completion) latency
1320system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1198 46.40% 70.84% # Table walker service (enqueue to completion) latency
1321system.cpu1.dtb.walker.walkCompletionTime::12288-16383 544 21.07% 91.91% # Table walker service (enqueue to completion) latency
1322system.cpu1.dtb.walker.walkCompletionTime::16384-20479 85 3.29% 95.20% # Table walker service (enqueue to completion) latency
1323system.cpu1.dtb.walker.walkCompletionTime::20480-24575 56 2.17% 97.37% # Table walker service (enqueue to completion) latency
1324system.cpu1.dtb.walker.walkCompletionTime::24576-28671 31 1.20% 98.57% # Table walker service (enqueue to completion) latency
1325system.cpu1.dtb.walker.walkCompletionTime::28672-32767 20 0.77% 99.34% # Table walker service (enqueue to completion) latency
1326system.cpu1.dtb.walker.walkCompletionTime::32768-36863 3 0.12% 99.46% # Table walker service (enqueue to completion) latency
1327system.cpu1.dtb.walker.walkCompletionTime::36864-40959 8 0.31% 99.77% # Table walker service (enqueue to completion) latency
1328system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency
1329system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.12% 100.00% # Table walker service (enqueue to completion) latency
1330system.cpu1.dtb.walker.walkCompletionTime::total 2582 # Table walker service (enqueue to completion) latency
1331system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution
1332system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution
1333system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution
1334system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.90% 74.90% # Table walker page sizes translated
1335system.cpu1.dtb.walker.walkPageSizes::1M 648 25.10% 100.00% # Table walker page sizes translated
1336system.cpu1.dtb.walker.walkPageSizes::total 2582 # Table walker page sizes translated
1337system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3352 # Table walker requests started/completed, data/inst
1338system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1339system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3352 # Table walker requests started/completed, data/inst
1340system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2582 # Table walker requests started/completed, data/inst
1341system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1342system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst
1343system.cpu1.dtb.walker.walkRequestOrigin::total 5934 # Table walker requests started/completed, data/inst
1344system.cpu1.dtb.inst_hits 0 # ITB inst hits
1345system.cpu1.dtb.inst_misses 0 # ITB inst misses
1346system.cpu1.dtb.read_hits 3941258 # DTB read hits
1347system.cpu1.dtb.read_misses 2845 # DTB read misses
1348system.cpu1.dtb.write_hits 3419362 # DTB write hits
1349system.cpu1.dtb.write_misses 507 # DTB write misses
1350system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1351system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1352system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1353system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1354system.cpu1.dtb.flush_entries 2044 # Number of entries that have been flushed from TLB
1355system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1356system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch
1357system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1358system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
1359system.cpu1.dtb.read_accesses 3944103 # DTB read accesses
1360system.cpu1.dtb.write_accesses 3419869 # DTB write accesses
1361system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1362system.cpu1.dtb.hits 7360620 # DTB hits
1363system.cpu1.dtb.misses 3352 # DTB misses
1364system.cpu1.dtb.accesses 7363972 # DTB accesses
1365system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1366system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1367system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1368system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1369system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1370system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1371system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1372system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
1373system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1374system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1375system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1376system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1377system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1378system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1379system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1380system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1381system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1382system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1383system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
1384system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
1385system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
1386system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1387system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1388system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1389system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1390system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1391system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1392system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1393system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1394system.cpu1.itb.walker.walks 1746 # Table walker walks requested
1395system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors
1396system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate
1397system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate
1398system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency
1399system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1400system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency
1401system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency
1402system.cpu1.itb.walker.walkCompletionTime::mean 12335.140018 # Table walker service (enqueue to completion) latency
1403system.cpu1.itb.walker.walkCompletionTime::gmean 11518.936586 # Table walker service (enqueue to completion) latency
1404system.cpu1.itb.walker.walkCompletionTime::stdev 5605.729039 # Table walker service (enqueue to completion) latency
1405system.cpu1.itb.walker.walkCompletionTime::4096-8191 174 15.72% 15.72% # Table walker service (enqueue to completion) latency
1406system.cpu1.itb.walker.walkCompletionTime::8192-12287 657 59.35% 75.07% # Table walker service (enqueue to completion) latency
1407system.cpu1.itb.walker.walkCompletionTime::12288-16383 169 15.27% 90.33% # Table walker service (enqueue to completion) latency
1408system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 95.03% # Table walker service (enqueue to completion) latency
1409system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.12% # Table walker service (enqueue to completion) latency
1410system.cpu1.itb.walker.walkCompletionTime::24576-28671 20 1.81% 96.93% # Table walker service (enqueue to completion) latency
1411system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.37% # Table walker service (enqueue to completion) latency
1412system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 98.64% # Table walker service (enqueue to completion) latency
1413system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.90% 99.55% # Table walker service (enqueue to completion) latency
1414system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.73% # Table walker service (enqueue to completion) latency
1415system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 99.91% # Table walker service (enqueue to completion) latency
1416system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
1417system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency
1418system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution
1419system.cpu1.itb.walker.walksPending::0 -2078939828 100.00% 100.00% # Table walker pending requests distribution
1420system.cpu1.itb.walker.walksPending::total -2078939828 # Table walker pending requests distribution
1421system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated
1422system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated
1423system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated
1424system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1425system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst
1426system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst
1427system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1428system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst
1429system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst
1430system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst
1431system.cpu1.itb.inst_hits 16556610 # ITB inst hits
1432system.cpu1.itb.inst_misses 1746 # ITB inst misses
1433system.cpu1.itb.read_hits 0 # DTB read hits
1434system.cpu1.itb.read_misses 0 # DTB read misses
1435system.cpu1.itb.write_hits 0 # DTB write hits
1436system.cpu1.itb.write_misses 0 # DTB write misses
1437system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1438system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1439system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1440system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1441system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB
1442system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1443system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1444system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1445system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1446system.cpu1.itb.read_accesses 0 # DTB read accesses
1447system.cpu1.itb.write_accesses 0 # DTB write accesses
1448system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses
1449system.cpu1.itb.hits 16556610 # DTB hits
1450system.cpu1.itb.misses 1746 # DTB misses
1451system.cpu1.itb.accesses 16558356 # DTB accesses
1452system.cpu1.numCycles 5738649789 # number of cpu cycles simulated
1453system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1454system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1455system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1456system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed
1457system.cpu1.committedInsts 16201169 # Number of instructions committed
1458system.cpu1.committedOps 19741428 # Number of ops (including micro ops) committed
1459system.cpu1.num_int_alu_accesses 17804295 # Number of integer alu accesses
1460system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses
1461system.cpu1.num_func_calls 1029080 # number of times a function call or return occured
1462system.cpu1.num_conditional_control_insts 1813608 # number of instructions that are conditional controls
1463system.cpu1.num_int_insts 17804295 # number of integer instructions
1464system.cpu1.num_fp_insts 1857 # number of float instructions
1465system.cpu1.num_int_register_reads 32314180 # number of times the integer registers were read
1466system.cpu1.num_int_register_writes 12487661 # number of times the integer registers were written
1467system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read
1468system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
1469system.cpu1.num_cc_register_reads 72166445 # number of times the CC registers were read
1470system.cpu1.num_cc_register_writes 6418557 # number of times the CC registers were written
1471system.cpu1.num_mem_refs 7593995 # number of memory refs
1472system.cpu1.num_load_insts 4052758 # Number of load instructions
1473system.cpu1.num_store_insts 3541237 # Number of store instructions
1474system.cpu1.num_idle_cycles 5686904242.264484 # Number of idle cycles
1475system.cpu1.num_busy_cycles 51745546.735515 # Number of busy cycles
1476system.cpu1.not_idle_fraction 0.009017 # Percentage of non-idle cycles
1477system.cpu1.idle_fraction 0.990983 # Percentage of idle cycles
1478system.cpu1.Branches 2921126 # Number of branches fetched
1479system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
1480system.cpu1.op_class::IntAlu 12468405 62.06% 62.06% # Class of executed instruction
1481system.cpu1.op_class::IntMult 26465 0.13% 62.19% # Class of executed instruction
1482system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction
1483system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction
1484system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction
1485system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction
1486system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction
1487system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction
1488system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction
1489system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction
1490system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction
1491system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction
1492system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction
1493system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction
1494system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction
1495system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction
1496system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction
1497system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction
1498system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction
1499system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction
1500system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction
1501system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction
1502system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction
1503system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction
1504system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction
1505system.cpu1.op_class::SimdFloatMisc 3319 0.02% 62.20% # Class of executed instruction
1506system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction
1507system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction
1508system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction
1509system.cpu1.op_class::MemRead 4052758 20.17% 82.38% # Class of executed instruction
1510system.cpu1.op_class::MemWrite 3541237 17.62% 100.00% # Class of executed instruction
1511system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1512system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1513system.cpu1.op_class::total 20092250 # Class of executed instruction
1514system.cpu1.dcache.tags.replacements 186389 # number of replacements
1515system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use
1516system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks.
1517system.cpu1.dcache.tags.sampled_refs 186755 # Sample count of references to valid blocks.
1518system.cpu1.dcache.tags.avg_refs 37.984359 # Average number of references to valid blocks.
1519system.cpu1.dcache.tags.warmup_cycle 127433218000 # Cycle when the warmup percentage was hit.
1520system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.298921 # Average occupied blocks per requestor
1521system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916599 # Average percentage of cache occupancy
1522system.cpu1.dcache.tags.occ_percent::total 0.916599 # Average percentage of cache occupancy
1523system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id
1524system.cpu1.dcache.tags.age_task_id_blocks_1024::2 285 # Occupied blocks per task id
1525system.cpu1.dcache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id
1526system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id
1527system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses
1528system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses
1529system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits
1530system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits
1531system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits
1532system.cpu1.dcache.WriteReq_hits::total 3230955 # number of WriteReq hits
1533system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48929 # number of SoftPFReq hits
1534system.cpu1.dcache.SoftPFReq_hits::total 48929 # number of SoftPFReq hits
1535system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78822 # number of LoadLockedReq hits
1536system.cpu1.dcache.LoadLockedReq_hits::total 78822 # number of LoadLockedReq hits
1537system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70747 # number of StoreCondReq hits
1538system.cpu1.dcache.StoreCondReq_hits::total 70747 # number of StoreCondReq hits
1539system.cpu1.dcache.demand_hits::cpu1.data 6860355 # number of demand (read+write) hits
1540system.cpu1.dcache.demand_hits::total 6860355 # number of demand (read+write) hits
1541system.cpu1.dcache.overall_hits::cpu1.data 6909284 # number of overall hits
1542system.cpu1.dcache.overall_hits::total 6909284 # number of overall hits
1543system.cpu1.dcache.ReadReq_misses::cpu1.data 133654 # number of ReadReq misses
1544system.cpu1.dcache.ReadReq_misses::total 133654 # number of ReadReq misses
1545system.cpu1.dcache.WriteReq_misses::cpu1.data 91683 # number of WriteReq misses
1546system.cpu1.dcache.WriteReq_misses::total 91683 # number of WriteReq misses
1547system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30306 # number of SoftPFReq misses
1548system.cpu1.dcache.SoftPFReq_misses::total 30306 # number of SoftPFReq misses
1549system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17079 # number of LoadLockedReq misses
1550system.cpu1.dcache.LoadLockedReq_misses::total 17079 # number of LoadLockedReq misses
1551system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23334 # number of StoreCondReq misses
1552system.cpu1.dcache.StoreCondReq_misses::total 23334 # number of StoreCondReq misses
1553system.cpu1.dcache.demand_misses::cpu1.data 225337 # number of demand (read+write) misses
1554system.cpu1.dcache.demand_misses::total 225337 # number of demand (read+write) misses
1555system.cpu1.dcache.overall_misses::cpu1.data 255643 # number of overall misses
1556system.cpu1.dcache.overall_misses::total 255643 # number of overall misses
1557system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1974580500 # number of ReadReq miss cycles
1558system.cpu1.dcache.ReadReq_miss_latency::total 1974580500 # number of ReadReq miss cycles
1559system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2414638500 # number of WriteReq miss cycles
1560system.cpu1.dcache.WriteReq_miss_latency::total 2414638500 # number of WriteReq miss cycles
1561system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320455500 # number of LoadLockedReq miss cycles
1562system.cpu1.dcache.LoadLockedReq_miss_latency::total 320455500 # number of LoadLockedReq miss cycles
1563system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 569715000 # number of StoreCondReq miss cycles
1564system.cpu1.dcache.StoreCondReq_miss_latency::total 569715000 # number of StoreCondReq miss cycles
1565system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3416500 # number of StoreCondFailReq miss cycles
1566system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3416500 # number of StoreCondFailReq miss cycles
1567system.cpu1.dcache.demand_miss_latency::cpu1.data 4389219000 # number of demand (read+write) miss cycles
1568system.cpu1.dcache.demand_miss_latency::total 4389219000 # number of demand (read+write) miss cycles
1569system.cpu1.dcache.overall_miss_latency::cpu1.data 4389219000 # number of overall miss cycles
1570system.cpu1.dcache.overall_miss_latency::total 4389219000 # number of overall miss cycles
1571system.cpu1.dcache.ReadReq_accesses::cpu1.data 3763054 # number of ReadReq accesses(hits+misses)
1572system.cpu1.dcache.ReadReq_accesses::total 3763054 # number of ReadReq accesses(hits+misses)
1573system.cpu1.dcache.WriteReq_accesses::cpu1.data 3322638 # number of WriteReq accesses(hits+misses)
1574system.cpu1.dcache.WriteReq_accesses::total 3322638 # number of WriteReq accesses(hits+misses)
1575system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79235 # number of SoftPFReq accesses(hits+misses)
1576system.cpu1.dcache.SoftPFReq_accesses::total 79235 # number of SoftPFReq accesses(hits+misses)
1577system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95901 # number of LoadLockedReq accesses(hits+misses)
1578system.cpu1.dcache.LoadLockedReq_accesses::total 95901 # number of LoadLockedReq accesses(hits+misses)
1579system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94081 # number of StoreCondReq accesses(hits+misses)
1580system.cpu1.dcache.StoreCondReq_accesses::total 94081 # number of StoreCondReq accesses(hits+misses)
1581system.cpu1.dcache.demand_accesses::cpu1.data 7085692 # number of demand (read+write) accesses
1582system.cpu1.dcache.demand_accesses::total 7085692 # number of demand (read+write) accesses
1583system.cpu1.dcache.overall_accesses::cpu1.data 7164927 # number of overall (read+write) accesses
1584system.cpu1.dcache.overall_accesses::total 7164927 # number of overall (read+write) accesses
1585system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses
1586system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses
1587system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027593 # miss rate for WriteReq accesses
1588system.cpu1.dcache.WriteReq_miss_rate::total 0.027593 # miss rate for WriteReq accesses
1589system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382482 # miss rate for SoftPFReq accesses
1590system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382482 # miss rate for SoftPFReq accesses
1591system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178090 # miss rate for LoadLockedReq accesses
1592system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178090 # miss rate for LoadLockedReq accesses
1593system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248020 # miss rate for StoreCondReq accesses
1594system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248020 # miss rate for StoreCondReq accesses
1595system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031802 # miss rate for demand accesses
1596system.cpu1.dcache.demand_miss_rate::total 0.031802 # miss rate for demand accesses
1597system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035680 # miss rate for overall accesses
1598system.cpu1.dcache.overall_miss_rate::total 0.035680 # miss rate for overall accesses
1599system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.822706 # average ReadReq miss latency
1600system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.822706 # average ReadReq miss latency
1601system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26336.818167 # average WriteReq miss latency
1602system.cpu1.dcache.WriteReq_avg_miss_latency::total 26336.818167 # average WriteReq miss latency
1603system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18763.130160 # average LoadLockedReq miss latency
1604system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18763.130160 # average LoadLockedReq miss latency
1605system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24415.659553 # average StoreCondReq miss latency
1606system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24415.659553 # average StoreCondReq miss latency
1607system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1608system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1609system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19478.465587 # average overall miss latency
1610system.cpu1.dcache.demand_avg_miss_latency::total 19478.465587 # average overall miss latency
1611system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17169.329886 # average overall miss latency
1612system.cpu1.dcache.overall_avg_miss_latency::total 17169.329886 # average overall miss latency
1613system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1614system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1615system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1616system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1617system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1618system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1619system.cpu1.dcache.writebacks::writebacks 186389 # number of writebacks
1620system.cpu1.dcache.writebacks::total 186389 # number of writebacks
1621system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits
1622system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits
1623system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12013 # number of LoadLockedReq MSHR hits
1624system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12013 # number of LoadLockedReq MSHR hits
1625system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits
1626system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits
1627system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits
1628system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits
1629system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133371 # number of ReadReq MSHR misses
1630system.cpu1.dcache.ReadReq_mshr_misses::total 133371 # number of ReadReq MSHR misses
1631system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91683 # number of WriteReq MSHR misses
1632system.cpu1.dcache.WriteReq_mshr_misses::total 91683 # number of WriteReq MSHR misses
1633system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29541 # number of SoftPFReq MSHR misses
1634system.cpu1.dcache.SoftPFReq_mshr_misses::total 29541 # number of SoftPFReq MSHR misses
1635system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5066 # number of LoadLockedReq MSHR misses
1636system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5066 # number of LoadLockedReq MSHR misses
1637system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23334 # number of StoreCondReq MSHR misses
1638system.cpu1.dcache.StoreCondReq_mshr_misses::total 23334 # number of StoreCondReq MSHR misses
1639system.cpu1.dcache.demand_mshr_misses::cpu1.data 225054 # number of demand (read+write) MSHR misses
1640system.cpu1.dcache.demand_mshr_misses::total 225054 # number of demand (read+write) MSHR misses
1641system.cpu1.dcache.overall_mshr_misses::cpu1.data 254595 # number of overall MSHR misses
1642system.cpu1.dcache.overall_mshr_misses::total 254595 # number of overall MSHR misses
1643system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable
1644system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3095 # number of ReadReq MSHR uncacheable
1645system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
1646system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable
1647system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses
1648system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5545 # number of overall MSHR uncacheable misses
1649system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1833975000 # number of ReadReq MSHR miss cycles
1650system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1833975000 # number of ReadReq MSHR miss cycles
1651system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2322955500 # number of WriteReq MSHR miss cycles
1652system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2322955500 # number of WriteReq MSHR miss cycles
1653system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 497374500 # number of SoftPFReq MSHR miss cycles
1654system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 497374500 # number of SoftPFReq MSHR miss cycles
1655system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87920500 # number of LoadLockedReq MSHR miss cycles
1656system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87920500 # number of LoadLockedReq MSHR miss cycles
1657system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 546440000 # number of StoreCondReq MSHR miss cycles
1658system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 546440000 # number of StoreCondReq MSHR miss cycles
1659system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3357500 # number of StoreCondFailReq MSHR miss cycles
1660system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3357500 # number of StoreCondFailReq MSHR miss cycles
1661system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4156930500 # number of demand (read+write) MSHR miss cycles
1662system.cpu1.dcache.demand_mshr_miss_latency::total 4156930500 # number of demand (read+write) MSHR miss cycles
1663system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4654305000 # number of overall MSHR miss cycles
1664system.cpu1.dcache.overall_mshr_miss_latency::total 4654305000 # number of overall MSHR miss cycles
1665system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443417000 # number of ReadReq MSHR uncacheable cycles
1666system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443417000 # number of ReadReq MSHR uncacheable cycles
1667system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443417000 # number of overall MSHR uncacheable cycles
1668system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443417000 # number of overall MSHR uncacheable cycles
1669system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses
1670system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses
1671system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027593 # mshr miss rate for WriteReq accesses
1672system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027593 # mshr miss rate for WriteReq accesses
1673system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372828 # mshr miss rate for SoftPFReq accesses
1674system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372828 # mshr miss rate for SoftPFReq accesses
1675system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052825 # mshr miss rate for LoadLockedReq accesses
1676system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052825 # mshr miss rate for LoadLockedReq accesses
1677system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248020 # mshr miss rate for StoreCondReq accesses
1678system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248020 # mshr miss rate for StoreCondReq accesses
1679system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for demand accesses
1680system.cpu1.dcache.demand_mshr_miss_rate::total 0.031762 # mshr miss rate for demand accesses
1681system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035534 # mshr miss rate for overall accesses
1682system.cpu1.dcache.overall_mshr_miss_rate::total 0.035534 # mshr miss rate for overall accesses
1683system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13750.927863 # average ReadReq mshr miss latency
1684system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13750.927863 # average ReadReq mshr miss latency
1685system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25336.818167 # average WriteReq mshr miss latency
1686system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25336.818167 # average WriteReq mshr miss latency
1687system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16836.752310 # average SoftPFReq mshr miss latency
1688system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16836.752310 # average SoftPFReq mshr miss latency
1689system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17355.013818 # average LoadLockedReq mshr miss latency
1690system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17355.013818 # average LoadLockedReq mshr miss latency
1691system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23418.188052 # average StoreCondReq mshr miss latency
1692system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23418.188052 # average StoreCondReq mshr miss latency
1693system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1694system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1695system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18470.813671 # average overall mshr miss latency
1696system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18470.813671 # average overall mshr miss latency
1697system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18281.211336 # average overall mshr miss latency
1698system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18281.211336 # average overall mshr miss latency
1699system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143268.820679 # average ReadReq mshr uncacheable latency
1700system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency
1701system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency
1702system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency
1703system.cpu1.icache.tags.replacements 505464 # number of replacements
1704system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use
1705system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks.
1706system.cpu1.icache.tags.sampled_refs 505976 # Sample count of references to valid blocks.
1707system.cpu1.icache.tags.avg_refs 31.722115 # Average number of references to valid blocks.
1708system.cpu1.icache.tags.warmup_cycle 85269924000 # Cycle when the warmup percentage was hit.
1709system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478732 # Average occupied blocks per requestor
1710system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy
1711system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy
1712system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1713system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
1714system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id
1715system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
1716system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1717system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses
1718system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses
1719system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits
1720system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits
1721system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits
1722system.cpu1.icache.demand_hits::total 16050629 # number of demand (read+write) hits
1723system.cpu1.icache.overall_hits::cpu1.inst 16050629 # number of overall hits
1724system.cpu1.icache.overall_hits::total 16050629 # number of overall hits
1725system.cpu1.icache.ReadReq_misses::cpu1.inst 505976 # number of ReadReq misses
1726system.cpu1.icache.ReadReq_misses::total 505976 # number of ReadReq misses
1727system.cpu1.icache.demand_misses::cpu1.inst 505976 # number of demand (read+write) misses
1728system.cpu1.icache.demand_misses::total 505976 # number of demand (read+write) misses
1729system.cpu1.icache.overall_misses::cpu1.inst 505976 # number of overall misses
1730system.cpu1.icache.overall_misses::total 505976 # number of overall misses
1731system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4528088500 # number of ReadReq miss cycles
1732system.cpu1.icache.ReadReq_miss_latency::total 4528088500 # number of ReadReq miss cycles
1733system.cpu1.icache.demand_miss_latency::cpu1.inst 4528088500 # number of demand (read+write) miss cycles
1734system.cpu1.icache.demand_miss_latency::total 4528088500 # number of demand (read+write) miss cycles
1735system.cpu1.icache.overall_miss_latency::cpu1.inst 4528088500 # number of overall miss cycles
1736system.cpu1.icache.overall_miss_latency::total 4528088500 # number of overall miss cycles
1737system.cpu1.icache.ReadReq_accesses::cpu1.inst 16556605 # number of ReadReq accesses(hits+misses)
1738system.cpu1.icache.ReadReq_accesses::total 16556605 # number of ReadReq accesses(hits+misses)
1739system.cpu1.icache.demand_accesses::cpu1.inst 16556605 # number of demand (read+write) accesses
1740system.cpu1.icache.demand_accesses::total 16556605 # number of demand (read+write) accesses
1741system.cpu1.icache.overall_accesses::cpu1.inst 16556605 # number of overall (read+write) accesses
1742system.cpu1.icache.overall_accesses::total 16556605 # number of overall (read+write) accesses
1743system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030560 # miss rate for ReadReq accesses
1744system.cpu1.icache.ReadReq_miss_rate::total 0.030560 # miss rate for ReadReq accesses
1745system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030560 # miss rate for demand accesses
1746system.cpu1.icache.demand_miss_rate::total 0.030560 # miss rate for demand accesses
1747system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030560 # miss rate for overall accesses
1748system.cpu1.icache.overall_miss_rate::total 0.030560 # miss rate for overall accesses
1749system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8949.215971 # average ReadReq miss latency
1750system.cpu1.icache.ReadReq_avg_miss_latency::total 8949.215971 # average ReadReq miss latency
1751system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency
1752system.cpu1.icache.demand_avg_miss_latency::total 8949.215971 # average overall miss latency
1753system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency
1754system.cpu1.icache.overall_avg_miss_latency::total 8949.215971 # average overall miss latency
1755system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1756system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1757system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1758system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1759system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1760system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1761system.cpu1.icache.writebacks::writebacks 505464 # number of writebacks
1762system.cpu1.icache.writebacks::total 505464 # number of writebacks
1763system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 505976 # number of ReadReq MSHR misses
1764system.cpu1.icache.ReadReq_mshr_misses::total 505976 # number of ReadReq MSHR misses
1765system.cpu1.icache.demand_mshr_misses::cpu1.inst 505976 # number of demand (read+write) MSHR misses
1766system.cpu1.icache.demand_mshr_misses::total 505976 # number of demand (read+write) MSHR misses
1767system.cpu1.icache.overall_mshr_misses::cpu1.inst 505976 # number of overall MSHR misses
1768system.cpu1.icache.overall_mshr_misses::total 505976 # number of overall MSHR misses
1769system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
1770system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
1771system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
1772system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
1773system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4275100500 # number of ReadReq MSHR miss cycles
1774system.cpu1.icache.ReadReq_mshr_miss_latency::total 4275100500 # number of ReadReq MSHR miss cycles
1775system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4275100500 # number of demand (read+write) MSHR miss cycles
1776system.cpu1.icache.demand_mshr_miss_latency::total 4275100500 # number of demand (read+write) MSHR miss cycles
1777system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4275100500 # number of overall MSHR miss cycles
1778system.cpu1.icache.overall_mshr_miss_latency::total 4275100500 # number of overall MSHR miss cycles
1779system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # number of ReadReq MSHR uncacheable cycles
1780system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15776500 # number of ReadReq MSHR uncacheable cycles
1781system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15776500 # number of overall MSHR uncacheable cycles
1782system.cpu1.icache.overall_mshr_uncacheable_latency::total 15776500 # number of overall MSHR uncacheable cycles
1783system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for ReadReq accesses
1784system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030560 # mshr miss rate for ReadReq accesses
1785system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for demand accesses
1786system.cpu1.icache.demand_mshr_miss_rate::total 0.030560 # mshr miss rate for demand accesses
1787system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for overall accesses
1788system.cpu1.icache.overall_mshr_miss_rate::total 0.030560 # mshr miss rate for overall accesses
1789system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average ReadReq mshr miss latency
1790system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8449.215971 # average ReadReq mshr miss latency
1791system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency
1792system.cpu1.icache.demand_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency
1793system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency
1794system.cpu1.icache.overall_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency
1795system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency
1796system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency
1797system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency
1798system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency
1799system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued
1800system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified
1801system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
1802system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1803system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1804system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing
1805system.cpu1.l2cache.tags.replacements 44688 # number of replacements
1806system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use
1807system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks.
1808system.cpu1.l2cache.tags.sampled_refs 59377 # Sample count of references to valid blocks.
1809system.cpu1.l2cache.tags.avg_refs 19.563737 # Average number of references to valid blocks.
1810system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1811system.cpu1.l2cache.tags.occ_blocks::writebacks 14464.281457 # Average occupied blocks per requestor
1812system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.152749 # Average occupied blocks per requestor
1813system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.089726 # Average occupied blocks per requestor
1814system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 468.961320 # Average occupied blocks per requestor
1815system.cpu1.l2cache.tags.occ_percent::writebacks 0.882830 # Average percentage of cache occupancy
1816system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy
1817system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy
1818system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028623 # Average percentage of cache occupancy
1819system.cpu1.l2cache.tags.occ_percent::total 0.911773 # Average percentage of cache occupancy
1820system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id
1821system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
1822system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13646 # Occupied blocks per task id
1823system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 36 # Occupied blocks per task id
1824system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 993 # Occupied blocks per task id
1825system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
1826system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
1827system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 280 # Occupied blocks per task id
1828system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id
1829system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11682 # Occupied blocks per task id
1830system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id
1831system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
1832system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832886 # Percentage of cache occupancy per task id
1833system.cpu1.l2cache.tags.tag_accesses 23775762 # Number of tag accesses
1834system.cpu1.l2cache.tags.data_accesses 23775762 # Number of data accesses
1835system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3761 # number of ReadReq hits
1836system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2010 # number of ReadReq hits
1837system.cpu1.l2cache.ReadReq_hits::total 5771 # number of ReadReq hits
1838system.cpu1.l2cache.WritebackDirty_hits::writebacks 113707 # number of WritebackDirty hits
1839system.cpu1.l2cache.WritebackDirty_hits::total 113707 # number of WritebackDirty hits
1840system.cpu1.l2cache.WritebackClean_hits::writebacks 567008 # number of WritebackClean hits
1841system.cpu1.l2cache.WritebackClean_hits::total 567008 # number of WritebackClean hits
1842system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27229 # number of ReadExReq hits
1843system.cpu1.l2cache.ReadExReq_hits::total 27229 # number of ReadExReq hits
1844system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 492726 # number of ReadCleanReq hits
1845system.cpu1.l2cache.ReadCleanReq_hits::total 492726 # number of ReadCleanReq hits
1846system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99930 # number of ReadSharedReq hits
1847system.cpu1.l2cache.ReadSharedReq_hits::total 99930 # number of ReadSharedReq hits
1848system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3761 # number of demand (read+write) hits
1849system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2010 # number of demand (read+write) hits
1850system.cpu1.l2cache.demand_hits::cpu1.inst 492726 # number of demand (read+write) hits
1851system.cpu1.l2cache.demand_hits::cpu1.data 127159 # number of demand (read+write) hits
1852system.cpu1.l2cache.demand_hits::total 625656 # number of demand (read+write) hits
1853system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3761 # number of overall hits
1854system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2010 # number of overall hits
1855system.cpu1.l2cache.overall_hits::cpu1.inst 492726 # number of overall hits
1856system.cpu1.l2cache.overall_hits::cpu1.data 127159 # number of overall hits
1857system.cpu1.l2cache.overall_hits::total 625656 # number of overall hits
1858system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 318 # number of ReadReq misses
1859system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses
1860system.cpu1.l2cache.ReadReq_misses::total 590 # number of ReadReq misses
1861system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29672 # number of UpgradeReq misses
1862system.cpu1.l2cache.UpgradeReq_misses::total 29672 # number of UpgradeReq misses
1863system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23330 # number of SCUpgradeReq misses
1864system.cpu1.l2cache.SCUpgradeReq_misses::total 23330 # number of SCUpgradeReq misses
1865system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses
1866system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
1867system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34782 # number of ReadExReq misses
1868system.cpu1.l2cache.ReadExReq_misses::total 34782 # number of ReadExReq misses
1869system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13250 # number of ReadCleanReq misses
1870system.cpu1.l2cache.ReadCleanReq_misses::total 13250 # number of ReadCleanReq misses
1871system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 68048 # number of ReadSharedReq misses
1872system.cpu1.l2cache.ReadSharedReq_misses::total 68048 # number of ReadSharedReq misses
1873system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 318 # number of demand (read+write) misses
1874system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses
1875system.cpu1.l2cache.demand_misses::cpu1.inst 13250 # number of demand (read+write) misses
1876system.cpu1.l2cache.demand_misses::cpu1.data 102830 # number of demand (read+write) misses
1877system.cpu1.l2cache.demand_misses::total 116670 # number of demand (read+write) misses
1878system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 318 # number of overall misses
1879system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses
1880system.cpu1.l2cache.overall_misses::cpu1.inst 13250 # number of overall misses
1881system.cpu1.l2cache.overall_misses::cpu1.data 102830 # number of overall misses
1882system.cpu1.l2cache.overall_misses::total 116670 # number of overall misses
1883system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6473000 # number of ReadReq miss cycles
1884system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5557000 # number of ReadReq miss cycles
1885system.cpu1.l2cache.ReadReq_miss_latency::total 12030000 # number of ReadReq miss cycles
1886system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 65067000 # number of UpgradeReq miss cycles
1887system.cpu1.l2cache.UpgradeReq_miss_latency::total 65067000 # number of UpgradeReq miss cycles
1888system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 32437500 # number of SCUpgradeReq miss cycles
1889system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 32437500 # number of SCUpgradeReq miss cycles
1890system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3268500 # number of SCUpgradeFailReq miss cycles
1891system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3268500 # number of SCUpgradeFailReq miss cycles
1892system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1333613500 # number of ReadExReq miss cycles
1893system.cpu1.l2cache.ReadExReq_miss_latency::total 1333613500 # number of ReadExReq miss cycles
1894system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 533576500 # number of ReadCleanReq miss cycles
1895system.cpu1.l2cache.ReadCleanReq_miss_latency::total 533576500 # number of ReadCleanReq miss cycles
1896system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1512816500 # number of ReadSharedReq miss cycles
1897system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1512816500 # number of ReadSharedReq miss cycles
1898system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6473000 # number of demand (read+write) miss cycles
1899system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5557000 # number of demand (read+write) miss cycles
1900system.cpu1.l2cache.demand_miss_latency::cpu1.inst 533576500 # number of demand (read+write) miss cycles
1901system.cpu1.l2cache.demand_miss_latency::cpu1.data 2846430000 # number of demand (read+write) miss cycles
1902system.cpu1.l2cache.demand_miss_latency::total 3392036500 # number of demand (read+write) miss cycles
1903system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6473000 # number of overall miss cycles
1904system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5557000 # number of overall miss cycles
1905system.cpu1.l2cache.overall_miss_latency::cpu1.inst 533576500 # number of overall miss cycles
1906system.cpu1.l2cache.overall_miss_latency::cpu1.data 2846430000 # number of overall miss cycles
1907system.cpu1.l2cache.overall_miss_latency::total 3392036500 # number of overall miss cycles
1908system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 4079 # number of ReadReq accesses(hits+misses)
1909system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2282 # number of ReadReq accesses(hits+misses)
1910system.cpu1.l2cache.ReadReq_accesses::total 6361 # number of ReadReq accesses(hits+misses)
1911system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113707 # number of WritebackDirty accesses(hits+misses)
1912system.cpu1.l2cache.WritebackDirty_accesses::total 113707 # number of WritebackDirty accesses(hits+misses)
1913system.cpu1.l2cache.WritebackClean_accesses::writebacks 567008 # number of WritebackClean accesses(hits+misses)
1914system.cpu1.l2cache.WritebackClean_accesses::total 567008 # number of WritebackClean accesses(hits+misses)
1915system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29672 # number of UpgradeReq accesses(hits+misses)
1916system.cpu1.l2cache.UpgradeReq_accesses::total 29672 # number of UpgradeReq accesses(hits+misses)
1917system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23330 # number of SCUpgradeReq accesses(hits+misses)
1918system.cpu1.l2cache.SCUpgradeReq_accesses::total 23330 # number of SCUpgradeReq accesses(hits+misses)
1919system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
1920system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
1921system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62011 # number of ReadExReq accesses(hits+misses)
1922system.cpu1.l2cache.ReadExReq_accesses::total 62011 # number of ReadExReq accesses(hits+misses)
1923system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 505976 # number of ReadCleanReq accesses(hits+misses)
1924system.cpu1.l2cache.ReadCleanReq_accesses::total 505976 # number of ReadCleanReq accesses(hits+misses)
1925system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167978 # number of ReadSharedReq accesses(hits+misses)
1926system.cpu1.l2cache.ReadSharedReq_accesses::total 167978 # number of ReadSharedReq accesses(hits+misses)
1927system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 4079 # number of demand (read+write) accesses
1928system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2282 # number of demand (read+write) accesses
1929system.cpu1.l2cache.demand_accesses::cpu1.inst 505976 # number of demand (read+write) accesses
1930system.cpu1.l2cache.demand_accesses::cpu1.data 229989 # number of demand (read+write) accesses
1931system.cpu1.l2cache.demand_accesses::total 742326 # number of demand (read+write) accesses
1932system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 4079 # number of overall (read+write) accesses
1933system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2282 # number of overall (read+write) accesses
1934system.cpu1.l2cache.overall_accesses::cpu1.inst 505976 # number of overall (read+write) accesses
1935system.cpu1.l2cache.overall_accesses::cpu1.data 229989 # number of overall (read+write) accesses
1936system.cpu1.l2cache.overall_accesses::total 742326 # number of overall (read+write) accesses
1937system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for ReadReq accesses
1938system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.119194 # miss rate for ReadReq accesses
1939system.cpu1.l2cache.ReadReq_miss_rate::total 0.092753 # miss rate for ReadReq accesses
1940system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1941system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1942system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1943system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1944system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1945system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1946system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.560900 # miss rate for ReadExReq accesses
1947system.cpu1.l2cache.ReadExReq_miss_rate::total 0.560900 # miss rate for ReadExReq accesses
1948system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026187 # miss rate for ReadCleanReq accesses
1949system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026187 # miss rate for ReadCleanReq accesses
1950system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.405101 # miss rate for ReadSharedReq accesses
1951system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.405101 # miss rate for ReadSharedReq accesses
1952system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for demand accesses
1953system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.119194 # miss rate for demand accesses
1954system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026187 # miss rate for demand accesses
1955system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.447108 # miss rate for demand accesses
1956system.cpu1.l2cache.demand_miss_rate::total 0.157168 # miss rate for demand accesses
1957system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.077960 # miss rate for overall accesses
1958system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.119194 # miss rate for overall accesses
1959system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026187 # miss rate for overall accesses
1960system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.447108 # miss rate for overall accesses
1961system.cpu1.l2cache.overall_miss_rate::total 0.157168 # miss rate for overall accesses
1962system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average ReadReq miss latency
1963system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20430.147059 # average ReadReq miss latency
1964system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20389.830508 # average ReadReq miss latency
1965system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2192.875438 # average UpgradeReq miss latency
1966system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2192.875438 # average UpgradeReq miss latency
1967system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1390.377197 # average SCUpgradeReq miss latency
1968system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1390.377197 # average SCUpgradeReq miss latency
1969system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 817125 # average SCUpgradeFailReq miss latency
1970system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 817125 # average SCUpgradeFailReq miss latency
1971system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38342.059111 # average ReadExReq miss latency
1972system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38342.059111 # average ReadExReq miss latency
1973system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40269.924528 # average ReadCleanReq miss latency
1974system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40269.924528 # average ReadCleanReq miss latency
1975system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22231.608570 # average ReadSharedReq miss latency
1976system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22231.608570 # average ReadSharedReq miss latency
1977system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency
1978system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency
1979system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency
1980system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency
1981system.cpu1.l2cache.demand_avg_miss_latency::total 29073.767892 # average overall miss latency
1982system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20355.345912 # average overall miss latency
1983system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20430.147059 # average overall miss latency
1984system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40269.924528 # average overall miss latency
1985system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27680.929690 # average overall miss latency
1986system.cpu1.l2cache.overall_avg_miss_latency::total 29073.767892 # average overall miss latency
1987system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1988system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1989system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1990system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1991system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1992system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1993system.cpu1.l2cache.unused_prefetches 790 # number of HardPF blocks evicted w/o reference
1994system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks
1995system.cpu1.l2cache.writebacks::total 33019 # number of writebacks
1996system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 57 # number of ReadExReq MSHR hits
1997system.cpu1.l2cache.ReadExReq_mshr_hits::total 57 # number of ReadExReq MSHR hits
1998system.cpu1.l2cache.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits
1999system.cpu1.l2cache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits
2000system.cpu1.l2cache.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits
2001system.cpu1.l2cache.overall_mshr_hits::total 57 # number of overall MSHR hits
2002system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 318 # number of ReadReq MSHR misses
2003system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 272 # number of ReadReq MSHR misses
2004system.cpu1.l2cache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses
2005system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of HardPFReq MSHR misses
2006system.cpu1.l2cache.HardPFReq_mshr_misses::total 24979 # number of HardPFReq MSHR misses
2007system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29672 # number of UpgradeReq MSHR misses
2008system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29672 # number of UpgradeReq MSHR misses
2009system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23330 # number of SCUpgradeReq MSHR misses
2010system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23330 # number of SCUpgradeReq MSHR misses
2011system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses
2012system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
2013system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34725 # number of ReadExReq MSHR misses
2014system.cpu1.l2cache.ReadExReq_mshr_misses::total 34725 # number of ReadExReq MSHR misses
2015system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13250 # number of ReadCleanReq MSHR misses
2016system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13250 # number of ReadCleanReq MSHR misses
2017system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 68048 # number of ReadSharedReq MSHR misses
2018system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 68048 # number of ReadSharedReq MSHR misses
2019system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 318 # number of demand (read+write) MSHR misses
2020system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 272 # number of demand (read+write) MSHR misses
2021system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13250 # number of demand (read+write) MSHR misses
2022system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102773 # number of demand (read+write) MSHR misses
2023system.cpu1.l2cache.demand_mshr_misses::total 116613 # number of demand (read+write) MSHR misses
2024system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 318 # number of overall MSHR misses
2025system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 272 # number of overall MSHR misses
2026system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13250 # number of overall MSHR misses
2027system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102773 # number of overall MSHR misses
2028system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24979 # number of overall MSHR misses
2029system.cpu1.l2cache.overall_mshr_misses::total 141592 # number of overall MSHR misses
2030system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2031system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable
2032system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3272 # number of ReadReq MSHR uncacheable
2033system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable
2034system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable
2035system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2036system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses
2037system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5722 # number of overall MSHR uncacheable misses
2038system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of ReadReq MSHR miss cycles
2039system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3925000 # number of ReadReq MSHR miss cycles
2040system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8490000 # number of ReadReq MSHR miss cycles
2041system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of HardPFReq MSHR miss cycles
2042system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 780424807 # number of HardPFReq MSHR miss cycles
2043system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 494079500 # number of UpgradeReq MSHR miss cycles
2044system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 494079500 # number of UpgradeReq MSHR miss cycles
2045system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 371536000 # number of SCUpgradeReq MSHR miss cycles
2046system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 371536000 # number of SCUpgradeReq MSHR miss cycles
2047system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2914500 # number of SCUpgradeFailReq MSHR miss cycles
2048system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2914500 # number of SCUpgradeFailReq MSHR miss cycles
2049system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1118604500 # number of ReadExReq MSHR miss cycles
2050system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1118604500 # number of ReadExReq MSHR miss cycles
2051system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 454076500 # number of ReadCleanReq MSHR miss cycles
2052system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 454076500 # number of ReadCleanReq MSHR miss cycles
2053system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1104528500 # number of ReadSharedReq MSHR miss cycles
2054system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1104528500 # number of ReadSharedReq MSHR miss cycles
2055system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of demand (read+write) MSHR miss cycles
2056system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3925000 # number of demand (read+write) MSHR miss cycles
2057system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454076500 # number of demand (read+write) MSHR miss cycles
2058system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2223133000 # number of demand (read+write) MSHR miss cycles
2059system.cpu1.l2cache.demand_mshr_miss_latency::total 2685699500 # number of demand (read+write) MSHR miss cycles
2060system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4565000 # number of overall MSHR miss cycles
2061system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3925000 # number of overall MSHR miss cycles
2062system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454076500 # number of overall MSHR miss cycles
2063system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2223133000 # number of overall MSHR miss cycles
2064system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 780424807 # number of overall MSHR miss cycles
2065system.cpu1.l2cache.overall_mshr_miss_latency::total 3466124307 # number of overall MSHR miss cycles
2066system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14449000 # number of ReadReq MSHR uncacheable cycles
2067system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418310000 # number of ReadReq MSHR uncacheable cycles
2068system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432759000 # number of ReadReq MSHR uncacheable cycles
2069system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14449000 # number of overall MSHR uncacheable cycles
2070system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418310000 # number of overall MSHR uncacheable cycles
2071system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432759000 # number of overall MSHR uncacheable cycles
2072system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for ReadReq accesses
2073system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for ReadReq accesses
2074system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.092753 # mshr miss rate for ReadReq accesses
2075system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2076system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2077system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2078system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2079system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2080system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2081system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2082system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2083system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559981 # mshr miss rate for ReadExReq accesses
2084system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559981 # mshr miss rate for ReadExReq accesses
2085system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for ReadCleanReq accesses
2086system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadCleanReq accesses
2087system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.405101 # mshr miss rate for ReadSharedReq accesses
2088system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405101 # mshr miss rate for ReadSharedReq accesses
2089system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for demand accesses
2090system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for demand accesses
2091system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for demand accesses
2092system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for demand accesses
2093system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157091 # mshr miss rate for demand accesses
2094system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for overall accesses
2095system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for overall accesses
2096system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for overall accesses
2097system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for overall accesses
2098system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2099system.cpu1.l2cache.overall_mshr_miss_rate::total 0.190741 # mshr miss rate for overall accesses
2100system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average ReadReq mshr miss latency
2101system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average ReadReq mshr miss latency
2102system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14389.830508 # average ReadReq mshr miss latency
2103system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average HardPFReq mshr miss latency
2104system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31243.236599 # average HardPFReq mshr miss latency
2105system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16651.371664 # average UpgradeReq mshr miss latency
2106system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16651.371664 # average UpgradeReq mshr miss latency
2107system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15925.246464 # average SCUpgradeReq mshr miss latency
2108system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15925.246464 # average SCUpgradeReq mshr miss latency
2109system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 728625 # average SCUpgradeFailReq mshr miss latency
2110system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 728625 # average SCUpgradeFailReq mshr miss latency
2111system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32213.232541 # average ReadExReq mshr miss latency
2112system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32213.232541 # average ReadExReq mshr miss latency
2113system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average ReadCleanReq mshr miss latency
2114system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34269.924528 # average ReadCleanReq mshr miss latency
2115system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16231.608570 # average ReadSharedReq mshr miss latency
2116system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16231.608570 # average ReadSharedReq mshr miss latency
2117system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency
2118system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency
2119system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency
2120system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency
2121system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23030.875631 # average overall mshr miss latency
2122system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency
2123system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency
2124system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency
2125system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency
2126system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average overall mshr miss latency
2127system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24479.662036 # average overall mshr miss latency
2128system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency
2129system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135156.704362 # average ReadReq mshr uncacheable latency
2130system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132261.308068 # average ReadReq mshr uncacheable latency
2131system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency
2132system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75439.134355 # average overall mshr uncacheable latency
2133system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75630.723523 # average overall mshr uncacheable latency
2134system.cpu1.toL2Bus.snoop_filter.tot_requests 1487204 # Total number of requests made to the snoop filter.
2135system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751274 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2136system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2137system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter.
2138system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2139system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2140system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution
2141system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution
2142system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution
2143system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution
2144system.cpu1.toL2Bus.trans_dist::WritebackDirty 147816 # Transaction distribution
2145system.cpu1.toL2Bus.trans_dist::WritebackClean 578146 # Transaction distribution
2146system.cpu1.toL2Bus.trans_dist::CleanEvict 101473 # Transaction distribution
2147system.cpu1.toL2Bus.trans_dist::HardPFReq 30088 # Transaction distribution
2148system.cpu1.toL2Bus.trans_dist::UpgradeReq 71412 # Transaction distribution
2149system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41204 # Transaction distribution
2150system.cpu1.toL2Bus.trans_dist::UpgradeResp 85825 # Transaction distribution
2151system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
2152system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution
2153system.cpu1.toL2Bus.trans_dist::ReadExReq 69105 # Transaction distribution
2154system.cpu1.toL2Bus.trans_dist::ReadExResp 66696 # Transaction distribution
2155system.cpu1.toL2Bus.trans_dist::ReadCleanReq 505976 # Transaction distribution
2156system.cpu1.toL2Bus.trans_dist::ReadSharedReq 245752 # Transaction distribution
2157system.cpu1.toL2Bus.trans_dist::InvalidateReq 247 # Transaction distribution
2158system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1517770 # Packet count per connected master and slave (bytes)
2159system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838774 # Packet count per connected master and slave (bytes)
2160system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5606 # Packet count per connected master and slave (bytes)
2161system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10127 # Packet count per connected master and slave (bytes)
2162system.cpu1.toL2Bus.pkt_count::total 2372277 # Packet count per connected master and slave (bytes)
2163system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64732868 # Cumulative packet size per connected master and slave (bytes)
2164system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29385740 # Cumulative packet size per connected master and slave (bytes)
2165system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9128 # Cumulative packet size per connected master and slave (bytes)
2166system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16316 # Cumulative packet size per connected master and slave (bytes)
2167system.cpu1.toL2Bus.pkt_size::total 94144052 # Cumulative packet size per connected master and slave (bytes)
2168system.cpu1.toL2Bus.snoops 388756 # Total snoops (count)
2169system.cpu1.toL2Bus.snoop_fanout::samples 1114505 # Request fanout histogram
2170system.cpu1.toL2Bus.snoop_fanout::mean 0.179300 # Request fanout histogram
2171system.cpu1.toL2Bus.snoop_fanout::stdev 0.390891 # Request fanout histogram
2172system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2173system.cpu1.toL2Bus.snoop_fanout::0 917819 82.35% 82.35% # Request fanout histogram
2174system.cpu1.toL2Bus.snoop_fanout::1 193541 17.37% 99.72% # Request fanout histogram
2175system.cpu1.toL2Bus.snoop_fanout::2 3145 0.28% 100.00% # Request fanout histogram
2176system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2177system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2178system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2179system.cpu1.toL2Bus.snoop_fanout::total 1114505 # Request fanout histogram
2180system.cpu1.toL2Bus.reqLayer0.occupancy 1441037000 # Layer occupancy (ticks)
2181system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2182system.cpu1.toL2Bus.snoopLayer0.occupancy 80111937 # Layer occupancy (ticks)
2183system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2184system.cpu1.toL2Bus.respLayer0.occupancy 759141000 # Layer occupancy (ticks)
2185system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2186system.cpu1.toL2Bus.respLayer1.occupancy 375865500 # Layer occupancy (ticks)
2187system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2188system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks)
2189system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2190system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks)
2191system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2192system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
2193system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
2194system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
2195system.iobus.trans_dist::WriteResp 59422 # Transaction distribution
2196system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
2197system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2198system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2199system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2200system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2201system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2202system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2203system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2204system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2205system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2206system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2207system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2208system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2209system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2210system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2211system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2212system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2213system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2214system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2215system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
2216system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
2217system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
2218system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes)
2219system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
2220system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2221system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2222system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2223system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2224system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2225system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2226system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2227system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2228system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2229system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2230system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2231system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2232system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2233system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2234system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2235system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2236system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2237system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2238system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
2239system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
2240system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
2241system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes)
2242system.iobus.reqLayer0.occupancy 48726000 # Layer occupancy (ticks)
2243system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2244system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks)
2245system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2246system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks)
2247system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2248system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks)
2249system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2250system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
2251system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2252system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks)
2253system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2254system.iobus.reqLayer8.occupancy 601500 # Layer occupancy (ticks)
2255system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2256system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks)
2257system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2258system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2259system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2260system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
2261system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2262system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
2263system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2264system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks)
2265system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2266system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
2267system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2268system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks)
2269system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2270system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2271system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2272system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2273system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2274system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2275system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2276system.iobus.reqLayer23.occupancy 6164000 # Layer occupancy (ticks)
2277system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2278system.iobus.reqLayer24.occupancy 32044500 # Layer occupancy (ticks)
2279system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2280system.iobus.reqLayer25.occupancy 187734328 # Layer occupancy (ticks)
2281system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2282system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
2283system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2284system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
2285system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2286system.iocache.tags.replacements 36445 # number of replacements
2287system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use
2288system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2289system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
2290system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2291system.iocache.tags.warmup_cycle 289174340000 # Cycle when the warmup percentage was hit.
2292system.iocache.tags.occ_blocks::realview.ide 14.386648 # Average occupied blocks per requestor
2293system.iocache.tags.occ_percent::realview.ide 0.899166 # Average percentage of cache occupancy
2294system.iocache.tags.occ_percent::total 0.899166 # Average percentage of cache occupancy
2295system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2296system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2297system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2298system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2299system.iocache.tags.data_accesses 328311 # Number of data accesses
2300system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2301system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2302system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2303system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2304system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
2305system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
2306system.iocache.overall_misses::realview.ide 36479 # number of overall misses
2307system.iocache.overall_misses::total 36479 # number of overall misses
2308system.iocache.ReadReq_miss_latency::realview.ide 36421877 # number of ReadReq miss cycles
2309system.iocache.ReadReq_miss_latency::total 36421877 # number of ReadReq miss cycles
2310system.iocache.WriteLineReq_miss_latency::realview.ide 4307524451 # number of WriteLineReq miss cycles
2311system.iocache.WriteLineReq_miss_latency::total 4307524451 # number of WriteLineReq miss cycles
2312system.iocache.demand_miss_latency::realview.ide 4343946328 # number of demand (read+write) miss cycles
2313system.iocache.demand_miss_latency::total 4343946328 # number of demand (read+write) miss cycles
2314system.iocache.overall_miss_latency::realview.ide 4343946328 # number of overall miss cycles
2315system.iocache.overall_miss_latency::total 4343946328 # number of overall miss cycles
2316system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2317system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2318system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2319system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2320system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
2321system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
2322system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
2323system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
2324system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2325system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2326system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2327system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2328system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2329system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2330system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2331system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2332system.iocache.ReadReq_avg_miss_latency::realview.ide 142830.890196 # average ReadReq miss latency
2333system.iocache.ReadReq_avg_miss_latency::total 142830.890196 # average ReadReq miss latency
2334system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118913.550436 # average WriteLineReq miss latency
2335system.iocache.WriteLineReq_avg_miss_latency::total 118913.550436 # average WriteLineReq miss latency
2336system.iocache.demand_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency
2337system.iocache.demand_avg_miss_latency::total 119080.740371 # average overall miss latency
2338system.iocache.overall_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency
2339system.iocache.overall_avg_miss_latency::total 119080.740371 # average overall miss latency
2340system.iocache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked
2341system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2342system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked
2343system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2344system.iocache.avg_blocked_cycles::no_mshrs 3.142857 # average number of cycles each access was blocked
2345system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2346system.iocache.writebacks::writebacks 36190 # number of writebacks
2347system.iocache.writebacks::total 36190 # number of writebacks
2348system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2349system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2350system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2351system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2352system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
2353system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
2354system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
2355system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
2356system.iocache.ReadReq_mshr_miss_latency::realview.ide 23671877 # number of ReadReq MSHR miss cycles
2357system.iocache.ReadReq_mshr_miss_latency::total 23671877 # number of ReadReq MSHR miss cycles
2358system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493982137 # number of WriteLineReq MSHR miss cycles
2359system.iocache.WriteLineReq_mshr_miss_latency::total 2493982137 # number of WriteLineReq MSHR miss cycles
2360system.iocache.demand_mshr_miss_latency::realview.ide 2517654014 # number of demand (read+write) MSHR miss cycles
2361system.iocache.demand_mshr_miss_latency::total 2517654014 # number of demand (read+write) MSHR miss cycles
2362system.iocache.overall_mshr_miss_latency::realview.ide 2517654014 # number of overall MSHR miss cycles
2363system.iocache.overall_mshr_miss_latency::total 2517654014 # number of overall MSHR miss cycles
2364system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2365system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2366system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2367system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2368system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2369system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2370system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2371system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2372system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 92830.890196 # average ReadReq mshr miss latency
2373system.iocache.ReadReq_avg_mshr_miss_latency::total 92830.890196 # average ReadReq mshr miss latency
2374system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68848.888499 # average WriteLineReq mshr miss latency
2375system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68848.888499 # average WriteLineReq mshr miss latency
2376system.iocache.demand_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency
2377system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency
2378system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency
2379system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency
2380system.l2c.tags.replacements 126308 # number of replacements
2381system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use
2382system.l2c.tags.total_refs 424315 # Total number of references to valid blocks.
2383system.l2c.tags.sampled_refs 190178 # Sample count of references to valid blocks.
2384system.l2c.tags.avg_refs 2.231147 # Average number of references to valid blocks.
2385system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2386system.l2c.tags.occ_blocks::writebacks 13637.426679 # Average occupied blocks per requestor
2387system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.018602 # Average occupied blocks per requestor
2388system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043991 # Average occupied blocks per requestor
2389system.l2c.tags.occ_blocks::cpu0.inst 7319.345128 # Average occupied blocks per requestor
2390system.l2c.tags.occ_blocks::cpu0.data 2841.087210 # Average occupied blocks per requestor
2391system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35552.012227 # Average occupied blocks per requestor
2392system.l2c.tags.occ_blocks::cpu1.inst 1437.607406 # Average occupied blocks per requestor
2393system.l2c.tags.occ_blocks::cpu1.data 447.669169 # Average occupied blocks per requestor
2394system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1777.834065 # Average occupied blocks per requestor
2395system.l2c.tags.occ_percent::writebacks 0.208091 # Average percentage of cache occupancy
2396system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy
2397system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2398system.l2c.tags.occ_percent::cpu0.inst 0.111684 # Average percentage of cache occupancy
2399system.l2c.tags.occ_percent::cpu0.data 0.043352 # Average percentage of cache occupancy
2400system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.542481 # Average percentage of cache occupancy
2401system.l2c.tags.occ_percent::cpu1.inst 0.021936 # Average percentage of cache occupancy
2402system.l2c.tags.occ_percent::cpu1.data 0.006831 # Average percentage of cache occupancy
2403system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027128 # Average percentage of cache occupancy
2404system.l2c.tags.occ_percent::total 0.961564 # Average percentage of cache occupancy
2405system.l2c.tags.occ_task_id_blocks::1022 30519 # Occupied blocks per task id
2406system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
2407system.l2c.tags.occ_task_id_blocks::1024 33346 # Occupied blocks per task id
2408system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
2409system.l2c.tags.age_task_id_blocks_1022::2 165 # Occupied blocks per task id
2410system.l2c.tags.age_task_id_blocks_1022::3 4688 # Occupied blocks per task id
2411system.l2c.tags.age_task_id_blocks_1022::4 25665 # Occupied blocks per task id
2412system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
2413system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
2414system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
2415system.l2c.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id
2416system.l2c.tags.age_task_id_blocks_1024::3 2267 # Occupied blocks per task id
2417system.l2c.tags.age_task_id_blocks_1024::4 30712 # Occupied blocks per task id
2418system.l2c.tags.occ_task_id_percent::1022 0.465683 # Percentage of cache occupancy per task id
2419system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
2420system.l2c.tags.occ_task_id_percent::1024 0.508820 # Percentage of cache occupancy per task id
2421system.l2c.tags.tag_accesses 5890164 # Number of tag accesses
2422system.l2c.tags.data_accesses 5890164 # Number of data accesses
2423system.l2c.WritebackDirty_hits::writebacks 260994 # number of WritebackDirty hits
2424system.l2c.WritebackDirty_hits::total 260994 # number of WritebackDirty hits
2425system.l2c.UpgradeReq_hits::cpu0.data 31980 # number of UpgradeReq hits
2426system.l2c.UpgradeReq_hits::cpu1.data 2487 # number of UpgradeReq hits
2427system.l2c.UpgradeReq_hits::total 34467 # number of UpgradeReq hits
2428system.l2c.SCUpgradeReq_hits::cpu0.data 1985 # number of SCUpgradeReq hits
2429system.l2c.SCUpgradeReq_hits::cpu1.data 965 # number of SCUpgradeReq hits
2430system.l2c.SCUpgradeReq_hits::total 2950 # number of SCUpgradeReq hits
2431system.l2c.ReadExReq_hits::cpu0.data 3870 # number of ReadExReq hits
2432system.l2c.ReadExReq_hits::cpu1.data 1490 # number of ReadExReq hits
2433system.l2c.ReadExReq_hits::total 5360 # number of ReadExReq hits
2434system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 97 # number of ReadSharedReq hits
2435system.l2c.ReadSharedReq_hits::cpu0.itb.walker 76 # number of ReadSharedReq hits
2436system.l2c.ReadSharedReq_hits::cpu0.inst 27673 # number of ReadSharedReq hits
2437system.l2c.ReadSharedReq_hits::cpu0.data 45621 # number of ReadSharedReq hits
2438system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45892 # number of ReadSharedReq hits
2439system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 31 # number of ReadSharedReq hits
2440system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits
2441system.l2c.ReadSharedReq_hits::cpu1.inst 10962 # number of ReadSharedReq hits
2442system.l2c.ReadSharedReq_hits::cpu1.data 9208 # number of ReadSharedReq hits
2443system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5411 # number of ReadSharedReq hits
2444system.l2c.ReadSharedReq_hits::total 145008 # number of ReadSharedReq hits
2445system.l2c.demand_hits::cpu0.dtb.walker 97 # number of demand (read+write) hits
2446system.l2c.demand_hits::cpu0.itb.walker 76 # number of demand (read+write) hits
2447system.l2c.demand_hits::cpu0.inst 27673 # number of demand (read+write) hits
2448system.l2c.demand_hits::cpu0.data 49491 # number of demand (read+write) hits
2449system.l2c.demand_hits::cpu0.l2cache.prefetcher 45892 # number of demand (read+write) hits
2450system.l2c.demand_hits::cpu1.dtb.walker 31 # number of demand (read+write) hits
2451system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits
2452system.l2c.demand_hits::cpu1.inst 10962 # number of demand (read+write) hits
2453system.l2c.demand_hits::cpu1.data 10698 # number of demand (read+write) hits
2454system.l2c.demand_hits::cpu1.l2cache.prefetcher 5411 # number of demand (read+write) hits
2455system.l2c.demand_hits::total 150368 # number of demand (read+write) hits
2456system.l2c.overall_hits::cpu0.dtb.walker 97 # number of overall hits
2457system.l2c.overall_hits::cpu0.itb.walker 76 # number of overall hits
2458system.l2c.overall_hits::cpu0.inst 27673 # number of overall hits
2459system.l2c.overall_hits::cpu0.data 49491 # number of overall hits
2460system.l2c.overall_hits::cpu0.l2cache.prefetcher 45892 # number of overall hits
2461system.l2c.overall_hits::cpu1.dtb.walker 31 # number of overall hits
2462system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits
2463system.l2c.overall_hits::cpu1.inst 10962 # number of overall hits
2464system.l2c.overall_hits::cpu1.data 10698 # number of overall hits
2465system.l2c.overall_hits::cpu1.l2cache.prefetcher 5411 # number of overall hits
2466system.l2c.overall_hits::total 150368 # number of overall hits
2467system.l2c.UpgradeReq_misses::cpu0.data 8680 # number of UpgradeReq misses
2468system.l2c.UpgradeReq_misses::cpu1.data 2870 # number of UpgradeReq misses
2469system.l2c.UpgradeReq_misses::total 11550 # number of UpgradeReq misses
2470system.l2c.SCUpgradeReq_misses::cpu0.data 542 # number of SCUpgradeReq misses
2471system.l2c.SCUpgradeReq_misses::cpu1.data 1323 # number of SCUpgradeReq misses
2472system.l2c.SCUpgradeReq_misses::total 1865 # number of SCUpgradeReq misses
2473system.l2c.ReadExReq_misses::cpu0.data 11368 # number of ReadExReq misses
2474system.l2c.ReadExReq_misses::cpu1.data 8031 # number of ReadExReq misses
2475system.l2c.ReadExReq_misses::total 19399 # number of ReadExReq misses
2476system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses
2477system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
2478system.l2c.ReadSharedReq_misses::cpu0.inst 17607 # number of ReadSharedReq misses
2479system.l2c.ReadSharedReq_misses::cpu0.data 8862 # number of ReadSharedReq misses
2480system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133884 # number of ReadSharedReq misses
2481system.l2c.ReadSharedReq_misses::cpu1.inst 2288 # number of ReadSharedReq misses
2482system.l2c.ReadSharedReq_misses::cpu1.data 856 # number of ReadSharedReq misses
2483system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6026 # number of ReadSharedReq misses
2484system.l2c.ReadSharedReq_misses::total 169532 # number of ReadSharedReq misses
2485system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
2486system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
2487system.l2c.demand_misses::cpu0.inst 17607 # number of demand (read+write) misses
2488system.l2c.demand_misses::cpu0.data 20230 # number of demand (read+write) misses
2489system.l2c.demand_misses::cpu0.l2cache.prefetcher 133884 # number of demand (read+write) misses
2490system.l2c.demand_misses::cpu1.inst 2288 # number of demand (read+write) misses
2491system.l2c.demand_misses::cpu1.data 8887 # number of demand (read+write) misses
2492system.l2c.demand_misses::cpu1.l2cache.prefetcher 6026 # number of demand (read+write) misses
2493system.l2c.demand_misses::total 188931 # number of demand (read+write) misses
2494system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
2495system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
2496system.l2c.overall_misses::cpu0.inst 17607 # number of overall misses
2497system.l2c.overall_misses::cpu0.data 20230 # number of overall misses
2498system.l2c.overall_misses::cpu0.l2cache.prefetcher 133884 # number of overall misses
2499system.l2c.overall_misses::cpu1.inst 2288 # number of overall misses
2500system.l2c.overall_misses::cpu1.data 8887 # number of overall misses
2501system.l2c.overall_misses::cpu1.l2cache.prefetcher 6026 # number of overall misses
2502system.l2c.overall_misses::total 188931 # number of overall misses
2503system.l2c.UpgradeReq_miss_latency::cpu0.data 11274000 # number of UpgradeReq miss cycles
2504system.l2c.UpgradeReq_miss_latency::cpu1.data 4127500 # number of UpgradeReq miss cycles
2505system.l2c.UpgradeReq_miss_latency::total 15401500 # number of UpgradeReq miss cycles
2506system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1640500 # number of SCUpgradeReq miss cycles
2507system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1015500 # number of SCUpgradeReq miss cycles
2508system.l2c.SCUpgradeReq_miss_latency::total 2656000 # number of SCUpgradeReq miss cycles
2509system.l2c.ReadExReq_miss_latency::cpu0.data 1087660500 # number of ReadExReq miss cycles
2510system.l2c.ReadExReq_miss_latency::cpu1.data 661855000 # number of ReadExReq miss cycles
2511system.l2c.ReadExReq_miss_latency::total 1749515500 # number of ReadExReq miss cycles
2512system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 703500 # number of ReadSharedReq miss cycles
2513system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles
2514system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1440677500 # number of ReadSharedReq miss cycles
|
2515system.l2c.ReadSharedReq_miss_latency::cpu0.data 776893500 # number of ReadSharedReq miss cycles
2516system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of ReadSharedReq miss cycles
| 2515system.l2c.ReadSharedReq_miss_latency::cpu0.data 776891500 # number of ReadSharedReq miss cycles
2516system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of ReadSharedReq miss cycles
|
2517system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles
2518system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles
2519system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles
| 2517system.l2c.ReadSharedReq_miss_latency::cpu1.inst 189843000 # number of ReadSharedReq miss cycles
2518system.l2c.ReadSharedReq_miss_latency::cpu1.data 77251000 # number of ReadSharedReq miss cycles
2519system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of ReadSharedReq miss cycles
|
2520system.l2c.ReadSharedReq_miss_latency::total 16119848689 # number of ReadSharedReq miss cycles
| 2520system.l2c.ReadSharedReq_miss_latency::total 16119828689 # number of ReadSharedReq miss cycles
|
2521system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles
2522system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles
2523system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles
| 2521system.l2c.demand_miss_latency::cpu0.dtb.walker 703500 # number of demand (read+write) miss cycles
2522system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles
2523system.l2c.demand_miss_latency::cpu0.inst 1440677500 # number of demand (read+write) miss cycles
|
2524system.l2c.demand_miss_latency::cpu0.data 1864554000 # number of demand (read+write) miss cycles
2525system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of demand (read+write) miss cycles
| 2524system.l2c.demand_miss_latency::cpu0.data 1864552000 # number of demand (read+write) miss cycles
2525system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of demand (read+write) miss cycles
|
2526system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles
2527system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles
2528system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles
| 2526system.l2c.demand_miss_latency::cpu1.inst 189843000 # number of demand (read+write) miss cycles
2527system.l2c.demand_miss_latency::cpu1.data 739106000 # number of demand (read+write) miss cycles
2528system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of demand (read+write) miss cycles
|
2529system.l2c.demand_miss_latency::total 17869364189 # number of demand (read+write) miss cycles
| 2529system.l2c.demand_miss_latency::total 17869344189 # number of demand (read+write) miss cycles
|
2530system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles
2531system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles
2532system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles
| 2530system.l2c.overall_miss_latency::cpu0.dtb.walker 703500 # number of overall miss cycles
2531system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles
2532system.l2c.overall_miss_latency::cpu0.inst 1440677500 # number of overall miss cycles
|
2533system.l2c.overall_miss_latency::cpu0.data 1864554000 # number of overall miss cycles
2534system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971819632 # number of overall miss cycles
| 2533system.l2c.overall_miss_latency::cpu0.data 1864552000 # number of overall miss cycles
2534system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12971801632 # number of overall miss cycles
|
2535system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles
2536system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles
2537system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles
| 2535system.l2c.overall_miss_latency::cpu1.inst 189843000 # number of overall miss cycles
2536system.l2c.overall_miss_latency::cpu1.data 739106000 # number of overall miss cycles
2537system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 662486557 # number of overall miss cycles
|
2538system.l2c.overall_miss_latency::total 17869364189 # number of overall miss cycles
| 2538system.l2c.overall_miss_latency::total 17869344189 # number of overall miss cycles
|
2539system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses)
2540system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses)
2541system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses)
2542system.l2c.UpgradeReq_accesses::cpu1.data 5357 # number of UpgradeReq accesses(hits+misses)
2543system.l2c.UpgradeReq_accesses::total 46017 # number of UpgradeReq accesses(hits+misses)
2544system.l2c.SCUpgradeReq_accesses::cpu0.data 2527 # number of SCUpgradeReq accesses(hits+misses)
2545system.l2c.SCUpgradeReq_accesses::cpu1.data 2288 # number of SCUpgradeReq accesses(hits+misses)
2546system.l2c.SCUpgradeReq_accesses::total 4815 # number of SCUpgradeReq accesses(hits+misses)
2547system.l2c.ReadExReq_accesses::cpu0.data 15238 # number of ReadExReq accesses(hits+misses)
2548system.l2c.ReadExReq_accesses::cpu1.data 9521 # number of ReadExReq accesses(hits+misses)
2549system.l2c.ReadExReq_accesses::total 24759 # number of ReadExReq accesses(hits+misses)
2550system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 104 # number of ReadSharedReq accesses(hits+misses)
2551system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses)
2552system.l2c.ReadSharedReq_accesses::cpu0.inst 45280 # number of ReadSharedReq accesses(hits+misses)
2553system.l2c.ReadSharedReq_accesses::cpu0.data 54483 # number of ReadSharedReq accesses(hits+misses)
2554system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179776 # number of ReadSharedReq accesses(hits+misses)
2555system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 31 # number of ReadSharedReq accesses(hits+misses)
2556system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 37 # number of ReadSharedReq accesses(hits+misses)
2557system.l2c.ReadSharedReq_accesses::cpu1.inst 13250 # number of ReadSharedReq accesses(hits+misses)
2558system.l2c.ReadSharedReq_accesses::cpu1.data 10064 # number of ReadSharedReq accesses(hits+misses)
2559system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11437 # number of ReadSharedReq accesses(hits+misses)
2560system.l2c.ReadSharedReq_accesses::total 314540 # number of ReadSharedReq accesses(hits+misses)
2561system.l2c.demand_accesses::cpu0.dtb.walker 104 # number of demand (read+write) accesses
2562system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses
2563system.l2c.demand_accesses::cpu0.inst 45280 # number of demand (read+write) accesses
2564system.l2c.demand_accesses::cpu0.data 69721 # number of demand (read+write) accesses
2565system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179776 # number of demand (read+write) accesses
2566system.l2c.demand_accesses::cpu1.dtb.walker 31 # number of demand (read+write) accesses
2567system.l2c.demand_accesses::cpu1.itb.walker 37 # number of demand (read+write) accesses
2568system.l2c.demand_accesses::cpu1.inst 13250 # number of demand (read+write) accesses
2569system.l2c.demand_accesses::cpu1.data 19585 # number of demand (read+write) accesses
2570system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11437 # number of demand (read+write) accesses
2571system.l2c.demand_accesses::total 339299 # number of demand (read+write) accesses
2572system.l2c.overall_accesses::cpu0.dtb.walker 104 # number of overall (read+write) accesses
2573system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses
2574system.l2c.overall_accesses::cpu0.inst 45280 # number of overall (read+write) accesses
2575system.l2c.overall_accesses::cpu0.data 69721 # number of overall (read+write) accesses
2576system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179776 # number of overall (read+write) accesses
2577system.l2c.overall_accesses::cpu1.dtb.walker 31 # number of overall (read+write) accesses
2578system.l2c.overall_accesses::cpu1.itb.walker 37 # number of overall (read+write) accesses
2579system.l2c.overall_accesses::cpu1.inst 13250 # number of overall (read+write) accesses
2580system.l2c.overall_accesses::cpu1.data 19585 # number of overall (read+write) accesses
2581system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11437 # number of overall (read+write) accesses
2582system.l2c.overall_accesses::total 339299 # number of overall (read+write) accesses
2583system.l2c.UpgradeReq_miss_rate::cpu0.data 0.213478 # miss rate for UpgradeReq accesses
2584system.l2c.UpgradeReq_miss_rate::cpu1.data 0.535748 # miss rate for UpgradeReq accesses
2585system.l2c.UpgradeReq_miss_rate::total 0.250994 # miss rate for UpgradeReq accesses
2586system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.214484 # miss rate for SCUpgradeReq accesses
2587system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.578234 # miss rate for SCUpgradeReq accesses
2588system.l2c.SCUpgradeReq_miss_rate::total 0.387331 # miss rate for SCUpgradeReq accesses
2589system.l2c.ReadExReq_miss_rate::cpu0.data 0.746030 # miss rate for ReadExReq accesses
2590system.l2c.ReadExReq_miss_rate::cpu1.data 0.843504 # miss rate for ReadExReq accesses
2591system.l2c.ReadExReq_miss_rate::total 0.783513 # miss rate for ReadExReq accesses
2592system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for ReadSharedReq accesses
2593system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025641 # miss rate for ReadSharedReq accesses
2594system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.388847 # miss rate for ReadSharedReq accesses
2595system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162656 # miss rate for ReadSharedReq accesses
2596system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for ReadSharedReq accesses
2597system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.172679 # miss rate for ReadSharedReq accesses
2598system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.085056 # miss rate for ReadSharedReq accesses
2599system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for ReadSharedReq accesses
2600system.l2c.ReadSharedReq_miss_rate::total 0.538984 # miss rate for ReadSharedReq accesses
2601system.l2c.demand_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for demand accesses
2602system.l2c.demand_miss_rate::cpu0.itb.walker 0.025641 # miss rate for demand accesses
2603system.l2c.demand_miss_rate::cpu0.inst 0.388847 # miss rate for demand accesses
2604system.l2c.demand_miss_rate::cpu0.data 0.290156 # miss rate for demand accesses
2605system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for demand accesses
2606system.l2c.demand_miss_rate::cpu1.inst 0.172679 # miss rate for demand accesses
2607system.l2c.demand_miss_rate::cpu1.data 0.453766 # miss rate for demand accesses
2608system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for demand accesses
2609system.l2c.demand_miss_rate::total 0.556827 # miss rate for demand accesses
2610system.l2c.overall_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for overall accesses
2611system.l2c.overall_miss_rate::cpu0.itb.walker 0.025641 # miss rate for overall accesses
2612system.l2c.overall_miss_rate::cpu0.inst 0.388847 # miss rate for overall accesses
2613system.l2c.overall_miss_rate::cpu0.data 0.290156 # miss rate for overall accesses
2614system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for overall accesses
2615system.l2c.overall_miss_rate::cpu1.inst 0.172679 # miss rate for overall accesses
2616system.l2c.overall_miss_rate::cpu1.data 0.453766 # miss rate for overall accesses
2617system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for overall accesses
2618system.l2c.overall_miss_rate::total 0.556827 # miss rate for overall accesses
2619system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1298.847926 # average UpgradeReq miss latency
2620system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1438.153310 # average UpgradeReq miss latency
2621system.l2c.UpgradeReq_avg_miss_latency::total 1333.463203 # average UpgradeReq miss latency
2622system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3026.752768 # average SCUpgradeReq miss latency
2623system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 767.573696 # average SCUpgradeReq miss latency
2624system.l2c.SCUpgradeReq_avg_miss_latency::total 1424.128686 # average SCUpgradeReq miss latency
2625system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95677.383885 # average ReadExReq miss latency
2626system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82412.526460 # average ReadExReq miss latency
2627system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 # average ReadExReq miss latency
2628system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency
2629system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency
2630system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency
| 2539system.l2c.WritebackDirty_accesses::writebacks 260994 # number of WritebackDirty accesses(hits+misses)
2540system.l2c.WritebackDirty_accesses::total 260994 # number of WritebackDirty accesses(hits+misses)
2541system.l2c.UpgradeReq_accesses::cpu0.data 40660 # number of UpgradeReq accesses(hits+misses)
2542system.l2c.UpgradeReq_accesses::cpu1.data 5357 # number of UpgradeReq accesses(hits+misses)
2543system.l2c.UpgradeReq_accesses::total 46017 # number of UpgradeReq accesses(hits+misses)
2544system.l2c.SCUpgradeReq_accesses::cpu0.data 2527 # number of SCUpgradeReq accesses(hits+misses)
2545system.l2c.SCUpgradeReq_accesses::cpu1.data 2288 # number of SCUpgradeReq accesses(hits+misses)
2546system.l2c.SCUpgradeReq_accesses::total 4815 # number of SCUpgradeReq accesses(hits+misses)
2547system.l2c.ReadExReq_accesses::cpu0.data 15238 # number of ReadExReq accesses(hits+misses)
2548system.l2c.ReadExReq_accesses::cpu1.data 9521 # number of ReadExReq accesses(hits+misses)
2549system.l2c.ReadExReq_accesses::total 24759 # number of ReadExReq accesses(hits+misses)
2550system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 104 # number of ReadSharedReq accesses(hits+misses)
2551system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 78 # number of ReadSharedReq accesses(hits+misses)
2552system.l2c.ReadSharedReq_accesses::cpu0.inst 45280 # number of ReadSharedReq accesses(hits+misses)
2553system.l2c.ReadSharedReq_accesses::cpu0.data 54483 # number of ReadSharedReq accesses(hits+misses)
2554system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 179776 # number of ReadSharedReq accesses(hits+misses)
2555system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 31 # number of ReadSharedReq accesses(hits+misses)
2556system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 37 # number of ReadSharedReq accesses(hits+misses)
2557system.l2c.ReadSharedReq_accesses::cpu1.inst 13250 # number of ReadSharedReq accesses(hits+misses)
2558system.l2c.ReadSharedReq_accesses::cpu1.data 10064 # number of ReadSharedReq accesses(hits+misses)
2559system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11437 # number of ReadSharedReq accesses(hits+misses)
2560system.l2c.ReadSharedReq_accesses::total 314540 # number of ReadSharedReq accesses(hits+misses)
2561system.l2c.demand_accesses::cpu0.dtb.walker 104 # number of demand (read+write) accesses
2562system.l2c.demand_accesses::cpu0.itb.walker 78 # number of demand (read+write) accesses
2563system.l2c.demand_accesses::cpu0.inst 45280 # number of demand (read+write) accesses
2564system.l2c.demand_accesses::cpu0.data 69721 # number of demand (read+write) accesses
2565system.l2c.demand_accesses::cpu0.l2cache.prefetcher 179776 # number of demand (read+write) accesses
2566system.l2c.demand_accesses::cpu1.dtb.walker 31 # number of demand (read+write) accesses
2567system.l2c.demand_accesses::cpu1.itb.walker 37 # number of demand (read+write) accesses
2568system.l2c.demand_accesses::cpu1.inst 13250 # number of demand (read+write) accesses
2569system.l2c.demand_accesses::cpu1.data 19585 # number of demand (read+write) accesses
2570system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11437 # number of demand (read+write) accesses
2571system.l2c.demand_accesses::total 339299 # number of demand (read+write) accesses
2572system.l2c.overall_accesses::cpu0.dtb.walker 104 # number of overall (read+write) accesses
2573system.l2c.overall_accesses::cpu0.itb.walker 78 # number of overall (read+write) accesses
2574system.l2c.overall_accesses::cpu0.inst 45280 # number of overall (read+write) accesses
2575system.l2c.overall_accesses::cpu0.data 69721 # number of overall (read+write) accesses
2576system.l2c.overall_accesses::cpu0.l2cache.prefetcher 179776 # number of overall (read+write) accesses
2577system.l2c.overall_accesses::cpu1.dtb.walker 31 # number of overall (read+write) accesses
2578system.l2c.overall_accesses::cpu1.itb.walker 37 # number of overall (read+write) accesses
2579system.l2c.overall_accesses::cpu1.inst 13250 # number of overall (read+write) accesses
2580system.l2c.overall_accesses::cpu1.data 19585 # number of overall (read+write) accesses
2581system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11437 # number of overall (read+write) accesses
2582system.l2c.overall_accesses::total 339299 # number of overall (read+write) accesses
2583system.l2c.UpgradeReq_miss_rate::cpu0.data 0.213478 # miss rate for UpgradeReq accesses
2584system.l2c.UpgradeReq_miss_rate::cpu1.data 0.535748 # miss rate for UpgradeReq accesses
2585system.l2c.UpgradeReq_miss_rate::total 0.250994 # miss rate for UpgradeReq accesses
2586system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.214484 # miss rate for SCUpgradeReq accesses
2587system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.578234 # miss rate for SCUpgradeReq accesses
2588system.l2c.SCUpgradeReq_miss_rate::total 0.387331 # miss rate for SCUpgradeReq accesses
2589system.l2c.ReadExReq_miss_rate::cpu0.data 0.746030 # miss rate for ReadExReq accesses
2590system.l2c.ReadExReq_miss_rate::cpu1.data 0.843504 # miss rate for ReadExReq accesses
2591system.l2c.ReadExReq_miss_rate::total 0.783513 # miss rate for ReadExReq accesses
2592system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for ReadSharedReq accesses
2593system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025641 # miss rate for ReadSharedReq accesses
2594system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.388847 # miss rate for ReadSharedReq accesses
2595system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.162656 # miss rate for ReadSharedReq accesses
2596system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for ReadSharedReq accesses
2597system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.172679 # miss rate for ReadSharedReq accesses
2598system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.085056 # miss rate for ReadSharedReq accesses
2599system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for ReadSharedReq accesses
2600system.l2c.ReadSharedReq_miss_rate::total 0.538984 # miss rate for ReadSharedReq accesses
2601system.l2c.demand_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for demand accesses
2602system.l2c.demand_miss_rate::cpu0.itb.walker 0.025641 # miss rate for demand accesses
2603system.l2c.demand_miss_rate::cpu0.inst 0.388847 # miss rate for demand accesses
2604system.l2c.demand_miss_rate::cpu0.data 0.290156 # miss rate for demand accesses
2605system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for demand accesses
2606system.l2c.demand_miss_rate::cpu1.inst 0.172679 # miss rate for demand accesses
2607system.l2c.demand_miss_rate::cpu1.data 0.453766 # miss rate for demand accesses
2608system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for demand accesses
2609system.l2c.demand_miss_rate::total 0.556827 # miss rate for demand accesses
2610system.l2c.overall_miss_rate::cpu0.dtb.walker 0.067308 # miss rate for overall accesses
2611system.l2c.overall_miss_rate::cpu0.itb.walker 0.025641 # miss rate for overall accesses
2612system.l2c.overall_miss_rate::cpu0.inst 0.388847 # miss rate for overall accesses
2613system.l2c.overall_miss_rate::cpu0.data 0.290156 # miss rate for overall accesses
2614system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.744727 # miss rate for overall accesses
2615system.l2c.overall_miss_rate::cpu1.inst 0.172679 # miss rate for overall accesses
2616system.l2c.overall_miss_rate::cpu1.data 0.453766 # miss rate for overall accesses
2617system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.526886 # miss rate for overall accesses
2618system.l2c.overall_miss_rate::total 0.556827 # miss rate for overall accesses
2619system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1298.847926 # average UpgradeReq miss latency
2620system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1438.153310 # average UpgradeReq miss latency
2621system.l2c.UpgradeReq_avg_miss_latency::total 1333.463203 # average UpgradeReq miss latency
2622system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3026.752768 # average SCUpgradeReq miss latency
2623system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 767.573696 # average SCUpgradeReq miss latency
2624system.l2c.SCUpgradeReq_avg_miss_latency::total 1424.128686 # average SCUpgradeReq miss latency
2625system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95677.383885 # average ReadExReq miss latency
2626system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82412.526460 # average ReadExReq miss latency
2627system.l2c.ReadExReq_avg_miss_latency::total 90185.860096 # average ReadExReq miss latency
2628system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100500 # average ReadSharedReq miss latency
2629system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency
2630system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81824.132447 # average ReadSharedReq miss latency
|
2631system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.707515 # average ReadSharedReq miss latency
2632system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average ReadSharedReq miss latency
| 2631system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87665.481833 # average ReadSharedReq miss latency
2632system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average ReadSharedReq miss latency
|
2633system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency
2634system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency
2635system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency
| 2633system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82973.339161 # average ReadSharedReq miss latency
2634system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90246.495327 # average ReadSharedReq miss latency
2635system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average ReadSharedReq miss latency
|
2636system.l2c.ReadSharedReq_avg_miss_latency::total 95084.401110 # average ReadSharedReq miss latency
| 2636system.l2c.ReadSharedReq_avg_miss_latency::total 95084.283138 # average ReadSharedReq miss latency
|
2637system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency
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2639system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency
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2638system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
2639system.l2c.demand_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency
|
2640system.l2c.demand_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency
2641system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency
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2641system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency
|
2642system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency
2643system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency
2644system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency
| 2642system.l2c.demand_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency
2643system.l2c.demand_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency
2644system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency
|
2645system.l2c.demand_avg_miss_latency::total 94581.430199 # average overall miss latency
| 2645system.l2c.demand_avg_miss_latency::total 94581.324341 # average overall miss latency
|
2646system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100500 # average overall miss latency
2647system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
2648system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency
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2647system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
2648system.l2c.overall_avg_miss_latency::cpu0.inst 81824.132447 # average overall miss latency
|
2649system.l2c.overall_avg_miss_latency::cpu0.data 92167.770638 # average overall miss latency
2650system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.497744 # average overall miss latency
| 2649system.l2c.overall_avg_miss_latency::cpu0.data 92167.671775 # average overall miss latency
2650system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96888.363300 # average overall miss latency
|
2651system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency
2652system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency
2653system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency
| 2651system.l2c.overall_avg_miss_latency::cpu1.inst 82973.339161 # average overall miss latency
2652system.l2c.overall_avg_miss_latency::cpu1.data 83167.098008 # average overall miss latency
2653system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 109938.028045 # average overall miss latency
|
2654system.l2c.overall_avg_miss_latency::total 94581.430199 # average overall miss latency
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|
2655system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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2734system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1264511501 # number of ReadSharedReq MSHR miss cycles
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2656system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2657system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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|
2735system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 688273500 # number of ReadSharedReq MSHR miss cycles
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2738system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 68690501 # number of ReadSharedReq MSHR miss cycles
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|
2740system.l2c.ReadSharedReq_mshr_miss_latency::total 14423954199 # number of ReadSharedReq MSHR miss cycles
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|
2741system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles
2742system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles
2743system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles
| 2741system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 633500 # number of demand (read+write) MSHR miss cycles
2742system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles
2743system.l2c.demand_mshr_miss_latency::cpu0.inst 1264511501 # number of demand (read+write) MSHR miss cycles
|
2744system.l2c.demand_mshr_miss_latency::cpu0.data 1662254000 # number of demand (read+write) MSHR miss cycles
2745system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of demand (read+write) MSHR miss cycles
| 2744system.l2c.demand_mshr_miss_latency::cpu0.data 1662252000 # number of demand (read+write) MSHR miss cycles
2745system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of demand (read+write) MSHR miss cycles
|
2746system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles
2747system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles
2748system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles
| 2746system.l2c.demand_mshr_miss_latency::cpu1.inst 166489000 # number of demand (read+write) MSHR miss cycles
2747system.l2c.demand_mshr_miss_latency::cpu1.data 650235501 # number of demand (read+write) MSHR miss cycles
2748system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of demand (read+write) MSHR miss cycles
|
2749system.l2c.demand_mshr_miss_latency::total 15979479699 # number of demand (read+write) MSHR miss cycles
| 2749system.l2c.demand_mshr_miss_latency::total 15979459699 # number of demand (read+write) MSHR miss cycles
|
2750system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles
2751system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles
2752system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles
| 2750system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 633500 # number of overall MSHR miss cycles
2751system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles
2752system.l2c.overall_mshr_miss_latency::cpu0.inst 1264511501 # number of overall MSHR miss cycles
|
2753system.l2c.overall_mshr_miss_latency::cpu0.data 1662254000 # number of overall MSHR miss cycles
2754system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632976638 # number of overall MSHR miss cycles
| 2753system.l2c.overall_mshr_miss_latency::cpu0.data 1662252000 # number of overall MSHR miss cycles
2754system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11632958638 # number of overall MSHR miss cycles
|
2755system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles
2756system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles
2757system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles
| 2755system.l2c.overall_mshr_miss_latency::cpu1.inst 166489000 # number of overall MSHR miss cycles
2756system.l2c.overall_mshr_miss_latency::cpu1.data 650235501 # number of overall MSHR miss cycles
2757system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 602225559 # number of overall MSHR miss cycles
|
2758system.l2c.overall_mshr_miss_latency::total 15979479699 # number of overall MSHR miss cycles
| 2758system.l2c.overall_mshr_miss_latency::total 15979459699 # number of overall MSHR miss cycles
|
2759system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles
2760system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles
2761system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles
2762system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362609000 # number of ReadReq MSHR uncacheable cycles
2763system.l2c.ReadReq_mshr_uncacheable_latency::total 6757114500 # number of ReadReq MSHR uncacheable cycles
2764system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles
2765system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801887500 # number of overall MSHR uncacheable cycles
2766system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles
2767system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362609000 # number of overall MSHR uncacheable cycles
2768system.l2c.overall_mshr_uncacheable_latency::total 6757114500 # number of overall MSHR uncacheable cycles
2769system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2770system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2771system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.213478 # mshr miss rate for UpgradeReq accesses
2772system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.535748 # mshr miss rate for UpgradeReq accesses
2773system.l2c.UpgradeReq_mshr_miss_rate::total 0.250994 # mshr miss rate for UpgradeReq accesses
2774system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.214484 # mshr miss rate for SCUpgradeReq accesses
2775system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.578234 # mshr miss rate for SCUpgradeReq accesses
2776system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.387331 # mshr miss rate for SCUpgradeReq accesses
2777system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746030 # mshr miss rate for ReadExReq accesses
2778system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.843504 # mshr miss rate for ReadExReq accesses
2779system.l2c.ReadExReq_mshr_miss_rate::total 0.783513 # mshr miss rate for ReadExReq accesses
2780system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for ReadSharedReq accesses
2781system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses
2782system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for ReadSharedReq accesses
2783system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162656 # mshr miss rate for ReadSharedReq accesses
2784system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for ReadSharedReq accesses
2785system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for ReadSharedReq accesses
2786system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.085056 # mshr miss rate for ReadSharedReq accesses
2787system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for ReadSharedReq accesses
2788system.l2c.ReadSharedReq_mshr_miss_rate::total 0.538939 # mshr miss rate for ReadSharedReq accesses
2789system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for demand accesses
2790system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for demand accesses
2791system.l2c.demand_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for demand accesses
2792system.l2c.demand_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for demand accesses
2793system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for demand accesses
2794system.l2c.demand_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for demand accesses
2795system.l2c.demand_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for demand accesses
2796system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for demand accesses
2797system.l2c.demand_mshr_miss_rate::total 0.556786 # mshr miss rate for demand accesses
2798system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for overall accesses
2799system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for overall accesses
2800system.l2c.overall_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for overall accesses
2801system.l2c.overall_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for overall accesses
2802system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for overall accesses
2803system.l2c.overall_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for overall accesses
2804system.l2c.overall_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for overall accesses
2805system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for overall accesses
2806system.l2c.overall_mshr_miss_rate::total 0.556786 # mshr miss rate for overall accesses
2807system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23964.516129 # average UpgradeReq mshr miss latency
2808system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22794.773519 # average UpgradeReq mshr miss latency
2809system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23673.852814 # average UpgradeReq mshr miss latency
2810system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25817.343173 # average SCUpgradeReq mshr miss latency
2811system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24925.170068 # average SCUpgradeReq mshr miss latency
2812system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25184.450402 # average SCUpgradeReq mshr miss latency
2813system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85677.383885 # average ReadExReq mshr miss latency
2814system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72412.526460 # average ReadExReq mshr miss latency
2815system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 # average ReadExReq mshr miss latency
2816system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency
2817system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency
2818system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency
| 2759system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles
2760system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801887500 # number of ReadReq MSHR uncacheable cycles
2761system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles
2762system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 362609000 # number of ReadReq MSHR uncacheable cycles
2763system.l2c.ReadReq_mshr_uncacheable_latency::total 6757114500 # number of ReadReq MSHR uncacheable cycles
2764system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles
2765system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801887500 # number of overall MSHR uncacheable cycles
2766system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles
2767system.l2c.overall_mshr_uncacheable_latency::cpu1.data 362609000 # number of overall MSHR uncacheable cycles
2768system.l2c.overall_mshr_uncacheable_latency::total 6757114500 # number of overall MSHR uncacheable cycles
2769system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2770system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2771system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.213478 # mshr miss rate for UpgradeReq accesses
2772system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.535748 # mshr miss rate for UpgradeReq accesses
2773system.l2c.UpgradeReq_mshr_miss_rate::total 0.250994 # mshr miss rate for UpgradeReq accesses
2774system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.214484 # mshr miss rate for SCUpgradeReq accesses
2775system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.578234 # mshr miss rate for SCUpgradeReq accesses
2776system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.387331 # mshr miss rate for SCUpgradeReq accesses
2777system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746030 # mshr miss rate for ReadExReq accesses
2778system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.843504 # mshr miss rate for ReadExReq accesses
2779system.l2c.ReadExReq_mshr_miss_rate::total 0.783513 # mshr miss rate for ReadExReq accesses
2780system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for ReadSharedReq accesses
2781system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for ReadSharedReq accesses
2782system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for ReadSharedReq accesses
2783system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.162656 # mshr miss rate for ReadSharedReq accesses
2784system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for ReadSharedReq accesses
2785system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for ReadSharedReq accesses
2786system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.085056 # mshr miss rate for ReadSharedReq accesses
2787system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for ReadSharedReq accesses
2788system.l2c.ReadSharedReq_mshr_miss_rate::total 0.538939 # mshr miss rate for ReadSharedReq accesses
2789system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for demand accesses
2790system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for demand accesses
2791system.l2c.demand_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for demand accesses
2792system.l2c.demand_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for demand accesses
2793system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for demand accesses
2794system.l2c.demand_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for demand accesses
2795system.l2c.demand_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for demand accesses
2796system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for demand accesses
2797system.l2c.demand_mshr_miss_rate::total 0.556786 # mshr miss rate for demand accesses
2798system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.067308 # mshr miss rate for overall accesses
2799system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.025641 # mshr miss rate for overall accesses
2800system.l2c.overall_mshr_miss_rate::cpu0.inst 0.388759 # mshr miss rate for overall accesses
2801system.l2c.overall_mshr_miss_rate::cpu0.data 0.290156 # mshr miss rate for overall accesses
2802system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.744727 # mshr miss rate for overall accesses
2803system.l2c.overall_mshr_miss_rate::cpu1.inst 0.171925 # mshr miss rate for overall accesses
2804system.l2c.overall_mshr_miss_rate::cpu1.data 0.453766 # mshr miss rate for overall accesses
2805system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.526886 # mshr miss rate for overall accesses
2806system.l2c.overall_mshr_miss_rate::total 0.556786 # mshr miss rate for overall accesses
2807system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23964.516129 # average UpgradeReq mshr miss latency
2808system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22794.773519 # average UpgradeReq mshr miss latency
2809system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23673.852814 # average UpgradeReq mshr miss latency
2810system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25817.343173 # average SCUpgradeReq mshr miss latency
2811system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24925.170068 # average SCUpgradeReq mshr miss latency
2812system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25184.450402 # average SCUpgradeReq mshr miss latency
2813system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85677.383885 # average ReadExReq mshr miss latency
2814system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72412.526460 # average ReadExReq mshr miss latency
2815system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 # average ReadExReq mshr miss latency
2816system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency
2817system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency
2818system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency
|
2819system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.707515 # average ReadSharedReq mshr miss latency
2820system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average ReadSharedReq mshr miss latency
| 2819system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.481833 # average ReadSharedReq mshr miss latency
2820system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average ReadSharedReq mshr miss latency
|
2821system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency
2822system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency
2823system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency
| 2821system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency
2822system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency
2823system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency
|
2824system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85088.039022 # average ReadSharedReq mshr miss latency
| 2824system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85087.921041 # average ReadSharedReq mshr miss latency
|
2825system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency
2826system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
2827system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency
| 2825system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency
2826system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
2827system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency
|
2828system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency
2829system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency
| 2828system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency
2829system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency
|
2830system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency
2831system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency
2832system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency
| 2830system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency
2831system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency
2832system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency
|
2833system.l2c.demand_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency
| 2833system.l2c.demand_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency
|
2834system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency
2835system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
2836system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency
| 2834system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency
2835system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
2836system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency
|
2837system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency
2838system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency
| 2837system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.671775 # average overall mshr miss latency
2838system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.340937 # average overall mshr miss latency
|
2839system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency
2840system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency
2841system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency
| 2839system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency
2840system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency
2841system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency
|
2842system.l2c.overall_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency
| 2842system.l2c.overall_avg_mshr_miss_latency::total 84584.551411 # average overall mshr miss latency
|
2843system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency
2844system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency
2845system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency
2846system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117273.285899 # average ReadReq mshr uncacheable latency
2847system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153281.639181 # average ReadReq mshr uncacheable latency
2848system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency
2849system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96288.897187 # average overall mshr uncacheable latency
2850system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency
2851system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.267412 # average overall mshr uncacheable latency
2852system.l2c.overall_avg_mshr_uncacheable_latency::total 90099.665315 # average overall mshr uncacheable latency
2853system.membus.snoop_filter.tot_requests 512702 # Total number of requests made to the snoop filter.
2854system.membus.snoop_filter.hit_single_requests 293222 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2855system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2856system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2857system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2858system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2859system.membus.trans_dist::ReadReq 44083 # Transaction distribution
2860system.membus.trans_dist::ReadResp 213856 # Transaction distribution
2861system.membus.trans_dist::WriteReq 30913 # Transaction distribution
2862system.membus.trans_dist::WriteResp 30913 # Transaction distribution
2863system.membus.trans_dist::WritebackDirty 135145 # Transaction distribution
2864system.membus.trans_dist::CleanEvict 15700 # Transaction distribution
2865system.membus.trans_dist::UpgradeReq 75854 # Transaction distribution
2866system.membus.trans_dist::SCUpgradeReq 40085 # Transaction distribution
2867system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
2868system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
2869system.membus.trans_dist::ReadExReq 39863 # Transaction distribution
2870system.membus.trans_dist::ReadExResp 19313 # Transaction distribution
2871system.membus.trans_dist::ReadSharedReq 169773 # Transaction distribution
2872system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2873system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
2874system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
2875system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes)
2876system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656506 # Packet count per connected master and slave (bytes)
2877system.membus.pkt_count_system.l2c.mem_side::total 778196 # Packet count per connected master and slave (bytes)
2878system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes)
2879system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes)
2880system.membus.pkt_count::total 851135 # Packet count per connected master and slave (bytes)
2881system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
2882system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
2883system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes)
2884system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18452748 # Cumulative packet size per connected master and slave (bytes)
2885system.membus.pkt_size_system.l2c.mem_side::total 18643092 # Cumulative packet size per connected master and slave (bytes)
2886system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
2887system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2888system.membus.pkt_size::total 20960212 # Cumulative packet size per connected master and slave (bytes)
2889system.membus.snoops 123593 # Total snoops (count)
2890system.membus.snoop_fanout::samples 436796 # Request fanout histogram
2891system.membus.snoop_fanout::mean 0.011900 # Request fanout histogram
2892system.membus.snoop_fanout::stdev 0.108438 # Request fanout histogram
2893system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2894system.membus.snoop_fanout::0 431598 98.81% 98.81% # Request fanout histogram
2895system.membus.snoop_fanout::1 5198 1.19% 100.00% # Request fanout histogram
2896system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2897system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2898system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2899system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2900system.membus.snoop_fanout::total 436796 # Request fanout histogram
2901system.membus.reqLayer0.occupancy 88259500 # Layer occupancy (ticks)
2902system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2903system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks)
2904system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2905system.membus.reqLayer2.occupancy 11350000 # Layer occupancy (ticks)
2906system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2907system.membus.reqLayer5.occupancy 980369236 # Layer occupancy (ticks)
2908system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2909system.membus.respLayer2.occupancy 1108695304 # Layer occupancy (ticks)
2910system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2911system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks)
2912system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2913system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
2914system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
2915system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
2916system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
2917system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
2918system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2919system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2920system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2921system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2922system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2923system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2924system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2925system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
2926system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
2927system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
2928system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
2929system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
2930system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
2931system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
2932system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
2933system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
2934system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
2935system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
2936system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
2937system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
2938system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
2939system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
2940system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
2941system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
2942system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
2943system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2944system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2945system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2946system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2947system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2948system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
2949system.realview.ethernet.droppedPackets 0 # number of packets dropped
2950system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
2951system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
2952system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
2953system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2954system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter.
2955system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2956system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2957system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter.
2958system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2959system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2960system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution
2961system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution
2962system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution
2963system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution
2964system.toL2Bus.trans_dist::WritebackDirty 359949 # Transaction distribution
2965system.toL2Bus.trans_dist::CleanEvict 109182 # Transaction distribution
2966system.toL2Bus.trans_dist::UpgradeReq 110235 # Transaction distribution
2967system.toL2Bus.trans_dist::SCUpgradeReq 43035 # Transaction distribution
2968system.toL2Bus.trans_dist::UpgradeResp 153270 # Transaction distribution
2969system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution
2970system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution
2971system.toL2Bus.trans_dist::ReadExReq 50915 # Transaction distribution
2972system.toL2Bus.trans_dist::ReadExResp 50915 # Transaction distribution
2973system.toL2Bus.trans_dist::ReadSharedReq 433367 # Transaction distribution
2974system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution
2975system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224504 # Packet count per connected master and slave (bytes)
2976system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 296079 # Packet count per connected master and slave (bytes)
2977system.toL2Bus.pkt_count::total 1520583 # Packet count per connected master and slave (bytes)
2978system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33710224 # Cumulative packet size per connected master and slave (bytes)
2979system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4970948 # Cumulative packet size per connected master and slave (bytes)
2980system.toL2Bus.pkt_size::total 38681172 # Cumulative packet size per connected master and slave (bytes)
2981system.toL2Bus.snoops 378680 # Total snoops (count)
2982system.toL2Bus.snoop_fanout::samples 843567 # Request fanout histogram
2983system.toL2Bus.snoop_fanout::mean 0.376795 # Request fanout histogram
2984system.toL2Bus.snoop_fanout::stdev 0.486500 # Request fanout histogram
2985system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2986system.toL2Bus.snoop_fanout::0 526500 62.41% 62.41% # Request fanout histogram
2987system.toL2Bus.snoop_fanout::1 316282 37.49% 99.91% # Request fanout histogram
2988system.toL2Bus.snoop_fanout::2 785 0.09% 100.00% # Request fanout histogram
2989system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2990system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2991system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2992system.toL2Bus.snoop_fanout::total 843567 # Request fanout histogram
2993system.toL2Bus.reqLayer0.occupancy 877207087 # Layer occupancy (ticks)
2994system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2995system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks)
2996system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2997system.toL2Bus.respLayer0.occupancy 640962681 # Layer occupancy (ticks)
2998system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2999system.toL2Bus.respLayer1.occupancy 223907403 # Layer occupancy (ticks)
3000system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3001
3002---------- End Simulation Statistics ----------
| 2843system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency
2844system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency
2845system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency
2846system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117273.285899 # average ReadReq mshr uncacheable latency
2847system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153281.639181 # average ReadReq mshr uncacheable latency
2848system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency
2849system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96288.897187 # average overall mshr uncacheable latency
2850system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency
2851system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.267412 # average overall mshr uncacheable latency
2852system.l2c.overall_avg_mshr_uncacheable_latency::total 90099.665315 # average overall mshr uncacheable latency
2853system.membus.snoop_filter.tot_requests 512702 # Total number of requests made to the snoop filter.
2854system.membus.snoop_filter.hit_single_requests 293222 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2855system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2856system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2857system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2858system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2859system.membus.trans_dist::ReadReq 44083 # Transaction distribution
2860system.membus.trans_dist::ReadResp 213856 # Transaction distribution
2861system.membus.trans_dist::WriteReq 30913 # Transaction distribution
2862system.membus.trans_dist::WriteResp 30913 # Transaction distribution
2863system.membus.trans_dist::WritebackDirty 135145 # Transaction distribution
2864system.membus.trans_dist::CleanEvict 15700 # Transaction distribution
2865system.membus.trans_dist::UpgradeReq 75854 # Transaction distribution
2866system.membus.trans_dist::SCUpgradeReq 40085 # Transaction distribution
2867system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
2868system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
2869system.membus.trans_dist::ReadExReq 39863 # Transaction distribution
2870system.membus.trans_dist::ReadExResp 19313 # Transaction distribution
2871system.membus.trans_dist::ReadSharedReq 169773 # Transaction distribution
2872system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2873system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
2874system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
2875system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes)
2876system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656506 # Packet count per connected master and slave (bytes)
2877system.membus.pkt_count_system.l2c.mem_side::total 778196 # Packet count per connected master and slave (bytes)
2878system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes)
2879system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes)
2880system.membus.pkt_count::total 851135 # Packet count per connected master and slave (bytes)
2881system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
2882system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
2883system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes)
2884system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18452748 # Cumulative packet size per connected master and slave (bytes)
2885system.membus.pkt_size_system.l2c.mem_side::total 18643092 # Cumulative packet size per connected master and slave (bytes)
2886system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
2887system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2888system.membus.pkt_size::total 20960212 # Cumulative packet size per connected master and slave (bytes)
2889system.membus.snoops 123593 # Total snoops (count)
2890system.membus.snoop_fanout::samples 436796 # Request fanout histogram
2891system.membus.snoop_fanout::mean 0.011900 # Request fanout histogram
2892system.membus.snoop_fanout::stdev 0.108438 # Request fanout histogram
2893system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2894system.membus.snoop_fanout::0 431598 98.81% 98.81% # Request fanout histogram
2895system.membus.snoop_fanout::1 5198 1.19% 100.00% # Request fanout histogram
2896system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2897system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2898system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2899system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2900system.membus.snoop_fanout::total 436796 # Request fanout histogram
2901system.membus.reqLayer0.occupancy 88259500 # Layer occupancy (ticks)
2902system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2903system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks)
2904system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2905system.membus.reqLayer2.occupancy 11350000 # Layer occupancy (ticks)
2906system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2907system.membus.reqLayer5.occupancy 980369236 # Layer occupancy (ticks)
2908system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2909system.membus.respLayer2.occupancy 1108695304 # Layer occupancy (ticks)
2910system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2911system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks)
2912system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2913system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
2914system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
2915system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
2916system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
2917system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
2918system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2919system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2920system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2921system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2922system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2923system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2924system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2925system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
2926system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
2927system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
2928system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
2929system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
2930system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
2931system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
2932system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
2933system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
2934system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
2935system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
2936system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
2937system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
2938system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
2939system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
2940system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
2941system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
2942system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
2943system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2944system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2945system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2946system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2947system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2948system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
2949system.realview.ethernet.droppedPackets 0 # number of packets dropped
2950system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
2951system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
2952system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
2953system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
2954system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter.
2955system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2956system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2957system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter.
2958system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2959system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2960system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution
2961system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution
2962system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution
2963system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution
2964system.toL2Bus.trans_dist::WritebackDirty 359949 # Transaction distribution
2965system.toL2Bus.trans_dist::CleanEvict 109182 # Transaction distribution
2966system.toL2Bus.trans_dist::UpgradeReq 110235 # Transaction distribution
2967system.toL2Bus.trans_dist::SCUpgradeReq 43035 # Transaction distribution
2968system.toL2Bus.trans_dist::UpgradeResp 153270 # Transaction distribution
2969system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution
2970system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution
2971system.toL2Bus.trans_dist::ReadExReq 50915 # Transaction distribution
2972system.toL2Bus.trans_dist::ReadExResp 50915 # Transaction distribution
2973system.toL2Bus.trans_dist::ReadSharedReq 433367 # Transaction distribution
2974system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution
2975system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224504 # Packet count per connected master and slave (bytes)
2976system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 296079 # Packet count per connected master and slave (bytes)
2977system.toL2Bus.pkt_count::total 1520583 # Packet count per connected master and slave (bytes)
2978system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33710224 # Cumulative packet size per connected master and slave (bytes)
2979system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4970948 # Cumulative packet size per connected master and slave (bytes)
2980system.toL2Bus.pkt_size::total 38681172 # Cumulative packet size per connected master and slave (bytes)
2981system.toL2Bus.snoops 378680 # Total snoops (count)
2982system.toL2Bus.snoop_fanout::samples 843567 # Request fanout histogram
2983system.toL2Bus.snoop_fanout::mean 0.376795 # Request fanout histogram
2984system.toL2Bus.snoop_fanout::stdev 0.486500 # Request fanout histogram
2985system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2986system.toL2Bus.snoop_fanout::0 526500 62.41% 62.41% # Request fanout histogram
2987system.toL2Bus.snoop_fanout::1 316282 37.49% 99.91% # Request fanout histogram
2988system.toL2Bus.snoop_fanout::2 785 0.09% 100.00% # Request fanout histogram
2989system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2990system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2991system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2992system.toL2Bus.snoop_fanout::total 843567 # Request fanout histogram
2993system.toL2Bus.reqLayer0.occupancy 877207087 # Layer occupancy (ticks)
2994system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2995system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks)
2996system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2997system.toL2Bus.respLayer0.occupancy 640962681 # Layer occupancy (ticks)
2998system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2999system.toL2Bus.respLayer1.occupancy 223907403 # Layer occupancy (ticks)
3000system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3001
3002---------- End Simulation Statistics ----------
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