Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt

Deleted Added

sdiff udiff text old ( 10038:7eccd14e2610 ) new ( 10063:9595c7a1d837 )

full compact

stats.txt (10038:7eccd14e2610)	stats.txt (10063:9595c7a1d837)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.196139 # Number of seconds simulated 4sim_ticks 1196139241000 # Number of ticks simulated 5final_tick 1196139241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.196139 # Number of seconds simulated 4sim_ticks 1196139241000 # Number of ticks simulated 5final_tick 1196139241000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 553961 # Simulator instruction rate (inst/s) 8host_op_rate 705843 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10781179789 # Simulator tick rate (ticks/s) 10host_mem_usage 425360 # Number of bytes of host memory used 11host_seconds 110.95 # Real time elapsed on the host	7host_inst_rate 363491 # Simulator instruction rate (inst/s) 8host_op_rate 463152 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7074263356 # Simulator tick rate (ticks/s) 10host_mem_usage 480032 # Number of bytes of host memory used 11host_seconds 169.08 # Real time elapsed on the host
12sim_insts 61460236 # Number of instructions simulated 13sim_ops 78311148 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 61460236 # Number of instructions simulated 13sim_ops 78311148 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
16system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 393164 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 4714556 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 4804536 # Number of bytes read from this memory 25system.physmem.bytes_read::total 62141956 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 393164 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::total 717840 # Number of instructions bytes read from this memory 29system.physmem.bytes_written::writebacks 4110528 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 32system.physmem.bytes_written::total 7137872 # Number of bytes written to this memory 33system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 12371 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 73739 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 75099 # Number of read requests responded to by this memory 42system.physmem.num_reads::total 6654445 # Number of read requests responded to by this memory 43system.physmem.num_writes::writebacks 64227 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 821063 # Number of write requests responded to by this memory 47system.physmem.bw_read::realview.clcd 43393369 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.inst 328694 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 3941478 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.inst 271437 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.data 4016703 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::total 51952109 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu0.inst 328694 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::cpu1.inst 271437 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_inst_read::total 600131 # Instruction read bandwidth from this memory (bytes/s) 60system.physmem.bw_write::writebacks 3436496 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.data 2516717 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 5967426 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 3436496 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::realview.clcd 43393369 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.inst 328694 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 3955690 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.inst 271437 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.data 6533420 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::total 57919534 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.readReqs 6654445 # Number of read requests accepted 76system.physmem.writeReqs 821063 # Number of write requests accepted 77system.physmem.readBursts 6654445 # Number of DRAM read bursts, including those serviced by the write queue 78system.physmem.writeBursts 821063 # Number of DRAM write bursts, including those merged in the write queue 79system.physmem.bytesReadDRAM 425854976 # Total number of bytes read from DRAM 80system.physmem.bytesReadWrQ 29504 # Total number of bytes read from write queue 81system.physmem.bytesWritten 7264576 # Total number of bytes written to DRAM 82system.physmem.bytesReadSys 62141956 # Total read bytes from the system interface side 83system.physmem.bytesWrittenSys 7137872 # Total written bytes from the system interface side 84system.physmem.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue 85system.physmem.mergedWrBursts 707541 # Number of DRAM write bursts merged with an existing one 86system.physmem.neitherReadNorWriteReqs 12043 # Number of requests that are neither read nor write 87system.physmem.perBankRdBursts::0 415328 # Per bank write bursts 88system.physmem.perBankRdBursts::1 415204 # Per bank write bursts 89system.physmem.perBankRdBursts::2 415403 # Per bank write bursts 90system.physmem.perBankRdBursts::3 415627 # Per bank write bursts 91system.physmem.perBankRdBursts::4 422407 # Per bank write bursts 92system.physmem.perBankRdBursts::5 415617 # Per bank write bursts 93system.physmem.perBankRdBursts::6 415785 # Per bank write bursts 94system.physmem.perBankRdBursts::7 415500 # Per bank write bursts 95system.physmem.perBankRdBursts::8 416027 # Per bank write bursts 96system.physmem.perBankRdBursts::9 415632 # Per bank write bursts 97system.physmem.perBankRdBursts::10 415316 # Per bank write bursts 98system.physmem.perBankRdBursts::11 414840 # Per bank write bursts 99system.physmem.perBankRdBursts::12 415044 # Per bank write bursts 100system.physmem.perBankRdBursts::13 415557 # Per bank write bursts 101system.physmem.perBankRdBursts::14 415554 # Per bank write bursts 102system.physmem.perBankRdBursts::15 415143 # Per bank write bursts 103system.physmem.perBankWrBursts::0 6946 # Per bank write bursts 104system.physmem.perBankWrBursts::1 6844 # Per bank write bursts 105system.physmem.perBankWrBursts::2 7080 # Per bank write bursts 106system.physmem.perBankWrBursts::3 7140 # Per bank write bursts 107system.physmem.perBankWrBursts::4 7438 # Per bank write bursts 108system.physmem.perBankWrBursts::5 7223 # Per bank write bursts 109system.physmem.perBankWrBursts::6 7431 # Per bank write bursts 110system.physmem.perBankWrBursts::7 7190 # Per bank write bursts 111system.physmem.perBankWrBursts::8 7575 # Per bank write bursts 112system.physmem.perBankWrBursts::9 7264 # Per bank write bursts 113system.physmem.perBankWrBursts::10 7139 # Per bank write bursts 114system.physmem.perBankWrBursts::11 6649 # Per bank write bursts 115system.physmem.perBankWrBursts::12 6729 # Per bank write bursts 116system.physmem.perBankWrBursts::13 7011 # Per bank write bursts 117system.physmem.perBankWrBursts::14 7090 # Per bank write bursts 118system.physmem.perBankWrBursts::15 6760 # Per bank write bursts 119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 120system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 121system.physmem.totGap 1196134740000 # Total gap between requests 122system.physmem.readPktSize::0 0 # Read request sizes (log2) 123system.physmem.readPktSize::1 0 # Read request sizes (log2) 124system.physmem.readPktSize::2 6849 # Read request sizes (log2) 125system.physmem.readPktSize::3 6488064 # Read request sizes (log2) 126system.physmem.readPktSize::4 0 # Read request sizes (log2) 127system.physmem.readPktSize::5 0 # Read request sizes (log2) 128system.physmem.readPktSize::6 159532 # Read request sizes (log2) 129system.physmem.writePktSize::0 0 # Write request sizes (log2) 130system.physmem.writePktSize::1 0 # Write request sizes (log2) 131system.physmem.writePktSize::2 756836 # Write request sizes (log2) 132system.physmem.writePktSize::3 0 # Write request sizes (log2) 133system.physmem.writePktSize::4 0 # Write request sizes (log2) 134system.physmem.writePktSize::5 0 # Write request sizes (log2) 135system.physmem.writePktSize::6 64227 # Write request sizes (log2) 136system.physmem.rdQLenPdf::0 627903 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::1 474579 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::2 475456 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::3 1579907 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::4 1133019 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::5 1127067 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::6 1123495 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::7 24904 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::8 24218 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::9 9367 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::10 9281 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::11 9166 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::12 8936 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::13 8867 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::14 8833 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::15 8794 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::16 186 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 168system.physmem.wrQLenPdf::0 5159 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::1 5163 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::2 5160 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::3 5160 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::4 5160 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::5 5160 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::6 5159 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::7 5160 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::8 5159 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::9 5159 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::10 5160 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::11 5159 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::13 5159 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::14 5161 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::15 5160 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::16 5158 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::17 5161 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 74432 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 5818.973345 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 397.615709 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 13075.139994 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::64-71 25664 34.48% 34.48% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-135 15269 20.51% 54.99% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::192-199 3288 4.42% 59.41% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-263 2378 3.19% 62.61% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::320-327 1591 2.14% 64.74% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::384-391 1326 1.78% 66.53% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::448-455 1035 1.39% 67.92% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::512-519 1141 1.53% 69.45% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::576-583 724 0.97% 70.42% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::640-647 588 0.79% 71.21% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::704-711 595 0.80% 72.01% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::768-775 643 0.86% 72.87% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::832-839 322 0.43% 73.31% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::896-903 287 0.39% 73.69% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::960-967 216 0.29% 73.98% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::1024-1031 358 0.48% 74.46% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1088-1095 180 0.24% 74.71% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::1152-1159 137 0.18% 74.89% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.08% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1280-1287 152 0.20% 75.28% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.45% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::1408-1415 2272 3.05% 78.50% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1472-1479 131 0.18% 78.68% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::1536-1543 156 0.21% 78.89% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::1600-1607 73 0.10% 78.98% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::1664-1671 70 0.09% 79.08% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.14% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::1792-1799 130 0.17% 79.32% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::1856-1863 52 0.07% 79.39% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::1920-1927 26 0.03% 79.42% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::1984-1991 15 0.02% 79.44% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::2048-2055 134 0.18% 79.62% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::2112-2119 21 0.03% 79.65% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.68% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::2240-2247 27 0.04% 79.71% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::2304-2311 25 0.03% 79.75% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::2368-2375 14 0.02% 79.76% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::2432-2439 24 0.03% 79.80% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::2496-2503 22 0.03% 79.83% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.95% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::2624-2631 23 0.03% 79.98% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::2688-2695 8 0.01% 79.99% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::2752-2759 25 0.03% 80.02% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::2816-2823 35 0.05% 80.07% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::2880-2887 11 0.01% 80.08% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::2944-2951 26 0.03% 80.12% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::3008-3015 8 0.01% 80.13% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::3072-3079 105 0.14% 80.27% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.30% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::3200-3207 6 0.01% 80.31% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::3264-3271 7 0.01% 80.32% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::3328-3335 41 0.06% 80.37% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::3392-3399 7 0.01% 80.38% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.39% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::3520-3527 26 0.03% 80.43% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::3584-3591 85 0.11% 80.54% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::3648-3655 5 0.01% 80.55% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::3712-3719 20 0.03% 80.58% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::3776-3783 29 0.04% 80.61% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::3840-3847 86 0.12% 80.73% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::3904-3911 19 0.03% 80.76% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.76% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.77% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::4096-4103 202 0.27% 81.04% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::4160-4167 3 0.00% 81.04% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::4224-4231 6 0.01% 81.05% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.07% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::4352-4359 18 0.02% 81.10% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.10% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.12% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::4544-4551 2 0.00% 81.13% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::4608-4615 20 0.03% 81.15% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::4672-4679 17 0.02% 81.18% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.18% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::4800-4807 2 0.00% 81.18% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::4864-4871 92 0.12% 81.31% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.32% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::5056-5063 17 0.02% 81.34% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::5120-5127 96 0.13% 81.47% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.48% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.50% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::5376-5383 30 0.04% 81.54% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::5440-5447 172 0.23% 81.77% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.85% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::5632-5639 8 0.01% 81.86% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.86% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::5888-5895 88 0.12% 81.98% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::6016-6023 2 0.00% 81.98% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::6144-6151 223 0.30% 82.28% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.29% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::6400-6407 29 0.04% 82.32% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.33% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.33% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::6656-6663 24 0.03% 82.36% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::6912-6919 22 0.03% 82.39% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.39% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.39% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::7168-7175 158 0.21% 82.61% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::7360-7367 1 0.00% 82.61% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::7424-7431 33 0.04% 82.65% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.65% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::7680-7687 14 0.02% 82.67% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.67% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.67% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::7936-7943 10 0.01% 82.69% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::8192-8199 260 0.35% 83.04% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.04% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::8448-8455 7 0.01% 83.05% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::8704-8711 14 0.02% 83.07% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::8960-8967 33 0.04% 83.11% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.11% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.11% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::9216-9223 155 0.21% 83.32% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::9280-9287 2 0.00% 83.32% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::9472-9479 19 0.03% 83.35% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.35% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::9728-9735 22 0.03% 83.38% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::9984-9991 27 0.04% 83.42% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::10240-10247 223 0.30% 83.72% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.72% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::10496-10503 89 0.12% 83.84% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::10752-10759 6 0.01% 83.85% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::11008-11015 22 0.03% 83.88% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::11072-11079 1 0.00% 83.88% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::11136-11143 2 0.00% 83.88% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::11200-11207 1 0.00% 83.88% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::11264-11271 98 0.13% 84.01% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::11520-11527 76 0.10% 84.11% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::11648-11655 1 0.00% 84.12% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::11776-11783 19 0.03% 84.14% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.14% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::12032-12039 15 0.02% 84.16% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::12288-12295 169 0.23% 84.39% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.39% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.39% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.39% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::12544-12551 85 0.11% 84.51% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::12800-12807 80 0.11% 84.62% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.64% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.64% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::13312-13319 90 0.12% 84.76% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::13504-13511 1 0.00% 84.77% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::13568-13575 22 0.03% 84.80% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.91% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::14016-14023 1 0.00% 84.91% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::14080-14087 7 0.01% 84.92% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::14208-14215 2 0.00% 84.92% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::14272-14279 1 0.00% 84.92% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::14336-14343 95 0.13% 85.05% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::14592-14599 100 0.13% 85.18% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::14656-14663 2 0.00% 85.19% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::14848-14855 74 0.10% 85.28% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.29% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::15104-15111 18 0.02% 85.31% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::15360-15367 105 0.14% 85.45% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.45% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::15616-15623 76 0.10% 85.55% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::15872-15879 18 0.02% 85.58% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.58% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.58% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::16128-16135 76 0.10% 85.68% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.68% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::16384-16391 161 0.22% 85.90% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::16512-16519 2 0.00% 85.90% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::16640-16647 77 0.10% 86.01% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::16768-16775 1 0.00% 86.01% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::16896-16903 23 0.03% 86.04% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.04% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::17152-17159 72 0.10% 86.14% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::17408-17415 107 0.14% 86.28% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.28% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::17664-17671 15 0.02% 86.30% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::17920-17927 76 0.10% 86.41% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::18112-18119 1 0.00% 86.41% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::18176-18183 97 0.13% 86.54% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::18432-18439 102 0.14% 86.68% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::18624-18631 2 0.00% 86.68% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::18688-18695 4 0.01% 86.68% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::18752-18759 1 0.00% 86.68% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::18944-18951 78 0.10% 86.79% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.82% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.83% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::19392-19399 1 0.00% 86.83% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::19456-19463 82 0.11% 86.94% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::19712-19719 16 0.02% 86.96% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::19968-19975 83 0.11% 87.07% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::20224-20231 81 0.11% 87.18% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.18% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::20480-20487 176 0.24% 87.42% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::20608-20615 2 0.00% 87.42% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::20736-20743 17 0.02% 87.44% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.46% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.46% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::21248-21255 73 0.10% 87.56% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.56% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::21504-21511 87 0.12% 87.68% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.68% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::21760-21767 23 0.03% 87.71% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::22016-22023 10 0.01% 87.73% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.85% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.85% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::22528-22535 223 0.30% 88.15% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::22784-22791 27 0.04% 88.18% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.18% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::23040-23047 22 0.03% 88.21% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::23296-23303 25 0.03% 88.25% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::23424-23431 2 0.00% 88.25% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.44% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.45% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::23808-23815 30 0.04% 88.49% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::24064-24071 16 0.02% 88.51% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.51% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::24320-24327 8 0.01% 88.52% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::24576-24583 269 0.36% 88.88% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::24704-24711 1 0.00% 88.88% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::24832-24839 5 0.01% 88.89% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.91% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::25344-25351 32 0.04% 88.95% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.96% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::25536-25543 1 0.00% 88.96% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::25600-25607 144 0.19% 89.15% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.15% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.15% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::25856-25863 22 0.03% 89.18% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::25920-25927 1 0.00% 89.18% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::26112-26119 20 0.03% 89.21% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.21% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::26368-26375 26 0.03% 89.25% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.25% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.25% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::26624-26631 224 0.30% 89.55% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::26880-26887 85 0.11% 89.67% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::26944-26951 1 0.00% 89.67% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::27136-27143 6 0.01% 89.68% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::27392-27399 26 0.03% 89.71% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::27456-27463 2 0.00% 89.71% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::27648-27655 89 0.12% 89.83% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::27712-27719 1 0.00% 89.83% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::27904-27911 73 0.10% 89.93% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::28160-28167 18 0.02% 89.96% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::28416-28423 16 0.02% 89.98% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.98% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::28544-28551 1 0.00% 89.98% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::28672-28679 161 0.22% 90.20% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.20% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::28864-28871 2 0.00% 90.20% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::28928-28935 84 0.11% 90.31% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::29184-29191 80 0.11% 90.42% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::29440-29447 15 0.02% 90.44% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::29696-29703 89 0.12% 90.56% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::29952-29959 19 0.03% 90.59% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::30208-30215 82 0.11% 90.70% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::30272-30279 2 0.00% 90.70% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::30464-30471 5 0.01% 90.71% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::30528-30535 1 0.00% 90.71% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.71% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.71% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::30720-30727 93 0.12% 90.83% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::30784-30791 1 0.00% 90.84% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::30976-30983 97 0.13% 90.97% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.97% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::31232-31239 74 0.10% 91.07% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::31296-31303 1 0.00% 91.07% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::31488-31495 16 0.02% 91.09% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::31744-31751 105 0.14% 91.23% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.23% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::31936-31943 2 0.00% 91.23% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::32000-32007 73 0.10% 91.33% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::32256-32263 21 0.03% 91.36% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::32512-32519 75 0.10% 91.46% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.46% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.46% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::32768-32775 157 0.21% 91.68% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::32832-32839 1 0.00% 91.68% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::32896-32903 1 0.00% 91.68% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::33024-33031 81 0.11% 91.79% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::33280-33287 29 0.04% 91.83% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::33344-33351 2 0.00% 91.83% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::33536-33543 73 0.10% 91.93% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::33664-33671 1 0.00% 91.93% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::33792-33799 105 0.14% 92.07% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.07% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::34048-34055 16 0.02% 92.09% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::34304-34311 71 0.10% 92.19% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.19% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::34560-34567 97 0.13% 92.32% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::34752-34759 1 0.00% 92.32% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::34816-34823 90 0.12% 92.44% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::34944-34951 1 0.00% 92.44% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::35008-35015 1 0.00% 92.44% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::35072-35079 3 0.00% 92.45% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::35328-35335 81 0.11% 92.56% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::35584-35591 18 0.02% 92.58% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::35840-35847 87 0.12% 92.70% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::36096-36103 13 0.02% 92.72% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.72% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::36352-36359 79 0.11% 92.82% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.94% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::36672-36679 2 0.00% 92.94% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::36864-36871 156 0.21% 93.15% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::36992-36999 1 0.00% 93.15% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::37056-37063 1 0.00% 93.15% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::37120-37127 14 0.02% 93.17% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::37376-37383 16 0.02% 93.19% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::37632-37639 75 0.10% 93.29% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::37888-37895 86 0.12% 93.41% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.41% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::38144-38151 24 0.03% 93.44% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::38400-38407 6 0.01% 93.45% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.45% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.45% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::38656-38663 85 0.11% 93.57% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::38912-38919 221 0.30% 93.86% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.86% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::39168-39175 25 0.03% 93.90% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::39360-39367 3 0.00% 93.90% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::39424-39431 18 0.02% 93.93% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::39552-39559 2 0.00% 93.93% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::39616-39623 1 0.00% 93.93% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.96% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::39936-39943 142 0.19% 94.15% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::40000-40007 1 0.00% 94.15% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::40192-40199 32 0.04% 94.19% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.21% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::40704-40711 5 0.01% 94.22% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::40960-40967 265 0.36% 94.57% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::41216-41223 6 0.01% 94.58% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::41408-41415 1 0.00% 94.58% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::41472-41479 13 0.02% 94.60% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::41600-41607 2 0.00% 94.60% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::41728-41735 31 0.04% 94.64% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.65% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.84% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::42240-42247 24 0.03% 94.87% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::42496-42503 20 0.03% 94.90% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::42752-42759 27 0.04% 94.94% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::43008-43015 221 0.30% 95.23% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::43264-43271 85 0.11% 95.35% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.36% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.36% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::43776-43783 22 0.03% 95.39% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::43840-43847 1 0.00% 95.39% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::44032-44039 84 0.11% 95.51% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.51% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::44288-44295 73 0.10% 95.61% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.61% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::44544-44551 13 0.02% 95.63% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.65% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.65% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::45056-45063 166 0.22% 95.87% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.87% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::45312-45319 79 0.11% 95.98% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::45376-45383 1 0.00% 95.98% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::45568-45575 82 0.11% 96.09% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::45824-45831 15 0.02% 96.11% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::46080-46087 87 0.12% 96.23% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.23% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::46336-46343 22 0.03% 96.26% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.37% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::46848-46855 6 0.01% 96.38% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.38% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::46976-46983 1 0.00% 96.38% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::47104-47111 93 0.12% 96.50% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::47232-47239 1 0.00% 96.51% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::47360-47367 101 0.14% 96.64% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.64% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::47616-47623 79 0.11% 96.75% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::47872-47879 16 0.02% 96.77% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.77% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::48128-48135 127 0.17% 96.94% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.94% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.95% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::48384-48391 87 0.12% 97.06% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::48640-48647 17 0.02% 97.09% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::48704-48711 1 0.00% 97.09% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.10% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::48896-48903 76 0.10% 97.20% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::48960-48967 12 0.02% 97.22% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.22% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::49088-49095 5 0.01% 97.23% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::49152-49159 2061 2.77% 100.00% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::total 74432 # Bytes accessed per row activation 588system.physmem.totQLat 159552537250 # Total ticks spent queuing 589system.physmem.totMemAccLat 202473692250 # Total ticks spent from burst creation until serviced by the DRAM 590system.physmem.totBusLat 33269920000 # Total ticks spent in databus transfers 591system.physmem.totBankLat 9651235000 # Total ticks spent accessing banks 592system.physmem.avgQLat 23978.50 # Average queueing delay per DRAM burst 593system.physmem.avgBankLat 1450.44 # Average bank access latency per DRAM burst 594system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 595system.physmem.avgMemAccLat 30428.94 # Average memory access latency per DRAM burst 596system.physmem.avgRdBW 356.02 # Average DRAM read bandwidth in MiByte/s 597system.physmem.avgWrBW 6.07 # Average achieved write bandwidth in MiByte/s 598system.physmem.avgRdBWSys 51.95 # Average system read bandwidth in MiByte/s 599system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s 600system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 601system.physmem.busUtil 2.83 # Data bus utilization in percentage 602system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads 603system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 604system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing 605system.physmem.avgWrQLen 12.50 # Average write queue length when enqueuing 606system.physmem.readRowHits 6598277 # Number of row buffer hits during reads 607system.physmem.writeRowHits 94784 # Number of row buffer hits during writes 608system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads 609system.physmem.writeRowHitRate 83.49 # Row buffer hit rate for writes 610system.physmem.avgGap 160007.15 # Average gap between requests 611system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined 612system.physmem.prechargeAllPercent 4.90 # Percentage of time for which DRAM has all the banks in precharge state	34system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu0.inst 393164 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 4714556 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory 42system.physmem.bytes_read::cpu1.data 4804536 # Number of bytes read from this memory 43system.physmem.bytes_read::total 62141956 # Number of bytes read from this memory 44system.physmem.bytes_inst_read::cpu0.inst 393164 # Number of instructions bytes read from this memory 45system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory 46system.physmem.bytes_inst_read::total 717840 # Number of instructions bytes read from this memory 47system.physmem.bytes_written::writebacks 4110528 # Number of bytes written to this memory 48system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 49system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 50system.physmem.bytes_written::total 7137872 # Number of bytes written to this memory 51system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu0.inst 12371 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu0.data 73739 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory 59system.physmem.num_reads::cpu1.data 75099 # Number of read requests responded to by this memory 60system.physmem.num_reads::total 6654445 # Number of read requests responded to by this memory 61system.physmem.num_writes::writebacks 64227 # Number of write requests responded to by this memory 62system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 63system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 64system.physmem.num_writes::total 821063 # Number of write requests responded to by this memory 65system.physmem.bw_read::realview.clcd 43393369 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu0.inst 328694 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu0.data 3941478 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu1.inst 271437 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::cpu1.data 4016703 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_read::total 51952109 # Total read bandwidth from this memory (bytes/s) 75system.physmem.bw_inst_read::cpu0.inst 328694 # Instruction read bandwidth from this memory (bytes/s) 76system.physmem.bw_inst_read::cpu1.inst 271437 # Instruction read bandwidth from this memory (bytes/s) 77system.physmem.bw_inst_read::total 600131 # Instruction read bandwidth from this memory (bytes/s) 78system.physmem.bw_write::writebacks 3436496 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_write::cpu0.data 14212 # Write bandwidth from this memory (bytes/s) 80system.physmem.bw_write::cpu1.data 2516717 # Write bandwidth from this memory (bytes/s) 81system.physmem.bw_write::total 5967426 # Write bandwidth from this memory (bytes/s) 82system.physmem.bw_total::writebacks 3436496 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::realview.clcd 43393369 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::cpu0.inst 328694 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu0.data 3955690 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::cpu1.inst 271437 # Total bandwidth to/from this memory (bytes/s) 91system.physmem.bw_total::cpu1.data 6533420 # Total bandwidth to/from this memory (bytes/s) 92system.physmem.bw_total::total 57919534 # Total bandwidth to/from this memory (bytes/s) 93system.physmem.readReqs 6654445 # Number of read requests accepted 94system.physmem.writeReqs 821063 # Number of write requests accepted 95system.physmem.readBursts 6654445 # Number of DRAM read bursts, including those serviced by the write queue 96system.physmem.writeBursts 821063 # Number of DRAM write bursts, including those merged in the write queue 97system.physmem.bytesReadDRAM 425854976 # Total number of bytes read from DRAM 98system.physmem.bytesReadWrQ 29504 # Total number of bytes read from write queue 99system.physmem.bytesWritten 7264576 # Total number of bytes written to DRAM 100system.physmem.bytesReadSys 62141956 # Total read bytes from the system interface side 101system.physmem.bytesWrittenSys 7137872 # Total written bytes from the system interface side 102system.physmem.servicedByWrQ 461 # Number of DRAM read bursts serviced by the write queue 103system.physmem.mergedWrBursts 707541 # Number of DRAM write bursts merged with an existing one 104system.physmem.neitherReadNorWriteReqs 12043 # Number of requests that are neither read nor write 105system.physmem.perBankRdBursts::0 415328 # Per bank write bursts 106system.physmem.perBankRdBursts::1 415204 # Per bank write bursts 107system.physmem.perBankRdBursts::2 415403 # Per bank write bursts 108system.physmem.perBankRdBursts::3 415627 # Per bank write bursts 109system.physmem.perBankRdBursts::4 422407 # Per bank write bursts 110system.physmem.perBankRdBursts::5 415617 # Per bank write bursts 111system.physmem.perBankRdBursts::6 415785 # Per bank write bursts 112system.physmem.perBankRdBursts::7 415500 # Per bank write bursts 113system.physmem.perBankRdBursts::8 416027 # Per bank write bursts 114system.physmem.perBankRdBursts::9 415632 # Per bank write bursts 115system.physmem.perBankRdBursts::10 415316 # Per bank write bursts 116system.physmem.perBankRdBursts::11 414840 # Per bank write bursts 117system.physmem.perBankRdBursts::12 415044 # Per bank write bursts 118system.physmem.perBankRdBursts::13 415557 # Per bank write bursts 119system.physmem.perBankRdBursts::14 415554 # Per bank write bursts 120system.physmem.perBankRdBursts::15 415143 # Per bank write bursts 121system.physmem.perBankWrBursts::0 6946 # Per bank write bursts 122system.physmem.perBankWrBursts::1 6844 # Per bank write bursts 123system.physmem.perBankWrBursts::2 7080 # Per bank write bursts 124system.physmem.perBankWrBursts::3 7140 # Per bank write bursts 125system.physmem.perBankWrBursts::4 7438 # Per bank write bursts 126system.physmem.perBankWrBursts::5 7223 # Per bank write bursts 127system.physmem.perBankWrBursts::6 7431 # Per bank write bursts 128system.physmem.perBankWrBursts::7 7190 # Per bank write bursts 129system.physmem.perBankWrBursts::8 7575 # Per bank write bursts 130system.physmem.perBankWrBursts::9 7264 # Per bank write bursts 131system.physmem.perBankWrBursts::10 7139 # Per bank write bursts 132system.physmem.perBankWrBursts::11 6649 # Per bank write bursts 133system.physmem.perBankWrBursts::12 6729 # Per bank write bursts 134system.physmem.perBankWrBursts::13 7011 # Per bank write bursts 135system.physmem.perBankWrBursts::14 7090 # Per bank write bursts 136system.physmem.perBankWrBursts::15 6760 # Per bank write bursts 137system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 138system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 139system.physmem.totGap 1196134740000 # Total gap between requests 140system.physmem.readPktSize::0 0 # Read request sizes (log2) 141system.physmem.readPktSize::1 0 # Read request sizes (log2) 142system.physmem.readPktSize::2 6849 # Read request sizes (log2) 143system.physmem.readPktSize::3 6488064 # Read request sizes (log2) 144system.physmem.readPktSize::4 0 # Read request sizes (log2) 145system.physmem.readPktSize::5 0 # Read request sizes (log2) 146system.physmem.readPktSize::6 159532 # Read request sizes (log2) 147system.physmem.writePktSize::0 0 # Write request sizes (log2) 148system.physmem.writePktSize::1 0 # Write request sizes (log2) 149system.physmem.writePktSize::2 756836 # Write request sizes (log2) 150system.physmem.writePktSize::3 0 # Write request sizes (log2) 151system.physmem.writePktSize::4 0 # Write request sizes (log2) 152system.physmem.writePktSize::5 0 # Write request sizes (log2) 153system.physmem.writePktSize::6 64227 # Write request sizes (log2) 154system.physmem.rdQLenPdf::0 627903 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::1 474579 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::2 475456 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::3 1579907 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::4 1133019 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::5 1127067 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::6 1123495 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::7 24904 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::8 24218 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::9 9367 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::10 9281 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::11 9166 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::12 8936 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::13 8867 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::14 8833 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::15 8794 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::16 186 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 183system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 186system.physmem.wrQLenPdf::0 5159 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::1 5163 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::2 5160 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::3 5160 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::4 5160 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::5 5160 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::6 5159 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::7 5160 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::8 5159 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::9 5159 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::10 5160 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::11 5159 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::12 5161 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::13 5159 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::14 5161 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::15 5160 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::16 5158 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::17 5161 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::18 5162 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::19 5159 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::20 5163 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 218system.physmem.bytesPerActivate::samples 74432 # Bytes accessed per row activation 219system.physmem.bytesPerActivate::mean 5818.973345 # Bytes accessed per row activation 220system.physmem.bytesPerActivate::gmean 397.615709 # Bytes accessed per row activation 221system.physmem.bytesPerActivate::stdev 13075.139994 # Bytes accessed per row activation 222system.physmem.bytesPerActivate::64-71 25664 34.48% 34.48% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::128-135 15269 20.51% 54.99% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::192-199 3288 4.42% 59.41% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::256-263 2378 3.19% 62.61% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::320-327 1591 2.14% 64.74% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::384-391 1326 1.78% 66.53% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::448-455 1035 1.39% 67.92% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::512-519 1141 1.53% 69.45% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::576-583 724 0.97% 70.42% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::640-647 588 0.79% 71.21% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::704-711 595 0.80% 72.01% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::768-775 643 0.86% 72.87% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::832-839 322 0.43% 73.31% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::896-903 287 0.39% 73.69% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::960-967 216 0.29% 73.98% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::1024-1031 358 0.48% 74.46% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::1088-1095 180 0.24% 74.71% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::1152-1159 137 0.18% 74.89% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::1216-1223 142 0.19% 75.08% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::1280-1287 152 0.20% 75.28% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::1344-1351 122 0.16% 75.45% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::1408-1415 2272 3.05% 78.50% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::1472-1479 131 0.18% 78.68% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::1536-1543 156 0.21% 78.89% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::1600-1607 73 0.10% 78.98% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::1664-1671 70 0.09% 79.08% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1728-1735 46 0.06% 79.14% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::1792-1799 130 0.17% 79.32% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::1856-1863 52 0.07% 79.39% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::1920-1927 26 0.03% 79.42% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1984-1991 15 0.02% 79.44% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::2048-2055 134 0.18% 79.62% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::2112-2119 21 0.03% 79.65% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::2176-2183 20 0.03% 79.68% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::2240-2247 27 0.04% 79.71% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::2304-2311 25 0.03% 79.75% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::2368-2375 14 0.02% 79.76% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::2432-2439 24 0.03% 79.80% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::2496-2503 22 0.03% 79.83% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::2560-2567 90 0.12% 79.95% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::2624-2631 23 0.03% 79.98% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::2688-2695 8 0.01% 79.99% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::2752-2759 25 0.03% 80.02% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::2816-2823 35 0.05% 80.07% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::2880-2887 11 0.01% 80.08% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::2944-2951 26 0.03% 80.12% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::3008-3015 8 0.01% 80.13% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::3072-3079 105 0.14% 80.27% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::3136-3143 21 0.03% 80.30% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::3200-3207 6 0.01% 80.31% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::3264-3271 7 0.01% 80.32% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::3328-3335 41 0.06% 80.37% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::3392-3399 7 0.01% 80.38% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::3456-3463 9 0.01% 80.39% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::3520-3527 26 0.03% 80.43% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::3584-3591 85 0.11% 80.54% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::3648-3655 5 0.01% 80.55% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::3712-3719 20 0.03% 80.58% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::3776-3783 29 0.04% 80.61% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::3840-3847 86 0.12% 80.73% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::3904-3911 19 0.03% 80.76% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::3968-3975 4 0.01% 80.76% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.77% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::4096-4103 202 0.27% 81.04% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::4160-4167 3 0.00% 81.04% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::4224-4231 6 0.01% 81.05% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::4288-4295 17 0.02% 81.07% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::4352-4359 18 0.02% 81.10% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::4416-4423 2 0.00% 81.10% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::4480-4487 18 0.02% 81.12% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::4544-4551 2 0.00% 81.13% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::4608-4615 20 0.03% 81.15% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::4672-4679 17 0.02% 81.18% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.18% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::4800-4807 2 0.00% 81.18% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::4864-4871 92 0.12% 81.31% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::4928-4935 4 0.01% 81.31% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.32% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::5056-5063 17 0.02% 81.34% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::5120-5127 96 0.13% 81.47% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::5184-5191 3 0.00% 81.48% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::5248-5255 19 0.03% 81.50% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::5376-5383 30 0.04% 81.54% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::5440-5447 172 0.23% 81.77% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::5504-5511 59 0.08% 81.85% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::5632-5639 8 0.01% 81.86% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::5696-5703 1 0.00% 81.86% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::5888-5895 88 0.12% 81.98% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::6016-6023 2 0.00% 81.98% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::6144-6151 223 0.30% 82.28% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::6336-6343 1 0.00% 82.29% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::6400-6407 29 0.04% 82.32% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::6528-6535 2 0.00% 82.33% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::6592-6599 1 0.00% 82.33% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::6656-6663 24 0.03% 82.36% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::6912-6919 22 0.03% 82.39% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::7040-7047 1 0.00% 82.39% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::7104-7111 1 0.00% 82.39% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::7168-7175 158 0.21% 82.61% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::7360-7367 1 0.00% 82.61% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::7424-7431 33 0.04% 82.65% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::7616-7623 1 0.00% 82.65% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::7680-7687 14 0.02% 82.67% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::7744-7751 1 0.00% 82.67% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::7808-7815 1 0.00% 82.67% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::7936-7943 10 0.01% 82.69% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::8192-8199 260 0.35% 83.04% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::8384-8391 1 0.00% 83.04% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::8448-8455 7 0.01% 83.05% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::8704-8711 14 0.02% 83.07% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::8960-8967 33 0.04% 83.11% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::9088-9095 1 0.00% 83.11% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::9152-9159 1 0.00% 83.11% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::9216-9223 155 0.21% 83.32% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::9280-9287 2 0.00% 83.32% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::9472-9479 19 0.03% 83.35% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::9664-9671 1 0.00% 83.35% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::9728-9735 22 0.03% 83.38% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::9984-9991 27 0.04% 83.42% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::10240-10247 223 0.30% 83.72% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.72% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::10496-10503 89 0.12% 83.84% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::10752-10759 6 0.01% 83.85% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::11008-11015 22 0.03% 83.88% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::11072-11079 1 0.00% 83.88% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::11136-11143 2 0.00% 83.88% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::11200-11207 1 0.00% 83.88% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::11264-11271 98 0.13% 84.01% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::11520-11527 76 0.10% 84.11% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::11648-11655 1 0.00% 84.12% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::11776-11783 19 0.03% 84.14% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.14% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::12032-12039 15 0.02% 84.16% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::12288-12295 169 0.23% 84.39% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::12352-12359 1 0.00% 84.39% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.39% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::12480-12487 1 0.00% 84.39% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::12544-12551 85 0.11% 84.51% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::12800-12807 80 0.11% 84.62% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.64% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.64% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::13312-13319 90 0.12% 84.76% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::13504-13511 1 0.00% 84.77% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::13568-13575 22 0.03% 84.80% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::13824-13831 82 0.11% 84.91% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::14016-14023 1 0.00% 84.91% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::14080-14087 7 0.01% 84.92% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::14208-14215 2 0.00% 84.92% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::14272-14279 1 0.00% 84.92% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::14336-14343 95 0.13% 85.05% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::14592-14599 100 0.13% 85.18% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::14656-14663 2 0.00% 85.19% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::14848-14855 74 0.10% 85.28% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::15040-15047 1 0.00% 85.29% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::15104-15111 18 0.02% 85.31% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::15360-15367 105 0.14% 85.45% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::15488-15495 1 0.00% 85.45% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::15616-15623 76 0.10% 85.55% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::15872-15879 18 0.02% 85.58% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::16000-16007 1 0.00% 85.58% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::16064-16071 1 0.00% 85.58% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::16128-16135 76 0.10% 85.68% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::16256-16263 1 0.00% 85.68% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::16384-16391 161 0.22% 85.90% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::16512-16519 2 0.00% 85.90% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::16640-16647 77 0.10% 86.01% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::16768-16775 1 0.00% 86.01% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::16896-16903 23 0.03% 86.04% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::17024-17031 2 0.00% 86.04% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::17152-17159 72 0.10% 86.14% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::17408-17415 107 0.14% 86.28% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.28% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::17664-17671 15 0.02% 86.30% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::17920-17927 76 0.10% 86.41% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::18112-18119 1 0.00% 86.41% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::18176-18183 97 0.13% 86.54% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::18432-18439 102 0.14% 86.68% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::18624-18631 2 0.00% 86.68% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::18688-18695 4 0.01% 86.68% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::18752-18759 1 0.00% 86.68% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::18944-18951 78 0.10% 86.79% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::19200-19207 26 0.03% 86.82% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::19328-19335 2 0.00% 86.83% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::19392-19399 1 0.00% 86.83% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::19456-19463 82 0.11% 86.94% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::19712-19719 16 0.02% 86.96% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::19968-19975 83 0.11% 87.07% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::20224-20231 81 0.11% 87.18% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::20352-20359 2 0.00% 87.18% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::20480-20487 176 0.24% 87.42% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::20608-20615 2 0.00% 87.42% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::20736-20743 17 0.02% 87.44% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::20992-20999 12 0.02% 87.46% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::21056-21063 1 0.00% 87.46% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::21248-21255 73 0.10% 87.56% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::21376-21383 2 0.00% 87.56% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::21504-21511 87 0.12% 87.68% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::21696-21703 1 0.00% 87.68% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::21760-21767 23 0.03% 87.71% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::22016-22023 10 0.01% 87.73% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::22272-22279 89 0.12% 87.85% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::22400-22407 1 0.00% 87.85% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::22528-22535 223 0.30% 88.15% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::22784-22791 27 0.04% 88.18% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::22848-22855 1 0.00% 88.18% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::23040-23047 22 0.03% 88.21% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::23296-23303 25 0.03% 88.25% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::23424-23431 2 0.00% 88.25% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::23552-23559 145 0.19% 88.44% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::23680-23687 1 0.00% 88.45% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::23808-23815 30 0.04% 88.49% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::24064-24071 16 0.02% 88.51% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::24128-24135 1 0.00% 88.51% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::24320-24327 8 0.01% 88.52% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::24576-24583 269 0.36% 88.88% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::24704-24711 1 0.00% 88.88% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::24832-24839 5 0.01% 88.89% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::25088-25095 15 0.02% 88.91% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::25344-25351 32 0.04% 88.95% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::25472-25479 2 0.00% 88.96% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::25536-25543 1 0.00% 88.96% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::25600-25607 144 0.19% 89.15% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::25664-25671 1 0.00% 89.15% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::25792-25799 1 0.00% 89.15% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::25856-25863 22 0.03% 89.18% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::25920-25927 1 0.00% 89.18% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::26112-26119 20 0.03% 89.21% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::26176-26183 2 0.00% 89.21% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::26368-26375 26 0.03% 89.25% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::26432-26439 1 0.00% 89.25% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::26496-26503 1 0.00% 89.25% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::26624-26631 224 0.30% 89.55% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::26880-26887 85 0.11% 89.67% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::26944-26951 1 0.00% 89.67% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::27136-27143 6 0.01% 89.68% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::27392-27399 26 0.03% 89.71% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::27456-27463 2 0.00% 89.71% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::27648-27655 89 0.12% 89.83% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::27712-27719 1 0.00% 89.83% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::27904-27911 73 0.10% 89.93% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::28160-28167 18 0.02% 89.96% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::28416-28423 16 0.02% 89.98% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::28480-28487 1 0.00% 89.98% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::28544-28551 1 0.00% 89.98% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::28672-28679 161 0.22% 90.20% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::28800-28807 1 0.00% 90.20% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::28864-28871 2 0.00% 90.20% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::28928-28935 84 0.11% 90.31% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::29184-29191 80 0.11% 90.42% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::29440-29447 15 0.02% 90.44% # Bytes accessed per row activation 472system.physmem.bytesPerActivate::29696-29703 89 0.12% 90.56% # Bytes accessed per row activation 473system.physmem.bytesPerActivate::29952-29959 19 0.03% 90.59% # Bytes accessed per row activation 474system.physmem.bytesPerActivate::30208-30215 82 0.11% 90.70% # Bytes accessed per row activation 475system.physmem.bytesPerActivate::30272-30279 2 0.00% 90.70% # Bytes accessed per row activation 476system.physmem.bytesPerActivate::30464-30471 5 0.01% 90.71% # Bytes accessed per row activation 477system.physmem.bytesPerActivate::30528-30535 1 0.00% 90.71% # Bytes accessed per row activation 478system.physmem.bytesPerActivate::30592-30599 1 0.00% 90.71% # Bytes accessed per row activation 479system.physmem.bytesPerActivate::30656-30663 1 0.00% 90.71% # Bytes accessed per row activation 480system.physmem.bytesPerActivate::30720-30727 93 0.12% 90.83% # Bytes accessed per row activation 481system.physmem.bytesPerActivate::30784-30791 1 0.00% 90.84% # Bytes accessed per row activation 482system.physmem.bytesPerActivate::30976-30983 97 0.13% 90.97% # Bytes accessed per row activation 483system.physmem.bytesPerActivate::31104-31111 1 0.00% 90.97% # Bytes accessed per row activation 484system.physmem.bytesPerActivate::31232-31239 74 0.10% 91.07% # Bytes accessed per row activation 485system.physmem.bytesPerActivate::31296-31303 1 0.00% 91.07% # Bytes accessed per row activation 486system.physmem.bytesPerActivate::31488-31495 16 0.02% 91.09% # Bytes accessed per row activation 487system.physmem.bytesPerActivate::31744-31751 105 0.14% 91.23% # Bytes accessed per row activation 488system.physmem.bytesPerActivate::31872-31879 1 0.00% 91.23% # Bytes accessed per row activation 489system.physmem.bytesPerActivate::31936-31943 2 0.00% 91.23% # Bytes accessed per row activation 490system.physmem.bytesPerActivate::32000-32007 73 0.10% 91.33% # Bytes accessed per row activation 491system.physmem.bytesPerActivate::32256-32263 21 0.03% 91.36% # Bytes accessed per row activation 492system.physmem.bytesPerActivate::32512-32519 75 0.10% 91.46% # Bytes accessed per row activation 493system.physmem.bytesPerActivate::32640-32647 1 0.00% 91.46% # Bytes accessed per row activation 494system.physmem.bytesPerActivate::32704-32711 1 0.00% 91.46% # Bytes accessed per row activation 495system.physmem.bytesPerActivate::32768-32775 157 0.21% 91.68% # Bytes accessed per row activation 496system.physmem.bytesPerActivate::32832-32839 1 0.00% 91.68% # Bytes accessed per row activation 497system.physmem.bytesPerActivate::32896-32903 1 0.00% 91.68% # Bytes accessed per row activation 498system.physmem.bytesPerActivate::33024-33031 81 0.11% 91.79% # Bytes accessed per row activation 499system.physmem.bytesPerActivate::33280-33287 29 0.04% 91.83% # Bytes accessed per row activation 500system.physmem.bytesPerActivate::33344-33351 2 0.00% 91.83% # Bytes accessed per row activation 501system.physmem.bytesPerActivate::33536-33543 73 0.10% 91.93% # Bytes accessed per row activation 502system.physmem.bytesPerActivate::33664-33671 1 0.00% 91.93% # Bytes accessed per row activation 503system.physmem.bytesPerActivate::33792-33799 105 0.14% 92.07% # Bytes accessed per row activation 504system.physmem.bytesPerActivate::33920-33927 1 0.00% 92.07% # Bytes accessed per row activation 505system.physmem.bytesPerActivate::34048-34055 16 0.02% 92.09% # Bytes accessed per row activation 506system.physmem.bytesPerActivate::34304-34311 71 0.10% 92.19% # Bytes accessed per row activation 507system.physmem.bytesPerActivate::34432-34439 1 0.00% 92.19% # Bytes accessed per row activation 508system.physmem.bytesPerActivate::34560-34567 97 0.13% 92.32% # Bytes accessed per row activation 509system.physmem.bytesPerActivate::34752-34759 1 0.00% 92.32% # Bytes accessed per row activation 510system.physmem.bytesPerActivate::34816-34823 90 0.12% 92.44% # Bytes accessed per row activation 511system.physmem.bytesPerActivate::34944-34951 1 0.00% 92.44% # Bytes accessed per row activation 512system.physmem.bytesPerActivate::35008-35015 1 0.00% 92.44% # Bytes accessed per row activation 513system.physmem.bytesPerActivate::35072-35079 3 0.00% 92.45% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::35328-35335 81 0.11% 92.56% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::35584-35591 18 0.02% 92.58% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::35840-35847 87 0.12% 92.70% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::36096-36103 13 0.02% 92.72% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::36224-36231 1 0.00% 92.72% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::36352-36359 79 0.11% 92.82% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::36608-36615 84 0.11% 92.94% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::36672-36679 2 0.00% 92.94% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::36864-36871 156 0.21% 93.15% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::36992-36999 1 0.00% 93.15% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::37056-37063 1 0.00% 93.15% # Bytes accessed per row activation 525system.physmem.bytesPerActivate::37120-37127 14 0.02% 93.17% # Bytes accessed per row activation 526system.physmem.bytesPerActivate::37376-37383 16 0.02% 93.19% # Bytes accessed per row activation 527system.physmem.bytesPerActivate::37632-37639 75 0.10% 93.29% # Bytes accessed per row activation 528system.physmem.bytesPerActivate::37888-37895 86 0.12% 93.41% # Bytes accessed per row activation 529system.physmem.bytesPerActivate::38080-38087 1 0.00% 93.41% # Bytes accessed per row activation 530system.physmem.bytesPerActivate::38144-38151 24 0.03% 93.44% # Bytes accessed per row activation 531system.physmem.bytesPerActivate::38400-38407 6 0.01% 93.45% # Bytes accessed per row activation 532system.physmem.bytesPerActivate::38528-38535 1 0.00% 93.45% # Bytes accessed per row activation 533system.physmem.bytesPerActivate::38592-38599 1 0.00% 93.45% # Bytes accessed per row activation 534system.physmem.bytesPerActivate::38656-38663 85 0.11% 93.57% # Bytes accessed per row activation 535system.physmem.bytesPerActivate::38912-38919 221 0.30% 93.86% # Bytes accessed per row activation 536system.physmem.bytesPerActivate::39104-39111 1 0.00% 93.86% # Bytes accessed per row activation 537system.physmem.bytesPerActivate::39168-39175 25 0.03% 93.90% # Bytes accessed per row activation 538system.physmem.bytesPerActivate::39360-39367 3 0.00% 93.90% # Bytes accessed per row activation 539system.physmem.bytesPerActivate::39424-39431 18 0.02% 93.93% # Bytes accessed per row activation 540system.physmem.bytesPerActivate::39552-39559 2 0.00% 93.93% # Bytes accessed per row activation 541system.physmem.bytesPerActivate::39616-39623 1 0.00% 93.93% # Bytes accessed per row activation 542system.physmem.bytesPerActivate::39680-39687 20 0.03% 93.96% # Bytes accessed per row activation 543system.physmem.bytesPerActivate::39936-39943 142 0.19% 94.15% # Bytes accessed per row activation 544system.physmem.bytesPerActivate::40000-40007 1 0.00% 94.15% # Bytes accessed per row activation 545system.physmem.bytesPerActivate::40192-40199 32 0.04% 94.19% # Bytes accessed per row activation 546system.physmem.bytesPerActivate::40448-40455 14 0.02% 94.21% # Bytes accessed per row activation 547system.physmem.bytesPerActivate::40704-40711 5 0.01% 94.22% # Bytes accessed per row activation 548system.physmem.bytesPerActivate::40960-40967 265 0.36% 94.57% # Bytes accessed per row activation 549system.physmem.bytesPerActivate::41216-41223 6 0.01% 94.58% # Bytes accessed per row activation 550system.physmem.bytesPerActivate::41408-41415 1 0.00% 94.58% # Bytes accessed per row activation 551system.physmem.bytesPerActivate::41472-41479 13 0.02% 94.60% # Bytes accessed per row activation 552system.physmem.bytesPerActivate::41600-41607 2 0.00% 94.60% # Bytes accessed per row activation 553system.physmem.bytesPerActivate::41728-41735 31 0.04% 94.64% # Bytes accessed per row activation 554system.physmem.bytesPerActivate::41856-41863 1 0.00% 94.65% # Bytes accessed per row activation 555system.physmem.bytesPerActivate::41984-41991 146 0.20% 94.84% # Bytes accessed per row activation 556system.physmem.bytesPerActivate::42240-42247 24 0.03% 94.87% # Bytes accessed per row activation 557system.physmem.bytesPerActivate::42496-42503 20 0.03% 94.90% # Bytes accessed per row activation 558system.physmem.bytesPerActivate::42752-42759 27 0.04% 94.94% # Bytes accessed per row activation 559system.physmem.bytesPerActivate::43008-43015 221 0.30% 95.23% # Bytes accessed per row activation 560system.physmem.bytesPerActivate::43264-43271 85 0.11% 95.35% # Bytes accessed per row activation 561system.physmem.bytesPerActivate::43520-43527 9 0.01% 95.36% # Bytes accessed per row activation 562system.physmem.bytesPerActivate::43648-43655 2 0.00% 95.36% # Bytes accessed per row activation 563system.physmem.bytesPerActivate::43776-43783 22 0.03% 95.39% # Bytes accessed per row activation 564system.physmem.bytesPerActivate::43840-43847 1 0.00% 95.39% # Bytes accessed per row activation 565system.physmem.bytesPerActivate::44032-44039 84 0.11% 95.51% # Bytes accessed per row activation 566system.physmem.bytesPerActivate::44224-44231 1 0.00% 95.51% # Bytes accessed per row activation 567system.physmem.bytesPerActivate::44288-44295 73 0.10% 95.61% # Bytes accessed per row activation 568system.physmem.bytesPerActivate::44480-44487 1 0.00% 95.61% # Bytes accessed per row activation 569system.physmem.bytesPerActivate::44544-44551 13 0.02% 95.63% # Bytes accessed per row activation 570system.physmem.bytesPerActivate::44800-44807 17 0.02% 95.65% # Bytes accessed per row activation 571system.physmem.bytesPerActivate::44928-44935 1 0.00% 95.65% # Bytes accessed per row activation 572system.physmem.bytesPerActivate::45056-45063 166 0.22% 95.87% # Bytes accessed per row activation 573system.physmem.bytesPerActivate::45184-45191 1 0.00% 95.87% # Bytes accessed per row activation 574system.physmem.bytesPerActivate::45312-45319 79 0.11% 95.98% # Bytes accessed per row activation 575system.physmem.bytesPerActivate::45376-45383 1 0.00% 95.98% # Bytes accessed per row activation 576system.physmem.bytesPerActivate::45568-45575 82 0.11% 96.09% # Bytes accessed per row activation 577system.physmem.bytesPerActivate::45696-45703 2 0.00% 96.09% # Bytes accessed per row activation 578system.physmem.bytesPerActivate::45824-45831 15 0.02% 96.11% # Bytes accessed per row activation 579system.physmem.bytesPerActivate::46080-46087 87 0.12% 96.23% # Bytes accessed per row activation 580system.physmem.bytesPerActivate::46144-46151 1 0.00% 96.23% # Bytes accessed per row activation 581system.physmem.bytesPerActivate::46336-46343 22 0.03% 96.26% # Bytes accessed per row activation 582system.physmem.bytesPerActivate::46592-46599 79 0.11% 96.37% # Bytes accessed per row activation 583system.physmem.bytesPerActivate::46848-46855 6 0.01% 96.38% # Bytes accessed per row activation 584system.physmem.bytesPerActivate::46912-46919 1 0.00% 96.38% # Bytes accessed per row activation 585system.physmem.bytesPerActivate::46976-46983 1 0.00% 96.38% # Bytes accessed per row activation 586system.physmem.bytesPerActivate::47104-47111 93 0.12% 96.50% # Bytes accessed per row activation 587system.physmem.bytesPerActivate::47232-47239 1 0.00% 96.51% # Bytes accessed per row activation 588system.physmem.bytesPerActivate::47360-47367 101 0.14% 96.64% # Bytes accessed per row activation 589system.physmem.bytesPerActivate::47424-47431 1 0.00% 96.64% # Bytes accessed per row activation 590system.physmem.bytesPerActivate::47616-47623 79 0.11% 96.75% # Bytes accessed per row activation 591system.physmem.bytesPerActivate::47872-47879 16 0.02% 96.77% # Bytes accessed per row activation 592system.physmem.bytesPerActivate::48000-48007 2 0.00% 96.77% # Bytes accessed per row activation 593system.physmem.bytesPerActivate::48128-48135 127 0.17% 96.94% # Bytes accessed per row activation 594system.physmem.bytesPerActivate::48192-48199 1 0.00% 96.94% # Bytes accessed per row activation 595system.physmem.bytesPerActivate::48256-48263 1 0.00% 96.95% # Bytes accessed per row activation 596system.physmem.bytesPerActivate::48384-48391 87 0.12% 97.06% # Bytes accessed per row activation 597system.physmem.bytesPerActivate::48640-48647 17 0.02% 97.09% # Bytes accessed per row activation 598system.physmem.bytesPerActivate::48704-48711 1 0.00% 97.09% # Bytes accessed per row activation 599system.physmem.bytesPerActivate::48768-48775 11 0.01% 97.10% # Bytes accessed per row activation 600system.physmem.bytesPerActivate::48896-48903 76 0.10% 97.20% # Bytes accessed per row activation 601system.physmem.bytesPerActivate::48960-48967 12 0.02% 97.22% # Bytes accessed per row activation 602system.physmem.bytesPerActivate::49024-49031 3 0.00% 97.22% # Bytes accessed per row activation 603system.physmem.bytesPerActivate::49088-49095 5 0.01% 97.23% # Bytes accessed per row activation 604system.physmem.bytesPerActivate::49152-49159 2061 2.77% 100.00% # Bytes accessed per row activation 605system.physmem.bytesPerActivate::total 74432 # Bytes accessed per row activation 606system.physmem.totQLat 159552537250 # Total ticks spent queuing 607system.physmem.totMemAccLat 202473692250 # Total ticks spent from burst creation until serviced by the DRAM 608system.physmem.totBusLat 33269920000 # Total ticks spent in databus transfers 609system.physmem.totBankLat 9651235000 # Total ticks spent accessing banks 610system.physmem.avgQLat 23978.50 # Average queueing delay per DRAM burst 611system.physmem.avgBankLat 1450.44 # Average bank access latency per DRAM burst 612system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 613system.physmem.avgMemAccLat 30428.94 # Average memory access latency per DRAM burst 614system.physmem.avgRdBW 356.02 # Average DRAM read bandwidth in MiByte/s 615system.physmem.avgWrBW 6.07 # Average achieved write bandwidth in MiByte/s 616system.physmem.avgRdBWSys 51.95 # Average system read bandwidth in MiByte/s 617system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s 618system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 619system.physmem.busUtil 2.83 # Data bus utilization in percentage 620system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads 621system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes 622system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing 623system.physmem.avgWrQLen 12.50 # Average write queue length when enqueuing 624system.physmem.readRowHits 6598277 # Number of row buffer hits during reads 625system.physmem.writeRowHits 94784 # Number of row buffer hits during writes 626system.physmem.readRowHitRate 99.16 # Row buffer hit rate for reads 627system.physmem.writeRowHitRate 83.49 # Row buffer hit rate for writes 628system.physmem.avgGap 160007.15 # Average gap between requests 629system.physmem.pageHitRate 98.90 # Row buffer hit rate, read and write combined 630system.physmem.prechargeAllPercent 4.90 # Percentage of time for which DRAM has all the banks in precharge state
613system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 614system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 615system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 616system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 617system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 618system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 619system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 620system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 621system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 622system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 623system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) 624system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 625system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 626system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) 627system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 628system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 629system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) 630system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
631system.membus.throughput 59936382 # Throughput (bytes/s) 632system.membus.trans_dist::ReadReq 7703367 # Transaction distribution 633system.membus.trans_dist::ReadResp 7703367 # Transaction distribution 634system.membus.trans_dist::WriteReq 767572 # Transaction distribution 635system.membus.trans_dist::WriteResp 767572 # Transaction distribution 636system.membus.trans_dist::Writeback 64227 # Transaction distribution 637system.membus.trans_dist::UpgradeReq 31703 # Transaction distribution 638system.membus.trans_dist::SCUpgradeReq 17214 # Transaction distribution 639system.membus.trans_dist::UpgradeResp 12043 # Transaction distribution 640system.membus.trans_dist::ReadExReq 137706 # Transaction distribution 641system.membus.trans_dist::ReadExResp 137264 # Transaction distribution 642system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382576 # Packet count per connected master and slave (bytes) 643system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 644system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10320 # Packet count per connected master and slave (bytes) 645system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 646system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) 647system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972063 # Packet count per connected master and slave (bytes) 648system.membus.pkt_count_system.l2c.mem_side::total 4365907 # Packet count per connected master and slave (bytes) 649system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 650system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) 651system.membus.pkt_count::total 17342035 # Packet count per connected master and slave (bytes) 652system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) 653system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 654system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20640 # Cumulative packet size per connected master and slave (bytes) 655system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 656system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) 657system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375316 # Cumulative packet size per connected master and slave (bytes) 658system.membus.tot_pkt_size_system.l2c.mem_side::total 19787746 # Cumulative packet size per connected master and slave (bytes) 659system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 660system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) 661system.membus.tot_pkt_size::total 71692258 # Cumulative packet size per connected master and slave (bytes) 662system.membus.data_through_bus 71692258 # Total data (bytes) 663system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 664system.membus.reqLayer0.occupancy 1224733500 # Layer occupancy (ticks) 665system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 666system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 667system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 668system.membus.reqLayer2.occupancy 9246500 # Layer occupancy (ticks) 669system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 670system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 671system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 672system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) 673system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 674system.membus.reqLayer6.occupancy 9211003500 # Layer occupancy (ticks) 675system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) 676system.membus.respLayer1.occupancy 5080947314 # Layer occupancy (ticks) 677system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 678system.membus.respLayer2.occupancy 14657701499 # Layer occupancy (ticks) 679system.membus.respLayer2.utilization 1.2 # Layer utilization (%) 680system.cpu_clk_domain.clock 500 # Clock period in ticks 681system.l2c.tags.replacements 69413 # number of replacements 682system.l2c.tags.tagsinuse 53013.525953 # Cycle average of tags in use 683system.l2c.tags.total_refs 1672541 # Total number of references to valid blocks. 684system.l2c.tags.sampled_refs 134599 # Sample count of references to valid blocks. 685system.l2c.tags.avg_refs 12.426103 # Average number of references to valid blocks. 686system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 687system.l2c.tags.occ_blocks::writebacks 40184.108166 # Average occupied blocks per requestor 688system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor 689system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001543 # Average occupied blocks per requestor 690system.l2c.tags.occ_blocks::cpu0.inst 3710.656491 # Average occupied blocks per requestor 691system.l2c.tags.occ_blocks::cpu0.data 4243.565236 # Average occupied blocks per requestor 692system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742460 # Average occupied blocks per requestor 693system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor 694system.l2c.tags.occ_blocks::cpu1.inst 2809.342303 # Average occupied blocks per requestor 695system.l2c.tags.occ_blocks::cpu1.data 2063.107654 # Average occupied blocks per requestor 696system.l2c.tags.occ_percent::writebacks 0.613161 # Average percentage of cache occupancy 697system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 698system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 699system.l2c.tags.occ_percent::cpu0.inst 0.056620 # Average percentage of cache occupancy 700system.l2c.tags.occ_percent::cpu0.data 0.064752 # Average percentage of cache occupancy 701system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 702system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 703system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy 704system.l2c.tags.occ_percent::cpu1.data 0.031481 # Average percentage of cache occupancy 705system.l2c.tags.occ_percent::total 0.808922 # Average percentage of cache occupancy 706system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 707system.l2c.tags.occ_task_id_blocks::1024 65181 # Occupied blocks per task id 708system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 709system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 710system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 711system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id 712system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id 713system.l2c.tags.age_task_id_blocks_1024::3 8037 # Occupied blocks per task id 714system.l2c.tags.age_task_id_blocks_1024::4 55165 # Occupied blocks per task id 715system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 716system.l2c.tags.occ_task_id_percent::1024 0.994583 # Percentage of cache occupancy per task id 717system.l2c.tags.tag_accesses 17211018 # Number of tag accesses 718system.l2c.tags.data_accesses 17211018 # Number of data accesses 719system.l2c.ReadReq_hits::cpu0.dtb.walker 3808 # number of ReadReq hits 720system.l2c.ReadReq_hits::cpu0.itb.walker 1739 # number of ReadReq hits 721system.l2c.ReadReq_hits::cpu0.inst 419108 # number of ReadReq hits 722system.l2c.ReadReq_hits::cpu0.data 205927 # number of ReadReq hits 723system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits 724system.l2c.ReadReq_hits::cpu1.itb.walker 1908 # number of ReadReq hits 725system.l2c.ReadReq_hits::cpu1.inst 464853 # number of ReadReq hits 726system.l2c.ReadReq_hits::cpu1.data 143402 # number of ReadReq hits 727system.l2c.ReadReq_hits::total 1246251 # number of ReadReq hits 728system.l2c.Writeback_hits::writebacks 571037 # number of Writeback hits 729system.l2c.Writeback_hits::total 571037 # number of Writeback hits 730system.l2c.UpgradeReq_hits::cpu0.data 1156 # number of UpgradeReq hits 731system.l2c.UpgradeReq_hits::cpu1.data 566 # number of UpgradeReq hits 732system.l2c.UpgradeReq_hits::total 1722 # number of UpgradeReq hits 733system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits 734system.l2c.SCUpgradeReq_hits::cpu1.data 102 # number of SCUpgradeReq hits 735system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits 736system.l2c.ReadExReq_hits::cpu0.data 56302 # number of ReadExReq hits 737system.l2c.ReadExReq_hits::cpu1.data 52763 # number of ReadExReq hits 738system.l2c.ReadExReq_hits::total 109065 # number of ReadExReq hits 739system.l2c.demand_hits::cpu0.dtb.walker 3808 # number of demand (read+write) hits 740system.l2c.demand_hits::cpu0.itb.walker 1739 # number of demand (read+write) hits 741system.l2c.demand_hits::cpu0.inst 419108 # number of demand (read+write) hits 742system.l2c.demand_hits::cpu0.data 262229 # number of demand (read+write) hits 743system.l2c.demand_hits::cpu1.dtb.walker 5506 # number of demand (read+write) hits 744system.l2c.demand_hits::cpu1.itb.walker 1908 # number of demand (read+write) hits 745system.l2c.demand_hits::cpu1.inst 464853 # number of demand (read+write) hits 746system.l2c.demand_hits::cpu1.data 196165 # number of demand (read+write) hits 747system.l2c.demand_hits::total 1355316 # number of demand (read+write) hits 748system.l2c.overall_hits::cpu0.dtb.walker 3808 # number of overall hits 749system.l2c.overall_hits::cpu0.itb.walker 1739 # number of overall hits 750system.l2c.overall_hits::cpu0.inst 419108 # number of overall hits 751system.l2c.overall_hits::cpu0.data 262229 # number of overall hits 752system.l2c.overall_hits::cpu1.dtb.walker 5506 # number of overall hits 753system.l2c.overall_hits::cpu1.itb.walker 1908 # number of overall hits 754system.l2c.overall_hits::cpu1.inst 464853 # number of overall hits 755system.l2c.overall_hits::cpu1.data 196165 # number of overall hits 756system.l2c.overall_hits::total 1355316 # number of overall hits 757system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 758system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 759system.l2c.ReadReq_misses::cpu0.inst 5729 # number of ReadReq misses 760system.l2c.ReadReq_misses::cpu0.data 7851 # number of ReadReq misses 761system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 762system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 763system.l2c.ReadReq_misses::cpu1.inst 5067 # number of ReadReq misses 764system.l2c.ReadReq_misses::cpu1.data 3614 # number of ReadReq misses 765system.l2c.ReadReq_misses::total 22269 # number of ReadReq misses 766system.l2c.UpgradeReq_misses::cpu0.data 4919 # number of UpgradeReq misses 767system.l2c.UpgradeReq_misses::cpu1.data 3647 # number of UpgradeReq misses 768system.l2c.UpgradeReq_misses::total 8566 # number of UpgradeReq misses 769system.l2c.SCUpgradeReq_misses::cpu0.data 560 # number of SCUpgradeReq misses 770system.l2c.SCUpgradeReq_misses::cpu1.data 475 # number of SCUpgradeReq misses 771system.l2c.SCUpgradeReq_misses::total 1035 # number of SCUpgradeReq misses 772system.l2c.ReadExReq_misses::cpu0.data 67124 # number of ReadExReq misses 773system.l2c.ReadExReq_misses::cpu1.data 72582 # number of ReadExReq misses 774system.l2c.ReadExReq_misses::total 139706 # number of ReadExReq misses 775system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 776system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 777system.l2c.demand_misses::cpu0.inst 5729 # number of demand (read+write) misses 778system.l2c.demand_misses::cpu0.data 74975 # number of demand (read+write) misses 779system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses 780system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 781system.l2c.demand_misses::cpu1.inst 5067 # number of demand (read+write) misses 782system.l2c.demand_misses::cpu1.data 76196 # number of demand (read+write) misses 783system.l2c.demand_misses::total 161975 # number of demand (read+write) misses 784system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 785system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 786system.l2c.overall_misses::cpu0.inst 5729 # number of overall misses 787system.l2c.overall_misses::cpu0.data 74975 # number of overall misses 788system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 789system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 790system.l2c.overall_misses::cpu1.inst 5067 # number of overall misses 791system.l2c.overall_misses::cpu1.data 76196 # number of overall misses 792system.l2c.overall_misses::total 161975 # number of overall misses 793system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles 794system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles 795system.l2c.ReadReq_miss_latency::cpu0.inst 409309750 # number of ReadReq miss cycles 796system.l2c.ReadReq_miss_latency::cpu0.data 588242499 # number of ReadReq miss cycles 797system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 347000 # number of ReadReq miss cycles 798system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles 799system.l2c.ReadReq_miss_latency::cpu1.inst 364513250 # number of ReadReq miss cycles 800system.l2c.ReadReq_miss_latency::cpu1.data 283018000 # number of ReadReq miss cycles 801system.l2c.ReadReq_miss_latency::total 1645686499 # number of ReadReq miss cycles 802system.l2c.UpgradeReq_miss_latency::cpu0.data 13362921 # number of UpgradeReq miss cycles 803system.l2c.UpgradeReq_miss_latency::cpu1.data 11997484 # number of UpgradeReq miss cycles 804system.l2c.UpgradeReq_miss_latency::total 25360405 # number of UpgradeReq miss cycles 805system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1671428 # number of SCUpgradeReq miss cycles 806system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2463894 # number of SCUpgradeReq miss cycles 807system.l2c.SCUpgradeReq_miss_latency::total 4135322 # number of SCUpgradeReq miss cycles 808system.l2c.ReadExReq_miss_latency::cpu0.data 4512260183 # number of ReadExReq miss cycles 809system.l2c.ReadExReq_miss_latency::cpu1.data 5472708624 # number of ReadExReq miss cycles 810system.l2c.ReadExReq_miss_latency::total 9984968807 # number of ReadExReq miss cycles 811system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles 812system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles 813system.l2c.demand_miss_latency::cpu0.inst 409309750 # number of demand (read+write) miss cycles 814system.l2c.demand_miss_latency::cpu0.data 5100502682 # number of demand (read+write) miss cycles 815system.l2c.demand_miss_latency::cpu1.dtb.walker 347000 # number of demand (read+write) miss cycles 816system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles 817system.l2c.demand_miss_latency::cpu1.inst 364513250 # number of demand (read+write) miss cycles 818system.l2c.demand_miss_latency::cpu1.data 5755726624 # number of demand (read+write) miss cycles 819system.l2c.demand_miss_latency::total 11630655306 # number of demand (read+write) miss cycles 820system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles 821system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles 822system.l2c.overall_miss_latency::cpu0.inst 409309750 # number of overall miss cycles 823system.l2c.overall_miss_latency::cpu0.data 5100502682 # number of overall miss cycles 824system.l2c.overall_miss_latency::cpu1.dtb.walker 347000 # number of overall miss cycles 825system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles 826system.l2c.overall_miss_latency::cpu1.inst 364513250 # number of overall miss cycles 827system.l2c.overall_miss_latency::cpu1.data 5755726624 # number of overall miss cycles 828system.l2c.overall_miss_latency::total 11630655306 # number of overall miss cycles 829system.l2c.ReadReq_accesses::cpu0.dtb.walker 3809 # number of ReadReq accesses(hits+misses) 830system.l2c.ReadReq_accesses::cpu0.itb.walker 1741 # number of ReadReq accesses(hits+misses) 831system.l2c.ReadReq_accesses::cpu0.inst 424837 # number of ReadReq accesses(hits+misses) 832system.l2c.ReadReq_accesses::cpu0.data 213778 # number of ReadReq accesses(hits+misses) 833system.l2c.ReadReq_accesses::cpu1.dtb.walker 5510 # number of ReadReq accesses(hits+misses) 834system.l2c.ReadReq_accesses::cpu1.itb.walker 1909 # number of ReadReq accesses(hits+misses) 835system.l2c.ReadReq_accesses::cpu1.inst 469920 # number of ReadReq accesses(hits+misses) 836system.l2c.ReadReq_accesses::cpu1.data 147016 # number of ReadReq accesses(hits+misses) 837system.l2c.ReadReq_accesses::total 1268520 # number of ReadReq accesses(hits+misses) 838system.l2c.Writeback_accesses::writebacks 571037 # number of Writeback accesses(hits+misses) 839system.l2c.Writeback_accesses::total 571037 # number of Writeback accesses(hits+misses) 840system.l2c.UpgradeReq_accesses::cpu0.data 6075 # number of UpgradeReq accesses(hits+misses) 841system.l2c.UpgradeReq_accesses::cpu1.data 4213 # number of UpgradeReq accesses(hits+misses) 842system.l2c.UpgradeReq_accesses::total 10288 # number of UpgradeReq accesses(hits+misses) 843system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses) 844system.l2c.SCUpgradeReq_accesses::cpu1.data 577 # number of SCUpgradeReq accesses(hits+misses) 845system.l2c.SCUpgradeReq_accesses::total 1353 # number of SCUpgradeReq accesses(hits+misses) 846system.l2c.ReadExReq_accesses::cpu0.data 123426 # number of ReadExReq accesses(hits+misses) 847system.l2c.ReadExReq_accesses::cpu1.data 125345 # number of ReadExReq accesses(hits+misses) 848system.l2c.ReadExReq_accesses::total 248771 # number of ReadExReq accesses(hits+misses) 849system.l2c.demand_accesses::cpu0.dtb.walker 3809 # number of demand (read+write) accesses 850system.l2c.demand_accesses::cpu0.itb.walker 1741 # number of demand (read+write) accesses 851system.l2c.demand_accesses::cpu0.inst 424837 # number of demand (read+write) accesses 852system.l2c.demand_accesses::cpu0.data 337204 # number of demand (read+write) accesses 853system.l2c.demand_accesses::cpu1.dtb.walker 5510 # number of demand (read+write) accesses 854system.l2c.demand_accesses::cpu1.itb.walker 1909 # number of demand (read+write) accesses 855system.l2c.demand_accesses::cpu1.inst 469920 # number of demand (read+write) accesses 856system.l2c.demand_accesses::cpu1.data 272361 # number of demand (read+write) accesses 857system.l2c.demand_accesses::total 1517291 # number of demand (read+write) accesses 858system.l2c.overall_accesses::cpu0.dtb.walker 3809 # number of overall (read+write) accesses 859system.l2c.overall_accesses::cpu0.itb.walker 1741 # number of overall (read+write) accesses 860system.l2c.overall_accesses::cpu0.inst 424837 # number of overall (read+write) accesses 861system.l2c.overall_accesses::cpu0.data 337204 # number of overall (read+write) accesses 862system.l2c.overall_accesses::cpu1.dtb.walker 5510 # number of overall (read+write) accesses 863system.l2c.overall_accesses::cpu1.itb.walker 1909 # number of overall (read+write) accesses 864system.l2c.overall_accesses::cpu1.inst 469920 # number of overall (read+write) accesses 865system.l2c.overall_accesses::cpu1.data 272361 # number of overall (read+write) accesses 866system.l2c.overall_accesses::total 1517291 # number of overall (read+write) accesses 867system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000263 # miss rate for ReadReq accesses 868system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001149 # miss rate for ReadReq accesses 869system.l2c.ReadReq_miss_rate::cpu0.inst 0.013485 # miss rate for ReadReq accesses 870system.l2c.ReadReq_miss_rate::cpu0.data 0.036725 # miss rate for ReadReq accesses 871system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses 872system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000524 # miss rate for ReadReq accesses 873system.l2c.ReadReq_miss_rate::cpu1.inst 0.010783 # miss rate for ReadReq accesses 874system.l2c.ReadReq_miss_rate::cpu1.data 0.024582 # miss rate for ReadReq accesses 875system.l2c.ReadReq_miss_rate::total 0.017555 # miss rate for ReadReq accesses 876system.l2c.UpgradeReq_miss_rate::cpu0.data 0.809712 # miss rate for UpgradeReq accesses 877system.l2c.UpgradeReq_miss_rate::cpu1.data 0.865654 # miss rate for UpgradeReq accesses 878system.l2c.UpgradeReq_miss_rate::total 0.832621 # miss rate for UpgradeReq accesses 879system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721649 # miss rate for SCUpgradeReq accesses 880system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.823224 # miss rate for SCUpgradeReq accesses 881system.l2c.SCUpgradeReq_miss_rate::total 0.764967 # miss rate for SCUpgradeReq accesses 882system.l2c.ReadExReq_miss_rate::cpu0.data 0.543840 # miss rate for ReadExReq accesses 883system.l2c.ReadExReq_miss_rate::cpu1.data 0.579058 # miss rate for ReadExReq accesses 884system.l2c.ReadExReq_miss_rate::total 0.561585 # miss rate for ReadExReq accesses 885system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000263 # miss rate for demand accesses 886system.l2c.demand_miss_rate::cpu0.itb.walker 0.001149 # miss rate for demand accesses 887system.l2c.demand_miss_rate::cpu0.inst 0.013485 # miss rate for demand accesses 888system.l2c.demand_miss_rate::cpu0.data 0.222343 # miss rate for demand accesses 889system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses 890system.l2c.demand_miss_rate::cpu1.itb.walker 0.000524 # miss rate for demand accesses 891system.l2c.demand_miss_rate::cpu1.inst 0.010783 # miss rate for demand accesses 892system.l2c.demand_miss_rate::cpu1.data 0.279761 # miss rate for demand accesses 893system.l2c.demand_miss_rate::total 0.106753 # miss rate for demand accesses 894system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000263 # miss rate for overall accesses 895system.l2c.overall_miss_rate::cpu0.itb.walker 0.001149 # miss rate for overall accesses 896system.l2c.overall_miss_rate::cpu0.inst 0.013485 # miss rate for overall accesses 897system.l2c.overall_miss_rate::cpu0.data 0.222343 # miss rate for overall accesses 898system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses 899system.l2c.overall_miss_rate::cpu1.itb.walker 0.000524 # miss rate for overall accesses 900system.l2c.overall_miss_rate::cpu1.inst 0.010783 # miss rate for overall accesses 901system.l2c.overall_miss_rate::cpu1.data 0.279761 # miss rate for overall accesses 902system.l2c.overall_miss_rate::total 0.106753 # miss rate for overall accesses 903system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency 904system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 905system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71445.234770 # average ReadReq miss latency 906system.l2c.ReadReq_avg_miss_latency::cpu0.data 74925.805502 # average ReadReq miss latency 907system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86750 # average ReadReq miss latency 908system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency 909system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71938.671798 # average ReadReq miss latency 910system.l2c.ReadReq_avg_miss_latency::cpu1.data 78311.566132 # average ReadReq miss latency 911system.l2c.ReadReq_avg_miss_latency::total 73900.332256 # average ReadReq miss latency 912system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2716.593007 # average UpgradeReq miss latency 913system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3289.685769 # average UpgradeReq miss latency 914system.l2c.UpgradeReq_avg_miss_latency::total 2960.588956 # average UpgradeReq miss latency 915system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2984.692857 # average SCUpgradeReq miss latency 916system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5187.145263 # average SCUpgradeReq miss latency 917system.l2c.SCUpgradeReq_avg_miss_latency::total 3995.480193 # average SCUpgradeReq miss latency 918system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67222.754648 # average ReadExReq miss latency 919system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75400.355791 # average ReadExReq miss latency 920system.l2c.ReadExReq_avg_miss_latency::total 71471.295485 # average ReadExReq miss latency 921system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency 922system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 923system.l2c.demand_avg_miss_latency::cpu0.inst 71445.234770 # average overall miss latency 924system.l2c.demand_avg_miss_latency::cpu0.data 68029.378886 # average overall miss latency 925system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency 926system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 927system.l2c.demand_avg_miss_latency::cpu1.inst 71938.671798 # average overall miss latency 928system.l2c.demand_avg_miss_latency::cpu1.data 75538.435403 # average overall miss latency 929system.l2c.demand_avg_miss_latency::total 71805.249613 # average overall miss latency 930system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency 931system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 932system.l2c.overall_avg_miss_latency::cpu0.inst 71445.234770 # average overall miss latency 933system.l2c.overall_avg_miss_latency::cpu0.data 68029.378886 # average overall miss latency 934system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency 935system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 936system.l2c.overall_avg_miss_latency::cpu1.inst 71938.671798 # average overall miss latency 937system.l2c.overall_avg_miss_latency::cpu1.data 75538.435403 # average overall miss latency 938system.l2c.overall_avg_miss_latency::total 71805.249613 # average overall miss latency 939system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 940system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 941system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 942system.l2c.blocked::no_targets 0 # number of cycles access was blocked 943system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 944system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 945system.l2c.fast_writes 0 # number of fast writes performed 946system.l2c.cache_copies 0 # number of cache copies performed 947system.l2c.writebacks::writebacks 64227 # number of writebacks 948system.l2c.writebacks::total 64227 # number of writebacks 949system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 950system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 951system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 952system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 953system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 954system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 955system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses 956system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 957system.l2c.ReadReq_mshr_misses::cpu0.inst 5728 # number of ReadReq MSHR misses 958system.l2c.ReadReq_mshr_misses::cpu0.data 7851 # number of ReadReq MSHR misses 959system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses 960system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 961system.l2c.ReadReq_mshr_misses::cpu1.inst 5067 # number of ReadReq MSHR misses 962system.l2c.ReadReq_mshr_misses::cpu1.data 3614 # number of ReadReq MSHR misses 963system.l2c.ReadReq_mshr_misses::total 22268 # number of ReadReq MSHR misses 964system.l2c.UpgradeReq_mshr_misses::cpu0.data 4919 # number of UpgradeReq MSHR misses 965system.l2c.UpgradeReq_mshr_misses::cpu1.data 3647 # number of UpgradeReq MSHR misses 966system.l2c.UpgradeReq_mshr_misses::total 8566 # number of UpgradeReq MSHR misses 967system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 560 # number of SCUpgradeReq MSHR misses 968system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 475 # number of SCUpgradeReq MSHR misses 969system.l2c.SCUpgradeReq_mshr_misses::total 1035 # number of SCUpgradeReq MSHR misses 970system.l2c.ReadExReq_mshr_misses::cpu0.data 67124 # number of ReadExReq MSHR misses 971system.l2c.ReadExReq_mshr_misses::cpu1.data 72582 # number of ReadExReq MSHR misses 972system.l2c.ReadExReq_mshr_misses::total 139706 # number of ReadExReq MSHR misses 973system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses 974system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 975system.l2c.demand_mshr_misses::cpu0.inst 5728 # number of demand (read+write) MSHR misses 976system.l2c.demand_mshr_misses::cpu0.data 74975 # number of demand (read+write) MSHR misses 977system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses 978system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 979system.l2c.demand_mshr_misses::cpu1.inst 5067 # number of demand (read+write) MSHR misses 980system.l2c.demand_mshr_misses::cpu1.data 76196 # number of demand (read+write) MSHR misses 981system.l2c.demand_mshr_misses::total 161974 # number of demand (read+write) MSHR misses 982system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses 983system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 984system.l2c.overall_mshr_misses::cpu0.inst 5728 # number of overall MSHR misses 985system.l2c.overall_mshr_misses::cpu0.data 74975 # number of overall MSHR misses 986system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses 987system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 988system.l2c.overall_mshr_misses::cpu1.inst 5067 # number of overall MSHR misses 989system.l2c.overall_mshr_misses::cpu1.data 76196 # number of overall MSHR misses 990system.l2c.overall_mshr_misses::total 161974 # number of overall MSHR misses 991system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20000 # number of ReadReq MSHR miss cycles 992system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles 993system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 336674000 # number of ReadReq MSHR miss cycles 994system.l2c.ReadReq_mshr_miss_latency::cpu0.data 490296499 # number of ReadReq MSHR miss cycles 995system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 297000 # number of ReadReq MSHR miss cycles 996system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles 997system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300318250 # number of ReadReq MSHR miss cycles 998system.l2c.ReadReq_mshr_miss_latency::cpu1.data 238087000 # number of ReadReq MSHR miss cycles 999system.l2c.ReadReq_mshr_miss_latency::total 1365880249 # number of ReadReq MSHR miss cycles 1000system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 49210416 # number of UpgradeReq MSHR miss cycles 1001system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36526138 # number of UpgradeReq MSHR miss cycles 1002system.l2c.UpgradeReq_mshr_miss_latency::total 85736554 # number of UpgradeReq MSHR miss cycles 1003system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5602558 # number of SCUpgradeReq MSHR miss cycles 1004system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4753973 # number of SCUpgradeReq MSHR miss cycles 1005system.l2c.SCUpgradeReq_mshr_miss_latency::total 10356531 # number of SCUpgradeReq MSHR miss cycles 1006system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3645878311 # number of ReadExReq MSHR miss cycles 1007system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4548664376 # number of ReadExReq MSHR miss cycles 1008system.l2c.ReadExReq_mshr_miss_latency::total 8194542687 # number of ReadExReq MSHR miss cycles 1009system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 20000 # number of demand (read+write) MSHR miss cycles 1010system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 1011system.l2c.demand_mshr_miss_latency::cpu0.inst 336674000 # number of demand (read+write) MSHR miss cycles 1012system.l2c.demand_mshr_miss_latency::cpu0.data 4136174810 # number of demand (read+write) MSHR miss cycles 1013system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 297000 # number of demand (read+write) MSHR miss cycles 1014system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 1015system.l2c.demand_mshr_miss_latency::cpu1.inst 300318250 # number of demand (read+write) MSHR miss cycles 1016system.l2c.demand_mshr_miss_latency::cpu1.data 4786751376 # number of demand (read+write) MSHR miss cycles 1017system.l2c.demand_mshr_miss_latency::total 9560422936 # number of demand (read+write) MSHR miss cycles 1018system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20000 # number of overall MSHR miss cycles 1019system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles 1020system.l2c.overall_mshr_miss_latency::cpu0.inst 336674000 # number of overall MSHR miss cycles 1021system.l2c.overall_mshr_miss_latency::cpu0.data 4136174810 # number of overall MSHR miss cycles 1022system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 297000 # number of overall MSHR miss cycles 1023system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles 1024system.l2c.overall_mshr_miss_latency::cpu1.inst 300318250 # number of overall MSHR miss cycles 1025system.l2c.overall_mshr_miss_latency::cpu1.data 4786751376 # number of overall MSHR miss cycles 1026system.l2c.overall_mshr_miss_latency::total 9560422936 # number of overall MSHR miss cycles 1027system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 345201250 # number of ReadReq MSHR uncacheable cycles 1028system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12449699492 # number of ReadReq MSHR uncacheable cycles 1029system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5636750 # number of ReadReq MSHR uncacheable cycles 1030system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154292835997 # number of ReadReq MSHR uncacheable cycles 1031system.l2c.ReadReq_mshr_uncacheable_latency::total 167093373489 # number of ReadReq MSHR uncacheable cycles 1032system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1043988495 # number of WriteReq MSHR uncacheable cycles 1033system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15722457655 # number of WriteReq MSHR uncacheable cycles 1034system.l2c.WriteReq_mshr_uncacheable_latency::total 16766446150 # number of WriteReq MSHR uncacheable cycles 1035system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 345201250 # number of overall MSHR uncacheable cycles 1036system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13493687987 # number of overall MSHR uncacheable cycles 1037system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5636750 # number of overall MSHR uncacheable cycles 1038system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170015293652 # number of overall MSHR uncacheable cycles 1039system.l2c.overall_mshr_uncacheable_latency::total 183859819639 # number of overall MSHR uncacheable cycles 1040system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for ReadReq accesses 1041system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for ReadReq accesses 1042system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for ReadReq accesses 1043system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036725 # mshr miss rate for ReadReq accesses 1044system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses 1045system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for ReadReq accesses 1046system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for ReadReq accesses 1047system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for ReadReq accesses 1048system.l2c.ReadReq_mshr_miss_rate::total 0.017554 # mshr miss rate for ReadReq accesses 1049system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.809712 # mshr miss rate for UpgradeReq accesses 1050system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865654 # mshr miss rate for UpgradeReq accesses 1051system.l2c.UpgradeReq_mshr_miss_rate::total 0.832621 # mshr miss rate for UpgradeReq accesses 1052system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721649 # mshr miss rate for SCUpgradeReq accesses 1053system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823224 # mshr miss rate for SCUpgradeReq accesses 1054system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for SCUpgradeReq accesses 1055system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543840 # mshr miss rate for ReadExReq accesses 1056system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.579058 # mshr miss rate for ReadExReq accesses 1057system.l2c.ReadExReq_mshr_miss_rate::total 0.561585 # mshr miss rate for ReadExReq accesses 1058system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for demand accesses 1059system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for demand accesses 1060system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for demand accesses 1061system.l2c.demand_mshr_miss_rate::cpu0.data 0.222343 # mshr miss rate for demand accesses 1062system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses 1063system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for demand accesses 1064system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for demand accesses 1065system.l2c.demand_mshr_miss_rate::cpu1.data 0.279761 # mshr miss rate for demand accesses 1066system.l2c.demand_mshr_miss_rate::total 0.106752 # mshr miss rate for demand accesses 1067system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for overall accesses 1068system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for overall accesses 1069system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for overall accesses 1070system.l2c.overall_mshr_miss_rate::cpu0.data 0.222343 # mshr miss rate for overall accesses 1071system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses 1072system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for overall accesses 1073system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for overall accesses 1074system.l2c.overall_mshr_miss_rate::cpu1.data 0.279761 # mshr miss rate for overall accesses 1075system.l2c.overall_mshr_miss_rate::total 0.106752 # mshr miss rate for overall accesses 1076system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency 1077system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 1078system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average ReadReq mshr miss latency 1079system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62450.197300 # average ReadReq mshr miss latency 1080system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average ReadReq mshr miss latency 1081system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 1082system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average ReadReq mshr miss latency 1083system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65879.081350 # average ReadReq mshr miss latency 1084system.l2c.ReadReq_avg_mshr_miss_latency::total 61338.254401 # average ReadReq mshr miss latency 1085system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.150437 # average UpgradeReq mshr miss latency 1086system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.392926 # average UpgradeReq mshr miss latency 1087system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.936960 # average UpgradeReq mshr miss latency 1088system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.567857 # average SCUpgradeReq mshr miss latency 1089system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.364211 # average SCUpgradeReq mshr miss latency 1090system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10006.310145 # average SCUpgradeReq mshr miss latency 1091system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54315.569856 # average ReadExReq mshr miss latency 1092system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62669.317131 # average ReadExReq mshr miss latency 1093system.l2c.ReadExReq_avg_mshr_miss_latency::total 58655.624576 # average ReadExReq mshr miss latency 1094system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 1095system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 1096system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency 1097system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency 1098system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency 1099system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 1100system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency 1101system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency 1102system.l2c.demand_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency 1103system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 1104system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 1105system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency 1106system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency 1107system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency 1108system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 1109system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency 1110system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency 1111system.l2c.overall_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency 1112system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1113system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1114system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1115system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1116system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1117system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1118system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1119system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1120system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1121system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1122system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1123system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1124system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1125system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1126system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1127system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1128system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1129system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1130system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1131system.cf0.dma_write_txs 0 # Number of DMA write transactions. 1132system.toL2Bus.throughput 119505667 # Throughput (bytes/s) 1133system.toL2Bus.trans_dist::ReadReq 2535246 # Transaction distribution 1134system.toL2Bus.trans_dist::ReadResp 2535246 # Transaction distribution 1135system.toL2Bus.trans_dist::WriteReq 767572 # Transaction distribution 1136system.toL2Bus.trans_dist::WriteResp 767572 # Transaction distribution 1137system.toL2Bus.trans_dist::Writeback 571037 # Transaction distribution 1138system.toL2Bus.trans_dist::UpgradeReq 30983 # Transaction distribution 1139system.toL2Bus.trans_dist::SCUpgradeReq 17532 # Transaction distribution 1140system.toL2Bus.trans_dist::UpgradeResp 48515 # Transaction distribution 1141system.toL2Bus.trans_dist::ReadExReq 260644 # Transaction distribution 1142system.toL2Bus.trans_dist::ReadExResp 260644 # Transaction distribution 1143system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863518 # Packet count per connected master and slave (bytes) 1144system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226193 # Packet count per connected master and slave (bytes) 1145system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) 1146system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12684 # Packet count per connected master and slave (bytes) 1147system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940579 # Packet count per connected master and slave (bytes) 1148system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601780 # Packet count per connected master and slave (bytes) 1149system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6235 # Packet count per connected master and slave (bytes) 1150system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15427 # Packet count per connected master and slave (bytes) 1151system.toL2Bus.pkt_count::total 7672553 # Packet count per connected master and slave (bytes) 1152system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27216160 # Cumulative packet size per connected master and slave (bytes) 1153system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41363346 # Cumulative packet size per connected master and slave (bytes) 1154system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) 1155system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15236 # Cumulative packet size per connected master and slave (bytes) 1156system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30075316 # Cumulative packet size per connected master and slave (bytes) 1157system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39635324 # Cumulative packet size per connected master and slave (bytes) 1158system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7636 # Cumulative packet size per connected master and slave (bytes) 1159system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22040 # Cumulative packet size per connected master and slave (bytes) 1160system.toL2Bus.tot_pkt_size::total 138342022 # Cumulative packet size per connected master and slave (bytes) 1161system.toL2Bus.data_through_bus 138342022 # Total data (bytes) 1162system.toL2Bus.snoop_data_through_bus 4603396 # Total snoop data (bytes) 1163system.toL2Bus.reqLayer0.occupancy 4759597686 # Layer occupancy (ticks) 1164system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 1165system.toL2Bus.respLayer0.occupancy 1923628472 # Layer occupancy (ticks) 1166system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1167system.toL2Bus.respLayer1.occupancy 1753100289 # Layer occupancy (ticks) 1168system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1169system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) 1170system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1171system.toL2Bus.respLayer3.occupancy 8875000 # Layer occupancy (ticks) 1172system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1173system.toL2Bus.respLayer6.occupancy 2118090473 # Layer occupancy (ticks) 1174system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 1175system.toL2Bus.respLayer7.occupancy 2927544636 # Layer occupancy (ticks) 1176system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1177system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) 1178system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) 1179system.toL2Bus.respLayer9.occupancy 9917499 # Layer occupancy (ticks) 1180system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) 1181system.iobus.throughput 45391376 # Throughput (bytes/s) 1182system.iobus.trans_dist::ReadReq 7671402 # Transaction distribution 1183system.iobus.trans_dist::ReadResp 7671402 # Transaction distribution 1184system.iobus.trans_dist::WriteReq 7950 # Transaction distribution 1185system.iobus.trans_dist::WriteResp 7950 # Transaction distribution 1186system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) 1187system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) 1188system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1189system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) 1190system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1192system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1195system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1196system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1197system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1198system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1199system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1200system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1201system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1202system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1203system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1204system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1205system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1206system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1207system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1208system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1209system.iobus.pkt_count_system.bridge.master::total 2382576 # Packet count per connected master and slave (bytes) 1210system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 1211system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) 1212system.iobus.pkt_count::total 15358704 # Packet count per connected master and slave (bytes) 1213system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) 1217system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1218system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1219system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) 1220system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1221system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1222system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1223system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1224system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1225system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1226system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1227system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1228system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1229system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1230system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1231system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1232system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1233system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1234system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1235system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1236system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) 1237system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 1238system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) 1239system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) 1240system.iobus.data_through_bus 54294406 # Total data (bytes) 1241system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) 1242system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1243system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) 1244system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1246system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1247system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) 1248system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1249system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 1250system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1251system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 1252system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1253system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) 1254system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1255system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 1256system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) 1257system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 1258system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1259system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1260system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1261system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 1262system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1263system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 1264system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 1265system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1266system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1267system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 1268system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1269system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1270system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1271system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 1272system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1273system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1274system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1275system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1276system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1277system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 1278system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1279system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1280system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1281system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1282system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1283system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1284system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1285system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1286system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1287system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 1288system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) 1289system.iobus.respLayer0.occupancy 2374626000 # Layer occupancy (ticks) 1290system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) 1291system.iobus.respLayer1.occupancy 17778333501 # Layer occupancy (ticks) 1292system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 1293system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1294system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1295system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1296system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1297system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1298system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1299system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1300system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1301system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1302system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1303system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1304system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1305system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1306system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1307system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1308system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1309system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1310system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1311system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1312system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1313system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1314system.cpu0.dtb.inst_hits 0 # ITB inst hits 1315system.cpu0.dtb.inst_misses 0 # ITB inst misses 1316system.cpu0.dtb.read_hits 7064121 # DTB read hits 1317system.cpu0.dtb.read_misses 3756 # DTB read misses 1318system.cpu0.dtb.write_hits 5649416 # DTB write hits 1319system.cpu0.dtb.write_misses 801 # DTB write misses 1320system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1321system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1322system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1323system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1324system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB 1325system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1326system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch 1327system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1328system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 1329system.cpu0.dtb.read_accesses 7067877 # DTB read accesses 1330system.cpu0.dtb.write_accesses 5650217 # DTB write accesses 1331system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 1332system.cpu0.dtb.hits 12713537 # DTB hits 1333system.cpu0.dtb.misses 4557 # DTB misses 1334system.cpu0.dtb.accesses 12718094 # DTB accesses 1335system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1336system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1337system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1338system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1339system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1340system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1341system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1342system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1343system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1344system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1345system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1346system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1347system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1348system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1349system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1350system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1351system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1352system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1353system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1354system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1355system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1356system.cpu0.itb.inst_hits 29561361 # ITB inst hits 1357system.cpu0.itb.inst_misses 2205 # ITB inst misses 1358system.cpu0.itb.read_hits 0 # DTB read hits 1359system.cpu0.itb.read_misses 0 # DTB read misses 1360system.cpu0.itb.write_hits 0 # DTB write hits 1361system.cpu0.itb.write_misses 0 # DTB write misses 1362system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1363system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1364system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1365system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1366system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB 1367system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1368system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1369system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1370system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1371system.cpu0.itb.read_accesses 0 # DTB read accesses 1372system.cpu0.itb.write_accesses 0 # DTB write accesses 1373system.cpu0.itb.inst_accesses 29563566 # ITB inst accesses 1374system.cpu0.itb.hits 29561361 # DTB hits 1375system.cpu0.itb.misses 2205 # DTB misses 1376system.cpu0.itb.accesses 29563566 # DTB accesses 1377system.cpu0.numCycles 2392278482 # number of cpu cycles simulated 1378system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1379system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 1380system.cpu0.committedInsts 28863304 # Number of instructions committed 1381system.cpu0.committedOps 37189208 # Number of ops (including micro ops) committed 1382system.cpu0.num_int_alu_accesses 33114268 # Number of integer alu accesses 1383system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 1384system.cpu0.num_func_calls 1241816 # number of times a function call or return occured 1385system.cpu0.num_conditional_control_insts 4372124 # number of instructions that are conditional controls 1386system.cpu0.num_int_insts 33114268 # number of integer instructions 1387system.cpu0.num_fp_insts 3860 # number of float instructions 1388system.cpu0.num_int_register_reads 192166322 # number of times the integer registers were read 1389system.cpu0.num_int_register_writes 36246326 # number of times the integer registers were written 1390system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1391system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 1392system.cpu0.num_mem_refs 13380719 # number of memory refs 1393system.cpu0.num_load_insts 7401377 # Number of load instructions 1394system.cpu0.num_store_insts 5979342 # Number of store instructions 1395system.cpu0.num_idle_cycles 2246536230.490122 # Number of idle cycles 1396system.cpu0.num_busy_cycles 145742251.509878 # Number of busy cycles 1397system.cpu0.not_idle_fraction 0.060922 # Percentage of non-idle cycles 1398system.cpu0.idle_fraction 0.939078 # Percentage of idle cycles	631system.membus.throughput 59936382 # Throughput (bytes/s) 632system.membus.trans_dist::ReadReq 7703367 # Transaction distribution 633system.membus.trans_dist::ReadResp 7703367 # Transaction distribution 634system.membus.trans_dist::WriteReq 767572 # Transaction distribution 635system.membus.trans_dist::WriteResp 767572 # Transaction distribution 636system.membus.trans_dist::Writeback 64227 # Transaction distribution 637system.membus.trans_dist::UpgradeReq 31703 # Transaction distribution 638system.membus.trans_dist::SCUpgradeReq 17214 # Transaction distribution 639system.membus.trans_dist::UpgradeResp 12043 # Transaction distribution 640system.membus.trans_dist::ReadExReq 137706 # Transaction distribution 641system.membus.trans_dist::ReadExResp 137264 # Transaction distribution 642system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382576 # Packet count per connected master and slave (bytes) 643system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 644system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10320 # Packet count per connected master and slave (bytes) 645system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 646system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) 647system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972063 # Packet count per connected master and slave (bytes) 648system.membus.pkt_count_system.l2c.mem_side::total 4365907 # Packet count per connected master and slave (bytes) 649system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) 650system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) 651system.membus.pkt_count::total 17342035 # Packet count per connected master and slave (bytes) 652system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389894 # Cumulative packet size per connected master and slave (bytes) 653system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 654system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20640 # Cumulative packet size per connected master and slave (bytes) 655system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 656system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) 657system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375316 # Cumulative packet size per connected master and slave (bytes) 658system.membus.tot_pkt_size_system.l2c.mem_side::total 19787746 # Cumulative packet size per connected master and slave (bytes) 659system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) 660system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) 661system.membus.tot_pkt_size::total 71692258 # Cumulative packet size per connected master and slave (bytes) 662system.membus.data_through_bus 71692258 # Total data (bytes) 663system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 664system.membus.reqLayer0.occupancy 1224733500 # Layer occupancy (ticks) 665system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 666system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) 667system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 668system.membus.reqLayer2.occupancy 9246500 # Layer occupancy (ticks) 669system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 670system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) 671system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 672system.membus.reqLayer5.occupancy 782500 # Layer occupancy (ticks) 673system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 674system.membus.reqLayer6.occupancy 9211003500 # Layer occupancy (ticks) 675system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) 676system.membus.respLayer1.occupancy 5080947314 # Layer occupancy (ticks) 677system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 678system.membus.respLayer2.occupancy 14657701499 # Layer occupancy (ticks) 679system.membus.respLayer2.utilization 1.2 # Layer utilization (%) 680system.cpu_clk_domain.clock 500 # Clock period in ticks 681system.l2c.tags.replacements 69413 # number of replacements 682system.l2c.tags.tagsinuse 53013.525953 # Cycle average of tags in use 683system.l2c.tags.total_refs 1672541 # Total number of references to valid blocks. 684system.l2c.tags.sampled_refs 134599 # Sample count of references to valid blocks. 685system.l2c.tags.avg_refs 12.426103 # Average number of references to valid blocks. 686system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 687system.l2c.tags.occ_blocks::writebacks 40184.108166 # Average occupied blocks per requestor 688system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor 689system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001543 # Average occupied blocks per requestor 690system.l2c.tags.occ_blocks::cpu0.inst 3710.656491 # Average occupied blocks per requestor 691system.l2c.tags.occ_blocks::cpu0.data 4243.565236 # Average occupied blocks per requestor 692system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742460 # Average occupied blocks per requestor 693system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor 694system.l2c.tags.occ_blocks::cpu1.inst 2809.342303 # Average occupied blocks per requestor 695system.l2c.tags.occ_blocks::cpu1.data 2063.107654 # Average occupied blocks per requestor 696system.l2c.tags.occ_percent::writebacks 0.613161 # Average percentage of cache occupancy 697system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 698system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 699system.l2c.tags.occ_percent::cpu0.inst 0.056620 # Average percentage of cache occupancy 700system.l2c.tags.occ_percent::cpu0.data 0.064752 # Average percentage of cache occupancy 701system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 702system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 703system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy 704system.l2c.tags.occ_percent::cpu1.data 0.031481 # Average percentage of cache occupancy 705system.l2c.tags.occ_percent::total 0.808922 # Average percentage of cache occupancy 706system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 707system.l2c.tags.occ_task_id_blocks::1024 65181 # Occupied blocks per task id 708system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 709system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 710system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 711system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id 712system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id 713system.l2c.tags.age_task_id_blocks_1024::3 8037 # Occupied blocks per task id 714system.l2c.tags.age_task_id_blocks_1024::4 55165 # Occupied blocks per task id 715system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 716system.l2c.tags.occ_task_id_percent::1024 0.994583 # Percentage of cache occupancy per task id 717system.l2c.tags.tag_accesses 17211018 # Number of tag accesses 718system.l2c.tags.data_accesses 17211018 # Number of data accesses 719system.l2c.ReadReq_hits::cpu0.dtb.walker 3808 # number of ReadReq hits 720system.l2c.ReadReq_hits::cpu0.itb.walker 1739 # number of ReadReq hits 721system.l2c.ReadReq_hits::cpu0.inst 419108 # number of ReadReq hits 722system.l2c.ReadReq_hits::cpu0.data 205927 # number of ReadReq hits 723system.l2c.ReadReq_hits::cpu1.dtb.walker 5506 # number of ReadReq hits 724system.l2c.ReadReq_hits::cpu1.itb.walker 1908 # number of ReadReq hits 725system.l2c.ReadReq_hits::cpu1.inst 464853 # number of ReadReq hits 726system.l2c.ReadReq_hits::cpu1.data 143402 # number of ReadReq hits 727system.l2c.ReadReq_hits::total 1246251 # number of ReadReq hits 728system.l2c.Writeback_hits::writebacks 571037 # number of Writeback hits 729system.l2c.Writeback_hits::total 571037 # number of Writeback hits 730system.l2c.UpgradeReq_hits::cpu0.data 1156 # number of UpgradeReq hits 731system.l2c.UpgradeReq_hits::cpu1.data 566 # number of UpgradeReq hits 732system.l2c.UpgradeReq_hits::total 1722 # number of UpgradeReq hits 733system.l2c.SCUpgradeReq_hits::cpu0.data 216 # number of SCUpgradeReq hits 734system.l2c.SCUpgradeReq_hits::cpu1.data 102 # number of SCUpgradeReq hits 735system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits 736system.l2c.ReadExReq_hits::cpu0.data 56302 # number of ReadExReq hits 737system.l2c.ReadExReq_hits::cpu1.data 52763 # number of ReadExReq hits 738system.l2c.ReadExReq_hits::total 109065 # number of ReadExReq hits 739system.l2c.demand_hits::cpu0.dtb.walker 3808 # number of demand (read+write) hits 740system.l2c.demand_hits::cpu0.itb.walker 1739 # number of demand (read+write) hits 741system.l2c.demand_hits::cpu0.inst 419108 # number of demand (read+write) hits 742system.l2c.demand_hits::cpu0.data 262229 # number of demand (read+write) hits 743system.l2c.demand_hits::cpu1.dtb.walker 5506 # number of demand (read+write) hits 744system.l2c.demand_hits::cpu1.itb.walker 1908 # number of demand (read+write) hits 745system.l2c.demand_hits::cpu1.inst 464853 # number of demand (read+write) hits 746system.l2c.demand_hits::cpu1.data 196165 # number of demand (read+write) hits 747system.l2c.demand_hits::total 1355316 # number of demand (read+write) hits 748system.l2c.overall_hits::cpu0.dtb.walker 3808 # number of overall hits 749system.l2c.overall_hits::cpu0.itb.walker 1739 # number of overall hits 750system.l2c.overall_hits::cpu0.inst 419108 # number of overall hits 751system.l2c.overall_hits::cpu0.data 262229 # number of overall hits 752system.l2c.overall_hits::cpu1.dtb.walker 5506 # number of overall hits 753system.l2c.overall_hits::cpu1.itb.walker 1908 # number of overall hits 754system.l2c.overall_hits::cpu1.inst 464853 # number of overall hits 755system.l2c.overall_hits::cpu1.data 196165 # number of overall hits 756system.l2c.overall_hits::total 1355316 # number of overall hits 757system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 758system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 759system.l2c.ReadReq_misses::cpu0.inst 5729 # number of ReadReq misses 760system.l2c.ReadReq_misses::cpu0.data 7851 # number of ReadReq misses 761system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 762system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 763system.l2c.ReadReq_misses::cpu1.inst 5067 # number of ReadReq misses 764system.l2c.ReadReq_misses::cpu1.data 3614 # number of ReadReq misses 765system.l2c.ReadReq_misses::total 22269 # number of ReadReq misses 766system.l2c.UpgradeReq_misses::cpu0.data 4919 # number of UpgradeReq misses 767system.l2c.UpgradeReq_misses::cpu1.data 3647 # number of UpgradeReq misses 768system.l2c.UpgradeReq_misses::total 8566 # number of UpgradeReq misses 769system.l2c.SCUpgradeReq_misses::cpu0.data 560 # number of SCUpgradeReq misses 770system.l2c.SCUpgradeReq_misses::cpu1.data 475 # number of SCUpgradeReq misses 771system.l2c.SCUpgradeReq_misses::total 1035 # number of SCUpgradeReq misses 772system.l2c.ReadExReq_misses::cpu0.data 67124 # number of ReadExReq misses 773system.l2c.ReadExReq_misses::cpu1.data 72582 # number of ReadExReq misses 774system.l2c.ReadExReq_misses::total 139706 # number of ReadExReq misses 775system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 776system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 777system.l2c.demand_misses::cpu0.inst 5729 # number of demand (read+write) misses 778system.l2c.demand_misses::cpu0.data 74975 # number of demand (read+write) misses 779system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses 780system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 781system.l2c.demand_misses::cpu1.inst 5067 # number of demand (read+write) misses 782system.l2c.demand_misses::cpu1.data 76196 # number of demand (read+write) misses 783system.l2c.demand_misses::total 161975 # number of demand (read+write) misses 784system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 785system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 786system.l2c.overall_misses::cpu0.inst 5729 # number of overall misses 787system.l2c.overall_misses::cpu0.data 74975 # number of overall misses 788system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses 789system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 790system.l2c.overall_misses::cpu1.inst 5067 # number of overall misses 791system.l2c.overall_misses::cpu1.data 76196 # number of overall misses 792system.l2c.overall_misses::total 161975 # number of overall misses 793system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles 794system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles 795system.l2c.ReadReq_miss_latency::cpu0.inst 409309750 # number of ReadReq miss cycles 796system.l2c.ReadReq_miss_latency::cpu0.data 588242499 # number of ReadReq miss cycles 797system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 347000 # number of ReadReq miss cycles 798system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles 799system.l2c.ReadReq_miss_latency::cpu1.inst 364513250 # number of ReadReq miss cycles 800system.l2c.ReadReq_miss_latency::cpu1.data 283018000 # number of ReadReq miss cycles 801system.l2c.ReadReq_miss_latency::total 1645686499 # number of ReadReq miss cycles 802system.l2c.UpgradeReq_miss_latency::cpu0.data 13362921 # number of UpgradeReq miss cycles 803system.l2c.UpgradeReq_miss_latency::cpu1.data 11997484 # number of UpgradeReq miss cycles 804system.l2c.UpgradeReq_miss_latency::total 25360405 # number of UpgradeReq miss cycles 805system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1671428 # number of SCUpgradeReq miss cycles 806system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2463894 # number of SCUpgradeReq miss cycles 807system.l2c.SCUpgradeReq_miss_latency::total 4135322 # number of SCUpgradeReq miss cycles 808system.l2c.ReadExReq_miss_latency::cpu0.data 4512260183 # number of ReadExReq miss cycles 809system.l2c.ReadExReq_miss_latency::cpu1.data 5472708624 # number of ReadExReq miss cycles 810system.l2c.ReadExReq_miss_latency::total 9984968807 # number of ReadExReq miss cycles 811system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles 812system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles 813system.l2c.demand_miss_latency::cpu0.inst 409309750 # number of demand (read+write) miss cycles 814system.l2c.demand_miss_latency::cpu0.data 5100502682 # number of demand (read+write) miss cycles 815system.l2c.demand_miss_latency::cpu1.dtb.walker 347000 # number of demand (read+write) miss cycles 816system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles 817system.l2c.demand_miss_latency::cpu1.inst 364513250 # number of demand (read+write) miss cycles 818system.l2c.demand_miss_latency::cpu1.data 5755726624 # number of demand (read+write) miss cycles 819system.l2c.demand_miss_latency::total 11630655306 # number of demand (read+write) miss cycles 820system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles 821system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles 822system.l2c.overall_miss_latency::cpu0.inst 409309750 # number of overall miss cycles 823system.l2c.overall_miss_latency::cpu0.data 5100502682 # number of overall miss cycles 824system.l2c.overall_miss_latency::cpu1.dtb.walker 347000 # number of overall miss cycles 825system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles 826system.l2c.overall_miss_latency::cpu1.inst 364513250 # number of overall miss cycles 827system.l2c.overall_miss_latency::cpu1.data 5755726624 # number of overall miss cycles 828system.l2c.overall_miss_latency::total 11630655306 # number of overall miss cycles 829system.l2c.ReadReq_accesses::cpu0.dtb.walker 3809 # number of ReadReq accesses(hits+misses) 830system.l2c.ReadReq_accesses::cpu0.itb.walker 1741 # number of ReadReq accesses(hits+misses) 831system.l2c.ReadReq_accesses::cpu0.inst 424837 # number of ReadReq accesses(hits+misses) 832system.l2c.ReadReq_accesses::cpu0.data 213778 # number of ReadReq accesses(hits+misses) 833system.l2c.ReadReq_accesses::cpu1.dtb.walker 5510 # number of ReadReq accesses(hits+misses) 834system.l2c.ReadReq_accesses::cpu1.itb.walker 1909 # number of ReadReq accesses(hits+misses) 835system.l2c.ReadReq_accesses::cpu1.inst 469920 # number of ReadReq accesses(hits+misses) 836system.l2c.ReadReq_accesses::cpu1.data 147016 # number of ReadReq accesses(hits+misses) 837system.l2c.ReadReq_accesses::total 1268520 # number of ReadReq accesses(hits+misses) 838system.l2c.Writeback_accesses::writebacks 571037 # number of Writeback accesses(hits+misses) 839system.l2c.Writeback_accesses::total 571037 # number of Writeback accesses(hits+misses) 840system.l2c.UpgradeReq_accesses::cpu0.data 6075 # number of UpgradeReq accesses(hits+misses) 841system.l2c.UpgradeReq_accesses::cpu1.data 4213 # number of UpgradeReq accesses(hits+misses) 842system.l2c.UpgradeReq_accesses::total 10288 # number of UpgradeReq accesses(hits+misses) 843system.l2c.SCUpgradeReq_accesses::cpu0.data 776 # number of SCUpgradeReq accesses(hits+misses) 844system.l2c.SCUpgradeReq_accesses::cpu1.data 577 # number of SCUpgradeReq accesses(hits+misses) 845system.l2c.SCUpgradeReq_accesses::total 1353 # number of SCUpgradeReq accesses(hits+misses) 846system.l2c.ReadExReq_accesses::cpu0.data 123426 # number of ReadExReq accesses(hits+misses) 847system.l2c.ReadExReq_accesses::cpu1.data 125345 # number of ReadExReq accesses(hits+misses) 848system.l2c.ReadExReq_accesses::total 248771 # number of ReadExReq accesses(hits+misses) 849system.l2c.demand_accesses::cpu0.dtb.walker 3809 # number of demand (read+write) accesses 850system.l2c.demand_accesses::cpu0.itb.walker 1741 # number of demand (read+write) accesses 851system.l2c.demand_accesses::cpu0.inst 424837 # number of demand (read+write) accesses 852system.l2c.demand_accesses::cpu0.data 337204 # number of demand (read+write) accesses 853system.l2c.demand_accesses::cpu1.dtb.walker 5510 # number of demand (read+write) accesses 854system.l2c.demand_accesses::cpu1.itb.walker 1909 # number of demand (read+write) accesses 855system.l2c.demand_accesses::cpu1.inst 469920 # number of demand (read+write) accesses 856system.l2c.demand_accesses::cpu1.data 272361 # number of demand (read+write) accesses 857system.l2c.demand_accesses::total 1517291 # number of demand (read+write) accesses 858system.l2c.overall_accesses::cpu0.dtb.walker 3809 # number of overall (read+write) accesses 859system.l2c.overall_accesses::cpu0.itb.walker 1741 # number of overall (read+write) accesses 860system.l2c.overall_accesses::cpu0.inst 424837 # number of overall (read+write) accesses 861system.l2c.overall_accesses::cpu0.data 337204 # number of overall (read+write) accesses 862system.l2c.overall_accesses::cpu1.dtb.walker 5510 # number of overall (read+write) accesses 863system.l2c.overall_accesses::cpu1.itb.walker 1909 # number of overall (read+write) accesses 864system.l2c.overall_accesses::cpu1.inst 469920 # number of overall (read+write) accesses 865system.l2c.overall_accesses::cpu1.data 272361 # number of overall (read+write) accesses 866system.l2c.overall_accesses::total 1517291 # number of overall (read+write) accesses 867system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000263 # miss rate for ReadReq accesses 868system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001149 # miss rate for ReadReq accesses 869system.l2c.ReadReq_miss_rate::cpu0.inst 0.013485 # miss rate for ReadReq accesses 870system.l2c.ReadReq_miss_rate::cpu0.data 0.036725 # miss rate for ReadReq accesses 871system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for ReadReq accesses 872system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000524 # miss rate for ReadReq accesses 873system.l2c.ReadReq_miss_rate::cpu1.inst 0.010783 # miss rate for ReadReq accesses 874system.l2c.ReadReq_miss_rate::cpu1.data 0.024582 # miss rate for ReadReq accesses 875system.l2c.ReadReq_miss_rate::total 0.017555 # miss rate for ReadReq accesses 876system.l2c.UpgradeReq_miss_rate::cpu0.data 0.809712 # miss rate for UpgradeReq accesses 877system.l2c.UpgradeReq_miss_rate::cpu1.data 0.865654 # miss rate for UpgradeReq accesses 878system.l2c.UpgradeReq_miss_rate::total 0.832621 # miss rate for UpgradeReq accesses 879system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.721649 # miss rate for SCUpgradeReq accesses 880system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.823224 # miss rate for SCUpgradeReq accesses 881system.l2c.SCUpgradeReq_miss_rate::total 0.764967 # miss rate for SCUpgradeReq accesses 882system.l2c.ReadExReq_miss_rate::cpu0.data 0.543840 # miss rate for ReadExReq accesses 883system.l2c.ReadExReq_miss_rate::cpu1.data 0.579058 # miss rate for ReadExReq accesses 884system.l2c.ReadExReq_miss_rate::total 0.561585 # miss rate for ReadExReq accesses 885system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000263 # miss rate for demand accesses 886system.l2c.demand_miss_rate::cpu0.itb.walker 0.001149 # miss rate for demand accesses 887system.l2c.demand_miss_rate::cpu0.inst 0.013485 # miss rate for demand accesses 888system.l2c.demand_miss_rate::cpu0.data 0.222343 # miss rate for demand accesses 889system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for demand accesses 890system.l2c.demand_miss_rate::cpu1.itb.walker 0.000524 # miss rate for demand accesses 891system.l2c.demand_miss_rate::cpu1.inst 0.010783 # miss rate for demand accesses 892system.l2c.demand_miss_rate::cpu1.data 0.279761 # miss rate for demand accesses 893system.l2c.demand_miss_rate::total 0.106753 # miss rate for demand accesses 894system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000263 # miss rate for overall accesses 895system.l2c.overall_miss_rate::cpu0.itb.walker 0.001149 # miss rate for overall accesses 896system.l2c.overall_miss_rate::cpu0.inst 0.013485 # miss rate for overall accesses 897system.l2c.overall_miss_rate::cpu0.data 0.222343 # miss rate for overall accesses 898system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000726 # miss rate for overall accesses 899system.l2c.overall_miss_rate::cpu1.itb.walker 0.000524 # miss rate for overall accesses 900system.l2c.overall_miss_rate::cpu1.inst 0.010783 # miss rate for overall accesses 901system.l2c.overall_miss_rate::cpu1.data 0.279761 # miss rate for overall accesses 902system.l2c.overall_miss_rate::total 0.106753 # miss rate for overall accesses 903system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 32000 # average ReadReq miss latency 904system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency 905system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71445.234770 # average ReadReq miss latency 906system.l2c.ReadReq_avg_miss_latency::cpu0.data 74925.805502 # average ReadReq miss latency 907system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86750 # average ReadReq miss latency 908system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency 909system.l2c.ReadReq_avg_miss_latency::cpu1.inst 71938.671798 # average ReadReq miss latency 910system.l2c.ReadReq_avg_miss_latency::cpu1.data 78311.566132 # average ReadReq miss latency 911system.l2c.ReadReq_avg_miss_latency::total 73900.332256 # average ReadReq miss latency 912system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2716.593007 # average UpgradeReq miss latency 913system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3289.685769 # average UpgradeReq miss latency 914system.l2c.UpgradeReq_avg_miss_latency::total 2960.588956 # average UpgradeReq miss latency 915system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2984.692857 # average SCUpgradeReq miss latency 916system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5187.145263 # average SCUpgradeReq miss latency 917system.l2c.SCUpgradeReq_avg_miss_latency::total 3995.480193 # average SCUpgradeReq miss latency 918system.l2c.ReadExReq_avg_miss_latency::cpu0.data 67222.754648 # average ReadExReq miss latency 919system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75400.355791 # average ReadExReq miss latency 920system.l2c.ReadExReq_avg_miss_latency::total 71471.295485 # average ReadExReq miss latency 921system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency 922system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 923system.l2c.demand_avg_miss_latency::cpu0.inst 71445.234770 # average overall miss latency 924system.l2c.demand_avg_miss_latency::cpu0.data 68029.378886 # average overall miss latency 925system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency 926system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 927system.l2c.demand_avg_miss_latency::cpu1.inst 71938.671798 # average overall miss latency 928system.l2c.demand_avg_miss_latency::cpu1.data 75538.435403 # average overall miss latency 929system.l2c.demand_avg_miss_latency::total 71805.249613 # average overall miss latency 930system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 32000 # average overall miss latency 931system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency 932system.l2c.overall_avg_miss_latency::cpu0.inst 71445.234770 # average overall miss latency 933system.l2c.overall_avg_miss_latency::cpu0.data 68029.378886 # average overall miss latency 934system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86750 # average overall miss latency 935system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency 936system.l2c.overall_avg_miss_latency::cpu1.inst 71938.671798 # average overall miss latency 937system.l2c.overall_avg_miss_latency::cpu1.data 75538.435403 # average overall miss latency 938system.l2c.overall_avg_miss_latency::total 71805.249613 # average overall miss latency 939system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 940system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 941system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 942system.l2c.blocked::no_targets 0 # number of cycles access was blocked 943system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 944system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 945system.l2c.fast_writes 0 # number of fast writes performed 946system.l2c.cache_copies 0 # number of cache copies performed 947system.l2c.writebacks::writebacks 64227 # number of writebacks 948system.l2c.writebacks::total 64227 # number of writebacks 949system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits 950system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 951system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 952system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 953system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 954system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits 955system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses 956system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses 957system.l2c.ReadReq_mshr_misses::cpu0.inst 5728 # number of ReadReq MSHR misses 958system.l2c.ReadReq_mshr_misses::cpu0.data 7851 # number of ReadReq MSHR misses 959system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses 960system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses 961system.l2c.ReadReq_mshr_misses::cpu1.inst 5067 # number of ReadReq MSHR misses 962system.l2c.ReadReq_mshr_misses::cpu1.data 3614 # number of ReadReq MSHR misses 963system.l2c.ReadReq_mshr_misses::total 22268 # number of ReadReq MSHR misses 964system.l2c.UpgradeReq_mshr_misses::cpu0.data 4919 # number of UpgradeReq MSHR misses 965system.l2c.UpgradeReq_mshr_misses::cpu1.data 3647 # number of UpgradeReq MSHR misses 966system.l2c.UpgradeReq_mshr_misses::total 8566 # number of UpgradeReq MSHR misses 967system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 560 # number of SCUpgradeReq MSHR misses 968system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 475 # number of SCUpgradeReq MSHR misses 969system.l2c.SCUpgradeReq_mshr_misses::total 1035 # number of SCUpgradeReq MSHR misses 970system.l2c.ReadExReq_mshr_misses::cpu0.data 67124 # number of ReadExReq MSHR misses 971system.l2c.ReadExReq_mshr_misses::cpu1.data 72582 # number of ReadExReq MSHR misses 972system.l2c.ReadExReq_mshr_misses::total 139706 # number of ReadExReq MSHR misses 973system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses 974system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 975system.l2c.demand_mshr_misses::cpu0.inst 5728 # number of demand (read+write) MSHR misses 976system.l2c.demand_mshr_misses::cpu0.data 74975 # number of demand (read+write) MSHR misses 977system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses 978system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses 979system.l2c.demand_mshr_misses::cpu1.inst 5067 # number of demand (read+write) MSHR misses 980system.l2c.demand_mshr_misses::cpu1.data 76196 # number of demand (read+write) MSHR misses 981system.l2c.demand_mshr_misses::total 161974 # number of demand (read+write) MSHR misses 982system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses 983system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 984system.l2c.overall_mshr_misses::cpu0.inst 5728 # number of overall MSHR misses 985system.l2c.overall_mshr_misses::cpu0.data 74975 # number of overall MSHR misses 986system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses 987system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses 988system.l2c.overall_mshr_misses::cpu1.inst 5067 # number of overall MSHR misses 989system.l2c.overall_mshr_misses::cpu1.data 76196 # number of overall MSHR misses 990system.l2c.overall_mshr_misses::total 161974 # number of overall MSHR misses 991system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 20000 # number of ReadReq MSHR miss cycles 992system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles 993system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 336674000 # number of ReadReq MSHR miss cycles 994system.l2c.ReadReq_mshr_miss_latency::cpu0.data 490296499 # number of ReadReq MSHR miss cycles 995system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 297000 # number of ReadReq MSHR miss cycles 996system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles 997system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300318250 # number of ReadReq MSHR miss cycles 998system.l2c.ReadReq_mshr_miss_latency::cpu1.data 238087000 # number of ReadReq MSHR miss cycles 999system.l2c.ReadReq_mshr_miss_latency::total 1365880249 # number of ReadReq MSHR miss cycles 1000system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 49210416 # number of UpgradeReq MSHR miss cycles 1001system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 36526138 # number of UpgradeReq MSHR miss cycles 1002system.l2c.UpgradeReq_mshr_miss_latency::total 85736554 # number of UpgradeReq MSHR miss cycles 1003system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5602558 # number of SCUpgradeReq MSHR miss cycles 1004system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4753973 # number of SCUpgradeReq MSHR miss cycles 1005system.l2c.SCUpgradeReq_mshr_miss_latency::total 10356531 # number of SCUpgradeReq MSHR miss cycles 1006system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3645878311 # number of ReadExReq MSHR miss cycles 1007system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4548664376 # number of ReadExReq MSHR miss cycles 1008system.l2c.ReadExReq_mshr_miss_latency::total 8194542687 # number of ReadExReq MSHR miss cycles 1009system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 20000 # number of demand (read+write) MSHR miss cycles 1010system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 1011system.l2c.demand_mshr_miss_latency::cpu0.inst 336674000 # number of demand (read+write) MSHR miss cycles 1012system.l2c.demand_mshr_miss_latency::cpu0.data 4136174810 # number of demand (read+write) MSHR miss cycles 1013system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 297000 # number of demand (read+write) MSHR miss cycles 1014system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles 1015system.l2c.demand_mshr_miss_latency::cpu1.inst 300318250 # number of demand (read+write) MSHR miss cycles 1016system.l2c.demand_mshr_miss_latency::cpu1.data 4786751376 # number of demand (read+write) MSHR miss cycles 1017system.l2c.demand_mshr_miss_latency::total 9560422936 # number of demand (read+write) MSHR miss cycles 1018system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 20000 # number of overall MSHR miss cycles 1019system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles 1020system.l2c.overall_mshr_miss_latency::cpu0.inst 336674000 # number of overall MSHR miss cycles 1021system.l2c.overall_mshr_miss_latency::cpu0.data 4136174810 # number of overall MSHR miss cycles 1022system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 297000 # number of overall MSHR miss cycles 1023system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles 1024system.l2c.overall_mshr_miss_latency::cpu1.inst 300318250 # number of overall MSHR miss cycles 1025system.l2c.overall_mshr_miss_latency::cpu1.data 4786751376 # number of overall MSHR miss cycles 1026system.l2c.overall_mshr_miss_latency::total 9560422936 # number of overall MSHR miss cycles 1027system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 345201250 # number of ReadReq MSHR uncacheable cycles 1028system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12449699492 # number of ReadReq MSHR uncacheable cycles 1029system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5636750 # number of ReadReq MSHR uncacheable cycles 1030system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154292835997 # number of ReadReq MSHR uncacheable cycles 1031system.l2c.ReadReq_mshr_uncacheable_latency::total 167093373489 # number of ReadReq MSHR uncacheable cycles 1032system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1043988495 # number of WriteReq MSHR uncacheable cycles 1033system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15722457655 # number of WriteReq MSHR uncacheable cycles 1034system.l2c.WriteReq_mshr_uncacheable_latency::total 16766446150 # number of WriteReq MSHR uncacheable cycles 1035system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 345201250 # number of overall MSHR uncacheable cycles 1036system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13493687987 # number of overall MSHR uncacheable cycles 1037system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5636750 # number of overall MSHR uncacheable cycles 1038system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170015293652 # number of overall MSHR uncacheable cycles 1039system.l2c.overall_mshr_uncacheable_latency::total 183859819639 # number of overall MSHR uncacheable cycles 1040system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for ReadReq accesses 1041system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for ReadReq accesses 1042system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for ReadReq accesses 1043system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036725 # mshr miss rate for ReadReq accesses 1044system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for ReadReq accesses 1045system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for ReadReq accesses 1046system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for ReadReq accesses 1047system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for ReadReq accesses 1048system.l2c.ReadReq_mshr_miss_rate::total 0.017554 # mshr miss rate for ReadReq accesses 1049system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.809712 # mshr miss rate for UpgradeReq accesses 1050system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.865654 # mshr miss rate for UpgradeReq accesses 1051system.l2c.UpgradeReq_mshr_miss_rate::total 0.832621 # mshr miss rate for UpgradeReq accesses 1052system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.721649 # mshr miss rate for SCUpgradeReq accesses 1053system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.823224 # mshr miss rate for SCUpgradeReq accesses 1054system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for SCUpgradeReq accesses 1055system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.543840 # mshr miss rate for ReadExReq accesses 1056system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.579058 # mshr miss rate for ReadExReq accesses 1057system.l2c.ReadExReq_mshr_miss_rate::total 0.561585 # mshr miss rate for ReadExReq accesses 1058system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for demand accesses 1059system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for demand accesses 1060system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for demand accesses 1061system.l2c.demand_mshr_miss_rate::cpu0.data 0.222343 # mshr miss rate for demand accesses 1062system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for demand accesses 1063system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for demand accesses 1064system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for demand accesses 1065system.l2c.demand_mshr_miss_rate::cpu1.data 0.279761 # mshr miss rate for demand accesses 1066system.l2c.demand_mshr_miss_rate::total 0.106752 # mshr miss rate for demand accesses 1067system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000263 # mshr miss rate for overall accesses 1068system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001149 # mshr miss rate for overall accesses 1069system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013483 # mshr miss rate for overall accesses 1070system.l2c.overall_mshr_miss_rate::cpu0.data 0.222343 # mshr miss rate for overall accesses 1071system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000726 # mshr miss rate for overall accesses 1072system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000524 # mshr miss rate for overall accesses 1073system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010783 # mshr miss rate for overall accesses 1074system.l2c.overall_mshr_miss_rate::cpu1.data 0.279761 # mshr miss rate for overall accesses 1075system.l2c.overall_mshr_miss_rate::total 0.106752 # mshr miss rate for overall accesses 1076system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average ReadReq mshr miss latency 1077system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency 1078system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average ReadReq mshr miss latency 1079system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62450.197300 # average ReadReq mshr miss latency 1080system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average ReadReq mshr miss latency 1081system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency 1082system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average ReadReq mshr miss latency 1083system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65879.081350 # average ReadReq mshr miss latency 1084system.l2c.ReadReq_avg_mshr_miss_latency::total 61338.254401 # average ReadReq mshr miss latency 1085system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.150437 # average UpgradeReq mshr miss latency 1086system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.392926 # average UpgradeReq mshr miss latency 1087system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.936960 # average UpgradeReq mshr miss latency 1088system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.567857 # average SCUpgradeReq mshr miss latency 1089system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.364211 # average SCUpgradeReq mshr miss latency 1090system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10006.310145 # average SCUpgradeReq mshr miss latency 1091system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54315.569856 # average ReadExReq mshr miss latency 1092system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62669.317131 # average ReadExReq mshr miss latency 1093system.l2c.ReadExReq_avg_mshr_miss_latency::total 58655.624576 # average ReadExReq mshr miss latency 1094system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 1095system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 1096system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency 1097system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency 1098system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency 1099system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 1100system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency 1101system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency 1102system.l2c.demand_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency 1103system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency 1104system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency 1105system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58776.885475 # average overall mshr miss latency 1106system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55167.386596 # average overall mshr miss latency 1107system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74250 # average overall mshr miss latency 1108system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency 1109system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59269.439511 # average overall mshr miss latency 1110system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62821.557247 # average overall mshr miss latency 1111system.l2c.overall_avg_mshr_miss_latency::total 59024.429452 # average overall mshr miss latency 1112system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1113system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1114system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1115system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1116system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1117system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1118system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1119system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1120system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1121system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1122system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1123system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1124system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1125system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1126system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1127system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1128system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1129system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 1130system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 1131system.cf0.dma_write_txs 0 # Number of DMA write transactions. 1132system.toL2Bus.throughput 119505667 # Throughput (bytes/s) 1133system.toL2Bus.trans_dist::ReadReq 2535246 # Transaction distribution 1134system.toL2Bus.trans_dist::ReadResp 2535246 # Transaction distribution 1135system.toL2Bus.trans_dist::WriteReq 767572 # Transaction distribution 1136system.toL2Bus.trans_dist::WriteResp 767572 # Transaction distribution 1137system.toL2Bus.trans_dist::Writeback 571037 # Transaction distribution 1138system.toL2Bus.trans_dist::UpgradeReq 30983 # Transaction distribution 1139system.toL2Bus.trans_dist::SCUpgradeReq 17532 # Transaction distribution 1140system.toL2Bus.trans_dist::UpgradeResp 48515 # Transaction distribution 1141system.toL2Bus.trans_dist::ReadExReq 260644 # Transaction distribution 1142system.toL2Bus.trans_dist::ReadExResp 260644 # Transaction distribution 1143system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863518 # Packet count per connected master and slave (bytes) 1144system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226193 # Packet count per connected master and slave (bytes) 1145system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) 1146system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12684 # Packet count per connected master and slave (bytes) 1147system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940579 # Packet count per connected master and slave (bytes) 1148system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601780 # Packet count per connected master and slave (bytes) 1149system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6235 # Packet count per connected master and slave (bytes) 1150system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15427 # Packet count per connected master and slave (bytes) 1151system.toL2Bus.pkt_count::total 7672553 # Packet count per connected master and slave (bytes) 1152system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27216160 # Cumulative packet size per connected master and slave (bytes) 1153system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41363346 # Cumulative packet size per connected master and slave (bytes) 1154system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) 1155system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15236 # Cumulative packet size per connected master and slave (bytes) 1156system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30075316 # Cumulative packet size per connected master and slave (bytes) 1157system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39635324 # Cumulative packet size per connected master and slave (bytes) 1158system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7636 # Cumulative packet size per connected master and slave (bytes) 1159system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22040 # Cumulative packet size per connected master and slave (bytes) 1160system.toL2Bus.tot_pkt_size::total 138342022 # Cumulative packet size per connected master and slave (bytes) 1161system.toL2Bus.data_through_bus 138342022 # Total data (bytes) 1162system.toL2Bus.snoop_data_through_bus 4603396 # Total snoop data (bytes) 1163system.toL2Bus.reqLayer0.occupancy 4759597686 # Layer occupancy (ticks) 1164system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 1165system.toL2Bus.respLayer0.occupancy 1923628472 # Layer occupancy (ticks) 1166system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 1167system.toL2Bus.respLayer1.occupancy 1753100289 # Layer occupancy (ticks) 1168system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1169system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) 1170system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1171system.toL2Bus.respLayer3.occupancy 8875000 # Layer occupancy (ticks) 1172system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1173system.toL2Bus.respLayer6.occupancy 2118090473 # Layer occupancy (ticks) 1174system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) 1175system.toL2Bus.respLayer7.occupancy 2927544636 # Layer occupancy (ticks) 1176system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) 1177system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) 1178system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) 1179system.toL2Bus.respLayer9.occupancy 9917499 # Layer occupancy (ticks) 1180system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) 1181system.iobus.throughput 45391376 # Throughput (bytes/s) 1182system.iobus.trans_dist::ReadReq 7671402 # Transaction distribution 1183system.iobus.trans_dist::ReadResp 7671402 # Transaction distribution 1184system.iobus.trans_dist::WriteReq 7950 # Transaction distribution 1185system.iobus.trans_dist::WriteResp 7950 # Transaction distribution 1186system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) 1187system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) 1188system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1189system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) 1190system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 1191system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1192system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) 1193system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 1194system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 1195system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1196system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1197system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1198system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 1199system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 1200system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1201system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 1202system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 1203system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 1204system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 1205system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 1206system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1207system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1208system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1209system.iobus.pkt_count_system.bridge.master::total 2382576 # Packet count per connected master and slave (bytes) 1210system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) 1211system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) 1212system.iobus.pkt_count::total 15358704 # Packet count per connected master and slave (bytes) 1213system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) 1217system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 1218system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1219system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) 1220system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 1221system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1222system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1223system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1224system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1225system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1226system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 1227system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1228system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1229system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1230system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1231system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1232system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1233system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1234system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1235system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1236system.iobus.tot_pkt_size_system.bridge.master::total 2389894 # Cumulative packet size per connected master and slave (bytes) 1237system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) 1238system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) 1239system.iobus.tot_pkt_size::total 54294406 # Cumulative packet size per connected master and slave (bytes) 1240system.iobus.data_through_bus 54294406 # Total data (bytes) 1241system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) 1242system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1243system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) 1244system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1245system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) 1246system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1247system.iobus.reqLayer3.occupancy 377000 # Layer occupancy (ticks) 1248system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1249system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) 1250system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1251system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) 1252system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1253system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) 1254system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1255system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) 1256system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) 1257system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) 1258system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1259system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1260system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1261system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) 1262system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1263system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) 1264system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 1265system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1266system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1267system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) 1268system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1269system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1270system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1271system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) 1272system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1273system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1274system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1275system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1276system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1277system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) 1278system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1279system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1280system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1281system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1282system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1283system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 1284system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 1285system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 1286system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1287system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) 1288system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) 1289system.iobus.respLayer0.occupancy 2374626000 # Layer occupancy (ticks) 1290system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) 1291system.iobus.respLayer1.occupancy 17778333501 # Layer occupancy (ticks) 1292system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) 1293system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1294system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1295system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1296system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1297system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1298system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1299system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1300system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1301system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1302system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1303system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1304system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1305system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1306system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1307system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1308system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1309system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1310system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1311system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1312system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1313system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1314system.cpu0.dtb.inst_hits 0 # ITB inst hits 1315system.cpu0.dtb.inst_misses 0 # ITB inst misses 1316system.cpu0.dtb.read_hits 7064121 # DTB read hits 1317system.cpu0.dtb.read_misses 3756 # DTB read misses 1318system.cpu0.dtb.write_hits 5649416 # DTB write hits 1319system.cpu0.dtb.write_misses 801 # DTB write misses 1320system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1321system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1322system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1323system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1324system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB 1325system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1326system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch 1327system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1328system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 1329system.cpu0.dtb.read_accesses 7067877 # DTB read accesses 1330system.cpu0.dtb.write_accesses 5650217 # DTB write accesses 1331system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 1332system.cpu0.dtb.hits 12713537 # DTB hits 1333system.cpu0.dtb.misses 4557 # DTB misses 1334system.cpu0.dtb.accesses 12718094 # DTB accesses 1335system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1336system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1337system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1338system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1339system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1340system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1341system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1342system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1343system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1344system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1345system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1346system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1347system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1348system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1349system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1350system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1351system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1352system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1353system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1354system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1355system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1356system.cpu0.itb.inst_hits 29561361 # ITB inst hits 1357system.cpu0.itb.inst_misses 2205 # ITB inst misses 1358system.cpu0.itb.read_hits 0 # DTB read hits 1359system.cpu0.itb.read_misses 0 # DTB read misses 1360system.cpu0.itb.write_hits 0 # DTB write hits 1361system.cpu0.itb.write_misses 0 # DTB write misses 1362system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 1363system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1364system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1365system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1366system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB 1367system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1368system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1369system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1370system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1371system.cpu0.itb.read_accesses 0 # DTB read accesses 1372system.cpu0.itb.write_accesses 0 # DTB write accesses 1373system.cpu0.itb.inst_accesses 29563566 # ITB inst accesses 1374system.cpu0.itb.hits 29561361 # DTB hits 1375system.cpu0.itb.misses 2205 # DTB misses 1376system.cpu0.itb.accesses 29563566 # DTB accesses 1377system.cpu0.numCycles 2392278482 # number of cpu cycles simulated 1378system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 1379system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 1380system.cpu0.committedInsts 28863304 # Number of instructions committed 1381system.cpu0.committedOps 37189208 # Number of ops (including micro ops) committed 1382system.cpu0.num_int_alu_accesses 33114268 # Number of integer alu accesses 1383system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 1384system.cpu0.num_func_calls 1241816 # number of times a function call or return occured 1385system.cpu0.num_conditional_control_insts 4372124 # number of instructions that are conditional controls 1386system.cpu0.num_int_insts 33114268 # number of integer instructions 1387system.cpu0.num_fp_insts 3860 # number of float instructions 1388system.cpu0.num_int_register_reads 192166322 # number of times the integer registers were read 1389system.cpu0.num_int_register_writes 36246326 # number of times the integer registers were written 1390system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 1391system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 1392system.cpu0.num_mem_refs 13380719 # number of memory refs 1393system.cpu0.num_load_insts 7401377 # Number of load instructions 1394system.cpu0.num_store_insts 5979342 # Number of store instructions 1395system.cpu0.num_idle_cycles 2246536230.490122 # Number of idle cycles 1396system.cpu0.num_busy_cycles 145742251.509878 # Number of busy cycles 1397system.cpu0.not_idle_fraction 0.060922 # Percentage of non-idle cycles 1398system.cpu0.idle_fraction 0.939078 # Percentage of idle cycles
	1399system.cpu0.Branches 5599941 # Number of branches fetched
1399system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1400system.cpu0.kern.inst.quiesce 46939 # number of quiesce instructions executed 1401system.cpu0.icache.tags.replacements 424872 # number of replacements 1402system.cpu0.icache.tags.tagsinuse 509.359183 # Cycle average of tags in use 1403system.cpu0.icache.tags.total_refs 29135959 # Total number of references to valid blocks. 1404system.cpu0.icache.tags.sampled_refs 425384 # Sample count of references to valid blocks. 1405system.cpu0.icache.tags.avg_refs 68.493312 # Average number of references to valid blocks. 1406system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit. 1407system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359183 # Average occupied blocks per requestor 1408system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994842 # Average percentage of cache occupancy 1409system.cpu0.icache.tags.occ_percent::total 0.994842 # Average percentage of cache occupancy 1410system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1411system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 1412system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id 1413system.cpu0.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id 1414system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 1415system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1416system.cpu0.icache.tags.tag_accesses 29986729 # Number of tag accesses 1417system.cpu0.icache.tags.data_accesses 29986729 # Number of data accesses 1418system.cpu0.icache.ReadReq_hits::cpu0.inst 29135959 # number of ReadReq hits 1419system.cpu0.icache.ReadReq_hits::total 29135959 # number of ReadReq hits 1420system.cpu0.icache.demand_hits::cpu0.inst 29135959 # number of demand (read+write) hits 1421system.cpu0.icache.demand_hits::total 29135959 # number of demand (read+write) hits 1422system.cpu0.icache.overall_hits::cpu0.inst 29135959 # number of overall hits 1423system.cpu0.icache.overall_hits::total 29135959 # number of overall hits 1424system.cpu0.icache.ReadReq_misses::cpu0.inst 425385 # number of ReadReq misses 1425system.cpu0.icache.ReadReq_misses::total 425385 # number of ReadReq misses 1426system.cpu0.icache.demand_misses::cpu0.inst 425385 # number of demand (read+write) misses 1427system.cpu0.icache.demand_misses::total 425385 # number of demand (read+write) misses 1428system.cpu0.icache.overall_misses::cpu0.inst 425385 # number of overall misses 1429system.cpu0.icache.overall_misses::total 425385 # number of overall misses 1430system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5898245722 # number of ReadReq miss cycles 1431system.cpu0.icache.ReadReq_miss_latency::total 5898245722 # number of ReadReq miss cycles 1432system.cpu0.icache.demand_miss_latency::cpu0.inst 5898245722 # number of demand (read+write) miss cycles 1433system.cpu0.icache.demand_miss_latency::total 5898245722 # number of demand (read+write) miss cycles 1434system.cpu0.icache.overall_miss_latency::cpu0.inst 5898245722 # number of overall miss cycles 1435system.cpu0.icache.overall_miss_latency::total 5898245722 # number of overall miss cycles 1436system.cpu0.icache.ReadReq_accesses::cpu0.inst 29561344 # number of ReadReq accesses(hits+misses) 1437system.cpu0.icache.ReadReq_accesses::total 29561344 # number of ReadReq accesses(hits+misses) 1438system.cpu0.icache.demand_accesses::cpu0.inst 29561344 # number of demand (read+write) accesses 1439system.cpu0.icache.demand_accesses::total 29561344 # number of demand (read+write) accesses 1440system.cpu0.icache.overall_accesses::cpu0.inst 29561344 # number of overall (read+write) accesses 1441system.cpu0.icache.overall_accesses::total 29561344 # number of overall (read+write) accesses 1442system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014390 # miss rate for ReadReq accesses 1443system.cpu0.icache.ReadReq_miss_rate::total 0.014390 # miss rate for ReadReq accesses 1444system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014390 # miss rate for demand accesses 1445system.cpu0.icache.demand_miss_rate::total 0.014390 # miss rate for demand accesses 1446system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014390 # miss rate for overall accesses 1447system.cpu0.icache.overall_miss_rate::total 0.014390 # miss rate for overall accesses 1448system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13865.664567 # average ReadReq miss latency 1449system.cpu0.icache.ReadReq_avg_miss_latency::total 13865.664567 # average ReadReq miss latency 1450system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency 1451system.cpu0.icache.demand_avg_miss_latency::total 13865.664567 # average overall miss latency 1452system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency 1453system.cpu0.icache.overall_avg_miss_latency::total 13865.664567 # average overall miss latency 1454system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1455system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1456system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1457system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1458system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1459system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1460system.cpu0.icache.fast_writes 0 # number of fast writes performed 1461system.cpu0.icache.cache_copies 0 # number of cache copies performed 1462system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425385 # number of ReadReq MSHR misses 1463system.cpu0.icache.ReadReq_mshr_misses::total 425385 # number of ReadReq MSHR misses 1464system.cpu0.icache.demand_mshr_misses::cpu0.inst 425385 # number of demand (read+write) MSHR misses 1465system.cpu0.icache.demand_mshr_misses::total 425385 # number of demand (read+write) MSHR misses 1466system.cpu0.icache.overall_mshr_misses::cpu0.inst 425385 # number of overall MSHR misses 1467system.cpu0.icache.overall_mshr_misses::total 425385 # number of overall MSHR misses 1468system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045266278 # number of ReadReq MSHR miss cycles 1469system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045266278 # number of ReadReq MSHR miss cycles 1470system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045266278 # number of demand (read+write) MSHR miss cycles 1471system.cpu0.icache.demand_mshr_miss_latency::total 5045266278 # number of demand (read+write) MSHR miss cycles 1472system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045266278 # number of overall MSHR miss cycles 1473system.cpu0.icache.overall_mshr_miss_latency::total 5045266278 # number of overall MSHR miss cycles 1474system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 437016250 # number of ReadReq MSHR uncacheable cycles 1475system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles 1476system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 437016250 # number of overall MSHR uncacheable cycles 1477system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles 1478system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for ReadReq accesses 1479system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014390 # mshr miss rate for ReadReq accesses 1480system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for demand accesses 1481system.cpu0.icache.demand_mshr_miss_rate::total 0.014390 # mshr miss rate for demand accesses 1482system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for overall accesses 1483system.cpu0.icache.overall_mshr_miss_rate::total 0.014390 # mshr miss rate for overall accesses 1484system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average ReadReq mshr miss latency 1485system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11860.470581 # average ReadReq mshr miss latency 1486system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency 1487system.cpu0.icache.demand_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency 1488system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency 1489system.cpu0.icache.overall_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency 1490system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1491system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1492system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1493system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1494system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1495system.cpu0.dcache.tags.replacements 329699 # number of replacements 1496system.cpu0.dcache.tags.tagsinuse 455.775151 # Cycle average of tags in use 1497system.cpu0.dcache.tags.total_refs 12258801 # Total number of references to valid blocks. 1498system.cpu0.dcache.tags.sampled_refs 330211 # Sample count of references to valid blocks. 1499system.cpu0.dcache.tags.avg_refs 37.124145 # Average number of references to valid blocks. 1500system.cpu0.dcache.tags.warmup_cycle 667204250 # Cycle when the warmup percentage was hit. 1501system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.775151 # Average occupied blocks per requestor 1502system.cpu0.dcache.tags.occ_percent::cpu0.data 0.890186 # Average percentage of cache occupancy 1503system.cpu0.dcache.tags.occ_percent::total 0.890186 # Average percentage of cache occupancy 1504system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1505system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 1506system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 1507system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 1508system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1509system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1510system.cpu0.dcache.tags.tag_accesses 50852132 # Number of tag accesses 1511system.cpu0.dcache.tags.data_accesses 50852132 # Number of data accesses 1512system.cpu0.dcache.ReadReq_hits::cpu0.data 6594161 # number of ReadReq hits 1513system.cpu0.dcache.ReadReq_hits::total 6594161 # number of ReadReq hits 1514system.cpu0.dcache.WriteReq_hits::cpu0.data 5344638 # number of WriteReq hits 1515system.cpu0.dcache.WriteReq_hits::total 5344638 # number of WriteReq hits 1516system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148004 # number of LoadLockedReq hits 1517system.cpu0.dcache.LoadLockedReq_hits::total 148004 # number of LoadLockedReq hits 1518system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149654 # number of StoreCondReq hits 1519system.cpu0.dcache.StoreCondReq_hits::total 149654 # number of StoreCondReq hits 1520system.cpu0.dcache.demand_hits::cpu0.data 11938799 # number of demand (read+write) hits 1521system.cpu0.dcache.demand_hits::total 11938799 # number of demand (read+write) hits 1522system.cpu0.dcache.overall_hits::cpu0.data 11938799 # number of overall hits 1523system.cpu0.dcache.overall_hits::total 11938799 # number of overall hits 1524system.cpu0.dcache.ReadReq_misses::cpu0.data 227537 # number of ReadReq misses 1525system.cpu0.dcache.ReadReq_misses::total 227537 # number of ReadReq misses 1526system.cpu0.dcache.WriteReq_misses::cpu0.data 141373 # number of WriteReq misses 1527system.cpu0.dcache.WriteReq_misses::total 141373 # number of WriteReq misses 1528system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9339 # number of LoadLockedReq misses 1529system.cpu0.dcache.LoadLockedReq_misses::total 9339 # number of LoadLockedReq misses 1530system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7481 # number of StoreCondReq misses 1531system.cpu0.dcache.StoreCondReq_misses::total 7481 # number of StoreCondReq misses 1532system.cpu0.dcache.demand_misses::cpu0.data 368910 # number of demand (read+write) misses 1533system.cpu0.dcache.demand_misses::total 368910 # number of demand (read+write) misses 1534system.cpu0.dcache.overall_misses::cpu0.data 368910 # number of overall misses 1535system.cpu0.dcache.overall_misses::total 368910 # number of overall misses 1536system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3307426746 # number of ReadReq miss cycles 1537system.cpu0.dcache.ReadReq_miss_latency::total 3307426746 # number of ReadReq miss cycles 1538system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5667209233 # number of WriteReq miss cycles 1539system.cpu0.dcache.WriteReq_miss_latency::total 5667209233 # number of WriteReq miss cycles 1540system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93091750 # number of LoadLockedReq miss cycles 1541system.cpu0.dcache.LoadLockedReq_miss_latency::total 93091750 # number of LoadLockedReq miss cycles 1542system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44245560 # number of StoreCondReq miss cycles 1543system.cpu0.dcache.StoreCondReq_miss_latency::total 44245560 # number of StoreCondReq miss cycles 1544system.cpu0.dcache.demand_miss_latency::cpu0.data 8974635979 # number of demand (read+write) miss cycles 1545system.cpu0.dcache.demand_miss_latency::total 8974635979 # number of demand (read+write) miss cycles 1546system.cpu0.dcache.overall_miss_latency::cpu0.data 8974635979 # number of overall miss cycles 1547system.cpu0.dcache.overall_miss_latency::total 8974635979 # number of overall miss cycles 1548system.cpu0.dcache.ReadReq_accesses::cpu0.data 6821698 # number of ReadReq accesses(hits+misses) 1549system.cpu0.dcache.ReadReq_accesses::total 6821698 # number of ReadReq accesses(hits+misses) 1550system.cpu0.dcache.WriteReq_accesses::cpu0.data 5486011 # number of WriteReq accesses(hits+misses) 1551system.cpu0.dcache.WriteReq_accesses::total 5486011 # number of WriteReq accesses(hits+misses) 1552system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157343 # number of LoadLockedReq accesses(hits+misses) 1553system.cpu0.dcache.LoadLockedReq_accesses::total 157343 # number of LoadLockedReq accesses(hits+misses) 1554system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157135 # number of StoreCondReq accesses(hits+misses) 1555system.cpu0.dcache.StoreCondReq_accesses::total 157135 # number of StoreCondReq accesses(hits+misses) 1556system.cpu0.dcache.demand_accesses::cpu0.data 12307709 # number of demand (read+write) accesses 1557system.cpu0.dcache.demand_accesses::total 12307709 # number of demand (read+write) accesses 1558system.cpu0.dcache.overall_accesses::cpu0.data 12307709 # number of overall (read+write) accesses 1559system.cpu0.dcache.overall_accesses::total 12307709 # number of overall (read+write) accesses 1560system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033355 # miss rate for ReadReq accesses 1561system.cpu0.dcache.ReadReq_miss_rate::total 0.033355 # miss rate for ReadReq accesses 1562system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025770 # miss rate for WriteReq accesses 1563system.cpu0.dcache.WriteReq_miss_rate::total 0.025770 # miss rate for WriteReq accesses 1564system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059354 # miss rate for LoadLockedReq accesses 1565system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059354 # miss rate for LoadLockedReq accesses 1566system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047609 # miss rate for StoreCondReq accesses 1567system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047609 # miss rate for StoreCondReq accesses 1568system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029974 # miss rate for demand accesses 1569system.cpu0.dcache.demand_miss_rate::total 0.029974 # miss rate for demand accesses 1570system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029974 # miss rate for overall accesses 1571system.cpu0.dcache.overall_miss_rate::total 0.029974 # miss rate for overall accesses 1572system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14535.775483 # average ReadReq miss latency 1573system.cpu0.dcache.ReadReq_avg_miss_latency::total 14535.775483 # average ReadReq miss latency 1574system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40086.927723 # average WriteReq miss latency 1575system.cpu0.dcache.WriteReq_avg_miss_latency::total 40086.927723 # average WriteReq miss latency 1576system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.064033 # average LoadLockedReq miss latency 1577system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.064033 # average LoadLockedReq miss latency 1578system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5914.391124 # average StoreCondReq miss latency 1579system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5914.391124 # average StoreCondReq miss latency 1580system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency 1581system.cpu0.dcache.demand_avg_miss_latency::total 24327.440240 # average overall miss latency 1582system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency 1583system.cpu0.dcache.overall_avg_miss_latency::total 24327.440240 # average overall miss latency 1584system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1585system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1586system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1587system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1588system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1589system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1590system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1591system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1592system.cpu0.dcache.writebacks::writebacks 305670 # number of writebacks 1593system.cpu0.dcache.writebacks::total 305670 # number of writebacks 1594system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227537 # number of ReadReq MSHR misses 1595system.cpu0.dcache.ReadReq_mshr_misses::total 227537 # number of ReadReq MSHR misses 1596system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141373 # number of WriteReq MSHR misses 1597system.cpu0.dcache.WriteReq_mshr_misses::total 141373 # number of WriteReq MSHR misses 1598system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9339 # number of LoadLockedReq MSHR misses 1599system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9339 # number of LoadLockedReq MSHR misses 1600system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7479 # number of StoreCondReq MSHR misses 1601system.cpu0.dcache.StoreCondReq_mshr_misses::total 7479 # number of StoreCondReq MSHR misses 1602system.cpu0.dcache.demand_mshr_misses::cpu0.data 368910 # number of demand (read+write) MSHR misses 1603system.cpu0.dcache.demand_mshr_misses::total 368910 # number of demand (read+write) MSHR misses 1604system.cpu0.dcache.overall_mshr_misses::cpu0.data 368910 # number of overall MSHR misses 1605system.cpu0.dcache.overall_mshr_misses::total 368910 # number of overall MSHR misses 1606system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2850420254 # number of ReadReq MSHR miss cycles 1607system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2850420254 # number of ReadReq MSHR miss cycles 1608system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5353542767 # number of WriteReq MSHR miss cycles 1609system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5353542767 # number of WriteReq MSHR miss cycles 1610system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 74365250 # number of LoadLockedReq MSHR miss cycles 1611system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74365250 # number of LoadLockedReq MSHR miss cycles 1612system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29286440 # number of StoreCondReq MSHR miss cycles 1613system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29286440 # number of StoreCondReq MSHR miss cycles 1614system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8203963021 # number of demand (read+write) MSHR miss cycles 1615system.cpu0.dcache.demand_mshr_miss_latency::total 8203963021 # number of demand (read+write) MSHR miss cycles 1616system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8203963021 # number of overall MSHR miss cycles 1617system.cpu0.dcache.overall_mshr_miss_latency::total 8203963021 # number of overall MSHR miss cycles 1618system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13556999000 # number of ReadReq MSHR uncacheable cycles 1619system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13556999000 # number of ReadReq MSHR uncacheable cycles 1620system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167889500 # number of WriteReq MSHR uncacheable cycles 1621system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167889500 # number of WriteReq MSHR uncacheable cycles 1622system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14724888500 # number of overall MSHR uncacheable cycles 1623system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14724888500 # number of overall MSHR uncacheable cycles 1624system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033355 # mshr miss rate for ReadReq accesses 1625system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033355 # mshr miss rate for ReadReq accesses 1626system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025770 # mshr miss rate for WriteReq accesses 1627system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025770 # mshr miss rate for WriteReq accesses 1628system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059354 # mshr miss rate for LoadLockedReq accesses 1629system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059354 # mshr miss rate for LoadLockedReq accesses 1630system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047596 # mshr miss rate for StoreCondReq accesses 1631system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047596 # mshr miss rate for StoreCondReq accesses 1632system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for demand accesses 1633system.cpu0.dcache.demand_mshr_miss_rate::total 0.029974 # mshr miss rate for demand accesses 1634system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for overall accesses 1635system.cpu0.dcache.overall_mshr_miss_rate::total 0.029974 # mshr miss rate for overall accesses 1636system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12527.282394 # average ReadReq mshr miss latency 1637system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12527.282394 # average ReadReq mshr miss latency 1638system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37868.212226 # average WriteReq mshr miss latency 1639system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37868.212226 # average WriteReq mshr miss latency 1640system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7962.870757 # average LoadLockedReq mshr miss latency 1641system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7962.870757 # average LoadLockedReq mshr miss latency 1642system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.822971 # average StoreCondReq mshr miss latency 1643system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.822971 # average StoreCondReq mshr miss latency 1644system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency 1645system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency 1646system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency 1647system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency 1648system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1649system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1650system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1651system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1652system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1653system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1654system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1655system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1656system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1657system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1658system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1659system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1660system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1661system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1662system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1663system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1664system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1665system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1666system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1667system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1668system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1669system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1670system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1671system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1672system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1673system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1674system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1675system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1676system.cpu1.dtb.inst_hits 0 # ITB inst hits 1677system.cpu1.dtb.inst_misses 0 # ITB inst misses 1678system.cpu1.dtb.read_hits 8319266 # DTB read hits 1679system.cpu1.dtb.read_misses 3647 # DTB read misses 1680system.cpu1.dtb.write_hits 5834802 # DTB write hits 1681system.cpu1.dtb.write_misses 1433 # DTB write misses 1682system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1683system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1684system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1685system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1686system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB 1687system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1688system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch 1689system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1690system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 1691system.cpu1.dtb.read_accesses 8322913 # DTB read accesses 1692system.cpu1.dtb.write_accesses 5836235 # DTB write accesses 1693system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1694system.cpu1.dtb.hits 14154068 # DTB hits 1695system.cpu1.dtb.misses 5080 # DTB misses 1696system.cpu1.dtb.accesses 14159148 # DTB accesses 1697system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1698system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1699system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1700system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1701system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1702system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1703system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1704system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1705system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1706system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1707system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1708system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1709system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1710system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1711system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1712system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1713system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1714system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1715system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1716system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1717system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1718system.cpu1.itb.inst_hits 33207997 # ITB inst hits 1719system.cpu1.itb.inst_misses 2171 # ITB inst misses 1720system.cpu1.itb.read_hits 0 # DTB read hits 1721system.cpu1.itb.read_misses 0 # DTB read misses 1722system.cpu1.itb.write_hits 0 # DTB write hits 1723system.cpu1.itb.write_misses 0 # DTB write misses 1724system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1725system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1726system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1727system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1728system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB 1729system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1730system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1731system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1732system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1733system.cpu1.itb.read_accesses 0 # DTB read accesses 1734system.cpu1.itb.write_accesses 0 # DTB write accesses 1735system.cpu1.itb.inst_accesses 33210168 # ITB inst accesses 1736system.cpu1.itb.hits 33207997 # DTB hits 1737system.cpu1.itb.misses 2171 # DTB misses 1738system.cpu1.itb.accesses 33210168 # DTB accesses 1739system.cpu1.numCycles 2390803785 # number of cpu cycles simulated 1740system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1741system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1742system.cpu1.committedInsts 32596932 # Number of instructions committed 1743system.cpu1.committedOps 41121940 # Number of ops (including micro ops) committed 1744system.cpu1.num_int_alu_accesses 37644247 # Number of integer alu accesses 1745system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 1746system.cpu1.num_func_calls 962790 # number of times a function call or return occured 1747system.cpu1.num_conditional_control_insts 3735035 # number of instructions that are conditional controls 1748system.cpu1.num_int_insts 37644247 # number of integer instructions 1749system.cpu1.num_fp_insts 6793 # number of float instructions 1750system.cpu1.num_int_register_reads 218344706 # number of times the integer registers were read 1751system.cpu1.num_int_register_writes 39781553 # number of times the integer registers were written 1752system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1753system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 1754system.cpu1.num_mem_refs 14692820 # number of memory refs 1755system.cpu1.num_load_insts 8641241 # Number of load instructions 1756system.cpu1.num_store_insts 6051579 # Number of store instructions 1757system.cpu1.num_idle_cycles 1874235342.195830 # Number of idle cycles 1758system.cpu1.num_busy_cycles 516568442.804169 # Number of busy cycles 1759system.cpu1.not_idle_fraction 0.216065 # Percentage of non-idle cycles 1760system.cpu1.idle_fraction 0.783935 # Percentage of idle cycles	1400system.cpu0.kern.inst.arm 0 # number of arm instructions executed 1401system.cpu0.kern.inst.quiesce 46939 # number of quiesce instructions executed 1402system.cpu0.icache.tags.replacements 424872 # number of replacements 1403system.cpu0.icache.tags.tagsinuse 509.359183 # Cycle average of tags in use 1404system.cpu0.icache.tags.total_refs 29135959 # Total number of references to valid blocks. 1405system.cpu0.icache.tags.sampled_refs 425384 # Sample count of references to valid blocks. 1406system.cpu0.icache.tags.avg_refs 68.493312 # Average number of references to valid blocks. 1407system.cpu0.icache.tags.warmup_cycle 76218358000 # Cycle when the warmup percentage was hit. 1408system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.359183 # Average occupied blocks per requestor 1409system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994842 # Average percentage of cache occupancy 1410system.cpu0.icache.tags.occ_percent::total 0.994842 # Average percentage of cache occupancy 1411system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1412system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 1413system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id 1414system.cpu0.icache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id 1415system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 1416system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1417system.cpu0.icache.tags.tag_accesses 29986729 # Number of tag accesses 1418system.cpu0.icache.tags.data_accesses 29986729 # Number of data accesses 1419system.cpu0.icache.ReadReq_hits::cpu0.inst 29135959 # number of ReadReq hits 1420system.cpu0.icache.ReadReq_hits::total 29135959 # number of ReadReq hits 1421system.cpu0.icache.demand_hits::cpu0.inst 29135959 # number of demand (read+write) hits 1422system.cpu0.icache.demand_hits::total 29135959 # number of demand (read+write) hits 1423system.cpu0.icache.overall_hits::cpu0.inst 29135959 # number of overall hits 1424system.cpu0.icache.overall_hits::total 29135959 # number of overall hits 1425system.cpu0.icache.ReadReq_misses::cpu0.inst 425385 # number of ReadReq misses 1426system.cpu0.icache.ReadReq_misses::total 425385 # number of ReadReq misses 1427system.cpu0.icache.demand_misses::cpu0.inst 425385 # number of demand (read+write) misses 1428system.cpu0.icache.demand_misses::total 425385 # number of demand (read+write) misses 1429system.cpu0.icache.overall_misses::cpu0.inst 425385 # number of overall misses 1430system.cpu0.icache.overall_misses::total 425385 # number of overall misses 1431system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5898245722 # number of ReadReq miss cycles 1432system.cpu0.icache.ReadReq_miss_latency::total 5898245722 # number of ReadReq miss cycles 1433system.cpu0.icache.demand_miss_latency::cpu0.inst 5898245722 # number of demand (read+write) miss cycles 1434system.cpu0.icache.demand_miss_latency::total 5898245722 # number of demand (read+write) miss cycles 1435system.cpu0.icache.overall_miss_latency::cpu0.inst 5898245722 # number of overall miss cycles 1436system.cpu0.icache.overall_miss_latency::total 5898245722 # number of overall miss cycles 1437system.cpu0.icache.ReadReq_accesses::cpu0.inst 29561344 # number of ReadReq accesses(hits+misses) 1438system.cpu0.icache.ReadReq_accesses::total 29561344 # number of ReadReq accesses(hits+misses) 1439system.cpu0.icache.demand_accesses::cpu0.inst 29561344 # number of demand (read+write) accesses 1440system.cpu0.icache.demand_accesses::total 29561344 # number of demand (read+write) accesses 1441system.cpu0.icache.overall_accesses::cpu0.inst 29561344 # number of overall (read+write) accesses 1442system.cpu0.icache.overall_accesses::total 29561344 # number of overall (read+write) accesses 1443system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014390 # miss rate for ReadReq accesses 1444system.cpu0.icache.ReadReq_miss_rate::total 0.014390 # miss rate for ReadReq accesses 1445system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014390 # miss rate for demand accesses 1446system.cpu0.icache.demand_miss_rate::total 0.014390 # miss rate for demand accesses 1447system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014390 # miss rate for overall accesses 1448system.cpu0.icache.overall_miss_rate::total 0.014390 # miss rate for overall accesses 1449system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13865.664567 # average ReadReq miss latency 1450system.cpu0.icache.ReadReq_avg_miss_latency::total 13865.664567 # average ReadReq miss latency 1451system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency 1452system.cpu0.icache.demand_avg_miss_latency::total 13865.664567 # average overall miss latency 1453system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13865.664567 # average overall miss latency 1454system.cpu0.icache.overall_avg_miss_latency::total 13865.664567 # average overall miss latency 1455system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1456system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1457system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1458system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 1459system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1460system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1461system.cpu0.icache.fast_writes 0 # number of fast writes performed 1462system.cpu0.icache.cache_copies 0 # number of cache copies performed 1463system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425385 # number of ReadReq MSHR misses 1464system.cpu0.icache.ReadReq_mshr_misses::total 425385 # number of ReadReq MSHR misses 1465system.cpu0.icache.demand_mshr_misses::cpu0.inst 425385 # number of demand (read+write) MSHR misses 1466system.cpu0.icache.demand_mshr_misses::total 425385 # number of demand (read+write) MSHR misses 1467system.cpu0.icache.overall_mshr_misses::cpu0.inst 425385 # number of overall MSHR misses 1468system.cpu0.icache.overall_mshr_misses::total 425385 # number of overall MSHR misses 1469system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5045266278 # number of ReadReq MSHR miss cycles 1470system.cpu0.icache.ReadReq_mshr_miss_latency::total 5045266278 # number of ReadReq MSHR miss cycles 1471system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5045266278 # number of demand (read+write) MSHR miss cycles 1472system.cpu0.icache.demand_mshr_miss_latency::total 5045266278 # number of demand (read+write) MSHR miss cycles 1473system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5045266278 # number of overall MSHR miss cycles 1474system.cpu0.icache.overall_mshr_miss_latency::total 5045266278 # number of overall MSHR miss cycles 1475system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 437016250 # number of ReadReq MSHR uncacheable cycles 1476system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 437016250 # number of ReadReq MSHR uncacheable cycles 1477system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 437016250 # number of overall MSHR uncacheable cycles 1478system.cpu0.icache.overall_mshr_uncacheable_latency::total 437016250 # number of overall MSHR uncacheable cycles 1479system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for ReadReq accesses 1480system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014390 # mshr miss rate for ReadReq accesses 1481system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for demand accesses 1482system.cpu0.icache.demand_mshr_miss_rate::total 0.014390 # mshr miss rate for demand accesses 1483system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014390 # mshr miss rate for overall accesses 1484system.cpu0.icache.overall_mshr_miss_rate::total 0.014390 # mshr miss rate for overall accesses 1485system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average ReadReq mshr miss latency 1486system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11860.470581 # average ReadReq mshr miss latency 1487system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency 1488system.cpu0.icache.demand_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency 1489system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11860.470581 # average overall mshr miss latency 1490system.cpu0.icache.overall_avg_mshr_miss_latency::total 11860.470581 # average overall mshr miss latency 1491system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1492system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1493system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1494system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1495system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1496system.cpu0.dcache.tags.replacements 329699 # number of replacements 1497system.cpu0.dcache.tags.tagsinuse 455.775151 # Cycle average of tags in use 1498system.cpu0.dcache.tags.total_refs 12258801 # Total number of references to valid blocks. 1499system.cpu0.dcache.tags.sampled_refs 330211 # Sample count of references to valid blocks. 1500system.cpu0.dcache.tags.avg_refs 37.124145 # Average number of references to valid blocks. 1501system.cpu0.dcache.tags.warmup_cycle 667204250 # Cycle when the warmup percentage was hit. 1502system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.775151 # Average occupied blocks per requestor 1503system.cpu0.dcache.tags.occ_percent::cpu0.data 0.890186 # Average percentage of cache occupancy 1504system.cpu0.dcache.tags.occ_percent::total 0.890186 # Average percentage of cache occupancy 1505system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1506system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 1507system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 1508system.cpu0.dcache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id 1509system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 1510system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1511system.cpu0.dcache.tags.tag_accesses 50852132 # Number of tag accesses 1512system.cpu0.dcache.tags.data_accesses 50852132 # Number of data accesses 1513system.cpu0.dcache.ReadReq_hits::cpu0.data 6594161 # number of ReadReq hits 1514system.cpu0.dcache.ReadReq_hits::total 6594161 # number of ReadReq hits 1515system.cpu0.dcache.WriteReq_hits::cpu0.data 5344638 # number of WriteReq hits 1516system.cpu0.dcache.WriteReq_hits::total 5344638 # number of WriteReq hits 1517system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148004 # number of LoadLockedReq hits 1518system.cpu0.dcache.LoadLockedReq_hits::total 148004 # number of LoadLockedReq hits 1519system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149654 # number of StoreCondReq hits 1520system.cpu0.dcache.StoreCondReq_hits::total 149654 # number of StoreCondReq hits 1521system.cpu0.dcache.demand_hits::cpu0.data 11938799 # number of demand (read+write) hits 1522system.cpu0.dcache.demand_hits::total 11938799 # number of demand (read+write) hits 1523system.cpu0.dcache.overall_hits::cpu0.data 11938799 # number of overall hits 1524system.cpu0.dcache.overall_hits::total 11938799 # number of overall hits 1525system.cpu0.dcache.ReadReq_misses::cpu0.data 227537 # number of ReadReq misses 1526system.cpu0.dcache.ReadReq_misses::total 227537 # number of ReadReq misses 1527system.cpu0.dcache.WriteReq_misses::cpu0.data 141373 # number of WriteReq misses 1528system.cpu0.dcache.WriteReq_misses::total 141373 # number of WriteReq misses 1529system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9339 # number of LoadLockedReq misses 1530system.cpu0.dcache.LoadLockedReq_misses::total 9339 # number of LoadLockedReq misses 1531system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7481 # number of StoreCondReq misses 1532system.cpu0.dcache.StoreCondReq_misses::total 7481 # number of StoreCondReq misses 1533system.cpu0.dcache.demand_misses::cpu0.data 368910 # number of demand (read+write) misses 1534system.cpu0.dcache.demand_misses::total 368910 # number of demand (read+write) misses 1535system.cpu0.dcache.overall_misses::cpu0.data 368910 # number of overall misses 1536system.cpu0.dcache.overall_misses::total 368910 # number of overall misses 1537system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3307426746 # number of ReadReq miss cycles 1538system.cpu0.dcache.ReadReq_miss_latency::total 3307426746 # number of ReadReq miss cycles 1539system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5667209233 # number of WriteReq miss cycles 1540system.cpu0.dcache.WriteReq_miss_latency::total 5667209233 # number of WriteReq miss cycles 1541system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93091750 # number of LoadLockedReq miss cycles 1542system.cpu0.dcache.LoadLockedReq_miss_latency::total 93091750 # number of LoadLockedReq miss cycles 1543system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44245560 # number of StoreCondReq miss cycles 1544system.cpu0.dcache.StoreCondReq_miss_latency::total 44245560 # number of StoreCondReq miss cycles 1545system.cpu0.dcache.demand_miss_latency::cpu0.data 8974635979 # number of demand (read+write) miss cycles 1546system.cpu0.dcache.demand_miss_latency::total 8974635979 # number of demand (read+write) miss cycles 1547system.cpu0.dcache.overall_miss_latency::cpu0.data 8974635979 # number of overall miss cycles 1548system.cpu0.dcache.overall_miss_latency::total 8974635979 # number of overall miss cycles 1549system.cpu0.dcache.ReadReq_accesses::cpu0.data 6821698 # number of ReadReq accesses(hits+misses) 1550system.cpu0.dcache.ReadReq_accesses::total 6821698 # number of ReadReq accesses(hits+misses) 1551system.cpu0.dcache.WriteReq_accesses::cpu0.data 5486011 # number of WriteReq accesses(hits+misses) 1552system.cpu0.dcache.WriteReq_accesses::total 5486011 # number of WriteReq accesses(hits+misses) 1553system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157343 # number of LoadLockedReq accesses(hits+misses) 1554system.cpu0.dcache.LoadLockedReq_accesses::total 157343 # number of LoadLockedReq accesses(hits+misses) 1555system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157135 # number of StoreCondReq accesses(hits+misses) 1556system.cpu0.dcache.StoreCondReq_accesses::total 157135 # number of StoreCondReq accesses(hits+misses) 1557system.cpu0.dcache.demand_accesses::cpu0.data 12307709 # number of demand (read+write) accesses 1558system.cpu0.dcache.demand_accesses::total 12307709 # number of demand (read+write) accesses 1559system.cpu0.dcache.overall_accesses::cpu0.data 12307709 # number of overall (read+write) accesses 1560system.cpu0.dcache.overall_accesses::total 12307709 # number of overall (read+write) accesses 1561system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033355 # miss rate for ReadReq accesses 1562system.cpu0.dcache.ReadReq_miss_rate::total 0.033355 # miss rate for ReadReq accesses 1563system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025770 # miss rate for WriteReq accesses 1564system.cpu0.dcache.WriteReq_miss_rate::total 0.025770 # miss rate for WriteReq accesses 1565system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059354 # miss rate for LoadLockedReq accesses 1566system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059354 # miss rate for LoadLockedReq accesses 1567system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047609 # miss rate for StoreCondReq accesses 1568system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047609 # miss rate for StoreCondReq accesses 1569system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029974 # miss rate for demand accesses 1570system.cpu0.dcache.demand_miss_rate::total 0.029974 # miss rate for demand accesses 1571system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029974 # miss rate for overall accesses 1572system.cpu0.dcache.overall_miss_rate::total 0.029974 # miss rate for overall accesses 1573system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14535.775483 # average ReadReq miss latency 1574system.cpu0.dcache.ReadReq_avg_miss_latency::total 14535.775483 # average ReadReq miss latency 1575system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40086.927723 # average WriteReq miss latency 1576system.cpu0.dcache.WriteReq_avg_miss_latency::total 40086.927723 # average WriteReq miss latency 1577system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9968.064033 # average LoadLockedReq miss latency 1578system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9968.064033 # average LoadLockedReq miss latency 1579system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5914.391124 # average StoreCondReq miss latency 1580system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5914.391124 # average StoreCondReq miss latency 1581system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency 1582system.cpu0.dcache.demand_avg_miss_latency::total 24327.440240 # average overall miss latency 1583system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24327.440240 # average overall miss latency 1584system.cpu0.dcache.overall_avg_miss_latency::total 24327.440240 # average overall miss latency 1585system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1586system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1587system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1588system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 1589system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1590system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1591system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1592system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1593system.cpu0.dcache.writebacks::writebacks 305670 # number of writebacks 1594system.cpu0.dcache.writebacks::total 305670 # number of writebacks 1595system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227537 # number of ReadReq MSHR misses 1596system.cpu0.dcache.ReadReq_mshr_misses::total 227537 # number of ReadReq MSHR misses 1597system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141373 # number of WriteReq MSHR misses 1598system.cpu0.dcache.WriteReq_mshr_misses::total 141373 # number of WriteReq MSHR misses 1599system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9339 # number of LoadLockedReq MSHR misses 1600system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9339 # number of LoadLockedReq MSHR misses 1601system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7479 # number of StoreCondReq MSHR misses 1602system.cpu0.dcache.StoreCondReq_mshr_misses::total 7479 # number of StoreCondReq MSHR misses 1603system.cpu0.dcache.demand_mshr_misses::cpu0.data 368910 # number of demand (read+write) MSHR misses 1604system.cpu0.dcache.demand_mshr_misses::total 368910 # number of demand (read+write) MSHR misses 1605system.cpu0.dcache.overall_mshr_misses::cpu0.data 368910 # number of overall MSHR misses 1606system.cpu0.dcache.overall_mshr_misses::total 368910 # number of overall MSHR misses 1607system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2850420254 # number of ReadReq MSHR miss cycles 1608system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2850420254 # number of ReadReq MSHR miss cycles 1609system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5353542767 # number of WriteReq MSHR miss cycles 1610system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5353542767 # number of WriteReq MSHR miss cycles 1611system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 74365250 # number of LoadLockedReq MSHR miss cycles 1612system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74365250 # number of LoadLockedReq MSHR miss cycles 1613system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29286440 # number of StoreCondReq MSHR miss cycles 1614system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29286440 # number of StoreCondReq MSHR miss cycles 1615system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8203963021 # number of demand (read+write) MSHR miss cycles 1616system.cpu0.dcache.demand_mshr_miss_latency::total 8203963021 # number of demand (read+write) MSHR miss cycles 1617system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8203963021 # number of overall MSHR miss cycles 1618system.cpu0.dcache.overall_mshr_miss_latency::total 8203963021 # number of overall MSHR miss cycles 1619system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13556999000 # number of ReadReq MSHR uncacheable cycles 1620system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13556999000 # number of ReadReq MSHR uncacheable cycles 1621system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1167889500 # number of WriteReq MSHR uncacheable cycles 1622system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1167889500 # number of WriteReq MSHR uncacheable cycles 1623system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14724888500 # number of overall MSHR uncacheable cycles 1624system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14724888500 # number of overall MSHR uncacheable cycles 1625system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033355 # mshr miss rate for ReadReq accesses 1626system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033355 # mshr miss rate for ReadReq accesses 1627system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025770 # mshr miss rate for WriteReq accesses 1628system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025770 # mshr miss rate for WriteReq accesses 1629system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059354 # mshr miss rate for LoadLockedReq accesses 1630system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059354 # mshr miss rate for LoadLockedReq accesses 1631system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047596 # mshr miss rate for StoreCondReq accesses 1632system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047596 # mshr miss rate for StoreCondReq accesses 1633system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for demand accesses 1634system.cpu0.dcache.demand_mshr_miss_rate::total 0.029974 # mshr miss rate for demand accesses 1635system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029974 # mshr miss rate for overall accesses 1636system.cpu0.dcache.overall_mshr_miss_rate::total 0.029974 # mshr miss rate for overall accesses 1637system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12527.282394 # average ReadReq mshr miss latency 1638system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12527.282394 # average ReadReq mshr miss latency 1639system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37868.212226 # average WriteReq mshr miss latency 1640system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37868.212226 # average WriteReq mshr miss latency 1641system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7962.870757 # average LoadLockedReq mshr miss latency 1642system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7962.870757 # average LoadLockedReq mshr miss latency 1643system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.822971 # average StoreCondReq mshr miss latency 1644system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.822971 # average StoreCondReq mshr miss latency 1645system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency 1646system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency 1647system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22238.386113 # average overall mshr miss latency 1648system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22238.386113 # average overall mshr miss latency 1649system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1650system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1651system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1652system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1653system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1654system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1655system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1656system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1657system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1658system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1659system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1660system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1661system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1662system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1663system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1664system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1665system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1666system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1667system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1668system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1669system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1670system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1671system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1672system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1673system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1674system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1675system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1676system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1677system.cpu1.dtb.inst_hits 0 # ITB inst hits 1678system.cpu1.dtb.inst_misses 0 # ITB inst misses 1679system.cpu1.dtb.read_hits 8319266 # DTB read hits 1680system.cpu1.dtb.read_misses 3647 # DTB read misses 1681system.cpu1.dtb.write_hits 5834802 # DTB write hits 1682system.cpu1.dtb.write_misses 1433 # DTB write misses 1683system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 1684system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1685system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1686system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1687system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB 1688system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1689system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch 1690system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1691system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 1692system.cpu1.dtb.read_accesses 8322913 # DTB read accesses 1693system.cpu1.dtb.write_accesses 5836235 # DTB write accesses 1694system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1695system.cpu1.dtb.hits 14154068 # DTB hits 1696system.cpu1.dtb.misses 5080 # DTB misses 1697system.cpu1.dtb.accesses 14159148 # DTB accesses 1698system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1699system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1700system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1701system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1702system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1703system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1704system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1705system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1706system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1707system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1708system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1709system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1710system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1711system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1712system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1713system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1714system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1715system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1716system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1717system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1718system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1719system.cpu1.itb.inst_hits 33207997 # ITB inst hits 1720system.cpu1.itb.inst_misses 2171 # ITB inst misses 1721system.cpu1.itb.read_hits 0 # DTB read hits 1722system.cpu1.itb.read_misses 0 # DTB read misses 1723system.cpu1.itb.write_hits 0 # DTB write hits 1724system.cpu1.itb.write_misses 0 # DTB write misses 1725system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 1726system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1727system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 1728system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 1729system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB 1730system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1731system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1732system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1733system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1734system.cpu1.itb.read_accesses 0 # DTB read accesses 1735system.cpu1.itb.write_accesses 0 # DTB write accesses 1736system.cpu1.itb.inst_accesses 33210168 # ITB inst accesses 1737system.cpu1.itb.hits 33207997 # DTB hits 1738system.cpu1.itb.misses 2171 # DTB misses 1739system.cpu1.itb.accesses 33210168 # DTB accesses 1740system.cpu1.numCycles 2390803785 # number of cpu cycles simulated 1741system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1742system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1743system.cpu1.committedInsts 32596932 # Number of instructions committed 1744system.cpu1.committedOps 41121940 # Number of ops (including micro ops) committed 1745system.cpu1.num_int_alu_accesses 37644247 # Number of integer alu accesses 1746system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 1747system.cpu1.num_func_calls 962790 # number of times a function call or return occured 1748system.cpu1.num_conditional_control_insts 3735035 # number of instructions that are conditional controls 1749system.cpu1.num_int_insts 37644247 # number of integer instructions 1750system.cpu1.num_fp_insts 6793 # number of float instructions 1751system.cpu1.num_int_register_reads 218344706 # number of times the integer registers were read 1752system.cpu1.num_int_register_writes 39781553 # number of times the integer registers were written 1753system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1754system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 1755system.cpu1.num_mem_refs 14692820 # number of memory refs 1756system.cpu1.num_load_insts 8641241 # Number of load instructions 1757system.cpu1.num_store_insts 6051579 # Number of store instructions 1758system.cpu1.num_idle_cycles 1874235342.195830 # Number of idle cycles 1759system.cpu1.num_busy_cycles 516568442.804169 # Number of busy cycles 1760system.cpu1.not_idle_fraction 0.216065 # Percentage of non-idle cycles 1761system.cpu1.idle_fraction 0.783935 # Percentage of idle cycles
	1762system.cpu1.Branches 4947677 # Number of branches fetched
1761system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1762system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed 1763system.cpu1.icache.tags.replacements 469929 # number of replacements 1764system.cpu1.icache.tags.tagsinuse 478.566840 # Cycle average of tags in use 1765system.cpu1.icache.tags.total_refs 32737552 # Total number of references to valid blocks. 1766system.cpu1.icache.tags.sampled_refs 470441 # Sample count of references to valid blocks. 1767system.cpu1.icache.tags.avg_refs 69.589071 # Average number of references to valid blocks. 1768system.cpu1.icache.tags.warmup_cycle 93987616500 # Cycle when the warmup percentage was hit. 1769system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.566840 # Average occupied blocks per requestor 1770system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934701 # Average percentage of cache occupancy 1771system.cpu1.icache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy 1772system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1773system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 1774system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 1775system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 1776system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1777system.cpu1.icache.tags.tag_accesses 33678434 # Number of tag accesses 1778system.cpu1.icache.tags.data_accesses 33678434 # Number of data accesses 1779system.cpu1.icache.ReadReq_hits::cpu1.inst 32737552 # number of ReadReq hits 1780system.cpu1.icache.ReadReq_hits::total 32737552 # number of ReadReq hits 1781system.cpu1.icache.demand_hits::cpu1.inst 32737552 # number of demand (read+write) hits 1782system.cpu1.icache.demand_hits::total 32737552 # number of demand (read+write) hits 1783system.cpu1.icache.overall_hits::cpu1.inst 32737552 # number of overall hits 1784system.cpu1.icache.overall_hits::total 32737552 # number of overall hits 1785system.cpu1.icache.ReadReq_misses::cpu1.inst 470441 # number of ReadReq misses 1786system.cpu1.icache.ReadReq_misses::total 470441 # number of ReadReq misses 1787system.cpu1.icache.demand_misses::cpu1.inst 470441 # number of demand (read+write) misses 1788system.cpu1.icache.demand_misses::total 470441 # number of demand (read+write) misses 1789system.cpu1.icache.overall_misses::cpu1.inst 470441 # number of overall misses 1790system.cpu1.icache.overall_misses::total 470441 # number of overall misses 1791system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6446126723 # number of ReadReq miss cycles 1792system.cpu1.icache.ReadReq_miss_latency::total 6446126723 # number of ReadReq miss cycles 1793system.cpu1.icache.demand_miss_latency::cpu1.inst 6446126723 # number of demand (read+write) miss cycles 1794system.cpu1.icache.demand_miss_latency::total 6446126723 # number of demand (read+write) miss cycles 1795system.cpu1.icache.overall_miss_latency::cpu1.inst 6446126723 # number of overall miss cycles 1796system.cpu1.icache.overall_miss_latency::total 6446126723 # number of overall miss cycles 1797system.cpu1.icache.ReadReq_accesses::cpu1.inst 33207993 # number of ReadReq accesses(hits+misses) 1798system.cpu1.icache.ReadReq_accesses::total 33207993 # number of ReadReq accesses(hits+misses) 1799system.cpu1.icache.demand_accesses::cpu1.inst 33207993 # number of demand (read+write) accesses 1800system.cpu1.icache.demand_accesses::total 33207993 # number of demand (read+write) accesses 1801system.cpu1.icache.overall_accesses::cpu1.inst 33207993 # number of overall (read+write) accesses 1802system.cpu1.icache.overall_accesses::total 33207993 # number of overall (read+write) accesses 1803system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses 1804system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses 1805system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses 1806system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses 1807system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses 1808system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses 1809system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13702.306395 # average ReadReq miss latency 1810system.cpu1.icache.ReadReq_avg_miss_latency::total 13702.306395 # average ReadReq miss latency 1811system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency 1812system.cpu1.icache.demand_avg_miss_latency::total 13702.306395 # average overall miss latency 1813system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency 1814system.cpu1.icache.overall_avg_miss_latency::total 13702.306395 # average overall miss latency 1815system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1816system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1817system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1818system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1819system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1820system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1821system.cpu1.icache.fast_writes 0 # number of fast writes performed 1822system.cpu1.icache.cache_copies 0 # number of cache copies performed 1823system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470441 # number of ReadReq MSHR misses 1824system.cpu1.icache.ReadReq_mshr_misses::total 470441 # number of ReadReq MSHR misses 1825system.cpu1.icache.demand_mshr_misses::cpu1.inst 470441 # number of demand (read+write) MSHR misses 1826system.cpu1.icache.demand_mshr_misses::total 470441 # number of demand (read+write) MSHR misses 1827system.cpu1.icache.overall_mshr_misses::cpu1.inst 470441 # number of overall MSHR misses 1828system.cpu1.icache.overall_mshr_misses::total 470441 # number of overall MSHR misses 1829system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5503297277 # number of ReadReq MSHR miss cycles 1830system.cpu1.icache.ReadReq_mshr_miss_latency::total 5503297277 # number of ReadReq MSHR miss cycles 1831system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5503297277 # number of demand (read+write) MSHR miss cycles 1832system.cpu1.icache.demand_mshr_miss_latency::total 5503297277 # number of demand (read+write) MSHR miss cycles 1833system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5503297277 # number of overall MSHR miss cycles 1834system.cpu1.icache.overall_mshr_miss_latency::total 5503297277 # number of overall MSHR miss cycles 1835system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7106250 # number of ReadReq MSHR uncacheable cycles 1836system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7106250 # number of ReadReq MSHR uncacheable cycles 1837system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7106250 # number of overall MSHR uncacheable cycles 1838system.cpu1.icache.overall_mshr_uncacheable_latency::total 7106250 # number of overall MSHR uncacheable cycles 1839system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for ReadReq accesses 1840system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014166 # mshr miss rate for ReadReq accesses 1841system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for demand accesses 1842system.cpu1.icache.demand_mshr_miss_rate::total 0.014166 # mshr miss rate for demand accesses 1843system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for overall accesses 1844system.cpu1.icache.overall_mshr_miss_rate::total 0.014166 # mshr miss rate for overall accesses 1845system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average ReadReq mshr miss latency 1846system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11698.166778 # average ReadReq mshr miss latency 1847system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average overall mshr miss latency 1848system.cpu1.icache.demand_avg_mshr_miss_latency::total 11698.166778 # average overall mshr miss latency 1849system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average overall mshr miss latency 1850system.cpu1.icache.overall_avg_mshr_miss_latency::total 11698.166778 # average overall mshr miss latency 1851system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1852system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1853system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1854system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1855system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1856system.cpu1.dcache.tags.replacements 292485 # number of replacements 1857system.cpu1.dcache.tags.tagsinuse 471.346411 # Cycle average of tags in use 1858system.cpu1.dcache.tags.total_refs 11976402 # Total number of references to valid blocks. 1859system.cpu1.dcache.tags.sampled_refs 292833 # Sample count of references to valid blocks. 1860system.cpu1.dcache.tags.avg_refs 40.898403 # Average number of references to valid blocks. 1861system.cpu1.dcache.tags.warmup_cycle 85276695250 # Cycle when the warmup percentage was hit. 1862system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.346411 # Average occupied blocks per requestor 1863system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920598 # Average percentage of cache occupancy 1864system.cpu1.dcache.tags.occ_percent::total 0.920598 # Average percentage of cache occupancy 1865system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 1866system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id 1867system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id 1868system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id 1869system.cpu1.dcache.tags.tag_accesses 49497647 # Number of tag accesses 1870system.cpu1.dcache.tags.data_accesses 49497647 # Number of data accesses 1871system.cpu1.dcache.ReadReq_hits::cpu1.data 6954137 # number of ReadReq hits 1872system.cpu1.dcache.ReadReq_hits::total 6954137 # number of ReadReq hits 1873system.cpu1.dcache.WriteReq_hits::cpu1.data 4834149 # number of WriteReq hits 1874system.cpu1.dcache.WriteReq_hits::total 4834149 # number of WriteReq hits 1875system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82001 # number of LoadLockedReq hits 1876system.cpu1.dcache.LoadLockedReq_hits::total 82001 # number of LoadLockedReq hits 1877system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82789 # number of StoreCondReq hits 1878system.cpu1.dcache.StoreCondReq_hits::total 82789 # number of StoreCondReq hits 1879system.cpu1.dcache.demand_hits::cpu1.data 11788286 # number of demand (read+write) hits 1880system.cpu1.dcache.demand_hits::total 11788286 # number of demand (read+write) hits 1881system.cpu1.dcache.overall_hits::cpu1.data 11788286 # number of overall hits 1882system.cpu1.dcache.overall_hits::total 11788286 # number of overall hits 1883system.cpu1.dcache.ReadReq_misses::cpu1.data 170721 # number of ReadReq misses 1884system.cpu1.dcache.ReadReq_misses::total 170721 # number of ReadReq misses 1885system.cpu1.dcache.WriteReq_misses::cpu1.data 150254 # number of WriteReq misses 1886system.cpu1.dcache.WriteReq_misses::total 150254 # number of WriteReq misses 1887system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11274 # number of LoadLockedReq misses 1888system.cpu1.dcache.LoadLockedReq_misses::total 11274 # number of LoadLockedReq misses 1889system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10054 # number of StoreCondReq misses 1890system.cpu1.dcache.StoreCondReq_misses::total 10054 # number of StoreCondReq misses 1891system.cpu1.dcache.demand_misses::cpu1.data 320975 # number of demand (read+write) misses 1892system.cpu1.dcache.demand_misses::total 320975 # number of demand (read+write) misses 1893system.cpu1.dcache.overall_misses::cpu1.data 320975 # number of overall misses 1894system.cpu1.dcache.overall_misses::total 320975 # number of overall misses 1895system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219304994 # number of ReadReq miss cycles 1896system.cpu1.dcache.ReadReq_miss_latency::total 2219304994 # number of ReadReq miss cycles 1897system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6585994013 # number of WriteReq miss cycles 1898system.cpu1.dcache.WriteReq_miss_latency::total 6585994013 # number of WriteReq miss cycles 1899system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 97542000 # number of LoadLockedReq miss cycles 1900system.cpu1.dcache.LoadLockedReq_miss_latency::total 97542000 # number of LoadLockedReq miss cycles 1901system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52010474 # number of StoreCondReq miss cycles 1902system.cpu1.dcache.StoreCondReq_miss_latency::total 52010474 # number of StoreCondReq miss cycles 1903system.cpu1.dcache.demand_miss_latency::cpu1.data 8805299007 # number of demand (read+write) miss cycles 1904system.cpu1.dcache.demand_miss_latency::total 8805299007 # number of demand (read+write) miss cycles 1905system.cpu1.dcache.overall_miss_latency::cpu1.data 8805299007 # number of overall miss cycles 1906system.cpu1.dcache.overall_miss_latency::total 8805299007 # number of overall miss cycles 1907system.cpu1.dcache.ReadReq_accesses::cpu1.data 7124858 # number of ReadReq accesses(hits+misses) 1908system.cpu1.dcache.ReadReq_accesses::total 7124858 # number of ReadReq accesses(hits+misses) 1909system.cpu1.dcache.WriteReq_accesses::cpu1.data 4984403 # number of WriteReq accesses(hits+misses) 1910system.cpu1.dcache.WriteReq_accesses::total 4984403 # number of WriteReq accesses(hits+misses) 1911system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93275 # number of LoadLockedReq accesses(hits+misses) 1912system.cpu1.dcache.LoadLockedReq_accesses::total 93275 # number of LoadLockedReq accesses(hits+misses) 1913system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92843 # number of StoreCondReq accesses(hits+misses) 1914system.cpu1.dcache.StoreCondReq_accesses::total 92843 # number of StoreCondReq accesses(hits+misses) 1915system.cpu1.dcache.demand_accesses::cpu1.data 12109261 # number of demand (read+write) accesses 1916system.cpu1.dcache.demand_accesses::total 12109261 # number of demand (read+write) accesses 1917system.cpu1.dcache.overall_accesses::cpu1.data 12109261 # number of overall (read+write) accesses 1918system.cpu1.dcache.overall_accesses::total 12109261 # number of overall (read+write) accesses 1919system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023961 # miss rate for ReadReq accesses 1920system.cpu1.dcache.ReadReq_miss_rate::total 0.023961 # miss rate for ReadReq accesses 1921system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030145 # miss rate for WriteReq accesses 1922system.cpu1.dcache.WriteReq_miss_rate::total 0.030145 # miss rate for WriteReq accesses 1923system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120868 # miss rate for LoadLockedReq accesses 1924system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120868 # miss rate for LoadLockedReq accesses 1925system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108290 # miss rate for StoreCondReq accesses 1926system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108290 # miss rate for StoreCondReq accesses 1927system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026507 # miss rate for demand accesses 1928system.cpu1.dcache.demand_miss_rate::total 0.026507 # miss rate for demand accesses 1929system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026507 # miss rate for overall accesses 1930system.cpu1.dcache.overall_miss_rate::total 0.026507 # miss rate for overall accesses 1931system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12999.601654 # average ReadReq miss latency 1932system.cpu1.dcache.ReadReq_avg_miss_latency::total 12999.601654 # average ReadReq miss latency 1933system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43832.403883 # average WriteReq miss latency 1934system.cpu1.dcache.WriteReq_avg_miss_latency::total 43832.403883 # average WriteReq miss latency 1935system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8651.942523 # average LoadLockedReq miss latency 1936system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8651.942523 # average LoadLockedReq miss latency 1937system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5173.112592 # average StoreCondReq miss latency 1938system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5173.112592 # average StoreCondReq miss latency 1939system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency 1940system.cpu1.dcache.demand_avg_miss_latency::total 27432.974553 # average overall miss latency 1941system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency 1942system.cpu1.dcache.overall_avg_miss_latency::total 27432.974553 # average overall miss latency 1943system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1944system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1945system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1946system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1947system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1948system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1949system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1950system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1951system.cpu1.dcache.writebacks::writebacks 265367 # number of writebacks 1952system.cpu1.dcache.writebacks::total 265367 # number of writebacks 1953system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170721 # number of ReadReq MSHR misses 1954system.cpu1.dcache.ReadReq_mshr_misses::total 170721 # number of ReadReq MSHR misses 1955system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150254 # number of WriteReq MSHR misses 1956system.cpu1.dcache.WriteReq_mshr_misses::total 150254 # number of WriteReq MSHR misses 1957system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11274 # number of LoadLockedReq MSHR misses 1958system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11274 # number of LoadLockedReq MSHR misses 1959system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10053 # number of StoreCondReq MSHR misses 1960system.cpu1.dcache.StoreCondReq_mshr_misses::total 10053 # number of StoreCondReq MSHR misses 1961system.cpu1.dcache.demand_mshr_misses::cpu1.data 320975 # number of demand (read+write) MSHR misses 1962system.cpu1.dcache.demand_mshr_misses::total 320975 # number of demand (read+write) MSHR misses 1963system.cpu1.dcache.overall_mshr_misses::cpu1.data 320975 # number of overall MSHR misses 1964system.cpu1.dcache.overall_mshr_misses::total 320975 # number of overall MSHR misses 1965system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877186006 # number of ReadReq MSHR miss cycles 1966system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877186006 # number of ReadReq MSHR miss cycles 1967system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6262088987 # number of WriteReq MSHR miss cycles 1968system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6262088987 # number of WriteReq MSHR miss cycles 1969system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74982000 # number of LoadLockedReq MSHR miss cycles 1970system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74982000 # number of LoadLockedReq MSHR miss cycles 1971system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31903526 # number of StoreCondReq MSHR miss cycles 1972system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31903526 # number of StoreCondReq MSHR miss cycles 1973system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8139274993 # number of demand (read+write) MSHR miss cycles 1974system.cpu1.dcache.demand_mshr_miss_latency::total 8139274993 # number of demand (read+write) MSHR miss cycles 1975system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8139274993 # number of overall MSHR miss cycles 1976system.cpu1.dcache.overall_mshr_miss_latency::total 8139274993 # number of overall MSHR miss cycles 1977system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608498500 # number of ReadReq MSHR uncacheable cycles 1978system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608498500 # number of ReadReq MSHR uncacheable cycles 1979system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182871345 # number of WriteReq MSHR uncacheable cycles 1980system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182871345 # number of WriteReq MSHR uncacheable cycles 1981system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791369845 # number of overall MSHR uncacheable cycles 1982system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791369845 # number of overall MSHR uncacheable cycles 1983system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023961 # mshr miss rate for ReadReq accesses 1984system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023961 # mshr miss rate for ReadReq accesses 1985system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses 1986system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses 1987system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120868 # mshr miss rate for LoadLockedReq accesses 1988system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120868 # mshr miss rate for LoadLockedReq accesses 1989system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108280 # mshr miss rate for StoreCondReq accesses 1990system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108280 # mshr miss rate for StoreCondReq accesses 1991system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses 1992system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses 1993system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses 1994system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses 1995system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10995.636190 # average ReadReq mshr miss latency 1996system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10995.636190 # average ReadReq mshr miss latency 1997system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41676.687389 # average WriteReq mshr miss latency 1998system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41676.687389 # average WriteReq mshr miss latency 1999system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6650.878127 # average LoadLockedReq mshr miss latency 2000system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6650.878127 # average LoadLockedReq mshr miss latency 2001system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3173.532876 # average StoreCondReq mshr miss latency 2002system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3173.532876 # average StoreCondReq mshr miss latency 2003system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency 2004system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency 2005system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency 2006system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency 2007system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2008system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2009system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2010system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2011system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2012system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2013system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2014system.iocache.tags.replacements 0 # number of replacements 2015system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 2016system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2017system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 2018system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 2019system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2020system.iocache.tags.tag_accesses 0 # Number of tag accesses 2021system.iocache.tags.data_accesses 0 # Number of data accesses 2022system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2023system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2024system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2025system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2026system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2027system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2028system.iocache.fast_writes 0 # number of fast writes performed 2029system.iocache.cache_copies 0 # number of cache copies performed 2030system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651805197501 # number of ReadReq MSHR uncacheable cycles 2031system.iocache.ReadReq_mshr_uncacheable_latency::total 651805197501 # number of ReadReq MSHR uncacheable cycles 2032system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651805197501 # number of overall MSHR uncacheable cycles 2033system.iocache.overall_mshr_uncacheable_latency::total 651805197501 # number of overall MSHR uncacheable cycles 2034system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2035system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2036system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2037system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2038system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2039 2040---------- End Simulation Statistics ----------	1763system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1764system.cpu1.kern.inst.quiesce 44317 # number of quiesce instructions executed 1765system.cpu1.icache.tags.replacements 469929 # number of replacements 1766system.cpu1.icache.tags.tagsinuse 478.566840 # Cycle average of tags in use 1767system.cpu1.icache.tags.total_refs 32737552 # Total number of references to valid blocks. 1768system.cpu1.icache.tags.sampled_refs 470441 # Sample count of references to valid blocks. 1769system.cpu1.icache.tags.avg_refs 69.589071 # Average number of references to valid blocks. 1770system.cpu1.icache.tags.warmup_cycle 93987616500 # Cycle when the warmup percentage was hit. 1771system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.566840 # Average occupied blocks per requestor 1772system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934701 # Average percentage of cache occupancy 1773system.cpu1.icache.tags.occ_percent::total 0.934701 # Average percentage of cache occupancy 1774system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1775system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id 1776system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id 1777system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 1778system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1779system.cpu1.icache.tags.tag_accesses 33678434 # Number of tag accesses 1780system.cpu1.icache.tags.data_accesses 33678434 # Number of data accesses 1781system.cpu1.icache.ReadReq_hits::cpu1.inst 32737552 # number of ReadReq hits 1782system.cpu1.icache.ReadReq_hits::total 32737552 # number of ReadReq hits 1783system.cpu1.icache.demand_hits::cpu1.inst 32737552 # number of demand (read+write) hits 1784system.cpu1.icache.demand_hits::total 32737552 # number of demand (read+write) hits 1785system.cpu1.icache.overall_hits::cpu1.inst 32737552 # number of overall hits 1786system.cpu1.icache.overall_hits::total 32737552 # number of overall hits 1787system.cpu1.icache.ReadReq_misses::cpu1.inst 470441 # number of ReadReq misses 1788system.cpu1.icache.ReadReq_misses::total 470441 # number of ReadReq misses 1789system.cpu1.icache.demand_misses::cpu1.inst 470441 # number of demand (read+write) misses 1790system.cpu1.icache.demand_misses::total 470441 # number of demand (read+write) misses 1791system.cpu1.icache.overall_misses::cpu1.inst 470441 # number of overall misses 1792system.cpu1.icache.overall_misses::total 470441 # number of overall misses 1793system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6446126723 # number of ReadReq miss cycles 1794system.cpu1.icache.ReadReq_miss_latency::total 6446126723 # number of ReadReq miss cycles 1795system.cpu1.icache.demand_miss_latency::cpu1.inst 6446126723 # number of demand (read+write) miss cycles 1796system.cpu1.icache.demand_miss_latency::total 6446126723 # number of demand (read+write) miss cycles 1797system.cpu1.icache.overall_miss_latency::cpu1.inst 6446126723 # number of overall miss cycles 1798system.cpu1.icache.overall_miss_latency::total 6446126723 # number of overall miss cycles 1799system.cpu1.icache.ReadReq_accesses::cpu1.inst 33207993 # number of ReadReq accesses(hits+misses) 1800system.cpu1.icache.ReadReq_accesses::total 33207993 # number of ReadReq accesses(hits+misses) 1801system.cpu1.icache.demand_accesses::cpu1.inst 33207993 # number of demand (read+write) accesses 1802system.cpu1.icache.demand_accesses::total 33207993 # number of demand (read+write) accesses 1803system.cpu1.icache.overall_accesses::cpu1.inst 33207993 # number of overall (read+write) accesses 1804system.cpu1.icache.overall_accesses::total 33207993 # number of overall (read+write) accesses 1805system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014166 # miss rate for ReadReq accesses 1806system.cpu1.icache.ReadReq_miss_rate::total 0.014166 # miss rate for ReadReq accesses 1807system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014166 # miss rate for demand accesses 1808system.cpu1.icache.demand_miss_rate::total 0.014166 # miss rate for demand accesses 1809system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014166 # miss rate for overall accesses 1810system.cpu1.icache.overall_miss_rate::total 0.014166 # miss rate for overall accesses 1811system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13702.306395 # average ReadReq miss latency 1812system.cpu1.icache.ReadReq_avg_miss_latency::total 13702.306395 # average ReadReq miss latency 1813system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency 1814system.cpu1.icache.demand_avg_miss_latency::total 13702.306395 # average overall miss latency 1815system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13702.306395 # average overall miss latency 1816system.cpu1.icache.overall_avg_miss_latency::total 13702.306395 # average overall miss latency 1817system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1818system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1819system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1820system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1821system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1822system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1823system.cpu1.icache.fast_writes 0 # number of fast writes performed 1824system.cpu1.icache.cache_copies 0 # number of cache copies performed 1825system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 470441 # number of ReadReq MSHR misses 1826system.cpu1.icache.ReadReq_mshr_misses::total 470441 # number of ReadReq MSHR misses 1827system.cpu1.icache.demand_mshr_misses::cpu1.inst 470441 # number of demand (read+write) MSHR misses 1828system.cpu1.icache.demand_mshr_misses::total 470441 # number of demand (read+write) MSHR misses 1829system.cpu1.icache.overall_mshr_misses::cpu1.inst 470441 # number of overall MSHR misses 1830system.cpu1.icache.overall_mshr_misses::total 470441 # number of overall MSHR misses 1831system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5503297277 # number of ReadReq MSHR miss cycles 1832system.cpu1.icache.ReadReq_mshr_miss_latency::total 5503297277 # number of ReadReq MSHR miss cycles 1833system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5503297277 # number of demand (read+write) MSHR miss cycles 1834system.cpu1.icache.demand_mshr_miss_latency::total 5503297277 # number of demand (read+write) MSHR miss cycles 1835system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5503297277 # number of overall MSHR miss cycles 1836system.cpu1.icache.overall_mshr_miss_latency::total 5503297277 # number of overall MSHR miss cycles 1837system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7106250 # number of ReadReq MSHR uncacheable cycles 1838system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7106250 # number of ReadReq MSHR uncacheable cycles 1839system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7106250 # number of overall MSHR uncacheable cycles 1840system.cpu1.icache.overall_mshr_uncacheable_latency::total 7106250 # number of overall MSHR uncacheable cycles 1841system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for ReadReq accesses 1842system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014166 # mshr miss rate for ReadReq accesses 1843system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for demand accesses 1844system.cpu1.icache.demand_mshr_miss_rate::total 0.014166 # mshr miss rate for demand accesses 1845system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014166 # mshr miss rate for overall accesses 1846system.cpu1.icache.overall_mshr_miss_rate::total 0.014166 # mshr miss rate for overall accesses 1847system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average ReadReq mshr miss latency 1848system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11698.166778 # average ReadReq mshr miss latency 1849system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average overall mshr miss latency 1850system.cpu1.icache.demand_avg_mshr_miss_latency::total 11698.166778 # average overall mshr miss latency 1851system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11698.166778 # average overall mshr miss latency 1852system.cpu1.icache.overall_avg_mshr_miss_latency::total 11698.166778 # average overall mshr miss latency 1853system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1854system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1855system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1856system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1857system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1858system.cpu1.dcache.tags.replacements 292485 # number of replacements 1859system.cpu1.dcache.tags.tagsinuse 471.346411 # Cycle average of tags in use 1860system.cpu1.dcache.tags.total_refs 11976402 # Total number of references to valid blocks. 1861system.cpu1.dcache.tags.sampled_refs 292833 # Sample count of references to valid blocks. 1862system.cpu1.dcache.tags.avg_refs 40.898403 # Average number of references to valid blocks. 1863system.cpu1.dcache.tags.warmup_cycle 85276695250 # Cycle when the warmup percentage was hit. 1864system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.346411 # Average occupied blocks per requestor 1865system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920598 # Average percentage of cache occupancy 1866system.cpu1.dcache.tags.occ_percent::total 0.920598 # Average percentage of cache occupancy 1867system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 1868system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id 1869system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id 1870system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id 1871system.cpu1.dcache.tags.tag_accesses 49497647 # Number of tag accesses 1872system.cpu1.dcache.tags.data_accesses 49497647 # Number of data accesses 1873system.cpu1.dcache.ReadReq_hits::cpu1.data 6954137 # number of ReadReq hits 1874system.cpu1.dcache.ReadReq_hits::total 6954137 # number of ReadReq hits 1875system.cpu1.dcache.WriteReq_hits::cpu1.data 4834149 # number of WriteReq hits 1876system.cpu1.dcache.WriteReq_hits::total 4834149 # number of WriteReq hits 1877system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82001 # number of LoadLockedReq hits 1878system.cpu1.dcache.LoadLockedReq_hits::total 82001 # number of LoadLockedReq hits 1879system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82789 # number of StoreCondReq hits 1880system.cpu1.dcache.StoreCondReq_hits::total 82789 # number of StoreCondReq hits 1881system.cpu1.dcache.demand_hits::cpu1.data 11788286 # number of demand (read+write) hits 1882system.cpu1.dcache.demand_hits::total 11788286 # number of demand (read+write) hits 1883system.cpu1.dcache.overall_hits::cpu1.data 11788286 # number of overall hits 1884system.cpu1.dcache.overall_hits::total 11788286 # number of overall hits 1885system.cpu1.dcache.ReadReq_misses::cpu1.data 170721 # number of ReadReq misses 1886system.cpu1.dcache.ReadReq_misses::total 170721 # number of ReadReq misses 1887system.cpu1.dcache.WriteReq_misses::cpu1.data 150254 # number of WriteReq misses 1888system.cpu1.dcache.WriteReq_misses::total 150254 # number of WriteReq misses 1889system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11274 # number of LoadLockedReq misses 1890system.cpu1.dcache.LoadLockedReq_misses::total 11274 # number of LoadLockedReq misses 1891system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10054 # number of StoreCondReq misses 1892system.cpu1.dcache.StoreCondReq_misses::total 10054 # number of StoreCondReq misses 1893system.cpu1.dcache.demand_misses::cpu1.data 320975 # number of demand (read+write) misses 1894system.cpu1.dcache.demand_misses::total 320975 # number of demand (read+write) misses 1895system.cpu1.dcache.overall_misses::cpu1.data 320975 # number of overall misses 1896system.cpu1.dcache.overall_misses::total 320975 # number of overall misses 1897system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219304994 # number of ReadReq miss cycles 1898system.cpu1.dcache.ReadReq_miss_latency::total 2219304994 # number of ReadReq miss cycles 1899system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6585994013 # number of WriteReq miss cycles 1900system.cpu1.dcache.WriteReq_miss_latency::total 6585994013 # number of WriteReq miss cycles 1901system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 97542000 # number of LoadLockedReq miss cycles 1902system.cpu1.dcache.LoadLockedReq_miss_latency::total 97542000 # number of LoadLockedReq miss cycles 1903system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52010474 # number of StoreCondReq miss cycles 1904system.cpu1.dcache.StoreCondReq_miss_latency::total 52010474 # number of StoreCondReq miss cycles 1905system.cpu1.dcache.demand_miss_latency::cpu1.data 8805299007 # number of demand (read+write) miss cycles 1906system.cpu1.dcache.demand_miss_latency::total 8805299007 # number of demand (read+write) miss cycles 1907system.cpu1.dcache.overall_miss_latency::cpu1.data 8805299007 # number of overall miss cycles 1908system.cpu1.dcache.overall_miss_latency::total 8805299007 # number of overall miss cycles 1909system.cpu1.dcache.ReadReq_accesses::cpu1.data 7124858 # number of ReadReq accesses(hits+misses) 1910system.cpu1.dcache.ReadReq_accesses::total 7124858 # number of ReadReq accesses(hits+misses) 1911system.cpu1.dcache.WriteReq_accesses::cpu1.data 4984403 # number of WriteReq accesses(hits+misses) 1912system.cpu1.dcache.WriteReq_accesses::total 4984403 # number of WriteReq accesses(hits+misses) 1913system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93275 # number of LoadLockedReq accesses(hits+misses) 1914system.cpu1.dcache.LoadLockedReq_accesses::total 93275 # number of LoadLockedReq accesses(hits+misses) 1915system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92843 # number of StoreCondReq accesses(hits+misses) 1916system.cpu1.dcache.StoreCondReq_accesses::total 92843 # number of StoreCondReq accesses(hits+misses) 1917system.cpu1.dcache.demand_accesses::cpu1.data 12109261 # number of demand (read+write) accesses 1918system.cpu1.dcache.demand_accesses::total 12109261 # number of demand (read+write) accesses 1919system.cpu1.dcache.overall_accesses::cpu1.data 12109261 # number of overall (read+write) accesses 1920system.cpu1.dcache.overall_accesses::total 12109261 # number of overall (read+write) accesses 1921system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023961 # miss rate for ReadReq accesses 1922system.cpu1.dcache.ReadReq_miss_rate::total 0.023961 # miss rate for ReadReq accesses 1923system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030145 # miss rate for WriteReq accesses 1924system.cpu1.dcache.WriteReq_miss_rate::total 0.030145 # miss rate for WriteReq accesses 1925system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120868 # miss rate for LoadLockedReq accesses 1926system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120868 # miss rate for LoadLockedReq accesses 1927system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108290 # miss rate for StoreCondReq accesses 1928system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108290 # miss rate for StoreCondReq accesses 1929system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026507 # miss rate for demand accesses 1930system.cpu1.dcache.demand_miss_rate::total 0.026507 # miss rate for demand accesses 1931system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026507 # miss rate for overall accesses 1932system.cpu1.dcache.overall_miss_rate::total 0.026507 # miss rate for overall accesses 1933system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12999.601654 # average ReadReq miss latency 1934system.cpu1.dcache.ReadReq_avg_miss_latency::total 12999.601654 # average ReadReq miss latency 1935system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 43832.403883 # average WriteReq miss latency 1936system.cpu1.dcache.WriteReq_avg_miss_latency::total 43832.403883 # average WriteReq miss latency 1937system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8651.942523 # average LoadLockedReq miss latency 1938system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8651.942523 # average LoadLockedReq miss latency 1939system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5173.112592 # average StoreCondReq miss latency 1940system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5173.112592 # average StoreCondReq miss latency 1941system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency 1942system.cpu1.dcache.demand_avg_miss_latency::total 27432.974553 # average overall miss latency 1943system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27432.974553 # average overall miss latency 1944system.cpu1.dcache.overall_avg_miss_latency::total 27432.974553 # average overall miss latency 1945system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1946system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1947system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1948system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1949system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1950system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1951system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1952system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1953system.cpu1.dcache.writebacks::writebacks 265367 # number of writebacks 1954system.cpu1.dcache.writebacks::total 265367 # number of writebacks 1955system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170721 # number of ReadReq MSHR misses 1956system.cpu1.dcache.ReadReq_mshr_misses::total 170721 # number of ReadReq MSHR misses 1957system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150254 # number of WriteReq MSHR misses 1958system.cpu1.dcache.WriteReq_mshr_misses::total 150254 # number of WriteReq MSHR misses 1959system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11274 # number of LoadLockedReq MSHR misses 1960system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11274 # number of LoadLockedReq MSHR misses 1961system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10053 # number of StoreCondReq MSHR misses 1962system.cpu1.dcache.StoreCondReq_mshr_misses::total 10053 # number of StoreCondReq MSHR misses 1963system.cpu1.dcache.demand_mshr_misses::cpu1.data 320975 # number of demand (read+write) MSHR misses 1964system.cpu1.dcache.demand_mshr_misses::total 320975 # number of demand (read+write) MSHR misses 1965system.cpu1.dcache.overall_mshr_misses::cpu1.data 320975 # number of overall MSHR misses 1966system.cpu1.dcache.overall_mshr_misses::total 320975 # number of overall MSHR misses 1967system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1877186006 # number of ReadReq MSHR miss cycles 1968system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1877186006 # number of ReadReq MSHR miss cycles 1969system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6262088987 # number of WriteReq MSHR miss cycles 1970system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6262088987 # number of WriteReq MSHR miss cycles 1971system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74982000 # number of LoadLockedReq MSHR miss cycles 1972system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74982000 # number of LoadLockedReq MSHR miss cycles 1973system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31903526 # number of StoreCondReq MSHR miss cycles 1974system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31903526 # number of StoreCondReq MSHR miss cycles 1975system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8139274993 # number of demand (read+write) MSHR miss cycles 1976system.cpu1.dcache.demand_mshr_miss_latency::total 8139274993 # number of demand (read+write) MSHR miss cycles 1977system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8139274993 # number of overall MSHR miss cycles 1978system.cpu1.dcache.overall_mshr_miss_latency::total 8139274993 # number of overall MSHR miss cycles 1979system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608498500 # number of ReadReq MSHR uncacheable cycles 1980system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608498500 # number of ReadReq MSHR uncacheable cycles 1981system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25182871345 # number of WriteReq MSHR uncacheable cycles 1982system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25182871345 # number of WriteReq MSHR uncacheable cycles 1983system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791369845 # number of overall MSHR uncacheable cycles 1984system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791369845 # number of overall MSHR uncacheable cycles 1985system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023961 # mshr miss rate for ReadReq accesses 1986system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023961 # mshr miss rate for ReadReq accesses 1987system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses 1988system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses 1989system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120868 # mshr miss rate for LoadLockedReq accesses 1990system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120868 # mshr miss rate for LoadLockedReq accesses 1991system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108280 # mshr miss rate for StoreCondReq accesses 1992system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108280 # mshr miss rate for StoreCondReq accesses 1993system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses 1994system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses 1995system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses 1996system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses 1997system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10995.636190 # average ReadReq mshr miss latency 1998system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10995.636190 # average ReadReq mshr miss latency 1999system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41676.687389 # average WriteReq mshr miss latency 2000system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 41676.687389 # average WriteReq mshr miss latency 2001system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6650.878127 # average LoadLockedReq mshr miss latency 2002system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6650.878127 # average LoadLockedReq mshr miss latency 2003system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3173.532876 # average StoreCondReq mshr miss latency 2004system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3173.532876 # average StoreCondReq mshr miss latency 2005system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency 2006system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency 2007system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25357.971783 # average overall mshr miss latency 2008system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25357.971783 # average overall mshr miss latency 2009system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2010system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2011system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2012system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2013system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2014system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2015system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2016system.iocache.tags.replacements 0 # number of replacements 2017system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 2018system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2019system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 2020system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 2021system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2022system.iocache.tags.tag_accesses 0 # Number of tag accesses 2023system.iocache.tags.data_accesses 0 # Number of data accesses 2024system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2025system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2026system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2027system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2028system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2029system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2030system.iocache.fast_writes 0 # number of fast writes performed 2031system.iocache.cache_copies 0 # number of cache copies performed 2032system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 651805197501 # number of ReadReq MSHR uncacheable cycles 2033system.iocache.ReadReq_mshr_uncacheable_latency::total 651805197501 # number of ReadReq MSHR uncacheable cycles 2034system.iocache.overall_mshr_uncacheable_latency::realview.clcd 651805197501 # number of overall MSHR uncacheable cycles 2035system.iocache.overall_mshr_uncacheable_latency::total 651805197501 # number of overall MSHR uncacheable cycles 2036system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 2037system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2038system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 2039system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2040system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2041 2042---------- End Simulation Statistics ----------