1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.194884 # Number of seconds simulated
4sim_ticks 1194883580500 # Number of ticks simulated
5final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 298011 # Simulator instruction rate (inst/s)
8host_op_rate 379758 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5802481089 # Simulator tick rate (ticks/s)
10host_mem_usage 399660 # Number of bytes of host memory used
11host_seconds 205.93 # Real time elapsed on the host
12sim_insts 61368273 # Number of instructions simulated
13sim_ops 78202205 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory
22system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory
26system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory
27system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory
28system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
29system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory
30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory
38system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory
39system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory
40system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory
41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
42system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory
43system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s)
55system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s)
56system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s)
57system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s)
58system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller
70system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller
71system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
72system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
73system.physmem.bytesRead 425896384 # Total number of bytes read from memory
74system.physmem.bytesWritten 52573888 # Total number of bytes written to memory
75system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize()
76system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize()
77system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q
78system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed
79system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis
80system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis
81system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis
82system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis
83system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis
84system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis
85system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis
86system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis
87system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis
88system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis
89system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis
90system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis
91system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis
92system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis
93system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis
94system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis
95system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis
96system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis
97system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis
98system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis
99system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis
100system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis
101system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis
102system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis
103system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis
104system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis
105system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis
106system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis
107system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis
108system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis
109system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis
110system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis
111system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
112system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
113system.physmem.totGap 1194879167500 # Total gap between requests
114system.physmem.readPktSize::0 0 # Categorize read packet sizes
115system.physmem.readPktSize::1 0 # Categorize read packet sizes
116system.physmem.readPktSize::2 6825 # Categorize read packet sizes
117system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
118system.physmem.readPktSize::4 0 # Categorize read packet sizes
119system.physmem.readPktSize::5 0 # Categorize read packet sizes
120system.physmem.readPktSize::6 159742 # Categorize read packet sizes
121system.physmem.writePktSize::0 0 # Categorize write packet sizes
122system.physmem.writePktSize::1 0 # Categorize write packet sizes
123system.physmem.writePktSize::2 756836 # Categorize write packet sizes
124system.physmem.writePktSize::3 0 # Categorize write packet sizes
125system.physmem.writePktSize::4 0 # Categorize write packet sizes
126system.physmem.writePktSize::5 0 # Categorize write packet sizes
127system.physmem.writePktSize::6 64631 # Categorize write packet sizes
128system.physmem.rdQLenPdf::0 586175 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::1 426728 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::2 441027 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::3 1598520 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::4 1190036 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::5 1186243 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::6 1162812 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::7 9752 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::8 7190 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::9 12576 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::10 17869 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::11 12223 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::12 819 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::13 704 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::14 675 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::15 658 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
160system.physmem.wrQLenPdf::0 4962 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::2 4963 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::3 4963 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::5 4962 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::6 4962 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::7 4962 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::8 4962 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::9 4962 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::10 4962 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::11 4962 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::12 4962 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::13 4962 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::14 4962 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::15 4962 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::16 4962 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::17 4962 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::18 4962 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::19 4962 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::20 4962 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::21 4962 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::22 4962 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
192system.physmem.bytesPerActivate::samples 34155 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::mean 12682.337813 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::gmean 707.328285 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::stdev 25224.390929 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::64-127 7803 22.85% 22.85% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::128-191 4015 11.76% 34.60% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::192-255 2702 7.91% 42.51% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::256-319 1928 5.64% 48.16% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::320-383 1397 4.09% 52.25% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::384-447 1203 3.52% 55.77% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::448-511 946 2.77% 58.54% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::512-575 826 2.42% 60.96% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::576-639 667 1.95% 62.91% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-703 557 1.63% 64.54% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::704-767 438 1.28% 65.82% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::768-831 432 1.26% 67.09% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::832-895 317 0.93% 68.02% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::896-959 252 0.74% 68.75% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::960-1023 181 0.53% 69.28% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::1024-1087 297 0.87% 70.15% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1088-1151 146 0.43% 70.58% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::1152-1215 131 0.38% 70.96% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::1216-1279 122 0.36% 71.32% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::1280-1343 99 0.29% 71.61% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::1344-1407 97 0.28% 71.90% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::1408-1471 161 0.47% 72.37% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::1472-1535 728 2.13% 74.50% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::1536-1599 239 0.70% 75.20% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::1600-1663 168 0.49% 75.69% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::1664-1727 146 0.43% 76.12% # Bytes accessed per row activation
222system.physmem.bytesPerActivate::1728-1791 103 0.30% 76.42% # Bytes accessed per row activation
223system.physmem.bytesPerActivate::1792-1855 87 0.25% 76.67% # Bytes accessed per row activation
224system.physmem.bytesPerActivate::1856-1919 68 0.20% 76.87% # Bytes accessed per row activation
225system.physmem.bytesPerActivate::1920-1983 55 0.16% 77.03% # Bytes accessed per row activation
226system.physmem.bytesPerActivate::1984-2047 40 0.12% 77.15% # Bytes accessed per row activation
227system.physmem.bytesPerActivate::2048-2111 46 0.13% 77.29% # Bytes accessed per row activation
228system.physmem.bytesPerActivate::2112-2175 38 0.11% 77.40% # Bytes accessed per row activation
229system.physmem.bytesPerActivate::2176-2239 21 0.06% 77.46% # Bytes accessed per row activation
230system.physmem.bytesPerActivate::2240-2303 23 0.07% 77.53% # Bytes accessed per row activation
231system.physmem.bytesPerActivate::2304-2367 20 0.06% 77.58% # Bytes accessed per row activation
232system.physmem.bytesPerActivate::2368-2431 20 0.06% 77.64% # Bytes accessed per row activation
233system.physmem.bytesPerActivate::2432-2495 20 0.06% 77.70% # Bytes accessed per row activation
234system.physmem.bytesPerActivate::2496-2559 23 0.07% 77.77% # Bytes accessed per row activation
235system.physmem.bytesPerActivate::2560-2623 11 0.03% 77.80% # Bytes accessed per row activation
236system.physmem.bytesPerActivate::2624-2687 12 0.04% 77.84% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::2688-2751 19 0.06% 77.89% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::2752-2815 8 0.02% 77.92% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::2816-2879 17 0.05% 77.97% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::2880-2943 10 0.03% 77.99% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::2944-3007 5 0.01% 78.01% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::3008-3071 7 0.02% 78.03% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::3072-3135 13 0.04% 78.07% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::3136-3199 2 0.01% 78.07% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::3200-3263 15 0.04% 78.12% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::3264-3327 7 0.02% 78.14% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::3328-3391 12 0.04% 78.17% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::3392-3455 12 0.04% 78.21% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::3456-3519 8 0.02% 78.23% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::3520-3583 8 0.02% 78.26% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::3584-3647 11 0.03% 78.29% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::3648-3711 11 0.03% 78.32% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::3712-3775 6 0.02% 78.34% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::3776-3839 9 0.03% 78.36% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.38% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.39% # Bytes accessed per row activation
257system.physmem.bytesPerActivate::3968-4031 11 0.03% 78.42% # Bytes accessed per row activation
258system.physmem.bytesPerActivate::4032-4095 7 0.02% 78.44% # Bytes accessed per row activation
259system.physmem.bytesPerActivate::4096-4159 32 0.09% 78.54% # Bytes accessed per row activation
260system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.55% # Bytes accessed per row activation
261system.physmem.bytesPerActivate::4224-4287 3 0.01% 78.56% # Bytes accessed per row activation
262system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.57% # Bytes accessed per row activation
263system.physmem.bytesPerActivate::4352-4415 6 0.02% 78.59% # Bytes accessed per row activation
264system.physmem.bytesPerActivate::4416-4479 3 0.01% 78.60% # Bytes accessed per row activation
265system.physmem.bytesPerActivate::4480-4543 3 0.01% 78.61% # Bytes accessed per row activation
266system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.63% # Bytes accessed per row activation
267system.physmem.bytesPerActivate::4608-4671 7 0.02% 78.65% # Bytes accessed per row activation
268system.physmem.bytesPerActivate::4672-4735 5 0.01% 78.66% # Bytes accessed per row activation
269system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.67% # Bytes accessed per row activation
270system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.68% # Bytes accessed per row activation
271system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.69% # Bytes accessed per row activation
272system.physmem.bytesPerActivate::4928-4991 6 0.02% 78.71% # Bytes accessed per row activation
273system.physmem.bytesPerActivate::4992-5055 4 0.01% 78.72% # Bytes accessed per row activation
274system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.73% # Bytes accessed per row activation
275system.physmem.bytesPerActivate::5120-5183 5 0.01% 78.74% # Bytes accessed per row activation
276system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.75% # Bytes accessed per row activation
277system.physmem.bytesPerActivate::5248-5311 2 0.01% 78.75% # Bytes accessed per row activation
278system.physmem.bytesPerActivate::5376-5439 1 0.00% 78.76% # Bytes accessed per row activation
279system.physmem.bytesPerActivate::5568-5631 4 0.01% 78.77% # Bytes accessed per row activation
280system.physmem.bytesPerActivate::5632-5695 2 0.01% 78.77% # Bytes accessed per row activation
281system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.78% # Bytes accessed per row activation
282system.physmem.bytesPerActivate::5760-5823 3 0.01% 78.79% # Bytes accessed per row activation
283system.physmem.bytesPerActivate::5824-5887 4 0.01% 78.80% # Bytes accessed per row activation
284system.physmem.bytesPerActivate::5888-5951 1 0.00% 78.80% # Bytes accessed per row activation
285system.physmem.bytesPerActivate::5952-6015 2 0.01% 78.81% # Bytes accessed per row activation
286system.physmem.bytesPerActivate::6080-6143 4 0.01% 78.82% # Bytes accessed per row activation
287system.physmem.bytesPerActivate::6144-6207 5 0.01% 78.83% # Bytes accessed per row activation
288system.physmem.bytesPerActivate::6208-6271 1 0.00% 78.84% # Bytes accessed per row activation
289system.physmem.bytesPerActivate::6272-6335 2 0.01% 78.84% # Bytes accessed per row activation
290system.physmem.bytesPerActivate::6336-6399 2 0.01% 78.85% # Bytes accessed per row activation
291system.physmem.bytesPerActivate::6400-6463 1 0.00% 78.85% # Bytes accessed per row activation
292system.physmem.bytesPerActivate::6464-6527 2 0.01% 78.86% # Bytes accessed per row activation
293system.physmem.bytesPerActivate::6528-6591 1 0.00% 78.86% # Bytes accessed per row activation
294system.physmem.bytesPerActivate::6656-6719 4 0.01% 78.87% # Bytes accessed per row activation
295system.physmem.bytesPerActivate::6720-6783 1 0.00% 78.88% # Bytes accessed per row activation
296system.physmem.bytesPerActivate::6784-6847 22 0.06% 78.94% # Bytes accessed per row activation
297system.physmem.bytesPerActivate::6848-6911 3 0.01% 78.95% # Bytes accessed per row activation
298system.physmem.bytesPerActivate::6912-6975 1 0.00% 78.95% # Bytes accessed per row activation
299system.physmem.bytesPerActivate::6976-7039 1 0.00% 78.95% # Bytes accessed per row activation
300system.physmem.bytesPerActivate::7040-7103 5 0.01% 78.97% # Bytes accessed per row activation
301system.physmem.bytesPerActivate::7168-7231 7 0.02% 78.99% # Bytes accessed per row activation
302system.physmem.bytesPerActivate::7296-7359 3 0.01% 79.00% # Bytes accessed per row activation
303system.physmem.bytesPerActivate::7424-7487 2 0.01% 79.00% # Bytes accessed per row activation
304system.physmem.bytesPerActivate::7488-7551 2 0.01% 79.01% # Bytes accessed per row activation
305system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.02% # Bytes accessed per row activation
306system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.03% # Bytes accessed per row activation
307system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.04% # Bytes accessed per row activation
308system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.04% # Bytes accessed per row activation
309system.physmem.bytesPerActivate::7808-7871 6 0.02% 79.06% # Bytes accessed per row activation
310system.physmem.bytesPerActivate::7872-7935 7 0.02% 79.08% # Bytes accessed per row activation
311system.physmem.bytesPerActivate::7936-7999 1 0.00% 79.08% # Bytes accessed per row activation
312system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.09% # Bytes accessed per row activation
313system.physmem.bytesPerActivate::8064-8127 9 0.03% 79.12% # Bytes accessed per row activation
314system.physmem.bytesPerActivate::8128-8191 6 0.02% 79.14% # Bytes accessed per row activation
315system.physmem.bytesPerActivate::8192-8255 323 0.95% 80.08% # Bytes accessed per row activation
316system.physmem.bytesPerActivate::8256-8319 1 0.00% 80.08% # Bytes accessed per row activation
317system.physmem.bytesPerActivate::8448-8511 25 0.07% 80.16% # Bytes accessed per row activation
318system.physmem.bytesPerActivate::8512-8575 138 0.40% 80.56% # Bytes accessed per row activation
319system.physmem.bytesPerActivate::8576-8639 174 0.51% 81.07% # Bytes accessed per row activation
320system.physmem.bytesPerActivate::8704-8767 2 0.01% 81.08% # Bytes accessed per row activation
321system.physmem.bytesPerActivate::8832-8895 1 0.00% 81.08% # Bytes accessed per row activation
322system.physmem.bytesPerActivate::8896-8959 1 0.00% 81.08% # Bytes accessed per row activation
323system.physmem.bytesPerActivate::9408-9471 1 0.00% 81.09% # Bytes accessed per row activation
324system.physmem.bytesPerActivate::9984-10047 3 0.01% 81.10% # Bytes accessed per row activation
325system.physmem.bytesPerActivate::10240-10303 1 0.00% 81.10% # Bytes accessed per row activation
326system.physmem.bytesPerActivate::10752-10815 2 0.01% 81.10% # Bytes accessed per row activation
327system.physmem.bytesPerActivate::11008-11071 1 0.00% 81.11% # Bytes accessed per row activation
328system.physmem.bytesPerActivate::11264-11327 4 0.01% 81.12% # Bytes accessed per row activation
329system.physmem.bytesPerActivate::11776-11839 2 0.01% 81.12% # Bytes accessed per row activation
330system.physmem.bytesPerActivate::12032-12095 1 0.00% 81.13% # Bytes accessed per row activation
331system.physmem.bytesPerActivate::12288-12351 2 0.01% 81.13% # Bytes accessed per row activation
332system.physmem.bytesPerActivate::12544-12607 1 0.00% 81.14% # Bytes accessed per row activation
333system.physmem.bytesPerActivate::12800-12863 3 0.01% 81.14% # Bytes accessed per row activation
334system.physmem.bytesPerActivate::13056-13119 1 0.00% 81.15% # Bytes accessed per row activation
335system.physmem.bytesPerActivate::13312-13375 3 0.01% 81.16% # Bytes accessed per row activation
336system.physmem.bytesPerActivate::13568-13631 1 0.00% 81.16% # Bytes accessed per row activation
337system.physmem.bytesPerActivate::13824-13887 1 0.00% 81.16% # Bytes accessed per row activation
338system.physmem.bytesPerActivate::14080-14143 1 0.00% 81.17% # Bytes accessed per row activation
339system.physmem.bytesPerActivate::14208-14271 1 0.00% 81.17% # Bytes accessed per row activation
340system.physmem.bytesPerActivate::14336-14399 1 0.00% 81.17% # Bytes accessed per row activation
341system.physmem.bytesPerActivate::14848-14911 3 0.01% 81.18% # Bytes accessed per row activation
342system.physmem.bytesPerActivate::15104-15167 2 0.01% 81.19% # Bytes accessed per row activation
343system.physmem.bytesPerActivate::15360-15423 5 0.01% 81.20% # Bytes accessed per row activation
344system.physmem.bytesPerActivate::15616-15679 1 0.00% 81.20% # Bytes accessed per row activation
345system.physmem.bytesPerActivate::16128-16191 1 0.00% 81.21% # Bytes accessed per row activation
346system.physmem.bytesPerActivate::16384-16447 1 0.00% 81.21% # Bytes accessed per row activation
347system.physmem.bytesPerActivate::16640-16703 1 0.00% 81.21% # Bytes accessed per row activation
348system.physmem.bytesPerActivate::16896-16959 1 0.00% 81.22% # Bytes accessed per row activation
349system.physmem.bytesPerActivate::17152-17215 1 0.00% 81.22% # Bytes accessed per row activation
350system.physmem.bytesPerActivate::17408-17471 4 0.01% 81.23% # Bytes accessed per row activation
351system.physmem.bytesPerActivate::18176-18239 1 0.00% 81.23% # Bytes accessed per row activation
352system.physmem.bytesPerActivate::18432-18495 3 0.01% 81.24% # Bytes accessed per row activation
353system.physmem.bytesPerActivate::18688-18751 1 0.00% 81.24% # Bytes accessed per row activation
354system.physmem.bytesPerActivate::18944-19007 1 0.00% 81.25% # Bytes accessed per row activation
355system.physmem.bytesPerActivate::19136-19199 1 0.00% 81.25% # Bytes accessed per row activation
356system.physmem.bytesPerActivate::19200-19263 1 0.00% 81.25% # Bytes accessed per row activation
357system.physmem.bytesPerActivate::19328-19391 1 0.00% 81.26% # Bytes accessed per row activation
358system.physmem.bytesPerActivate::19456-19519 3 0.01% 81.26% # Bytes accessed per row activation
359system.physmem.bytesPerActivate::19712-19775 2 0.01% 81.27% # Bytes accessed per row activation
360system.physmem.bytesPerActivate::19968-20031 2 0.01% 81.28% # Bytes accessed per row activation
361system.physmem.bytesPerActivate::20480-20543 4 0.01% 81.29% # Bytes accessed per row activation
362system.physmem.bytesPerActivate::20992-21055 1 0.00% 81.29% # Bytes accessed per row activation
363system.physmem.bytesPerActivate::21248-21311 3 0.01% 81.30% # Bytes accessed per row activation
364system.physmem.bytesPerActivate::21504-21567 5 0.01% 81.31% # Bytes accessed per row activation
365system.physmem.bytesPerActivate::22272-22335 1 0.00% 81.32% # Bytes accessed per row activation
366system.physmem.bytesPerActivate::23552-23615 2 0.01% 81.32% # Bytes accessed per row activation
367system.physmem.bytesPerActivate::24064-24127 3 0.01% 81.33% # Bytes accessed per row activation
368system.physmem.bytesPerActivate::24320-24383 1 0.00% 81.34% # Bytes accessed per row activation
369system.physmem.bytesPerActivate::24576-24639 2 0.01% 81.34% # Bytes accessed per row activation
370system.physmem.bytesPerActivate::25088-25151 1 0.00% 81.34% # Bytes accessed per row activation
371system.physmem.bytesPerActivate::25600-25663 3 0.01% 81.35% # Bytes accessed per row activation
372system.physmem.bytesPerActivate::26112-26175 2 0.01% 81.36% # Bytes accessed per row activation
373system.physmem.bytesPerActivate::26368-26431 1 0.00% 81.36% # Bytes accessed per row activation
374system.physmem.bytesPerActivate::26624-26687 1 0.00% 81.36% # Bytes accessed per row activation
375system.physmem.bytesPerActivate::27136-27199 3 0.01% 81.37% # Bytes accessed per row activation
376system.physmem.bytesPerActivate::27392-27455 4 0.01% 81.38% # Bytes accessed per row activation
377system.physmem.bytesPerActivate::27648-27711 2 0.01% 81.39% # Bytes accessed per row activation
378system.physmem.bytesPerActivate::28416-28479 1 0.00% 81.39% # Bytes accessed per row activation
379system.physmem.bytesPerActivate::28672-28735 3 0.01% 81.40% # Bytes accessed per row activation
380system.physmem.bytesPerActivate::28928-28991 1 0.00% 81.41% # Bytes accessed per row activation
381system.physmem.bytesPerActivate::29184-29247 1 0.00% 81.41% # Bytes accessed per row activation
382system.physmem.bytesPerActivate::29440-29503 1 0.00% 81.41% # Bytes accessed per row activation
383system.physmem.bytesPerActivate::29696-29759 4 0.01% 81.42% # Bytes accessed per row activation
384system.physmem.bytesPerActivate::29952-30015 1 0.00% 81.43% # Bytes accessed per row activation
385system.physmem.bytesPerActivate::30208-30271 1 0.00% 81.43% # Bytes accessed per row activation
386system.physmem.bytesPerActivate::30976-31039 3 0.01% 81.44% # Bytes accessed per row activation
387system.physmem.bytesPerActivate::31232-31295 3 0.01% 81.45% # Bytes accessed per row activation
388system.physmem.bytesPerActivate::31488-31551 2 0.01% 81.45% # Bytes accessed per row activation
389system.physmem.bytesPerActivate::31744-31807 3 0.01% 81.46% # Bytes accessed per row activation
390system.physmem.bytesPerActivate::32768-32831 4 0.01% 81.47% # Bytes accessed per row activation
391system.physmem.bytesPerActivate::33024-33087 11 0.03% 81.50% # Bytes accessed per row activation
392system.physmem.bytesPerActivate::33280-33343 42 0.12% 81.63% # Bytes accessed per row activation
393system.physmem.bytesPerActivate::33792-33855 1 0.00% 81.63% # Bytes accessed per row activation
394system.physmem.bytesPerActivate::34048-34111 1 0.00% 81.63% # Bytes accessed per row activation
395system.physmem.bytesPerActivate::34112-34175 1 0.00% 81.64% # Bytes accessed per row activation
396system.physmem.bytesPerActivate::35072-35135 1 0.00% 81.64% # Bytes accessed per row activation
397system.physmem.bytesPerActivate::35840-35903 1 0.00% 81.64% # Bytes accessed per row activation
398system.physmem.bytesPerActivate::36864-36927 1 0.00% 81.65% # Bytes accessed per row activation
399system.physmem.bytesPerActivate::37120-37183 1 0.00% 81.65% # Bytes accessed per row activation
400system.physmem.bytesPerActivate::37888-37951 2 0.01% 81.65% # Bytes accessed per row activation
401system.physmem.bytesPerActivate::38144-38207 1 0.00% 81.66% # Bytes accessed per row activation
402system.physmem.bytesPerActivate::38912-38975 1 0.00% 81.66% # Bytes accessed per row activation
403system.physmem.bytesPerActivate::41472-41535 1 0.00% 81.66% # Bytes accessed per row activation
404system.physmem.bytesPerActivate::41984-42047 1 0.00% 81.67% # Bytes accessed per row activation
405system.physmem.bytesPerActivate::42240-42303 1 0.00% 81.67% # Bytes accessed per row activation
406system.physmem.bytesPerActivate::44032-44095 1 0.00% 81.67% # Bytes accessed per row activation
407system.physmem.bytesPerActivate::44800-44863 1 0.00% 81.67% # Bytes accessed per row activation
408system.physmem.bytesPerActivate::45056-45119 2 0.01% 81.68% # Bytes accessed per row activation
409system.physmem.bytesPerActivate::45568-45631 1 0.00% 81.68% # Bytes accessed per row activation
410system.physmem.bytesPerActivate::45824-45887 1 0.00% 81.69% # Bytes accessed per row activation
411system.physmem.bytesPerActivate::46208-46271 1 0.00% 81.69% # Bytes accessed per row activation
412system.physmem.bytesPerActivate::47360-47423 1 0.00% 81.69% # Bytes accessed per row activation
413system.physmem.bytesPerActivate::48128-48191 1 0.00% 81.70% # Bytes accessed per row activation
414system.physmem.bytesPerActivate::48896-48959 1 0.00% 81.70% # Bytes accessed per row activation
415system.physmem.bytesPerActivate::49152-49215 1 0.00% 81.70% # Bytes accessed per row activation
416system.physmem.bytesPerActivate::49408-49471 1 0.00% 81.70% # Bytes accessed per row activation
417system.physmem.bytesPerActivate::50176-50239 2 0.01% 81.71% # Bytes accessed per row activation
418system.physmem.bytesPerActivate::50688-50751 1 0.00% 81.71% # Bytes accessed per row activation
419system.physmem.bytesPerActivate::51328-51391 1 0.00% 81.72% # Bytes accessed per row activation
420system.physmem.bytesPerActivate::52224-52287 1 0.00% 81.72% # Bytes accessed per row activation
421system.physmem.bytesPerActivate::52480-52543 1 0.00% 81.72% # Bytes accessed per row activation
422system.physmem.bytesPerActivate::52992-53055 1 0.00% 81.72% # Bytes accessed per row activation
423system.physmem.bytesPerActivate::53248-53311 2 0.01% 81.73% # Bytes accessed per row activation
424system.physmem.bytesPerActivate::55552-55615 1 0.00% 81.73% # Bytes accessed per row activation
425system.physmem.bytesPerActivate::56128-56191 1 0.00% 81.74% # Bytes accessed per row activation
426system.physmem.bytesPerActivate::57088-57151 1 0.00% 81.74% # Bytes accessed per row activation
427system.physmem.bytesPerActivate::58112-58175 1 0.00% 81.74% # Bytes accessed per row activation
428system.physmem.bytesPerActivate::58368-58431 1 0.00% 81.74% # Bytes accessed per row activation
429system.physmem.bytesPerActivate::59392-59455 1 0.00% 81.75% # Bytes accessed per row activation
430system.physmem.bytesPerActivate::60928-60991 1 0.00% 81.75% # Bytes accessed per row activation
431system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.76% # Bytes accessed per row activation
432system.physmem.bytesPerActivate::61952-62015 1 0.00% 81.76% # Bytes accessed per row activation
433system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.76% # Bytes accessed per row activation
434system.physmem.bytesPerActivate::62720-62783 1 0.00% 81.77% # Bytes accessed per row activation
435system.physmem.bytesPerActivate::63680-63743 1 0.00% 81.77% # Bytes accessed per row activation
436system.physmem.bytesPerActivate::65024-65087 39 0.11% 81.88% # Bytes accessed per row activation
437system.physmem.bytesPerActivate::65280-65343 1 0.00% 81.89% # Bytes accessed per row activation
438system.physmem.bytesPerActivate::65472-65535 1 0.00% 81.89% # Bytes accessed per row activation
439system.physmem.bytesPerActivate::65536-65599 6180 18.09% 99.98% # Bytes accessed per row activation
440system.physmem.bytesPerActivate::66880-66943 1 0.00% 99.99% # Bytes accessed per row activation
441system.physmem.bytesPerActivate::66944-67007 1 0.00% 99.99% # Bytes accessed per row activation
442system.physmem.bytesPerActivate::67904-67967 1 0.00% 99.99% # Bytes accessed per row activation
443system.physmem.bytesPerActivate::74048-74111 1 0.00% 99.99% # Bytes accessed per row activation
444system.physmem.bytesPerActivate::74112-74175 1 0.00% 100.00% # Bytes accessed per row activation
445system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
446system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation
447system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays
448system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests
449system.physmem.totBusLat 33270500000 # Total cycles spent in databus access
450system.physmem.totBankLat 8590725000 # Total cycles spent in bank access
451system.physmem.avgQLat 19013.79 # Average queueing delay per request
452system.physmem.avgBankLat 1291.04 # Average bank access latency per request
453system.physmem.avgBusLat 5000.00 # Average bus latency per request
454system.physmem.avgMemAccLat 25304.84 # Average memory access latency
455system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s
456system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s
457system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s
458system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s
459system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
460system.physmem.busUtil 3.13 # Data bus utilization in percentage
461system.physmem.avgRdQLen 0.14 # Average read queue length over time
462system.physmem.avgWrQLen 14.04 # Average write queue length over time
463system.physmem.readRowHits 6636405 # Number of row buffer hits during reads
464system.physmem.writeRowHits 97666 # Number of row buffer hits during writes
465system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
466system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes
467system.physmem.avgGap 159826.58 # Average gap between requests
468system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
469system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
470system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
471system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
472system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
473system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
474system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
475system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
476system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
477system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
478system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s)
479system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
480system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
481system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s)
482system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
483system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
484system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
485system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
486system.membus.throughput 60029719 # Throughput (bytes/s)
487system.membus.trans_dist::ReadReq 7703148 # Transaction distribution
488system.membus.trans_dist::ReadResp 7703148 # Transaction distribution
489system.membus.trans_dist::WriteReq 767203 # Transaction distribution
490system.membus.trans_dist::WriteResp 767203 # Transaction distribution
491system.membus.trans_dist::Writeback 64631 # Transaction distribution
492system.membus.trans_dist::UpgradeReq 27692 # Transaction distribution
493system.membus.trans_dist::SCUpgradeReq 16414 # Transaction distribution
494system.membus.trans_dist::UpgradeResp 10643 # Transaction distribution
495system.membus.trans_dist::ReadExReq 137763 # Transaction distribution
496system.membus.trans_dist::ReadExResp 137302 # Transaction distribution
497system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382562 # Packet count per connected master and slave (bytes)
498system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
499system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8866 # Packet count per connected master and slave (bytes)
500system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
501system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes)
502system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966647 # Packet count per connected master and slave (bytes)
503system.membus.pkt_count_system.l2c.mem_side::total 4359019 # Packet count per connected master and slave (bytes)
504system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes)
505system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes)
506system.membus.pkt_count::total 17335147 # Packet count per connected master and slave (bytes)
507system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389878 # Cumulative packet size per connected master and slave (bytes)
508system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
509system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17732 # Cumulative packet size per connected master and slave (bytes)
510system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
511system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes)
512system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414516 # Cumulative packet size per connected master and slave (bytes)
513system.membus.tot_pkt_size_system.l2c.mem_side::total 19824014 # Cumulative packet size per connected master and slave (bytes)
514system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes)
515system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes)
516system.membus.tot_pkt_size::total 71728526 # Cumulative packet size per connected master and slave (bytes)
517system.membus.data_through_bus 71728526 # Total data (bytes)
518system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
519system.membus.reqLayer0.occupancy 1208318500 # Layer occupancy (ticks)
520system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
521system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks)
522system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
523system.membus.reqLayer2.occupancy 7968000 # Layer occupancy (ticks)
524system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
525system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
526system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
527system.membus.reqLayer5.occupancy 776500 # Layer occupancy (ticks)
528system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
529system.membus.reqLayer6.occupancy 9149406000 # Layer occupancy (ticks)
530system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
531system.membus.respLayer1.occupancy 5034563338 # Layer occupancy (ticks)
532system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
533system.membus.respLayer2.occupancy 14646378749 # Layer occupancy (ticks)
534system.membus.respLayer2.utilization 1.2 # Layer utilization (%)
535system.l2c.tags.replacements 69624 # number of replacements
536system.l2c.tags.tagsinuse 53154.717455 # Cycle average of tags in use
537system.l2c.tags.total_refs 1650852 # Total number of references to valid blocks.
538system.l2c.tags.sampled_refs 134785 # Sample count of references to valid blocks.
539system.l2c.tags.avg_refs 12.248039 # Average number of references to valid blocks.
540system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
541system.l2c.tags.occ_blocks::writebacks 40039.692381 # Average occupied blocks per requestor
542system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667893 # Average occupied blocks per requestor
543system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor
544system.l2c.tags.occ_blocks::cpu0.inst 4638.680952 # Average occupied blocks per requestor
545system.l2c.tags.occ_blocks::cpu0.data 5789.816440 # Average occupied blocks per requestor
546system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor
547system.l2c.tags.occ_blocks::cpu1.inst 1927.067698 # Average occupied blocks per requestor
548system.l2c.tags.occ_blocks::cpu1.data 756.788910 # Average occupied blocks per requestor
549system.l2c.tags.occ_percent::writebacks 0.610957 # Average percentage of cache occupancy
550system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy
551system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
552system.l2c.tags.occ_percent::cpu0.inst 0.070781 # Average percentage of cache occupancy
553system.l2c.tags.occ_percent::cpu0.data 0.088346 # Average percentage of cache occupancy
554system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
555system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy
556system.l2c.tags.occ_percent::cpu1.data 0.011548 # Average percentage of cache occupancy
557system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy
558system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits
559system.l2c.ReadReq_hits::cpu0.itb.walker 1438 # number of ReadReq hits
560system.l2c.ReadReq_hits::cpu0.inst 483013 # number of ReadReq hits
561system.l2c.ReadReq_hits::cpu0.data 241892 # number of ReadReq hits
562system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits
563system.l2c.ReadReq_hits::cpu1.itb.walker 1869 # number of ReadReq hits
564system.l2c.ReadReq_hits::cpu1.inst 372280 # number of ReadReq hits
565system.l2c.ReadReq_hits::cpu1.data 110462 # number of ReadReq hits
566system.l2c.ReadReq_hits::total 1219260 # number of ReadReq hits
567system.l2c.Writeback_hits::writebacks 576006 # number of Writeback hits
568system.l2c.Writeback_hits::total 576006 # number of Writeback hits
569system.l2c.UpgradeReq_hits::cpu0.data 1292 # number of UpgradeReq hits
570system.l2c.UpgradeReq_hits::cpu1.data 416 # number of UpgradeReq hits
571system.l2c.UpgradeReq_hits::total 1708 # number of UpgradeReq hits
572system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits
573system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits
574system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits
575system.l2c.ReadExReq_hits::cpu0.data 65542 # number of ReadExReq hits
576system.l2c.ReadExReq_hits::cpu1.data 45349 # number of ReadExReq hits
577system.l2c.ReadExReq_hits::total 110891 # number of ReadExReq hits
578system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits
579system.l2c.demand_hits::cpu0.itb.walker 1438 # number of demand (read+write) hits
580system.l2c.demand_hits::cpu0.inst 483013 # number of demand (read+write) hits
581system.l2c.demand_hits::cpu0.data 307434 # number of demand (read+write) hits
582system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits
583system.l2c.demand_hits::cpu1.itb.walker 1869 # number of demand (read+write) hits
584system.l2c.demand_hits::cpu1.inst 372280 # number of demand (read+write) hits
585system.l2c.demand_hits::cpu1.data 155811 # number of demand (read+write) hits
586system.l2c.demand_hits::total 1330151 # number of demand (read+write) hits
587system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits
588system.l2c.overall_hits::cpu0.itb.walker 1438 # number of overall hits
589system.l2c.overall_hits::cpu0.inst 483013 # number of overall hits
590system.l2c.overall_hits::cpu0.data 307434 # number of overall hits
591system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits
592system.l2c.overall_hits::cpu1.itb.walker 1869 # number of overall hits
593system.l2c.overall_hits::cpu1.inst 372280 # number of overall hits
594system.l2c.overall_hits::cpu1.data 155811 # number of overall hits
595system.l2c.overall_hits::total 1330151 # number of overall hits
596system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
597system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
598system.l2c.ReadReq_misses::cpu0.inst 6832 # number of ReadReq misses
599system.l2c.ReadReq_misses::cpu0.data 9716 # number of ReadReq misses
600system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
601system.l2c.ReadReq_misses::cpu1.inst 3996 # number of ReadReq misses
602system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses
603system.l2c.ReadReq_misses::total 22441 # number of ReadReq misses
604system.l2c.UpgradeReq_misses::cpu0.data 3974 # number of UpgradeReq misses
605system.l2c.UpgradeReq_misses::cpu1.data 3371 # number of UpgradeReq misses
606system.l2c.UpgradeReq_misses::total 7345 # number of UpgradeReq misses
607system.l2c.SCUpgradeReq_misses::cpu0.data 385 # number of SCUpgradeReq misses
608system.l2c.SCUpgradeReq_misses::cpu1.data 476 # number of SCUpgradeReq misses
609system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses
610system.l2c.ReadExReq_misses::cpu0.data 95136 # number of ReadExReq misses
611system.l2c.ReadExReq_misses::cpu1.data 44603 # number of ReadExReq misses
612system.l2c.ReadExReq_misses::total 139739 # number of ReadExReq misses
613system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
614system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
615system.l2c.demand_misses::cpu0.inst 6832 # number of demand (read+write) misses
616system.l2c.demand_misses::cpu0.data 104852 # number of demand (read+write) misses
617system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
618system.l2c.demand_misses::cpu1.inst 3996 # number of demand (read+write) misses
619system.l2c.demand_misses::cpu1.data 46493 # number of demand (read+write) misses
620system.l2c.demand_misses::total 162180 # number of demand (read+write) misses
621system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
622system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
623system.l2c.overall_misses::cpu0.inst 6832 # number of overall misses
624system.l2c.overall_misses::cpu0.data 104852 # number of overall misses
625system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
626system.l2c.overall_misses::cpu1.inst 3996 # number of overall misses
627system.l2c.overall_misses::cpu1.data 46493 # number of overall misses
628system.l2c.overall_misses::total 162180 # number of overall misses
629system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 687750 # number of ReadReq miss cycles
630system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles
631system.l2c.ReadReq_miss_latency::cpu0.inst 482771250 # number of ReadReq miss cycles
632system.l2c.ReadReq_miss_latency::cpu0.data 688091749 # number of ReadReq miss cycles
633system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles
634system.l2c.ReadReq_miss_latency::cpu1.inst 282183750 # number of ReadReq miss cycles
635system.l2c.ReadReq_miss_latency::cpu1.data 151111000 # number of ReadReq miss cycles
636system.l2c.ReadReq_miss_latency::total 1605057249 # number of ReadReq miss cycles
637system.l2c.UpgradeReq_miss_latency::cpu0.data 11611000 # number of UpgradeReq miss cycles
638system.l2c.UpgradeReq_miss_latency::cpu1.data 12427970 # number of UpgradeReq miss cycles
639system.l2c.UpgradeReq_miss_latency::total 24038970 # number of UpgradeReq miss cycles
640system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1906918 # number of SCUpgradeReq miss cycles
641system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117452 # number of SCUpgradeReq miss cycles
642system.l2c.SCUpgradeReq_miss_latency::total 3024370 # number of SCUpgradeReq miss cycles
643system.l2c.ReadExReq_miss_latency::cpu0.data 6193599427 # number of ReadExReq miss cycles
644system.l2c.ReadExReq_miss_latency::cpu1.data 2824169884 # number of ReadExReq miss cycles
645system.l2c.ReadExReq_miss_latency::total 9017769311 # number of ReadExReq miss cycles
646system.l2c.demand_miss_latency::cpu0.dtb.walker 687750 # number of demand (read+write) miss cycles
647system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles
648system.l2c.demand_miss_latency::cpu0.inst 482771250 # number of demand (read+write) miss cycles
649system.l2c.demand_miss_latency::cpu0.data 6881691176 # number of demand (read+write) miss cycles
650system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles
651system.l2c.demand_miss_latency::cpu1.inst 282183750 # number of demand (read+write) miss cycles
652system.l2c.demand_miss_latency::cpu1.data 2975280884 # number of demand (read+write) miss cycles
653system.l2c.demand_miss_latency::total 10622826560 # number of demand (read+write) miss cycles
654system.l2c.overall_miss_latency::cpu0.dtb.walker 687750 # number of overall miss cycles
655system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles
656system.l2c.overall_miss_latency::cpu0.inst 482771250 # number of overall miss cycles
657system.l2c.overall_miss_latency::cpu0.data 6881691176 # number of overall miss cycles
658system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles
659system.l2c.overall_miss_latency::cpu1.inst 282183750 # number of overall miss cycles
660system.l2c.overall_miss_latency::cpu1.data 2975280884 # number of overall miss cycles
661system.l2c.overall_miss_latency::total 10622826560 # number of overall miss cycles
662system.l2c.ReadReq_accesses::cpu0.dtb.walker 4528 # number of ReadReq accesses(hits+misses)
663system.l2c.ReadReq_accesses::cpu0.itb.walker 1440 # number of ReadReq accesses(hits+misses)
664system.l2c.ReadReq_accesses::cpu0.inst 489845 # number of ReadReq accesses(hits+misses)
665system.l2c.ReadReq_accesses::cpu0.data 251608 # number of ReadReq accesses(hits+misses)
666system.l2c.ReadReq_accesses::cpu1.dtb.walker 3782 # number of ReadReq accesses(hits+misses)
667system.l2c.ReadReq_accesses::cpu1.itb.walker 1870 # number of ReadReq accesses(hits+misses)
668system.l2c.ReadReq_accesses::cpu1.inst 376276 # number of ReadReq accesses(hits+misses)
669system.l2c.ReadReq_accesses::cpu1.data 112352 # number of ReadReq accesses(hits+misses)
670system.l2c.ReadReq_accesses::total 1241701 # number of ReadReq accesses(hits+misses)
671system.l2c.Writeback_accesses::writebacks 576006 # number of Writeback accesses(hits+misses)
672system.l2c.Writeback_accesses::total 576006 # number of Writeback accesses(hits+misses)
673system.l2c.UpgradeReq_accesses::cpu0.data 5266 # number of UpgradeReq accesses(hits+misses)
674system.l2c.UpgradeReq_accesses::cpu1.data 3787 # number of UpgradeReq accesses(hits+misses)
675system.l2c.UpgradeReq_accesses::total 9053 # number of UpgradeReq accesses(hits+misses)
676system.l2c.SCUpgradeReq_accesses::cpu0.data 640 # number of SCUpgradeReq accesses(hits+misses)
677system.l2c.SCUpgradeReq_accesses::cpu1.data 576 # number of SCUpgradeReq accesses(hits+misses)
678system.l2c.SCUpgradeReq_accesses::total 1216 # number of SCUpgradeReq accesses(hits+misses)
679system.l2c.ReadExReq_accesses::cpu0.data 160678 # number of ReadExReq accesses(hits+misses)
680system.l2c.ReadExReq_accesses::cpu1.data 89952 # number of ReadExReq accesses(hits+misses)
681system.l2c.ReadExReq_accesses::total 250630 # number of ReadExReq accesses(hits+misses)
682system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses
683system.l2c.demand_accesses::cpu0.itb.walker 1440 # number of demand (read+write) accesses
684system.l2c.demand_accesses::cpu0.inst 489845 # number of demand (read+write) accesses
685system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses
686system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses
687system.l2c.demand_accesses::cpu1.itb.walker 1870 # number of demand (read+write) accesses
688system.l2c.demand_accesses::cpu1.inst 376276 # number of demand (read+write) accesses
689system.l2c.demand_accesses::cpu1.data 202304 # number of demand (read+write) accesses
690system.l2c.demand_accesses::total 1492331 # number of demand (read+write) accesses
691system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses
692system.l2c.overall_accesses::cpu0.itb.walker 1440 # number of overall (read+write) accesses
693system.l2c.overall_accesses::cpu0.inst 489845 # number of overall (read+write) accesses
694system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses
695system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses
696system.l2c.overall_accesses::cpu1.itb.walker 1870 # number of overall (read+write) accesses
697system.l2c.overall_accesses::cpu1.inst 376276 # number of overall (read+write) accesses
698system.l2c.overall_accesses::cpu1.data 202304 # number of overall (read+write) accesses
699system.l2c.overall_accesses::total 1492331 # number of overall (read+write) accesses
700system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses
701system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001389 # miss rate for ReadReq accesses
702system.l2c.ReadReq_miss_rate::cpu0.inst 0.013947 # miss rate for ReadReq accesses
703system.l2c.ReadReq_miss_rate::cpu0.data 0.038616 # miss rate for ReadReq accesses
704system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses
705system.l2c.ReadReq_miss_rate::cpu1.inst 0.010620 # miss rate for ReadReq accesses
706system.l2c.ReadReq_miss_rate::cpu1.data 0.016822 # miss rate for ReadReq accesses
707system.l2c.ReadReq_miss_rate::total 0.018073 # miss rate for ReadReq accesses
708system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754652 # miss rate for UpgradeReq accesses
709system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890151 # miss rate for UpgradeReq accesses
710system.l2c.UpgradeReq_miss_rate::total 0.811333 # miss rate for UpgradeReq accesses
711system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.601562 # miss rate for SCUpgradeReq accesses
712system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826389 # miss rate for SCUpgradeReq accesses
713system.l2c.SCUpgradeReq_miss_rate::total 0.708059 # miss rate for SCUpgradeReq accesses
714system.l2c.ReadExReq_miss_rate::cpu0.data 0.592091 # miss rate for ReadExReq accesses
715system.l2c.ReadExReq_miss_rate::cpu1.data 0.495853 # miss rate for ReadExReq accesses
716system.l2c.ReadExReq_miss_rate::total 0.557551 # miss rate for ReadExReq accesses
717system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses
718system.l2c.demand_miss_rate::cpu0.itb.walker 0.001389 # miss rate for demand accesses
719system.l2c.demand_miss_rate::cpu0.inst 0.013947 # miss rate for demand accesses
720system.l2c.demand_miss_rate::cpu0.data 0.254319 # miss rate for demand accesses
721system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses
722system.l2c.demand_miss_rate::cpu1.inst 0.010620 # miss rate for demand accesses
723system.l2c.demand_miss_rate::cpu1.data 0.229818 # miss rate for demand accesses
724system.l2c.demand_miss_rate::total 0.108676 # miss rate for demand accesses
725system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses
726system.l2c.overall_miss_rate::cpu0.itb.walker 0.001389 # miss rate for overall accesses
727system.l2c.overall_miss_rate::cpu0.inst 0.013947 # miss rate for overall accesses
728system.l2c.overall_miss_rate::cpu0.data 0.254319 # miss rate for overall accesses
729system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses
730system.l2c.overall_miss_rate::cpu1.inst 0.010620 # miss rate for overall accesses
731system.l2c.overall_miss_rate::cpu1.data 0.229818 # miss rate for overall accesses
732system.l2c.overall_miss_rate::total 0.108676 # miss rate for overall accesses
733system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average ReadReq miss latency
734system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency
735system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70663.239169 # average ReadReq miss latency
736system.l2c.ReadReq_avg_miss_latency::cpu0.data 70820.476431 # average ReadReq miss latency
737system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency
738system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70616.554054 # average ReadReq miss latency
739system.l2c.ReadReq_avg_miss_latency::cpu1.data 79952.910053 # average ReadReq miss latency
740system.l2c.ReadReq_avg_miss_latency::total 71523.428056 # average ReadReq miss latency
741system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2921.741319 # average UpgradeReq miss latency
742system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3686.730940 # average UpgradeReq miss latency
743system.l2c.UpgradeReq_avg_miss_latency::total 3272.834581 # average UpgradeReq miss latency
744system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4953.033766 # average SCUpgradeReq miss latency
745system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2347.588235 # average SCUpgradeReq miss latency
746system.l2c.SCUpgradeReq_avg_miss_latency::total 3512.624855 # average SCUpgradeReq miss latency
747system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65102.583953 # average ReadExReq miss latency
748system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63317.935655 # average ReadExReq miss latency
749system.l2c.ReadExReq_avg_miss_latency::total 64532.945785 # average ReadExReq miss latency
750system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency
751system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency
752system.l2c.demand_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency
753system.l2c.demand_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency
754system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency
755system.l2c.demand_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency
756system.l2c.demand_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency
757system.l2c.demand_avg_miss_latency::total 65500.225429 # average overall miss latency
758system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency
759system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency
760system.l2c.overall_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency
761system.l2c.overall_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency
762system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency
763system.l2c.overall_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency
764system.l2c.overall_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency
765system.l2c.overall_avg_miss_latency::total 65500.225429 # average overall miss latency
766system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
767system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
768system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
769system.l2c.blocked::no_targets 0 # number of cycles access was blocked
770system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
771system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
772system.l2c.fast_writes 0 # number of fast writes performed
773system.l2c.cache_copies 0 # number of cache copies performed
774system.l2c.writebacks::writebacks 64631 # number of writebacks
775system.l2c.writebacks::total 64631 # number of writebacks
776system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits
777system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
778system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
779system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
780system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
781system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
782system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses
783system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
784system.l2c.ReadReq_mshr_misses::cpu0.inst 6831 # number of ReadReq MSHR misses
785system.l2c.ReadReq_mshr_misses::cpu0.data 9716 # number of ReadReq MSHR misses
786system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
787system.l2c.ReadReq_mshr_misses::cpu1.inst 3996 # number of ReadReq MSHR misses
788system.l2c.ReadReq_mshr_misses::cpu1.data 1890 # number of ReadReq MSHR misses
789system.l2c.ReadReq_mshr_misses::total 22440 # number of ReadReq MSHR misses
790system.l2c.UpgradeReq_mshr_misses::cpu0.data 3974 # number of UpgradeReq MSHR misses
791system.l2c.UpgradeReq_mshr_misses::cpu1.data 3371 # number of UpgradeReq MSHR misses
792system.l2c.UpgradeReq_mshr_misses::total 7345 # number of UpgradeReq MSHR misses
793system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 385 # number of SCUpgradeReq MSHR misses
794system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 476 # number of SCUpgradeReq MSHR misses
795system.l2c.SCUpgradeReq_mshr_misses::total 861 # number of SCUpgradeReq MSHR misses
796system.l2c.ReadExReq_mshr_misses::cpu0.data 95136 # number of ReadExReq MSHR misses
797system.l2c.ReadExReq_mshr_misses::cpu1.data 44603 # number of ReadExReq MSHR misses
798system.l2c.ReadExReq_mshr_misses::total 139739 # number of ReadExReq MSHR misses
799system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses
800system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
801system.l2c.demand_mshr_misses::cpu0.inst 6831 # number of demand (read+write) MSHR misses
802system.l2c.demand_mshr_misses::cpu0.data 104852 # number of demand (read+write) MSHR misses
803system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
804system.l2c.demand_mshr_misses::cpu1.inst 3996 # number of demand (read+write) MSHR misses
805system.l2c.demand_mshr_misses::cpu1.data 46493 # number of demand (read+write) MSHR misses
806system.l2c.demand_mshr_misses::total 162179 # number of demand (read+write) MSHR misses
807system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses
808system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
809system.l2c.overall_mshr_misses::cpu0.inst 6831 # number of overall MSHR misses
810system.l2c.overall_mshr_misses::cpu0.data 104852 # number of overall MSHR misses
811system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
812system.l2c.overall_mshr_misses::cpu1.inst 3996 # number of overall MSHR misses
813system.l2c.overall_mshr_misses::cpu1.data 46493 # number of overall MSHR misses
814system.l2c.overall_mshr_misses::total 162179 # number of overall MSHR misses
815system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 635750 # number of ReadReq MSHR miss cycles
816system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles
817system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 396501000 # number of ReadReq MSHR miss cycles
818system.l2c.ReadReq_mshr_miss_latency::cpu0.data 564859249 # number of ReadReq MSHR miss cycles
819system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles
820system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 231739250 # number of ReadReq MSHR miss cycles
821system.l2c.ReadReq_mshr_miss_latency::cpu1.data 127085000 # number of ReadReq MSHR miss cycles
822system.l2c.ReadReq_mshr_miss_latency::total 1320993999 # number of ReadReq MSHR miss cycles
823system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39771967 # number of UpgradeReq MSHR miss cycles
824system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33821856 # number of UpgradeReq MSHR miss cycles
825system.l2c.UpgradeReq_mshr_miss_latency::total 73593823 # number of UpgradeReq MSHR miss cycles
826system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3851884 # number of SCUpgradeReq MSHR miss cycles
827system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768975 # number of SCUpgradeReq MSHR miss cycles
828system.l2c.SCUpgradeReq_mshr_miss_latency::total 8620859 # number of SCUpgradeReq MSHR miss cycles
829system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5000986069 # number of ReadExReq MSHR miss cycles
830system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2264195114 # number of ReadExReq MSHR miss cycles
831system.l2c.ReadExReq_mshr_miss_latency::total 7265181183 # number of ReadExReq MSHR miss cycles
832system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 635750 # number of demand (read+write) MSHR miss cycles
833system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles
834system.l2c.demand_mshr_miss_latency::cpu0.inst 396501000 # number of demand (read+write) MSHR miss cycles
835system.l2c.demand_mshr_miss_latency::cpu0.data 5565845318 # number of demand (read+write) MSHR miss cycles
836system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles
837system.l2c.demand_mshr_miss_latency::cpu1.inst 231739250 # number of demand (read+write) MSHR miss cycles
838system.l2c.demand_mshr_miss_latency::cpu1.data 2391280114 # number of demand (read+write) MSHR miss cycles
839system.l2c.demand_mshr_miss_latency::total 8586175182 # number of demand (read+write) MSHR miss cycles
840system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 635750 # number of overall MSHR miss cycles
841system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles
842system.l2c.overall_mshr_miss_latency::cpu0.inst 396501000 # number of overall MSHR miss cycles
843system.l2c.overall_mshr_miss_latency::cpu0.data 5565845318 # number of overall MSHR miss cycles
844system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles
845system.l2c.overall_mshr_miss_latency::cpu1.inst 231739250 # number of overall MSHR miss cycles
846system.l2c.overall_mshr_miss_latency::cpu1.data 2391280114 # number of overall MSHR miss cycles
847system.l2c.overall_mshr_miss_latency::total 8586175182 # number of overall MSHR miss cycles
848system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 323836500 # number of ReadReq MSHR uncacheable cycles
849system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12647640494 # number of ReadReq MSHR uncacheable cycles
850system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4849500 # number of ReadReq MSHR uncacheable cycles
851system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070543500 # number of ReadReq MSHR uncacheable cycles
852system.l2c.ReadReq_mshr_uncacheable_latency::total 167046869994 # number of ReadReq MSHR uncacheable cycles
853system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272049535 # number of WriteReq MSHR uncacheable cycles
854system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486218500 # number of WriteReq MSHR uncacheable cycles
855system.l2c.WriteReq_mshr_uncacheable_latency::total 16758268035 # number of WriteReq MSHR uncacheable cycles
856system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 323836500 # number of overall MSHR uncacheable cycles
857system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919690029 # number of overall MSHR uncacheable cycles
858system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4849500 # number of overall MSHR uncacheable cycles
859system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556762000 # number of overall MSHR uncacheable cycles
860system.l2c.overall_mshr_uncacheable_latency::total 183805138029 # number of overall MSHR uncacheable cycles
861system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses
862system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for ReadReq accesses
863system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for ReadReq accesses
864system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038616 # mshr miss rate for ReadReq accesses
865system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses
866system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for ReadReq accesses
867system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016822 # mshr miss rate for ReadReq accesses
868system.l2c.ReadReq_mshr_miss_rate::total 0.018072 # mshr miss rate for ReadReq accesses
869system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754652 # mshr miss rate for UpgradeReq accesses
870system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890151 # mshr miss rate for UpgradeReq accesses
871system.l2c.UpgradeReq_mshr_miss_rate::total 0.811333 # mshr miss rate for UpgradeReq accesses
872system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601562 # mshr miss rate for SCUpgradeReq accesses
873system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826389 # mshr miss rate for SCUpgradeReq accesses
874system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708059 # mshr miss rate for SCUpgradeReq accesses
875system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592091 # mshr miss rate for ReadExReq accesses
876system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495853 # mshr miss rate for ReadExReq accesses
877system.l2c.ReadExReq_mshr_miss_rate::total 0.557551 # mshr miss rate for ReadExReq accesses
878system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses
879system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for demand accesses
880system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for demand accesses
881system.l2c.demand_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for demand accesses
882system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses
883system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for demand accesses
884system.l2c.demand_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for demand accesses
885system.l2c.demand_mshr_miss_rate::total 0.108675 # mshr miss rate for demand accesses
886system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses
887system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for overall accesses
888system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for overall accesses
889system.l2c.overall_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for overall accesses
890system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses
891system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for overall accesses
892system.l2c.overall_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for overall accesses
893system.l2c.overall_mshr_miss_rate::total 0.108675 # mshr miss rate for overall accesses
894system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average ReadReq mshr miss latency
895system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency
896system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average ReadReq mshr miss latency
897system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58137.016159 # average ReadReq mshr miss latency
898system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency
899system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average ReadReq mshr miss latency
900system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67240.740741 # average ReadReq mshr miss latency
901system.l2c.ReadReq_avg_mshr_miss_latency::total 58867.825267 # average ReadReq mshr miss latency
902system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.044036 # average UpgradeReq mshr miss latency
903system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.181845 # average UpgradeReq mshr miss latency
904system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.581076 # average UpgradeReq mshr miss latency
905system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.893506 # average SCUpgradeReq mshr miss latency
906system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.855042 # average SCUpgradeReq mshr miss latency
907system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.612079 # average SCUpgradeReq mshr miss latency
908system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52566.705233 # average ReadExReq mshr miss latency
909system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50763.292021 # average ReadExReq mshr miss latency
910system.l2c.ReadExReq_avg_mshr_miss_latency::total 51991.077530 # average ReadExReq mshr miss latency
911system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency
912system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
913system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency
914system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency
915system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
916system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency
917system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency
918system.l2c.demand_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency
919system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency
920system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
921system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency
922system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency
923system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
924system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency
925system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency
926system.l2c.overall_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency
927system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
928system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
929system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
930system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
931system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
932system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
933system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
934system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency

--- 4 unchanged lines hidden (view full) ---

939system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
940system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
941system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
942system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
943system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
944system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
945system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
946system.cf0.dma_write_txs 0 # Number of DMA write transactions.
947system.toL2Bus.throughput 118384606 # Throughput (bytes/s)
948system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution
949system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution
950system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution
951system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution
952system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution
953system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution
954system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution
955system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution
956system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution
957system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution
958system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes)
959system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes)
960system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes)
961system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes)
962system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes)
963system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes)
964system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes)
965system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes)
966system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes)
967system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes)
968system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes)
969system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes)
970system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes)
971system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes)
972system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes)
973system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes)
974system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes)
975system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes)
976system.toL2Bus.data_through_bus 137140510 # Total data (bytes)
977system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes)
978system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks)
979system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
980system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks)
981system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
982system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks)
983system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
984system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks)
985system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
986system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks)
987system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
988system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks)
989system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
990system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks)
991system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
992system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks)
993system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
994system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks)
995system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
996system.iobus.throughput 45439063 # Throughput (bytes/s)
997system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution
998system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution
999system.iobus.trans_dist::WriteReq 7946 # Transaction distribution
1000system.iobus.trans_dist::WriteResp 7946 # Transaction distribution
1001system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
1002system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes)
1003system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1004system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
1005system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
1006system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1007system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
1008system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
1009system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
1010system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
1011system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
1012system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
1013system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
1014system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
1015system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
1016system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
1017system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
1018system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
1019system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
1020system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
1021system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
1022system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
1023system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
1024system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes)
1025system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
1026system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
1027system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes)
1028system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
1029system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes)
1030system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
1031system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
1032system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
1033system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
1034system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
1035system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
1036system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1037system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1038system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1039system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1040system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1041system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
1042system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1043system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1044system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1045system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1046system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1047system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1048system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1049system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
1050system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
1051system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes)
1052system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
1053system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
1054system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes)
1055system.iobus.data_through_bus 54294390 # Total data (bytes)
1056system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks)
1057system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
1058system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks)
1059system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
1060system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
1061system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
1062system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks)
1063system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
1064system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
1065system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
1066system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
1067system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
1068system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks)
1069system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1070system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)

--- 25 unchanged lines hidden (view full) ---

1096system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
1097system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1098system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
1099system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1100system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
1101system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1102system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks)
1103system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
1104system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks)
1105system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
1106system.iobus.respLayer1.occupancy 17783069251 # Layer occupancy (ticks)
1107system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
1108system.cpu0.dtb.inst_hits 0 # ITB inst hits
1109system.cpu0.dtb.inst_misses 0 # ITB inst misses
1110system.cpu0.dtb.read_hits 9653247 # DTB read hits
1111system.cpu0.dtb.read_misses 3738 # DTB read misses
1112system.cpu0.dtb.write_hits 7597488 # DTB write hits
1113system.cpu0.dtb.write_misses 1585 # DTB write misses
1114system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1115system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1116system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1117system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1118system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB
1119system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1120system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch
1121system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1122system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
1123system.cpu0.dtb.read_accesses 9656985 # DTB read accesses
1124system.cpu0.dtb.write_accesses 7599073 # DTB write accesses
1125system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
1126system.cpu0.dtb.hits 17250735 # DTB hits
1127system.cpu0.dtb.misses 5323 # DTB misses
1128system.cpu0.dtb.accesses 17256058 # DTB accesses
1129system.cpu0.itb.inst_hits 43297764 # ITB inst hits
1130system.cpu0.itb.inst_misses 2205 # ITB inst misses
1131system.cpu0.itb.read_hits 0 # DTB read hits
1132system.cpu0.itb.read_misses 0 # DTB read misses
1133system.cpu0.itb.write_hits 0 # DTB write hits
1134system.cpu0.itb.write_misses 0 # DTB write misses
1135system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
1136system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1137system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1138system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1139system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
1140system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1141system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1142system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1143system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1144system.cpu0.itb.read_accesses 0 # DTB read accesses
1145system.cpu0.itb.write_accesses 0 # DTB write accesses
1146system.cpu0.itb.inst_accesses 43299969 # ITB inst accesses
1147system.cpu0.itb.hits 43297764 # DTB hits
1148system.cpu0.itb.misses 2205 # DTB misses
1149system.cpu0.itb.accesses 43299969 # DTB accesses
1150system.cpu0.numCycles 2389767161 # number of cpu cycles simulated
1151system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1152system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1153system.cpu0.committedInsts 42570861 # Number of instructions committed
1154system.cpu0.committedOps 53303375 # Number of ops (including micro ops) committed
1155system.cpu0.num_int_alu_accesses 48060351 # Number of integer alu accesses
1156system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
1157system.cpu0.num_func_calls 1403492 # number of times a function call or return occured
1158system.cpu0.num_conditional_control_insts 5582702 # number of instructions that are conditional controls
1159system.cpu0.num_int_insts 48060351 # number of integer instructions
1160system.cpu0.num_fp_insts 3860 # number of float instructions
1161system.cpu0.num_int_register_reads 272449792 # number of times the integer registers were read
1162system.cpu0.num_int_register_writes 52270848 # number of times the integer registers were written
1163system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
1164system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
1165system.cpu0.num_mem_refs 18020156 # number of memory refs
1166system.cpu0.num_load_insts 10037111 # Number of load instructions
1167system.cpu0.num_store_insts 7983045 # Number of store instructions
1168system.cpu0.num_idle_cycles 2150298949.878201 # Number of idle cycles
1169system.cpu0.num_busy_cycles 239468211.121800 # Number of busy cycles
1170system.cpu0.not_idle_fraction 0.100206 # Percentage of non-idle cycles
1171system.cpu0.idle_fraction 0.899794 # Percentage of idle cycles
1172system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1173system.cpu0.kern.inst.quiesce 51312 # number of quiesce instructions executed
1174system.cpu0.icache.tags.replacements 490078 # number of replacements
1175system.cpu0.icache.tags.tagsinuse 509.399401 # Cycle average of tags in use
1176system.cpu0.icache.tags.total_refs 42807156 # Total number of references to valid blocks.
1177system.cpu0.icache.tags.sampled_refs 490590 # Sample count of references to valid blocks.
1178system.cpu0.icache.tags.avg_refs 87.256479 # Average number of references to valid blocks.
1179system.cpu0.icache.tags.warmup_cycle 76013480250 # Cycle when the warmup percentage was hit.
1180system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.399401 # Average occupied blocks per requestor
1181system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994921 # Average percentage of cache occupancy
1182system.cpu0.icache.tags.occ_percent::total 0.994921 # Average percentage of cache occupancy
1183system.cpu0.icache.ReadReq_hits::cpu0.inst 42807156 # number of ReadReq hits
1184system.cpu0.icache.ReadReq_hits::total 42807156 # number of ReadReq hits
1185system.cpu0.icache.demand_hits::cpu0.inst 42807156 # number of demand (read+write) hits
1186system.cpu0.icache.demand_hits::total 42807156 # number of demand (read+write) hits
1187system.cpu0.icache.overall_hits::cpu0.inst 42807156 # number of overall hits
1188system.cpu0.icache.overall_hits::total 42807156 # number of overall hits
1189system.cpu0.icache.ReadReq_misses::cpu0.inst 490591 # number of ReadReq misses
1190system.cpu0.icache.ReadReq_misses::total 490591 # number of ReadReq misses
1191system.cpu0.icache.demand_misses::cpu0.inst 490591 # number of demand (read+write) misses
1192system.cpu0.icache.demand_misses::total 490591 # number of demand (read+write) misses
1193system.cpu0.icache.overall_misses::cpu0.inst 490591 # number of overall misses
1194system.cpu0.icache.overall_misses::total 490591 # number of overall misses
1195system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6809993230 # number of ReadReq miss cycles
1196system.cpu0.icache.ReadReq_miss_latency::total 6809993230 # number of ReadReq miss cycles
1197system.cpu0.icache.demand_miss_latency::cpu0.inst 6809993230 # number of demand (read+write) miss cycles
1198system.cpu0.icache.demand_miss_latency::total 6809993230 # number of demand (read+write) miss cycles
1199system.cpu0.icache.overall_miss_latency::cpu0.inst 6809993230 # number of overall miss cycles
1200system.cpu0.icache.overall_miss_latency::total 6809993230 # number of overall miss cycles
1201system.cpu0.icache.ReadReq_accesses::cpu0.inst 43297747 # number of ReadReq accesses(hits+misses)
1202system.cpu0.icache.ReadReq_accesses::total 43297747 # number of ReadReq accesses(hits+misses)
1203system.cpu0.icache.demand_accesses::cpu0.inst 43297747 # number of demand (read+write) accesses
1204system.cpu0.icache.demand_accesses::total 43297747 # number of demand (read+write) accesses
1205system.cpu0.icache.overall_accesses::cpu0.inst 43297747 # number of overall (read+write) accesses
1206system.cpu0.icache.overall_accesses::total 43297747 # number of overall (read+write) accesses
1207system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011331 # miss rate for ReadReq accesses
1208system.cpu0.icache.ReadReq_miss_rate::total 0.011331 # miss rate for ReadReq accesses
1209system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011331 # miss rate for demand accesses
1210system.cpu0.icache.demand_miss_rate::total 0.011331 # miss rate for demand accesses
1211system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011331 # miss rate for overall accesses
1212system.cpu0.icache.overall_miss_rate::total 0.011331 # miss rate for overall accesses
1213system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13881.202937 # average ReadReq miss latency
1214system.cpu0.icache.ReadReq_avg_miss_latency::total 13881.202937 # average ReadReq miss latency
1215system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency
1216system.cpu0.icache.demand_avg_miss_latency::total 13881.202937 # average overall miss latency
1217system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency
1218system.cpu0.icache.overall_avg_miss_latency::total 13881.202937 # average overall miss latency
1219system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1220system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1221system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1222system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1223system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1224system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1225system.cpu0.icache.fast_writes 0 # number of fast writes performed
1226system.cpu0.icache.cache_copies 0 # number of cache copies performed
1227system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490591 # number of ReadReq MSHR misses
1228system.cpu0.icache.ReadReq_mshr_misses::total 490591 # number of ReadReq MSHR misses
1229system.cpu0.icache.demand_mshr_misses::cpu0.inst 490591 # number of demand (read+write) MSHR misses
1230system.cpu0.icache.demand_mshr_misses::total 490591 # number of demand (read+write) MSHR misses
1231system.cpu0.icache.overall_mshr_misses::cpu0.inst 490591 # number of overall MSHR misses
1232system.cpu0.icache.overall_mshr_misses::total 490591 # number of overall MSHR misses
1233system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5825469770 # number of ReadReq MSHR miss cycles
1234system.cpu0.icache.ReadReq_mshr_miss_latency::total 5825469770 # number of ReadReq MSHR miss cycles
1235system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5825469770 # number of demand (read+write) MSHR miss cycles
1236system.cpu0.icache.demand_mshr_miss_latency::total 5825469770 # number of demand (read+write) MSHR miss cycles
1237system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5825469770 # number of overall MSHR miss cycles
1238system.cpu0.icache.overall_mshr_miss_latency::total 5825469770 # number of overall MSHR miss cycles
1239system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 415499500 # number of ReadReq MSHR uncacheable cycles
1240system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 415499500 # number of ReadReq MSHR uncacheable cycles
1241system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 415499500 # number of overall MSHR uncacheable cycles
1242system.cpu0.icache.overall_mshr_uncacheable_latency::total 415499500 # number of overall MSHR uncacheable cycles
1243system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for ReadReq accesses
1244system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses
1245system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for demand accesses
1246system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses
1247system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for overall accesses
1248system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses
1249system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average ReadReq mshr miss latency
1250system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11874.391846 # average ReadReq mshr miss latency
1251system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency
1252system.cpu0.icache.demand_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency
1253system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency
1254system.cpu0.icache.overall_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency
1255system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1256system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1257system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1258system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1259system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1260system.cpu0.dcache.tags.replacements 406634 # number of replacements
1261system.cpu0.dcache.tags.tagsinuse 471.214045 # Cycle average of tags in use
1262system.cpu0.dcache.tags.total_refs 15967998 # Total number of references to valid blocks.
1263system.cpu0.dcache.tags.sampled_refs 407146 # Sample count of references to valid blocks.
1264system.cpu0.dcache.tags.avg_refs 39.219341 # Average number of references to valid blocks.
1265system.cpu0.dcache.tags.warmup_cycle 643231250 # Cycle when the warmup percentage was hit.
1266system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.214045 # Average occupied blocks per requestor
1267system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920340 # Average percentage of cache occupancy
1268system.cpu0.dcache.tags.occ_percent::total 0.920340 # Average percentage of cache occupancy
1269system.cpu0.dcache.ReadReq_hits::cpu0.data 9137347 # number of ReadReq hits
1270system.cpu0.dcache.ReadReq_hits::total 9137347 # number of ReadReq hits
1271system.cpu0.dcache.WriteReq_hits::cpu0.data 6494912 # number of WriteReq hits
1272system.cpu0.dcache.WriteReq_hits::total 6494912 # number of WriteReq hits
1273system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156532 # number of LoadLockedReq hits
1274system.cpu0.dcache.LoadLockedReq_hits::total 156532 # number of LoadLockedReq hits
1275system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159004 # number of StoreCondReq hits
1276system.cpu0.dcache.StoreCondReq_hits::total 159004 # number of StoreCondReq hits
1277system.cpu0.dcache.demand_hits::cpu0.data 15632259 # number of demand (read+write) hits
1278system.cpu0.dcache.demand_hits::total 15632259 # number of demand (read+write) hits
1279system.cpu0.dcache.overall_hits::cpu0.data 15632259 # number of overall hits
1280system.cpu0.dcache.overall_hits::total 15632259 # number of overall hits
1281system.cpu0.dcache.ReadReq_misses::cpu0.data 263669 # number of ReadReq misses
1282system.cpu0.dcache.ReadReq_misses::total 263669 # number of ReadReq misses
1283system.cpu0.dcache.WriteReq_misses::cpu0.data 176685 # number of WriteReq misses
1284system.cpu0.dcache.WriteReq_misses::total 176685 # number of WriteReq misses
1285system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9910 # number of LoadLockedReq misses
1286system.cpu0.dcache.LoadLockedReq_misses::total 9910 # number of LoadLockedReq misses
1287system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7384 # number of StoreCondReq misses
1288system.cpu0.dcache.StoreCondReq_misses::total 7384 # number of StoreCondReq misses
1289system.cpu0.dcache.demand_misses::cpu0.data 440354 # number of demand (read+write) misses
1290system.cpu0.dcache.demand_misses::total 440354 # number of demand (read+write) misses
1291system.cpu0.dcache.overall_misses::cpu0.data 440354 # number of overall misses
1292system.cpu0.dcache.overall_misses::total 440354 # number of overall misses
1293system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3876875497 # number of ReadReq miss cycles
1294system.cpu0.dcache.ReadReq_miss_latency::total 3876875497 # number of ReadReq miss cycles
1295system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7541622539 # number of WriteReq miss cycles
1296system.cpu0.dcache.WriteReq_miss_latency::total 7541622539 # number of WriteReq miss cycles
1297system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98733750 # number of LoadLockedReq miss cycles
1298system.cpu0.dcache.LoadLockedReq_miss_latency::total 98733750 # number of LoadLockedReq miss cycles
1299system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40506385 # number of StoreCondReq miss cycles
1300system.cpu0.dcache.StoreCondReq_miss_latency::total 40506385 # number of StoreCondReq miss cycles
1301system.cpu0.dcache.demand_miss_latency::cpu0.data 11418498036 # number of demand (read+write) miss cycles
1302system.cpu0.dcache.demand_miss_latency::total 11418498036 # number of demand (read+write) miss cycles
1303system.cpu0.dcache.overall_miss_latency::cpu0.data 11418498036 # number of overall miss cycles
1304system.cpu0.dcache.overall_miss_latency::total 11418498036 # number of overall miss cycles
1305system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401016 # number of ReadReq accesses(hits+misses)
1306system.cpu0.dcache.ReadReq_accesses::total 9401016 # number of ReadReq accesses(hits+misses)
1307system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671597 # number of WriteReq accesses(hits+misses)
1308system.cpu0.dcache.WriteReq_accesses::total 6671597 # number of WriteReq accesses(hits+misses)
1309system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166442 # number of LoadLockedReq accesses(hits+misses)
1310system.cpu0.dcache.LoadLockedReq_accesses::total 166442 # number of LoadLockedReq accesses(hits+misses)
1311system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166388 # number of StoreCondReq accesses(hits+misses)
1312system.cpu0.dcache.StoreCondReq_accesses::total 166388 # number of StoreCondReq accesses(hits+misses)
1313system.cpu0.dcache.demand_accesses::cpu0.data 16072613 # number of demand (read+write) accesses
1314system.cpu0.dcache.demand_accesses::total 16072613 # number of demand (read+write) accesses
1315system.cpu0.dcache.overall_accesses::cpu0.data 16072613 # number of overall (read+write) accesses
1316system.cpu0.dcache.overall_accesses::total 16072613 # number of overall (read+write) accesses
1317system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028047 # miss rate for ReadReq accesses
1318system.cpu0.dcache.ReadReq_miss_rate::total 0.028047 # miss rate for ReadReq accesses
1319system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026483 # miss rate for WriteReq accesses
1320system.cpu0.dcache.WriteReq_miss_rate::total 0.026483 # miss rate for WriteReq accesses
1321system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059540 # miss rate for LoadLockedReq accesses
1322system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059540 # miss rate for LoadLockedReq accesses
1323system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044378 # miss rate for StoreCondReq accesses
1324system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044378 # miss rate for StoreCondReq accesses
1325system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses
1326system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses
1327system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses
1328system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses
1329system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14703.569616 # average ReadReq miss latency
1330system.cpu0.dcache.ReadReq_avg_miss_latency::total 14703.569616 # average ReadReq miss latency
1331system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42683.999994 # average WriteReq miss latency
1332system.cpu0.dcache.WriteReq_avg_miss_latency::total 42683.999994 # average WriteReq miss latency
1333system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9963.042381 # average LoadLockedReq miss latency
1334system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9963.042381 # average LoadLockedReq miss latency
1335system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5485.696777 # average StoreCondReq miss latency
1336system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5485.696777 # average StoreCondReq miss latency
1337system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency
1338system.cpu0.dcache.demand_avg_miss_latency::total 25930.269819 # average overall miss latency
1339system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency
1340system.cpu0.dcache.overall_avg_miss_latency::total 25930.269819 # average overall miss latency
1341system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1342system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1343system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1344system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1345system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1346system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1347system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1348system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1349system.cpu0.dcache.writebacks::writebacks 376568 # number of writebacks
1350system.cpu0.dcache.writebacks::total 376568 # number of writebacks
1351system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263669 # number of ReadReq MSHR misses
1352system.cpu0.dcache.ReadReq_mshr_misses::total 263669 # number of ReadReq MSHR misses
1353system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176685 # number of WriteReq MSHR misses
1354system.cpu0.dcache.WriteReq_mshr_misses::total 176685 # number of WriteReq MSHR misses
1355system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9910 # number of LoadLockedReq MSHR misses
1356system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9910 # number of LoadLockedReq MSHR misses
1357system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7379 # number of StoreCondReq MSHR misses
1358system.cpu0.dcache.StoreCondReq_mshr_misses::total 7379 # number of StoreCondReq MSHR misses
1359system.cpu0.dcache.demand_mshr_misses::cpu0.data 440354 # number of demand (read+write) MSHR misses
1360system.cpu0.dcache.demand_mshr_misses::total 440354 # number of demand (read+write) MSHR misses
1361system.cpu0.dcache.overall_mshr_misses::cpu0.data 440354 # number of overall MSHR misses
1362system.cpu0.dcache.overall_mshr_misses::total 440354 # number of overall MSHR misses
1363system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3344880503 # number of ReadReq MSHR miss cycles
1364system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3344880503 # number of ReadReq MSHR miss cycles
1365system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7142186461 # number of WriteReq MSHR miss cycles
1366system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7142186461 # number of WriteReq MSHR miss cycles
1367system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78848250 # number of LoadLockedReq MSHR miss cycles
1368system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78848250 # number of LoadLockedReq MSHR miss cycles
1369system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25751615 # number of StoreCondReq MSHR miss cycles
1370system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25751615 # number of StoreCondReq MSHR miss cycles
1371system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles
1372system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles
1373system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10487066964 # number of demand (read+write) MSHR miss cycles
1374system.cpu0.dcache.demand_mshr_miss_latency::total 10487066964 # number of demand (read+write) MSHR miss cycles
1375system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10487066964 # number of overall MSHR miss cycles
1376system.cpu0.dcache.overall_mshr_miss_latency::total 10487066964 # number of overall MSHR miss cycles
1377system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764220500 # number of ReadReq MSHR uncacheable cycles
1378system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764220500 # number of ReadReq MSHR uncacheable cycles
1379system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807115461 # number of WriteReq MSHR uncacheable cycles
1380system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807115461 # number of WriteReq MSHR uncacheable cycles
1381system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39571335961 # number of overall MSHR uncacheable cycles
1382system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39571335961 # number of overall MSHR uncacheable cycles
1383system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028047 # mshr miss rate for ReadReq accesses
1384system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028047 # mshr miss rate for ReadReq accesses
1385system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026483 # mshr miss rate for WriteReq accesses
1386system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026483 # mshr miss rate for WriteReq accesses
1387system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059540 # mshr miss rate for LoadLockedReq accesses
1388system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059540 # mshr miss rate for LoadLockedReq accesses
1389system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044348 # mshr miss rate for StoreCondReq accesses
1390system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044348 # mshr miss rate for StoreCondReq accesses
1391system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses
1392system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses
1393system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses
1394system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses
1395system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency
1396system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency
1397system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666 # average WriteReq mshr miss latency
1398system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666 # average WriteReq mshr miss latency
1399system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency
1400system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency
1401system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3489.851606 # average StoreCondReq mshr miss latency
1402system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency
1403system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1404system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1405system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency
1406system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency
1407system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency
1408system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency
1409system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1410system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1411system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1412system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1413system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1414system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1415system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1416system.cpu1.dtb.inst_hits 0 # ITB inst hits
1417system.cpu1.dtb.inst_misses 0 # ITB inst misses
1418system.cpu1.dtb.read_hits 5705173 # DTB read hits
1419system.cpu1.dtb.read_misses 3576 # DTB read misses
1420system.cpu1.dtb.write_hits 3872049 # DTB write hits
1421system.cpu1.dtb.write_misses 645 # DTB write misses
1422system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1423system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1424system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1425system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1426system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB
1427system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1428system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
1429system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1430system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
1431system.cpu1.dtb.read_accesses 5708749 # DTB read accesses
1432system.cpu1.dtb.write_accesses 3872694 # DTB write accesses
1433system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1434system.cpu1.dtb.hits 9577222 # DTB hits
1435system.cpu1.dtb.misses 4221 # DTB misses
1436system.cpu1.dtb.accesses 9581443 # DTB accesses
1437system.cpu1.itb.inst_hits 19377969 # ITB inst hits
1438system.cpu1.itb.inst_misses 2171 # ITB inst misses
1439system.cpu1.itb.read_hits 0 # DTB read hits
1440system.cpu1.itb.read_misses 0 # DTB read misses
1441system.cpu1.itb.write_hits 0 # DTB write hits
1442system.cpu1.itb.write_misses 0 # DTB write misses
1443system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1444system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1445system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1446system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1447system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
1448system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1449system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1450system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1451system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1452system.cpu1.itb.read_accesses 0 # DTB read accesses
1453system.cpu1.itb.write_accesses 0 # DTB write accesses
1454system.cpu1.itb.inst_accesses 19380140 # ITB inst accesses
1455system.cpu1.itb.hits 19377969 # DTB hits
1456system.cpu1.itb.misses 2171 # DTB misses
1457system.cpu1.itb.accesses 19380140 # DTB accesses
1458system.cpu1.numCycles 2388332817 # number of cpu cycles simulated
1459system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1460system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1461system.cpu1.committedInsts 18797412 # Number of instructions committed
1462system.cpu1.committedOps 24898830 # Number of ops (including micro ops) committed
1463system.cpu1.num_int_alu_accesses 22263010 # Number of integer alu accesses
1464system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
1465system.cpu1.num_func_calls 796668 # number of times a function call or return occured
1466system.cpu1.num_conditional_control_insts 2514459 # number of instructions that are conditional controls
1467system.cpu1.num_int_insts 22263010 # number of integer instructions
1468system.cpu1.num_fp_insts 6793 # number of float instructions
1469system.cpu1.num_int_register_reads 130745617 # number of times the integer registers were read
1470system.cpu1.num_int_register_writes 23316317 # number of times the integer registers were written
1471system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
1472system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
1473system.cpu1.num_mem_refs 10012651 # number of memory refs
1474system.cpu1.num_load_insts 5981805 # Number of load instructions
1475system.cpu1.num_store_insts 4030846 # Number of store instructions
1476system.cpu1.num_idle_cycles 1968708722.646828 # Number of idle cycles
1477system.cpu1.num_busy_cycles 419624094.353172 # Number of busy cycles
1478system.cpu1.not_idle_fraction 0.175697 # Percentage of non-idle cycles
1479system.cpu1.idle_fraction 0.824303 # Percentage of idle cycles
1480system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1481system.cpu1.kern.inst.quiesce 39053 # number of quiesce instructions executed
1482system.cpu1.icache.tags.replacements 376539 # number of replacements
1483system.cpu1.icache.tags.tagsinuse 474.945138 # Cycle average of tags in use
1484system.cpu1.icache.tags.total_refs 19000914 # Total number of references to valid blocks.
1485system.cpu1.icache.tags.sampled_refs 377051 # Sample count of references to valid blocks.
1486system.cpu1.icache.tags.avg_refs 50.393485 # Average number of references to valid blocks.
1487system.cpu1.icache.tags.warmup_cycle 327002273500 # Cycle when the warmup percentage was hit.
1488system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.945138 # Average occupied blocks per requestor
1489system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927627 # Average percentage of cache occupancy
1490system.cpu1.icache.tags.occ_percent::total 0.927627 # Average percentage of cache occupancy
1491system.cpu1.icache.ReadReq_hits::cpu1.inst 19000914 # number of ReadReq hits
1492system.cpu1.icache.ReadReq_hits::total 19000914 # number of ReadReq hits
1493system.cpu1.icache.demand_hits::cpu1.inst 19000914 # number of demand (read+write) hits
1494system.cpu1.icache.demand_hits::total 19000914 # number of demand (read+write) hits
1495system.cpu1.icache.overall_hits::cpu1.inst 19000914 # number of overall hits
1496system.cpu1.icache.overall_hits::total 19000914 # number of overall hits
1497system.cpu1.icache.ReadReq_misses::cpu1.inst 377051 # number of ReadReq misses
1498system.cpu1.icache.ReadReq_misses::total 377051 # number of ReadReq misses
1499system.cpu1.icache.demand_misses::cpu1.inst 377051 # number of demand (read+write) misses
1500system.cpu1.icache.demand_misses::total 377051 # number of demand (read+write) misses
1501system.cpu1.icache.overall_misses::cpu1.inst 377051 # number of overall misses
1502system.cpu1.icache.overall_misses::total 377051 # number of overall misses
1503system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154764964 # number of ReadReq miss cycles
1504system.cpu1.icache.ReadReq_miss_latency::total 5154764964 # number of ReadReq miss cycles
1505system.cpu1.icache.demand_miss_latency::cpu1.inst 5154764964 # number of demand (read+write) miss cycles
1506system.cpu1.icache.demand_miss_latency::total 5154764964 # number of demand (read+write) miss cycles
1507system.cpu1.icache.overall_miss_latency::cpu1.inst 5154764964 # number of overall miss cycles
1508system.cpu1.icache.overall_miss_latency::total 5154764964 # number of overall miss cycles
1509system.cpu1.icache.ReadReq_accesses::cpu1.inst 19377965 # number of ReadReq accesses(hits+misses)
1510system.cpu1.icache.ReadReq_accesses::total 19377965 # number of ReadReq accesses(hits+misses)
1511system.cpu1.icache.demand_accesses::cpu1.inst 19377965 # number of demand (read+write) accesses
1512system.cpu1.icache.demand_accesses::total 19377965 # number of demand (read+write) accesses
1513system.cpu1.icache.overall_accesses::cpu1.inst 19377965 # number of overall (read+write) accesses
1514system.cpu1.icache.overall_accesses::total 19377965 # number of overall (read+write) accesses
1515system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019458 # miss rate for ReadReq accesses
1516system.cpu1.icache.ReadReq_miss_rate::total 0.019458 # miss rate for ReadReq accesses
1517system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019458 # miss rate for demand accesses
1518system.cpu1.icache.demand_miss_rate::total 0.019458 # miss rate for demand accesses
1519system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019458 # miss rate for overall accesses
1520system.cpu1.icache.overall_miss_rate::total 0.019458 # miss rate for overall accesses
1521system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187 # average ReadReq miss latency
1522system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187 # average ReadReq miss latency
1523system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency
1524system.cpu1.icache.demand_avg_miss_latency::total 13671.267187 # average overall miss latency
1525system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency
1526system.cpu1.icache.overall_avg_miss_latency::total 13671.267187 # average overall miss latency
1527system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1528system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1529system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1530system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1531system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1532system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1533system.cpu1.icache.fast_writes 0 # number of fast writes performed
1534system.cpu1.icache.cache_copies 0 # number of cache copies performed
1535system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377051 # number of ReadReq MSHR misses
1536system.cpu1.icache.ReadReq_mshr_misses::total 377051 # number of ReadReq MSHR misses
1537system.cpu1.icache.demand_mshr_misses::cpu1.inst 377051 # number of demand (read+write) MSHR misses
1538system.cpu1.icache.demand_mshr_misses::total 377051 # number of demand (read+write) MSHR misses
1539system.cpu1.icache.overall_mshr_misses::cpu1.inst 377051 # number of overall MSHR misses
1540system.cpu1.icache.overall_mshr_misses::total 377051 # number of overall MSHR misses
1541system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398685536 # number of ReadReq MSHR miss cycles
1542system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398685536 # number of ReadReq MSHR miss cycles
1543system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398685536 # number of demand (read+write) MSHR miss cycles
1544system.cpu1.icache.demand_mshr_miss_latency::total 4398685536 # number of demand (read+write) MSHR miss cycles
1545system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398685536 # number of overall MSHR miss cycles
1546system.cpu1.icache.overall_mshr_miss_latency::total 4398685536 # number of overall MSHR miss cycles
1547system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles
1548system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles
1549system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles
1550system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles
1551system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for ReadReq accesses
1552system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019458 # mshr miss rate for ReadReq accesses
1553system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for demand accesses
1554system.cpu1.icache.demand_mshr_miss_rate::total 0.019458 # mshr miss rate for demand accesses
1555system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for overall accesses
1556system.cpu1.icache.overall_mshr_miss_rate::total 0.019458 # mshr miss rate for overall accesses
1557system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average ReadReq mshr miss latency
1558system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11666.022729 # average ReadReq mshr miss latency
1559system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency
1560system.cpu1.icache.demand_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency
1561system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency
1562system.cpu1.icache.overall_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency
1563system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1564system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1565system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1566system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1567system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1568system.cpu1.dcache.tags.replacements 220336 # number of replacements
1569system.cpu1.dcache.tags.tagsinuse 471.526784 # Cycle average of tags in use
1570system.cpu1.dcache.tags.total_refs 8228665 # Total number of references to valid blocks.
1571system.cpu1.dcache.tags.sampled_refs 220703 # Sample count of references to valid blocks.
1572system.cpu1.dcache.tags.avg_refs 37.283884 # Average number of references to valid blocks.
1573system.cpu1.dcache.tags.warmup_cycle 106211109000 # Cycle when the warmup percentage was hit.
1574system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.526784 # Average occupied blocks per requestor
1575system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920951 # Average percentage of cache occupancy
1576system.cpu1.dcache.tags.occ_percent::total 0.920951 # Average percentage of cache occupancy
1577system.cpu1.dcache.ReadReq_hits::cpu1.data 4388185 # number of ReadReq hits
1578system.cpu1.dcache.ReadReq_hits::total 4388185 # number of ReadReq hits
1579system.cpu1.dcache.WriteReq_hits::cpu1.data 3672248 # number of WriteReq hits
1580system.cpu1.dcache.WriteReq_hits::total 3672248 # number of WriteReq hits
1581system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73451 # number of LoadLockedReq hits
1582system.cpu1.dcache.LoadLockedReq_hits::total 73451 # number of LoadLockedReq hits
1583system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73727 # number of StoreCondReq hits
1584system.cpu1.dcache.StoreCondReq_hits::total 73727 # number of StoreCondReq hits
1585system.cpu1.dcache.demand_hits::cpu1.data 8060433 # number of demand (read+write) hits
1586system.cpu1.dcache.demand_hits::total 8060433 # number of demand (read+write) hits
1587system.cpu1.dcache.overall_hits::cpu1.data 8060433 # number of overall hits
1588system.cpu1.dcache.overall_hits::total 8060433 # number of overall hits
1589system.cpu1.dcache.ReadReq_misses::cpu1.data 133748 # number of ReadReq misses
1590system.cpu1.dcache.ReadReq_misses::total 133748 # number of ReadReq misses
1591system.cpu1.dcache.WriteReq_misses::cpu1.data 112730 # number of WriteReq misses
1592system.cpu1.dcache.WriteReq_misses::total 112730 # number of WriteReq misses
1593system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9735 # number of LoadLockedReq misses
1594system.cpu1.dcache.LoadLockedReq_misses::total 9735 # number of LoadLockedReq misses
1595system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9394 # number of StoreCondReq misses
1596system.cpu1.dcache.StoreCondReq_misses::total 9394 # number of StoreCondReq misses
1597system.cpu1.dcache.demand_misses::cpu1.data 246478 # number of demand (read+write) misses
1598system.cpu1.dcache.demand_misses::total 246478 # number of demand (read+write) misses
1599system.cpu1.dcache.overall_misses::cpu1.data 246478 # number of overall misses
1600system.cpu1.dcache.overall_misses::total 246478 # number of overall misses
1601system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1649486235 # number of ReadReq miss cycles
1602system.cpu1.dcache.ReadReq_miss_latency::total 1649486235 # number of ReadReq miss cycles
1603system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3739097468 # number of WriteReq miss cycles
1604system.cpu1.dcache.WriteReq_miss_latency::total 3739097468 # number of WriteReq miss cycles
1605system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77937249 # number of LoadLockedReq miss cycles
1606system.cpu1.dcache.LoadLockedReq_miss_latency::total 77937249 # number of LoadLockedReq miss cycles
1607system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49168975 # number of StoreCondReq miss cycles
1608system.cpu1.dcache.StoreCondReq_miss_latency::total 49168975 # number of StoreCondReq miss cycles
1609system.cpu1.dcache.demand_miss_latency::cpu1.data 5388583703 # number of demand (read+write) miss cycles
1610system.cpu1.dcache.demand_miss_latency::total 5388583703 # number of demand (read+write) miss cycles
1611system.cpu1.dcache.overall_miss_latency::cpu1.data 5388583703 # number of overall miss cycles
1612system.cpu1.dcache.overall_miss_latency::total 5388583703 # number of overall miss cycles
1613system.cpu1.dcache.ReadReq_accesses::cpu1.data 4521933 # number of ReadReq accesses(hits+misses)
1614system.cpu1.dcache.ReadReq_accesses::total 4521933 # number of ReadReq accesses(hits+misses)
1615system.cpu1.dcache.WriteReq_accesses::cpu1.data 3784978 # number of WriteReq accesses(hits+misses)
1616system.cpu1.dcache.WriteReq_accesses::total 3784978 # number of WriteReq accesses(hits+misses)
1617system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83186 # number of LoadLockedReq accesses(hits+misses)
1618system.cpu1.dcache.LoadLockedReq_accesses::total 83186 # number of LoadLockedReq accesses(hits+misses)
1619system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83121 # number of StoreCondReq accesses(hits+misses)
1620system.cpu1.dcache.StoreCondReq_accesses::total 83121 # number of StoreCondReq accesses(hits+misses)
1621system.cpu1.dcache.demand_accesses::cpu1.data 8306911 # number of demand (read+write) accesses
1622system.cpu1.dcache.demand_accesses::total 8306911 # number of demand (read+write) accesses
1623system.cpu1.dcache.overall_accesses::cpu1.data 8306911 # number of overall (read+write) accesses
1624system.cpu1.dcache.overall_accesses::total 8306911 # number of overall (read+write) accesses
1625system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029578 # miss rate for ReadReq accesses
1626system.cpu1.dcache.ReadReq_miss_rate::total 0.029578 # miss rate for ReadReq accesses
1627system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029784 # miss rate for WriteReq accesses
1628system.cpu1.dcache.WriteReq_miss_rate::total 0.029784 # miss rate for WriteReq accesses
1629system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117027 # miss rate for LoadLockedReq accesses
1630system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117027 # miss rate for LoadLockedReq accesses
1631system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113016 # miss rate for StoreCondReq accesses
1632system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113016 # miss rate for StoreCondReq accesses
1633system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029671 # miss rate for demand accesses
1634system.cpu1.dcache.demand_miss_rate::total 0.029671 # miss rate for demand accesses
1635system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029671 # miss rate for overall accesses
1636system.cpu1.dcache.overall_miss_rate::total 0.029671 # miss rate for overall accesses
1637system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12332.791780 # average ReadReq miss latency
1638system.cpu1.dcache.ReadReq_avg_miss_latency::total 12332.791780 # average ReadReq miss latency
1639system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33168.610556 # average WriteReq miss latency
1640system.cpu1.dcache.WriteReq_avg_miss_latency::total 33168.610556 # average WriteReq miss latency
1641system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8005.880740 # average LoadLockedReq miss latency
1642system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8005.880740 # average LoadLockedReq miss latency
1643system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5234.082925 # average StoreCondReq miss latency
1644system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5234.082925 # average StoreCondReq miss latency
1645system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency
1646system.cpu1.dcache.demand_avg_miss_latency::total 21862.331336 # average overall miss latency
1647system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency
1648system.cpu1.dcache.overall_avg_miss_latency::total 21862.331336 # average overall miss latency
1649system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1650system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1651system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1652system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1653system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1654system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1655system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1656system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1657system.cpu1.dcache.writebacks::writebacks 199438 # number of writebacks
1658system.cpu1.dcache.writebacks::total 199438 # number of writebacks
1659system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133748 # number of ReadReq MSHR misses
1660system.cpu1.dcache.ReadReq_mshr_misses::total 133748 # number of ReadReq MSHR misses
1661system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112730 # number of WriteReq MSHR misses
1662system.cpu1.dcache.WriteReq_mshr_misses::total 112730 # number of WriteReq MSHR misses
1663system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9735 # number of LoadLockedReq MSHR misses
1664system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9735 # number of LoadLockedReq MSHR misses
1665system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9393 # number of StoreCondReq MSHR misses
1666system.cpu1.dcache.StoreCondReq_mshr_misses::total 9393 # number of StoreCondReq MSHR misses
1667system.cpu1.dcache.demand_mshr_misses::cpu1.data 246478 # number of demand (read+write) MSHR misses
1668system.cpu1.dcache.demand_mshr_misses::total 246478 # number of demand (read+write) MSHR misses
1669system.cpu1.dcache.overall_mshr_misses::cpu1.data 246478 # number of overall MSHR misses
1670system.cpu1.dcache.overall_mshr_misses::total 246478 # number of overall MSHR misses
1671system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1381071765 # number of ReadReq MSHR miss cycles
1672system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1381071765 # number of ReadReq MSHR miss cycles
1673system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3492633532 # number of WriteReq MSHR miss cycles
1674system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3492633532 # number of WriteReq MSHR miss cycles
1675system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58449751 # number of LoadLockedReq MSHR miss cycles
1676system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58449751 # number of LoadLockedReq MSHR miss cycles
1677system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30384025 # number of StoreCondReq MSHR miss cycles
1678system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30384025 # number of StoreCondReq MSHR miss cycles
1679system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
1680system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
1681system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4873705297 # number of demand (read+write) MSHR miss cycles
1682system.cpu1.dcache.demand_mshr_miss_latency::total 4873705297 # number of demand (read+write) MSHR miss cycles
1683system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4873705297 # number of overall MSHR miss cycles
1684system.cpu1.dcache.overall_mshr_miss_latency::total 4873705297 # number of overall MSHR miss cycles
1685system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000 # number of ReadReq MSHR uncacheable cycles
1686system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000 # number of ReadReq MSHR uncacheable cycles
1687system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531034000 # number of WriteReq MSHR uncacheable cycles
1688system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531034000 # number of WriteReq MSHR uncacheable cycles
1689system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000 # number of overall MSHR uncacheable cycles
1690system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000 # number of overall MSHR uncacheable cycles
1691system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029578 # mshr miss rate for ReadReq accesses
1692system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029578 # mshr miss rate for ReadReq accesses
1693system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029784 # mshr miss rate for WriteReq accesses
1694system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029784 # mshr miss rate for WriteReq accesses
1695system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117027 # mshr miss rate for LoadLockedReq accesses
1696system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117027 # mshr miss rate for LoadLockedReq accesses
1697system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113004 # mshr miss rate for StoreCondReq accesses
1698system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113004 # mshr miss rate for StoreCondReq accesses
1699system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for demand accesses
1700system.cpu1.dcache.demand_mshr_miss_rate::total 0.029671 # mshr miss rate for demand accesses
1701system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for overall accesses
1702system.cpu1.dcache.overall_mshr_miss_rate::total 0.029671 # mshr miss rate for overall accesses
1703system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612 # average ReadReq mshr miss latency
1704system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612 # average ReadReq mshr miss latency
1705system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825 # average WriteReq mshr miss latency
1706system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825 # average WriteReq mshr miss latency
1707system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6004.083308 # average LoadLockedReq mshr miss latency
1708system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6004.083308 # average LoadLockedReq mshr miss latency
1709system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3234.751943 # average StoreCondReq mshr miss latency
1710system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3234.751943 # average StoreCondReq mshr miss latency
1711system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1712system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1713system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency
1714system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency
1715system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency
1716system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency
1717system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1718system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1719system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1720system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1721system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1722system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1723system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1724system.iocache.tags.replacements 0 # number of replacements

--- 5 unchanged lines hidden (view full) ---

1730system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1731system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1732system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1733system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1734system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1735system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1736system.iocache.fast_writes 0 # number of fast writes performed
1737system.iocache.cache_copies 0 # number of cache copies performed
1738system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles
1739system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles
1740system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles
1741system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles
1742system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1743system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1744system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1745system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1746system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1747
1748---------- End Simulation Statistics ----------