1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.183003 # Number of seconds simulated
4sim_ticks 1183003114000 # Number of ticks simulated
5final_tick 1183003114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 673901 # Simulator instruction rate (inst/s)
8host_op_rate 858757 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 12970235901 # Simulator tick rate (ticks/s)
10host_mem_usage 408748 # Number of bytes of host memory used
11host_seconds 91.21 # Real time elapsed on the host
12sim_insts 61465824 # Number of instructions simulated
13sim_ops 78326377 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.inst 379748 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.data 4530164 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.inst 336668 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.data 4964784 # Number of bytes read from this memory
22system.physmem.bytes_read::total 62116388 # Number of bytes read from this memory
23system.physmem.bytes_inst_read::cpu0.inst 379748 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::cpu1.inst 336668 # Number of instructions bytes read from this memory
25system.physmem.bytes_inst_read::total 716416 # Number of instructions bytes read from this memory
26system.physmem.bytes_written::writebacks 4089728 # Number of bytes written to this memory
27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
29system.physmem.bytes_written::total 7117072 # Number of bytes written to this memory
30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu0.inst 12152 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.data 70856 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu1.inst 5342 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.data 77601 # Number of read requests responded to by this memory
38system.physmem.num_reads::total 6654023 # Number of read requests responded to by this memory
39system.physmem.num_writes::writebacks 63902 # Number of write requests responded to by this memory
40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
42system.physmem.num_writes::total 820738 # Number of write requests responded to by this memory
43system.physmem.bw_read::realview.clcd 43875212 # Total read bandwidth from this memory (bytes/s)
44system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
45system.physmem.bw_read::cpu0.itb.walker 162 # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu0.inst 321003 # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu0.data 3829376 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu1.inst 284588 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu1.data 4196763 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::total 52507375 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_inst_read::cpu0.inst 321003 # Instruction read bandwidth from this memory (bytes/s)
53system.physmem.bw_inst_read::cpu1.inst 284588 # Instruction read bandwidth from this memory (bytes/s)
54system.physmem.bw_inst_read::total 605591 # Instruction read bandwidth from this memory (bytes/s)
55system.physmem.bw_write::writebacks 3457073 # Write bandwidth from this memory (bytes/s)
56system.physmem.bw_write::cpu0.data 14370 # Write bandwidth from this memory (bytes/s)
57system.physmem.bw_write::cpu1.data 2544663 # Write bandwidth from this memory (bytes/s)
58system.physmem.bw_write::total 6016106 # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_total::writebacks 3457073 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::realview.clcd 43875212 # Total bandwidth to/from this memory (bytes/s)
61system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::cpu0.itb.walker 162 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::cpu0.inst 321003 # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu0.data 3843746 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu1.inst 284588 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu1.data 6741426 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::total 58523481 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.readReqs 6654023 # Total number of read requests seen
70system.physmem.writeReqs 820738 # Total number of write requests seen
71system.physmem.cpureqs 272097 # Reqs generatd by CPU via cache - shady
72system.physmem.bytesRead 425857472 # Total number of bytes read from memory
73system.physmem.bytesWritten 52527232 # Total number of bytes written to memory
74system.physmem.bytesConsumedRd 62116388 # bytesRead derated as per pkt->getSize()
75system.physmem.bytesConsumedWr 7117072 # bytesWritten derated as per pkt->getSize()
76system.physmem.servicedByWrQ 112 # Number of read reqs serviced by write Q
77system.physmem.neitherReadNorWrite 11760 # Reqs where no action is needed
78system.physmem.perBankRdReqs::0 422267 # Track reads on a per bank basis
79system.physmem.perBankRdReqs::1 415727 # Track reads on a per bank basis
80system.physmem.perBankRdReqs::2 415213 # Track reads on a per bank basis
81system.physmem.perBankRdReqs::3 415818 # Track reads on a per bank basis
82system.physmem.perBankRdReqs::4 415767 # Track reads on a per bank basis
83system.physmem.perBankRdReqs::5 415004 # Track reads on a per bank basis
84system.physmem.perBankRdReqs::6 415107 # Track reads on a per bank basis
85system.physmem.perBankRdReqs::7 415928 # Track reads on a per bank basis
86system.physmem.perBankRdReqs::8 415784 # Track reads on a per bank basis
87system.physmem.perBankRdReqs::9 415110 # Track reads on a per bank basis
88system.physmem.perBankRdReqs::10 415164 # Track reads on a per bank basis
89system.physmem.perBankRdReqs::11 415654 # Track reads on a per bank basis
90system.physmem.perBankRdReqs::12 415632 # Track reads on a per bank basis
91system.physmem.perBankRdReqs::13 415090 # Track reads on a per bank basis
92system.physmem.perBankRdReqs::14 415000 # Track reads on a per bank basis
93system.physmem.perBankRdReqs::15 415646 # Track reads on a per bank basis
94system.physmem.perBankWrReqs::0 51297 # Track writes on a per bank basis
95system.physmem.perBankWrReqs::1 51187 # Track writes on a per bank basis
96system.physmem.perBankWrReqs::2 50850 # Track writes on a per bank basis
97system.physmem.perBankWrReqs::3 51382 # Track writes on a per bank basis
98system.physmem.perBankWrReqs::4 51290 # Track writes on a per bank basis
99system.physmem.perBankWrReqs::5 50625 # Track writes on a per bank basis
100system.physmem.perBankWrReqs::6 50696 # Track writes on a per bank basis
101system.physmem.perBankWrReqs::7 51406 # Track writes on a per bank basis
102system.physmem.perBankWrReqs::8 51898 # Track writes on a per bank basis
103system.physmem.perBankWrReqs::9 51190 # Track writes on a per bank basis
104system.physmem.perBankWrReqs::10 51285 # Track writes on a per bank basis
105system.physmem.perBankWrReqs::11 51758 # Track writes on a per bank basis
106system.physmem.perBankWrReqs::12 51708 # Track writes on a per bank basis
107system.physmem.perBankWrReqs::13 51260 # Track writes on a per bank basis
108system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis
109system.physmem.perBankWrReqs::15 51768 # Track writes on a per bank basis
110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
111system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
112system.physmem.totGap 1182998675500 # Total gap between requests
113system.physmem.readPktSize::0 0 # Categorize read packet sizes
114system.physmem.readPktSize::1 0 # Categorize read packet sizes
115system.physmem.readPktSize::2 6825 # Categorize read packet sizes
116system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
117system.physmem.readPktSize::4 0 # Categorize read packet sizes
118system.physmem.readPktSize::5 0 # Categorize read packet sizes
119system.physmem.readPktSize::6 159134 # Categorize read packet sizes
120system.physmem.readPktSize::7 0 # Categorize read packet sizes
121system.physmem.readPktSize::8 0 # Categorize read packet sizes
122system.physmem.writePktSize::0 0 # categorize write packet sizes
123system.physmem.writePktSize::1 0 # categorize write packet sizes
124system.physmem.writePktSize::2 756836 # categorize write packet sizes
125system.physmem.writePktSize::3 0 # categorize write packet sizes
126system.physmem.writePktSize::4 0 # categorize write packet sizes
127system.physmem.writePktSize::5 0 # categorize write packet sizes
128system.physmem.writePktSize::6 63902 # categorize write packet sizes
129system.physmem.writePktSize::7 0 # categorize write packet sizes
130system.physmem.writePktSize::8 0 # categorize write packet sizes
131system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
132system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
133system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
134system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
135system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
136system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
137system.physmem.neitherpktsize::6 11760 # categorize neither packet sizes
138system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
139system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
140system.physmem.rdQLenPdf::0 570635 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::1 408572 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::2 415826 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::3 1537846 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::4 1165216 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::5 1169840 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::6 1140716 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::7 29537 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::8 27577 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::9 48457 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::10 69066 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::11 48178 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::12 5864 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::13 5691 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::14 5515 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::15 5307 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::16 68 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
172system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
173system.physmem.wrQLenPdf::0 35513 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::1 35658 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::2 35664 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::3 35672 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::4 35674 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::5 35678 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::6 35678 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::7 35681 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::8 35681 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::9 35684 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::10 35684 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::11 35684 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::12 35684 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::13 35684 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::14 35684 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::15 35684 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::16 35684 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::17 35684 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::18 35684 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::19 35684 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::20 35684 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::21 35684 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::22 35684 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::23 172 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::24 27 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::25 21 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::26 13 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::27 11 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
206system.physmem.totQLat 146986341539 # Total cycles spent in queuing delays
207system.physmem.totMemAccLat 189297882789 # Sum of mem lat for all requests
208system.physmem.totBusLat 33269555000 # Total cycles spent in databus access
209system.physmem.totBankLat 9041986250 # Total cycles spent in bank access
210system.physmem.avgQLat 22090.22 # Average queueing delay per request
211system.physmem.avgBankLat 1358.90 # Average bank access latency per request
212system.physmem.avgBusLat 5000.00 # Average bus latency per request
213system.physmem.avgMemAccLat 28449.12 # Average memory access latency
214system.physmem.avgRdBW 359.98 # Average achieved read bandwidth in MB/s
215system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s
216system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s
217system.physmem.avgConsumedWrBW 6.02 # Average consumed write bandwidth in MB/s
218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
219system.physmem.busUtil 3.16 # Data bus utilization in percentage
220system.physmem.avgRdQLen 0.16 # Average read queue length over time
221system.physmem.avgWrQLen 12.54 # Average write queue length over time
222system.physmem.readRowHits 6611960 # Number of row buffer hits during reads
223system.physmem.writeRowHits 800133 # Number of row buffer hits during writes
224system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads
225system.physmem.writeRowHitRate 97.49 # Row buffer hit rate for writes
226system.physmem.avgGap 158265.75 # Average gap between requests
227system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
228system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
229system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
230system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
231system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
232system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
233system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
234system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
235system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
236system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
237system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
238system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
239system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
240system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
241system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
242system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
243system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
244system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
245system.l2c.replacements 69015 # number of replacements
246system.l2c.tagsinuse 53041.665406 # Cycle average of tags in use
247system.l2c.total_refs 1678594 # Total number of references to valid blocks.
248system.l2c.sampled_refs 134211 # Sample count of references to valid blocks.
249system.l2c.avg_refs 12.507127 # Average number of references to valid blocks.
250system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
251system.l2c.occ_blocks::writebacks 40191.767552 # Average occupied blocks per requestor
252system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor
253system.l2c.occ_blocks::cpu0.itb.walker 0.003100 # Average occupied blocks per requestor
254system.l2c.occ_blocks::cpu0.inst 3723.993423 # Average occupied blocks per requestor
255system.l2c.occ_blocks::cpu0.data 4235.450091 # Average occupied blocks per requestor
256system.l2c.occ_blocks::cpu1.dtb.walker 2.742043 # Average occupied blocks per requestor
257system.l2c.occ_blocks::cpu1.inst 2826.235882 # Average occupied blocks per requestor
258system.l2c.occ_blocks::cpu1.data 2061.472909 # Average occupied blocks per requestor
259system.l2c.occ_percent::writebacks 0.613278 # Average percentage of cache occupancy
260system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
261system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
262system.l2c.occ_percent::cpu0.inst 0.056824 # Average percentage of cache occupancy
263system.l2c.occ_percent::cpu0.data 0.064628 # Average percentage of cache occupancy
264system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
265system.l2c.occ_percent::cpu1.inst 0.043125 # Average percentage of cache occupancy
266system.l2c.occ_percent::cpu1.data 0.031456 # Average percentage of cache occupancy
267system.l2c.occ_percent::total 0.809352 # Average percentage of cache occupancy
268system.l2c.ReadReq_hits::cpu0.dtb.walker 3013 # number of ReadReq hits
269system.l2c.ReadReq_hits::cpu0.itb.walker 1662 # number of ReadReq hits
270system.l2c.ReadReq_hits::cpu0.inst 349398 # number of ReadReq hits
271system.l2c.ReadReq_hits::cpu0.data 169915 # number of ReadReq hits
272system.l2c.ReadReq_hits::cpu1.dtb.walker 6389 # number of ReadReq hits
273system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits
274system.l2c.ReadReq_hits::cpu1.inst 534803 # number of ReadReq hits
275system.l2c.ReadReq_hits::cpu1.data 180813 # number of ReadReq hits
276system.l2c.ReadReq_hits::total 1247936 # number of ReadReq hits
277system.l2c.Writeback_hits::writebacks 573205 # number of Writeback hits
278system.l2c.Writeback_hits::total 573205 # number of Writeback hits
279system.l2c.UpgradeReq_hits::cpu0.data 1121 # number of UpgradeReq hits
280system.l2c.UpgradeReq_hits::cpu1.data 611 # number of UpgradeReq hits
281system.l2c.UpgradeReq_hits::total 1732 # number of UpgradeReq hits
282system.l2c.SCUpgradeReq_hits::cpu0.data 229 # number of SCUpgradeReq hits
283system.l2c.SCUpgradeReq_hits::cpu1.data 78 # number of SCUpgradeReq hits
284system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits
285system.l2c.ReadExReq_hits::cpu0.data 47508 # number of ReadExReq hits
286system.l2c.ReadExReq_hits::cpu1.data 62580 # number of ReadExReq hits
287system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits
288system.l2c.demand_hits::cpu0.dtb.walker 3013 # number of demand (read+write) hits
289system.l2c.demand_hits::cpu0.itb.walker 1662 # number of demand (read+write) hits
290system.l2c.demand_hits::cpu0.inst 349398 # number of demand (read+write) hits
291system.l2c.demand_hits::cpu0.data 217423 # number of demand (read+write) hits
292system.l2c.demand_hits::cpu1.dtb.walker 6389 # number of demand (read+write) hits
293system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits
294system.l2c.demand_hits::cpu1.inst 534803 # number of demand (read+write) hits
295system.l2c.demand_hits::cpu1.data 243393 # number of demand (read+write) hits
296system.l2c.demand_hits::total 1358024 # number of demand (read+write) hits
297system.l2c.overall_hits::cpu0.dtb.walker 3013 # number of overall hits
298system.l2c.overall_hits::cpu0.itb.walker 1662 # number of overall hits
299system.l2c.overall_hits::cpu0.inst 349398 # number of overall hits
300system.l2c.overall_hits::cpu0.data 217423 # number of overall hits
301system.l2c.overall_hits::cpu1.dtb.walker 6389 # number of overall hits
302system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits
303system.l2c.overall_hits::cpu1.inst 534803 # number of overall hits
304system.l2c.overall_hits::cpu1.data 243393 # number of overall hits
305system.l2c.overall_hits::total 1358024 # number of overall hits
306system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
307system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses
308system.l2c.ReadReq_misses::cpu0.inst 5520 # number of ReadReq misses
309system.l2c.ReadReq_misses::cpu0.data 7838 # number of ReadReq misses
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554system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197508 # number of overall MSHR miss cycles
555system.l2c.overall_mshr_miss_latency::cpu1.inst 225003397 # number of overall MSHR miss cycles
556system.l2c.overall_mshr_miss_latency::cpu1.data 2806521612 # number of overall MSHR miss cycles
557system.l2c.overall_mshr_miss_latency::total 5607353294 # number of overall MSHR miss cycles
558system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 209640082 # number of ReadReq MSHR uncacheable cycles
559system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 11218408858 # number of ReadReq MSHR uncacheable cycles
560system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3082174 # number of ReadReq MSHR uncacheable cycles
561system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 155565109792 # number of ReadReq MSHR uncacheable cycles
562system.l2c.ReadReq_mshr_uncacheable_latency::total 166996240906 # number of ReadReq MSHR uncacheable cycles
563system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 994820748 # number of WriteReq MSHR uncacheable cycles
564system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214915040 # number of WriteReq MSHR uncacheable cycles
565system.l2c.WriteReq_mshr_uncacheable_latency::total 9209735788 # number of WriteReq MSHR uncacheable cycles
566system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209640082 # number of overall MSHR uncacheable cycles
567system.l2c.overall_mshr_uncacheable_latency::cpu0.data 12213229606 # number of overall MSHR uncacheable cycles
568system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3082174 # number of overall MSHR uncacheable cycles
569system.l2c.overall_mshr_uncacheable_latency::cpu1.data 163780024832 # number of overall MSHR uncacheable cycles
570system.l2c.overall_mshr_uncacheable_latency::total 176205976694 # number of overall MSHR uncacheable cycles
571system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for ReadReq accesses
572system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for ReadReq accesses
573system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for ReadReq accesses
574system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044095 # mshr miss rate for ReadReq accesses
575system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for ReadReq accesses
576system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for ReadReq accesses
577system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.019755 # mshr miss rate for ReadReq accesses
578system.l2c.ReadReq_mshr_miss_rate::total 0.017528 # mshr miss rate for ReadReq accesses
579system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.761692 # mshr miss rate for UpgradeReq accesses
580system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.885452 # mshr miss rate for UpgradeReq accesses
581system.l2c.UpgradeReq_mshr_miss_rate::total 0.827456 # mshr miss rate for UpgradeReq accesses
582system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.713750 # mshr miss rate for SCUpgradeReq accesses
583system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.855288 # mshr miss rate for SCUpgradeReq accesses
584system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770724 # mshr miss rate for SCUpgradeReq accesses
585system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573338 # mshr miss rate for ReadExReq accesses
586system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.546627 # mshr miss rate for ReadExReq accesses
587system.l2c.ReadExReq_mshr_miss_rate::total 0.558553 # mshr miss rate for ReadExReq accesses
588system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for demand accesses
589system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for demand accesses
590system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for demand accesses
591system.l2c.demand_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for demand accesses
592system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for demand accesses
593system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for demand accesses
594system.l2c.demand_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for demand accesses
595system.l2c.demand_mshr_miss_rate::total 0.106316 # mshr miss rate for demand accesses
596system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000332 # mshr miss rate for overall accesses
597system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001802 # mshr miss rate for overall accesses
598system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015550 # mshr miss rate for overall accesses
599system.l2c.overall_mshr_miss_rate::cpu0.data 0.247934 # mshr miss rate for overall accesses
600system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000626 # mshr miss rate for overall accesses
601system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009730 # mshr miss rate for overall accesses
602system.l2c.overall_mshr_miss_rate::cpu1.data 0.245267 # mshr miss rate for overall accesses
603system.l2c.overall_mshr_miss_rate::total 0.106316 # mshr miss rate for overall accesses
604system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average ReadReq mshr miss latency
605system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average ReadReq mshr miss latency
606system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average ReadReq mshr miss latency
607system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40610.018244 # average ReadReq mshr miss latency
608system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average ReadReq mshr miss latency
609system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average ReadReq mshr miss latency
610system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48571.194566 # average ReadReq mshr miss latency
611system.l2c.ReadReq_avg_mshr_miss_latency::total 42133.820428 # average ReadReq mshr miss latency
612system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.341055 # average UpgradeReq mshr miss latency
613system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10030.735761 # average UpgradeReq mshr miss latency
614system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10027.114496 # average UpgradeReq mshr miss latency
615system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.758319 # average SCUpgradeReq mshr miss latency
616system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10032.444685 # average SCUpgradeReq mshr miss latency
617system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.384690 # average SCUpgradeReq mshr miss latency
618system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31951.092372 # average ReadExReq mshr miss latency
619system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34850.344312 # average ReadExReq mshr miss latency
620system.l2c.ReadExReq_avg_mshr_miss_latency::total 33521.565603 # average ReadExReq mshr miss latency
621system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency
622system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency
623system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency
624system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency
625system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency
626system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency
627system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency
628system.l2c.demand_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency
629system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56252 # average overall mshr miss latency
630system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 37918.666667 # average overall mshr miss latency
631system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39391.503714 # average overall mshr miss latency
632system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32897.947208 # average overall mshr miss latency
633system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49377 # average overall mshr miss latency
634system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42817.011798 # average overall mshr miss latency
635system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35482.472085 # average overall mshr miss latency
636system.l2c.overall_avg_mshr_miss_latency::total 34708.418715 # average overall mshr miss latency
637system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
638system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
639system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
640system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
641system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
642system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
643system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
644system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency

--- 6 unchanged lines hidden (view full) ---

651system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
652system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
653system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
654system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
655system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
656system.cf0.dma_write_txs 0 # Number of DMA write transactions.
657system.cpu0.dtb.inst_hits 0 # ITB inst hits
658system.cpu0.dtb.inst_misses 0 # ITB inst misses
659system.cpu0.dtb.read_hits 5883553 # DTB read hits
660system.cpu0.dtb.read_misses 2148 # DTB read misses
661system.cpu0.dtb.write_hits 4842455 # DTB write hits
662system.cpu0.dtb.write_misses 405 # DTB write misses
663system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
664system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
665system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
666system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
667system.cpu0.dtb.flush_entries 1536 # Number of entries that have been flushed from TLB
668system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
669system.cpu0.dtb.prefetch_faults 91 # Number of TLB faults due to prefetch
670system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
671system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions
672system.cpu0.dtb.read_accesses 5885701 # DTB read accesses
673system.cpu0.dtb.write_accesses 4842860 # DTB write accesses
674system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
675system.cpu0.dtb.hits 10726008 # DTB hits
676system.cpu0.dtb.misses 2553 # DTB misses
677system.cpu0.dtb.accesses 10728561 # DTB accesses
678system.cpu0.itb.inst_hits 24779849 # ITB inst hits
679system.cpu0.itb.inst_misses 1350 # ITB inst misses
680system.cpu0.itb.read_hits 0 # DTB read hits
681system.cpu0.itb.read_misses 0 # DTB read misses
682system.cpu0.itb.write_hits 0 # DTB write hits
683system.cpu0.itb.write_misses 0 # DTB write misses
684system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
685system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
686system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
687system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
688system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB
689system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
690system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
691system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
692system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
693system.cpu0.itb.read_accesses 0 # DTB read accesses
694system.cpu0.itb.write_accesses 0 # DTB write accesses
695system.cpu0.itb.inst_accesses 24781199 # ITB inst accesses
696system.cpu0.itb.hits 24779849 # DTB hits
697system.cpu0.itb.misses 1350 # DTB misses
698system.cpu0.itb.accesses 24781199 # DTB accesses
699system.cpu0.numCycles 2364565551 # number of cpu cycles simulated
700system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
701system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
702system.cpu0.committedInsts 24381823 # Number of instructions committed
703system.cpu0.committedOps 31476006 # Number of ops (including micro ops) committed
704system.cpu0.num_int_alu_accesses 28075203 # Number of integer alu accesses
705system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses
706system.cpu0.num_func_calls 1070639 # number of times a function call or return occured
707system.cpu0.num_conditional_control_insts 3752398 # number of instructions that are conditional controls
708system.cpu0.num_int_insts 28075203 # number of integer instructions
709system.cpu0.num_fp_insts 4364 # number of float instructions
710system.cpu0.num_int_register_reads 160702802 # number of times the integer registers were read
711system.cpu0.num_int_register_writes 30522196 # number of times the integer registers were written
712system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read
713system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written
714system.cpu0.num_mem_refs 11318426 # number of memory refs
715system.cpu0.num_load_insts 6163151 # Number of load instructions
716system.cpu0.num_store_insts 5155275 # Number of store instructions
717system.cpu0.num_idle_cycles 2243464250.276980 # Number of idle cycles
718system.cpu0.num_busy_cycles 121101300.723020 # Number of busy cycles
719system.cpu0.not_idle_fraction 0.051215 # Percentage of non-idle cycles
720system.cpu0.idle_fraction 0.948785 # Percentage of idle cycles
721system.cpu0.kern.inst.arm 0 # number of arm instructions executed
722system.cpu0.kern.inst.quiesce 38919 # number of quiesce instructions executed
723system.cpu0.icache.replacements 354669 # number of replacements
724system.cpu0.icache.tagsinuse 509.601981 # Cycle average of tags in use
725system.cpu0.icache.total_refs 24424650 # Total number of references to valid blocks.
726system.cpu0.icache.sampled_refs 355181 # Sample count of references to valid blocks.
727system.cpu0.icache.avg_refs 68.766770 # Average number of references to valid blocks.
728system.cpu0.icache.warmup_cycle 74995953000 # Cycle when the warmup percentage was hit.
729system.cpu0.icache.occ_blocks::cpu0.inst 509.601981 # Average occupied blocks per requestor
730system.cpu0.icache.occ_percent::cpu0.inst 0.995316 # Average percentage of cache occupancy
731system.cpu0.icache.occ_percent::total 0.995316 # Average percentage of cache occupancy
732system.cpu0.icache.ReadReq_hits::cpu0.inst 24424650 # number of ReadReq hits
733system.cpu0.icache.ReadReq_hits::total 24424650 # number of ReadReq hits
734system.cpu0.icache.demand_hits::cpu0.inst 24424650 # number of demand (read+write) hits
735system.cpu0.icache.demand_hits::total 24424650 # number of demand (read+write) hits
736system.cpu0.icache.overall_hits::cpu0.inst 24424650 # number of overall hits
737system.cpu0.icache.overall_hits::total 24424650 # number of overall hits
738system.cpu0.icache.ReadReq_misses::cpu0.inst 355182 # number of ReadReq misses
739system.cpu0.icache.ReadReq_misses::total 355182 # number of ReadReq misses
740system.cpu0.icache.demand_misses::cpu0.inst 355182 # number of demand (read+write) misses
741system.cpu0.icache.demand_misses::total 355182 # number of demand (read+write) misses
742system.cpu0.icache.overall_misses::cpu0.inst 355182 # number of overall misses
743system.cpu0.icache.overall_misses::total 355182 # number of overall misses
744system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4877233500 # number of ReadReq miss cycles
745system.cpu0.icache.ReadReq_miss_latency::total 4877233500 # number of ReadReq miss cycles
746system.cpu0.icache.demand_miss_latency::cpu0.inst 4877233500 # number of demand (read+write) miss cycles
747system.cpu0.icache.demand_miss_latency::total 4877233500 # number of demand (read+write) miss cycles
748system.cpu0.icache.overall_miss_latency::cpu0.inst 4877233500 # number of overall miss cycles
749system.cpu0.icache.overall_miss_latency::total 4877233500 # number of overall miss cycles
750system.cpu0.icache.ReadReq_accesses::cpu0.inst 24779832 # number of ReadReq accesses(hits+misses)
751system.cpu0.icache.ReadReq_accesses::total 24779832 # number of ReadReq accesses(hits+misses)
752system.cpu0.icache.demand_accesses::cpu0.inst 24779832 # number of demand (read+write) accesses
753system.cpu0.icache.demand_accesses::total 24779832 # number of demand (read+write) accesses
754system.cpu0.icache.overall_accesses::cpu0.inst 24779832 # number of overall (read+write) accesses
755system.cpu0.icache.overall_accesses::total 24779832 # number of overall (read+write) accesses
756system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014334 # miss rate for ReadReq accesses
757system.cpu0.icache.ReadReq_miss_rate::total 0.014334 # miss rate for ReadReq accesses
758system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014334 # miss rate for demand accesses
759system.cpu0.icache.demand_miss_rate::total 0.014334 # miss rate for demand accesses
760system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014334 # miss rate for overall accesses
761system.cpu0.icache.overall_miss_rate::total 0.014334 # miss rate for overall accesses
762system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13731.646029 # average ReadReq miss latency
763system.cpu0.icache.ReadReq_avg_miss_latency::total 13731.646029 # average ReadReq miss latency
764system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency
765system.cpu0.icache.demand_avg_miss_latency::total 13731.646029 # average overall miss latency
766system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13731.646029 # average overall miss latency
767system.cpu0.icache.overall_avg_miss_latency::total 13731.646029 # average overall miss latency
768system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
769system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
770system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
771system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
772system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
773system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
774system.cpu0.icache.fast_writes 0 # number of fast writes performed
775system.cpu0.icache.cache_copies 0 # number of cache copies performed
776system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355182 # number of ReadReq MSHR misses
777system.cpu0.icache.ReadReq_mshr_misses::total 355182 # number of ReadReq MSHR misses
778system.cpu0.icache.demand_mshr_misses::cpu0.inst 355182 # number of demand (read+write) MSHR misses
779system.cpu0.icache.demand_mshr_misses::total 355182 # number of demand (read+write) MSHR misses
780system.cpu0.icache.overall_mshr_misses::cpu0.inst 355182 # number of overall MSHR misses
781system.cpu0.icache.overall_mshr_misses::total 355182 # number of overall MSHR misses
782system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4166869500 # number of ReadReq MSHR miss cycles
783system.cpu0.icache.ReadReq_mshr_miss_latency::total 4166869500 # number of ReadReq MSHR miss cycles
784system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4166869500 # number of demand (read+write) MSHR miss cycles
785system.cpu0.icache.demand_mshr_miss_latency::total 4166869500 # number of demand (read+write) MSHR miss cycles
786system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4166869500 # number of overall MSHR miss cycles
787system.cpu0.icache.overall_mshr_miss_latency::total 4166869500 # number of overall MSHR miss cycles
788system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles
789system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles
790system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles
791system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles
792system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for ReadReq accesses
793system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014334 # mshr miss rate for ReadReq accesses
794system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for demand accesses
795system.cpu0.icache.demand_mshr_miss_rate::total 0.014334 # mshr miss rate for demand accesses
796system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014334 # mshr miss rate for overall accesses
797system.cpu0.icache.overall_mshr_miss_rate::total 0.014334 # mshr miss rate for overall accesses
798system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average ReadReq mshr miss latency
799system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11731.646029 # average ReadReq mshr miss latency
800system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency
801system.cpu0.icache.demand_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency
802system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11731.646029 # average overall mshr miss latency
803system.cpu0.icache.overall_avg_mshr_miss_latency::total 11731.646029 # average overall mshr miss latency
804system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
805system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
806system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
807system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
808system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
809system.cpu0.dcache.replacements 279602 # number of replacements
810system.cpu0.dcache.tagsinuse 452.516720 # Cycle average of tags in use
811system.cpu0.dcache.total_refs 10326636 # Total number of references to valid blocks.
812system.cpu0.dcache.sampled_refs 279931 # Sample count of references to valid blocks.
813system.cpu0.dcache.avg_refs 36.889934 # Average number of references to valid blocks.
814system.cpu0.dcache.warmup_cycle 473552000 # Cycle when the warmup percentage was hit.
815system.cpu0.dcache.occ_blocks::cpu0.data 452.516720 # Average occupied blocks per requestor
816system.cpu0.dcache.occ_percent::cpu0.data 0.883822 # Average percentage of cache occupancy
817system.cpu0.dcache.occ_percent::total 0.883822 # Average percentage of cache occupancy
818system.cpu0.dcache.ReadReq_hits::cpu0.data 5477555 # number of ReadReq hits
819system.cpu0.dcache.ReadReq_hits::total 5477555 # number of ReadReq hits
820system.cpu0.dcache.WriteReq_hits::cpu0.data 4571792 # number of WriteReq hits
821system.cpu0.dcache.WriteReq_hits::total 4571792 # number of WriteReq hits
822system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129360 # number of LoadLockedReq hits
823system.cpu0.dcache.LoadLockedReq_hits::total 129360 # number of LoadLockedReq hits
824system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130225 # number of StoreCondReq hits
825system.cpu0.dcache.StoreCondReq_hits::total 130225 # number of StoreCondReq hits
826system.cpu0.dcache.demand_hits::cpu0.data 10049347 # number of demand (read+write) hits
827system.cpu0.dcache.demand_hits::total 10049347 # number of demand (read+write) hits
828system.cpu0.dcache.overall_hits::cpu0.data 10049347 # number of overall hits
829system.cpu0.dcache.overall_hits::total 10049347 # number of overall hits
830system.cpu0.dcache.ReadReq_misses::cpu0.data 191756 # number of ReadReq misses
831system.cpu0.dcache.ReadReq_misses::total 191756 # number of ReadReq misses
832system.cpu0.dcache.WriteReq_misses::cpu0.data 126522 # number of WriteReq misses
833system.cpu0.dcache.WriteReq_misses::total 126522 # number of WriteReq misses
834system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8645 # number of LoadLockedReq misses
835system.cpu0.dcache.LoadLockedReq_misses::total 8645 # number of LoadLockedReq misses
836system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7703 # number of StoreCondReq misses
837system.cpu0.dcache.StoreCondReq_misses::total 7703 # number of StoreCondReq misses
838system.cpu0.dcache.demand_misses::cpu0.data 318278 # number of demand (read+write) misses
839system.cpu0.dcache.demand_misses::total 318278 # number of demand (read+write) misses
840system.cpu0.dcache.overall_misses::cpu0.data 318278 # number of overall misses
841system.cpu0.dcache.overall_misses::total 318278 # number of overall misses
842system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2678719000 # number of ReadReq miss cycles
843system.cpu0.dcache.ReadReq_miss_latency::total 2678719000 # number of ReadReq miss cycles
844system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 3810145000 # number of WriteReq miss cycles
845system.cpu0.dcache.WriteReq_miss_latency::total 3810145000 # number of WriteReq miss cycles
846system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 78655500 # number of LoadLockedReq miss cycles
847system.cpu0.dcache.LoadLockedReq_miss_latency::total 78655500 # number of LoadLockedReq miss cycles
848system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45606000 # number of StoreCondReq miss cycles
849system.cpu0.dcache.StoreCondReq_miss_latency::total 45606000 # number of StoreCondReq miss cycles
850system.cpu0.dcache.demand_miss_latency::cpu0.data 6488864000 # number of demand (read+write) miss cycles
851system.cpu0.dcache.demand_miss_latency::total 6488864000 # number of demand (read+write) miss cycles
852system.cpu0.dcache.overall_miss_latency::cpu0.data 6488864000 # number of overall miss cycles
853system.cpu0.dcache.overall_miss_latency::total 6488864000 # number of overall miss cycles
854system.cpu0.dcache.ReadReq_accesses::cpu0.data 5669311 # number of ReadReq accesses(hits+misses)
855system.cpu0.dcache.ReadReq_accesses::total 5669311 # number of ReadReq accesses(hits+misses)
856system.cpu0.dcache.WriteReq_accesses::cpu0.data 4698314 # number of WriteReq accesses(hits+misses)
857system.cpu0.dcache.WriteReq_accesses::total 4698314 # number of WriteReq accesses(hits+misses)
858system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138005 # number of LoadLockedReq accesses(hits+misses)
859system.cpu0.dcache.LoadLockedReq_accesses::total 138005 # number of LoadLockedReq accesses(hits+misses)
860system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137928 # number of StoreCondReq accesses(hits+misses)
861system.cpu0.dcache.StoreCondReq_accesses::total 137928 # number of StoreCondReq accesses(hits+misses)
862system.cpu0.dcache.demand_accesses::cpu0.data 10367625 # number of demand (read+write) accesses
863system.cpu0.dcache.demand_accesses::total 10367625 # number of demand (read+write) accesses
864system.cpu0.dcache.overall_accesses::cpu0.data 10367625 # number of overall (read+write) accesses
865system.cpu0.dcache.overall_accesses::total 10367625 # number of overall (read+write) accesses
866system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033824 # miss rate for ReadReq accesses
867system.cpu0.dcache.ReadReq_miss_rate::total 0.033824 # miss rate for ReadReq accesses
868system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses
869system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses
870system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.062643 # miss rate for LoadLockedReq accesses
871system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.062643 # miss rate for LoadLockedReq accesses
872system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.055848 # miss rate for StoreCondReq accesses
873system.cpu0.dcache.StoreCondReq_miss_rate::total 0.055848 # miss rate for StoreCondReq accesses
874system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030699 # miss rate for demand accesses
875system.cpu0.dcache.demand_miss_rate::total 0.030699 # miss rate for demand accesses
876system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030699 # miss rate for overall accesses
877system.cpu0.dcache.overall_miss_rate::total 0.030699 # miss rate for overall accesses
878system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13969.414256 # average ReadReq miss latency
879system.cpu0.dcache.ReadReq_avg_miss_latency::total 13969.414256 # average ReadReq miss latency
880system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30114.486018 # average WriteReq miss latency
881system.cpu0.dcache.WriteReq_avg_miss_latency::total 30114.486018 # average WriteReq miss latency
882system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9098.380567 # average LoadLockedReq miss latency
883system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9098.380567 # average LoadLockedReq miss latency
884system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5920.550435 # average StoreCondReq miss latency
885system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5920.550435 # average StoreCondReq miss latency
886system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency
887system.cpu0.dcache.demand_avg_miss_latency::total 20387.409749 # average overall miss latency
888system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20387.409749 # average overall miss latency
889system.cpu0.dcache.overall_avg_miss_latency::total 20387.409749 # average overall miss latency
890system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
891system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
892system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
893system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
894system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
895system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
896system.cpu0.dcache.fast_writes 0 # number of fast writes performed
897system.cpu0.dcache.cache_copies 0 # number of cache copies performed
898system.cpu0.dcache.writebacks::writebacks 257540 # number of writebacks
899system.cpu0.dcache.writebacks::total 257540 # number of writebacks
900system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191756 # number of ReadReq MSHR misses
901system.cpu0.dcache.ReadReq_mshr_misses::total 191756 # number of ReadReq MSHR misses
902system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126522 # number of WriteReq MSHR misses
903system.cpu0.dcache.WriteReq_mshr_misses::total 126522 # number of WriteReq MSHR misses
904system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8645 # number of LoadLockedReq MSHR misses
905system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8645 # number of LoadLockedReq MSHR misses
906system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7700 # number of StoreCondReq MSHR misses
907system.cpu0.dcache.StoreCondReq_mshr_misses::total 7700 # number of StoreCondReq MSHR misses
908system.cpu0.dcache.demand_mshr_misses::cpu0.data 318278 # number of demand (read+write) MSHR misses
909system.cpu0.dcache.demand_mshr_misses::total 318278 # number of demand (read+write) MSHR misses
910system.cpu0.dcache.overall_mshr_misses::cpu0.data 318278 # number of overall MSHR misses
911system.cpu0.dcache.overall_mshr_misses::total 318278 # number of overall MSHR misses
912system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295207000 # number of ReadReq MSHR miss cycles
913system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2295207000 # number of ReadReq MSHR miss cycles
914system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3557101000 # number of WriteReq MSHR miss cycles
915system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3557101000 # number of WriteReq MSHR miss cycles
916system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 61365500 # number of LoadLockedReq MSHR miss cycles
917system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 61365500 # number of LoadLockedReq MSHR miss cycles
918system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30208000 # number of StoreCondReq MSHR miss cycles
919system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30208000 # number of StoreCondReq MSHR miss cycles
920system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
921system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
922system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5852308000 # number of demand (read+write) MSHR miss cycles
923system.cpu0.dcache.demand_mshr_miss_latency::total 5852308000 # number of demand (read+write) MSHR miss cycles
924system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5852308000 # number of overall MSHR miss cycles
925system.cpu0.dcache.overall_mshr_miss_latency::total 5852308000 # number of overall MSHR miss cycles
926system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12211047000 # number of ReadReq MSHR uncacheable cycles
927system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12211047000 # number of ReadReq MSHR uncacheable cycles
928system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1122364500 # number of WriteReq MSHR uncacheable cycles
929system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1122364500 # number of WriteReq MSHR uncacheable cycles
930system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13333411500 # number of overall MSHR uncacheable cycles
931system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13333411500 # number of overall MSHR uncacheable cycles
932system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033824 # mshr miss rate for ReadReq accesses
933system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033824 # mshr miss rate for ReadReq accesses
934system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses
935system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses
936system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062643 # mshr miss rate for LoadLockedReq accesses
937system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062643 # mshr miss rate for LoadLockedReq accesses
938system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.055826 # mshr miss rate for StoreCondReq accesses
939system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.055826 # mshr miss rate for StoreCondReq accesses
940system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for demand accesses
941system.cpu0.dcache.demand_mshr_miss_rate::total 0.030699 # mshr miss rate for demand accesses
942system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030699 # mshr miss rate for overall accesses
943system.cpu0.dcache.overall_mshr_miss_rate::total 0.030699 # mshr miss rate for overall accesses
944system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11969.414256 # average ReadReq mshr miss latency
945system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11969.414256 # average ReadReq mshr miss latency
946system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28114.486018 # average WriteReq mshr miss latency
947system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28114.486018 # average WriteReq mshr miss latency
948system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7098.380567 # average LoadLockedReq mshr miss latency
949system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7098.380567 # average LoadLockedReq mshr miss latency
950system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3923.116883 # average StoreCondReq mshr miss latency
951system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3923.116883 # average StoreCondReq mshr miss latency
952system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
953system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
954system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
955system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
956system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18387.409749 # average overall mshr miss latency
957system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18387.409749 # average overall mshr miss latency
958system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
959system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
960system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
961system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
962system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
963system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
964system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
965system.cpu1.dtb.inst_hits 0 # ITB inst hits
966system.cpu1.dtb.inst_misses 0 # ITB inst misses
967system.cpu1.dtb.read_hits 9504194 # DTB read hits
968system.cpu1.dtb.read_misses 5263 # DTB read misses
969system.cpu1.dtb.write_hits 6646220 # DTB write hits
970system.cpu1.dtb.write_misses 1833 # DTB write misses
971system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
972system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
973system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
974system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
975system.cpu1.dtb.flush_entries 2237 # Number of entries that have been flushed from TLB
976system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
977system.cpu1.dtb.prefetch_faults 191 # Number of TLB faults due to prefetch
978system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
979system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions
980system.cpu1.dtb.read_accesses 9509457 # DTB read accesses
981system.cpu1.dtb.write_accesses 6648053 # DTB write accesses
982system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
983system.cpu1.dtb.hits 16150414 # DTB hits
984system.cpu1.dtb.misses 7096 # DTB misses
985system.cpu1.dtb.accesses 16157510 # DTB accesses
986system.cpu1.itb.inst_hits 37994467 # ITB inst hits
987system.cpu1.itb.inst_misses 3017 # ITB inst misses
988system.cpu1.itb.read_hits 0 # DTB read hits
989system.cpu1.itb.read_misses 0 # DTB read misses
990system.cpu1.itb.write_hits 0 # DTB write hits
991system.cpu1.itb.write_misses 0 # DTB write misses
992system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
993system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
994system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
995system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
996system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB
997system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
998system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
999system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1000system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1001system.cpu1.itb.read_accesses 0 # DTB read accesses
1002system.cpu1.itb.write_accesses 0 # DTB write accesses
1003system.cpu1.itb.inst_accesses 37997484 # ITB inst accesses
1004system.cpu1.itb.hits 37994467 # DTB hits
1005system.cpu1.itb.misses 3017 # DTB misses
1006system.cpu1.itb.accesses 37997484 # DTB accesses
1007system.cpu1.numCycles 2366006228 # number of cpu cycles simulated
1008system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1009system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1010system.cpu1.committedInsts 37084001 # Number of instructions committed
1011system.cpu1.committedOps 46850371 # Number of ops (including micro ops) committed
1012system.cpu1.num_int_alu_accesses 42360540 # Number of integer alu accesses
1013system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses
1014system.cpu1.num_func_calls 1133542 # number of times a function call or return occured
1015system.cpu1.num_conditional_control_insts 4355119 # number of instructions that are conditional controls
1016system.cpu1.num_int_insts 42360540 # number of integer instructions
1017system.cpu1.num_fp_insts 5457 # number of float instructions
1018system.cpu1.num_int_register_reads 243148462 # number of times the integer registers were read
1019system.cpu1.num_int_register_writes 45181015 # number of times the integer registers were written
1020system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read
1021system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written
1022system.cpu1.num_mem_refs 16764021 # number of memory refs
1023system.cpu1.num_load_insts 9884261 # Number of load instructions
1024system.cpu1.num_store_insts 6879760 # Number of store instructions
1025system.cpu1.num_idle_cycles 1849775265.196436 # Number of idle cycles
1026system.cpu1.num_busy_cycles 516230962.803564 # Number of busy cycles
1027system.cpu1.not_idle_fraction 0.218187 # Percentage of non-idle cycles
1028system.cpu1.idle_fraction 0.781813 # Percentage of idle cycles
1029system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1030system.cpu1.kern.inst.quiesce 51687 # number of quiesce instructions executed
1031system.cpu1.icache.replacements 540342 # number of replacements
1032system.cpu1.icache.tagsinuse 478.756805 # Cycle average of tags in use
1033system.cpu1.icache.total_refs 37453609 # Total number of references to valid blocks.
1034system.cpu1.icache.sampled_refs 540854 # Sample count of references to valid blocks.
1035system.cpu1.icache.avg_refs 69.249019 # Average number of references to valid blocks.
1036system.cpu1.icache.warmup_cycle 92137748500 # Cycle when the warmup percentage was hit.
1037system.cpu1.icache.occ_blocks::cpu1.inst 478.756805 # Average occupied blocks per requestor
1038system.cpu1.icache.occ_percent::cpu1.inst 0.935072 # Average percentage of cache occupancy
1039system.cpu1.icache.occ_percent::total 0.935072 # Average percentage of cache occupancy
1040system.cpu1.icache.ReadReq_hits::cpu1.inst 37453609 # number of ReadReq hits
1041system.cpu1.icache.ReadReq_hits::total 37453609 # number of ReadReq hits
1042system.cpu1.icache.demand_hits::cpu1.inst 37453609 # number of demand (read+write) hits
1043system.cpu1.icache.demand_hits::total 37453609 # number of demand (read+write) hits
1044system.cpu1.icache.overall_hits::cpu1.inst 37453609 # number of overall hits
1045system.cpu1.icache.overall_hits::total 37453609 # number of overall hits
1046system.cpu1.icache.ReadReq_misses::cpu1.inst 540854 # number of ReadReq misses
1047system.cpu1.icache.ReadReq_misses::total 540854 # number of ReadReq misses
1048system.cpu1.icache.demand_misses::cpu1.inst 540854 # number of demand (read+write) misses
1049system.cpu1.icache.demand_misses::total 540854 # number of demand (read+write) misses
1050system.cpu1.icache.overall_misses::cpu1.inst 540854 # number of overall misses
1051system.cpu1.icache.overall_misses::total 540854 # number of overall misses
1052system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7301553500 # number of ReadReq miss cycles
1053system.cpu1.icache.ReadReq_miss_latency::total 7301553500 # number of ReadReq miss cycles
1054system.cpu1.icache.demand_miss_latency::cpu1.inst 7301553500 # number of demand (read+write) miss cycles
1055system.cpu1.icache.demand_miss_latency::total 7301553500 # number of demand (read+write) miss cycles
1056system.cpu1.icache.overall_miss_latency::cpu1.inst 7301553500 # number of overall miss cycles
1057system.cpu1.icache.overall_miss_latency::total 7301553500 # number of overall miss cycles
1058system.cpu1.icache.ReadReq_accesses::cpu1.inst 37994463 # number of ReadReq accesses(hits+misses)
1059system.cpu1.icache.ReadReq_accesses::total 37994463 # number of ReadReq accesses(hits+misses)
1060system.cpu1.icache.demand_accesses::cpu1.inst 37994463 # number of demand (read+write) accesses
1061system.cpu1.icache.demand_accesses::total 37994463 # number of demand (read+write) accesses
1062system.cpu1.icache.overall_accesses::cpu1.inst 37994463 # number of overall (read+write) accesses
1063system.cpu1.icache.overall_accesses::total 37994463 # number of overall (read+write) accesses
1064system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014235 # miss rate for ReadReq accesses
1065system.cpu1.icache.ReadReq_miss_rate::total 0.014235 # miss rate for ReadReq accesses
1066system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014235 # miss rate for demand accesses
1067system.cpu1.icache.demand_miss_rate::total 0.014235 # miss rate for demand accesses
1068system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014235 # miss rate for overall accesses
1069system.cpu1.icache.overall_miss_rate::total 0.014235 # miss rate for overall accesses
1070system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13500.045299 # average ReadReq miss latency
1071system.cpu1.icache.ReadReq_avg_miss_latency::total 13500.045299 # average ReadReq miss latency
1072system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency
1073system.cpu1.icache.demand_avg_miss_latency::total 13500.045299 # average overall miss latency
1074system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13500.045299 # average overall miss latency
1075system.cpu1.icache.overall_avg_miss_latency::total 13500.045299 # average overall miss latency
1076system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1077system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1078system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1079system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1080system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1081system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1082system.cpu1.icache.fast_writes 0 # number of fast writes performed
1083system.cpu1.icache.cache_copies 0 # number of cache copies performed
1084system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 540854 # number of ReadReq MSHR misses
1085system.cpu1.icache.ReadReq_mshr_misses::total 540854 # number of ReadReq MSHR misses
1086system.cpu1.icache.demand_mshr_misses::cpu1.inst 540854 # number of demand (read+write) MSHR misses
1087system.cpu1.icache.demand_mshr_misses::total 540854 # number of demand (read+write) MSHR misses
1088system.cpu1.icache.overall_mshr_misses::cpu1.inst 540854 # number of overall MSHR misses
1089system.cpu1.icache.overall_mshr_misses::total 540854 # number of overall MSHR misses
1090system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6219845500 # number of ReadReq MSHR miss cycles
1091system.cpu1.icache.ReadReq_mshr_miss_latency::total 6219845500 # number of ReadReq MSHR miss cycles
1092system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6219845500 # number of demand (read+write) MSHR miss cycles
1093system.cpu1.icache.demand_mshr_miss_latency::total 6219845500 # number of demand (read+write) MSHR miss cycles
1094system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6219845500 # number of overall MSHR miss cycles
1095system.cpu1.icache.overall_mshr_miss_latency::total 6219845500 # number of overall MSHR miss cycles
1096system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4396000 # number of ReadReq MSHR uncacheable cycles
1097system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4396000 # number of ReadReq MSHR uncacheable cycles
1098system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4396000 # number of overall MSHR uncacheable cycles
1099system.cpu1.icache.overall_mshr_uncacheable_latency::total 4396000 # number of overall MSHR uncacheable cycles
1100system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for ReadReq accesses
1101system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014235 # mshr miss rate for ReadReq accesses
1102system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for demand accesses
1103system.cpu1.icache.demand_mshr_miss_rate::total 0.014235 # mshr miss rate for demand accesses
1104system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014235 # mshr miss rate for overall accesses
1105system.cpu1.icache.overall_mshr_miss_rate::total 0.014235 # mshr miss rate for overall accesses
1106system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average ReadReq mshr miss latency
1107system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11500.045299 # average ReadReq mshr miss latency
1108system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency
1109system.cpu1.icache.demand_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency
1110system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11500.045299 # average overall mshr miss latency
1111system.cpu1.icache.overall_avg_mshr_miss_latency::total 11500.045299 # average overall mshr miss latency
1112system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1113system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1114system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1115system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1116system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1117system.cpu1.dcache.replacements 343957 # number of replacements
1118system.cpu1.dcache.tagsinuse 473.088021 # Cycle average of tags in use
1119system.cpu1.dcache.total_refs 13916365 # Total number of references to valid blocks.
1120system.cpu1.dcache.sampled_refs 344469 # Sample count of references to valid blocks.
1121system.cpu1.dcache.avg_refs 40.399470 # Average number of references to valid blocks.
1122system.cpu1.dcache.warmup_cycle 83709904000 # Cycle when the warmup percentage was hit.
1123system.cpu1.dcache.occ_blocks::cpu1.data 473.088021 # Average occupied blocks per requestor
1124system.cpu1.dcache.occ_percent::cpu1.data 0.924000 # Average percentage of cache occupancy
1125system.cpu1.dcache.occ_percent::total 0.924000 # Average percentage of cache occupancy
1126system.cpu1.dcache.ReadReq_hits::cpu1.data 8074934 # number of ReadReq hits
1127system.cpu1.dcache.ReadReq_hits::total 8074934 # number of ReadReq hits
1128system.cpu1.dcache.WriteReq_hits::cpu1.data 5611325 # number of WriteReq hits
1129system.cpu1.dcache.WriteReq_hits::total 5611325 # number of WriteReq hits
1130system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 100335 # number of LoadLockedReq hits
1131system.cpu1.dcache.LoadLockedReq_hits::total 100335 # number of LoadLockedReq hits
1132system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102214 # number of StoreCondReq hits
1133system.cpu1.dcache.StoreCondReq_hits::total 102214 # number of StoreCondReq hits
1134system.cpu1.dcache.demand_hits::cpu1.data 13686259 # number of demand (read+write) hits
1135system.cpu1.dcache.demand_hits::total 13686259 # number of demand (read+write) hits
1136system.cpu1.dcache.overall_hits::cpu1.data 13686259 # number of overall hits
1137system.cpu1.dcache.overall_hits::total 13686259 # number of overall hits
1138system.cpu1.dcache.ReadReq_misses::cpu1.data 207178 # number of ReadReq misses
1139system.cpu1.dcache.ReadReq_misses::total 207178 # number of ReadReq misses
1140system.cpu1.dcache.WriteReq_misses::cpu1.data 165249 # number of WriteReq misses
1141system.cpu1.dcache.WriteReq_misses::total 165249 # number of WriteReq misses
1142system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11790 # number of LoadLockedReq misses
1143system.cpu1.dcache.LoadLockedReq_misses::total 11790 # number of LoadLockedReq misses
1144system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9834 # number of StoreCondReq misses
1145system.cpu1.dcache.StoreCondReq_misses::total 9834 # number of StoreCondReq misses
1146system.cpu1.dcache.demand_misses::cpu1.data 372427 # number of demand (read+write) misses
1147system.cpu1.dcache.demand_misses::total 372427 # number of demand (read+write) misses
1148system.cpu1.dcache.overall_misses::cpu1.data 372427 # number of overall misses
1149system.cpu1.dcache.overall_misses::total 372427 # number of overall misses
1150system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2639135500 # number of ReadReq miss cycles
1151system.cpu1.dcache.ReadReq_miss_latency::total 2639135500 # number of ReadReq miss cycles
1152system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4834942000 # number of WriteReq miss cycles
1153system.cpu1.dcache.WriteReq_miss_latency::total 4834942000 # number of WriteReq miss cycles
1154system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 103120000 # number of LoadLockedReq miss cycles
1155system.cpu1.dcache.LoadLockedReq_miss_latency::total 103120000 # number of LoadLockedReq miss cycles
1156system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50505000 # number of StoreCondReq miss cycles
1157system.cpu1.dcache.StoreCondReq_miss_latency::total 50505000 # number of StoreCondReq miss cycles
1158system.cpu1.dcache.demand_miss_latency::cpu1.data 7474077500 # number of demand (read+write) miss cycles
1159system.cpu1.dcache.demand_miss_latency::total 7474077500 # number of demand (read+write) miss cycles
1160system.cpu1.dcache.overall_miss_latency::cpu1.data 7474077500 # number of overall miss cycles
1161system.cpu1.dcache.overall_miss_latency::total 7474077500 # number of overall miss cycles
1162system.cpu1.dcache.ReadReq_accesses::cpu1.data 8282112 # number of ReadReq accesses(hits+misses)
1163system.cpu1.dcache.ReadReq_accesses::total 8282112 # number of ReadReq accesses(hits+misses)
1164system.cpu1.dcache.WriteReq_accesses::cpu1.data 5776574 # number of WriteReq accesses(hits+misses)
1165system.cpu1.dcache.WriteReq_accesses::total 5776574 # number of WriteReq accesses(hits+misses)
1166system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 112125 # number of LoadLockedReq accesses(hits+misses)
1167system.cpu1.dcache.LoadLockedReq_accesses::total 112125 # number of LoadLockedReq accesses(hits+misses)
1168system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 112048 # number of StoreCondReq accesses(hits+misses)
1169system.cpu1.dcache.StoreCondReq_accesses::total 112048 # number of StoreCondReq accesses(hits+misses)
1170system.cpu1.dcache.demand_accesses::cpu1.data 14058686 # number of demand (read+write) accesses
1171system.cpu1.dcache.demand_accesses::total 14058686 # number of demand (read+write) accesses
1172system.cpu1.dcache.overall_accesses::cpu1.data 14058686 # number of overall (read+write) accesses
1173system.cpu1.dcache.overall_accesses::total 14058686 # number of overall (read+write) accesses
1174system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.025015 # miss rate for ReadReq accesses
1175system.cpu1.dcache.ReadReq_miss_rate::total 0.025015 # miss rate for ReadReq accesses
1176system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028607 # miss rate for WriteReq accesses
1177system.cpu1.dcache.WriteReq_miss_rate::total 0.028607 # miss rate for WriteReq accesses
1178system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.105151 # miss rate for LoadLockedReq accesses
1179system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.105151 # miss rate for LoadLockedReq accesses
1180system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.087766 # miss rate for StoreCondReq accesses
1181system.cpu1.dcache.StoreCondReq_miss_rate::total 0.087766 # miss rate for StoreCondReq accesses
1182system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026491 # miss rate for demand accesses
1183system.cpu1.dcache.demand_miss_rate::total 0.026491 # miss rate for demand accesses
1184system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026491 # miss rate for overall accesses
1185system.cpu1.dcache.overall_miss_rate::total 0.026491 # miss rate for overall accesses
1186system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12738.492987 # average ReadReq miss latency
1187system.cpu1.dcache.ReadReq_avg_miss_latency::total 12738.492987 # average ReadReq miss latency
1188system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29258.525014 # average WriteReq miss latency
1189system.cpu1.dcache.WriteReq_avg_miss_latency::total 29258.525014 # average WriteReq miss latency
1190system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8746.395250 # average LoadLockedReq miss latency
1191system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8746.395250 # average LoadLockedReq miss latency
1192system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5135.753508 # average StoreCondReq miss latency
1193system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5135.753508 # average StoreCondReq miss latency
1194system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency
1195system.cpu1.dcache.demand_avg_miss_latency::total 20068.570485 # average overall miss latency
1196system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20068.570485 # average overall miss latency
1197system.cpu1.dcache.overall_avg_miss_latency::total 20068.570485 # average overall miss latency
1198system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1199system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1200system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1201system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1202system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1203system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1204system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1205system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1206system.cpu1.dcache.writebacks::writebacks 315665 # number of writebacks
1207system.cpu1.dcache.writebacks::total 315665 # number of writebacks
1208system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207178 # number of ReadReq MSHR misses
1209system.cpu1.dcache.ReadReq_mshr_misses::total 207178 # number of ReadReq MSHR misses
1210system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165249 # number of WriteReq MSHR misses
1211system.cpu1.dcache.WriteReq_mshr_misses::total 165249 # number of WriteReq MSHR misses
1212system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11790 # number of LoadLockedReq MSHR misses
1213system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11790 # number of LoadLockedReq MSHR misses
1214system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9830 # number of StoreCondReq MSHR misses
1215system.cpu1.dcache.StoreCondReq_mshr_misses::total 9830 # number of StoreCondReq MSHR misses
1216system.cpu1.dcache.demand_mshr_misses::cpu1.data 372427 # number of demand (read+write) MSHR misses
1217system.cpu1.dcache.demand_mshr_misses::total 372427 # number of demand (read+write) MSHR misses
1218system.cpu1.dcache.overall_mshr_misses::cpu1.data 372427 # number of overall MSHR misses
1219system.cpu1.dcache.overall_mshr_misses::total 372427 # number of overall MSHR misses
1220system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2224779500 # number of ReadReq MSHR miss cycles
1221system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2224779500 # number of ReadReq MSHR miss cycles
1222system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4504444000 # number of WriteReq MSHR miss cycles
1223system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4504444000 # number of WriteReq MSHR miss cycles
1224system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 79540000 # number of LoadLockedReq MSHR miss cycles
1225system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79540000 # number of LoadLockedReq MSHR miss cycles
1226system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30847000 # number of StoreCondReq MSHR miss cycles
1227system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30847000 # number of StoreCondReq MSHR miss cycles
1228system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
1229system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
1230system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6729223500 # number of demand (read+write) MSHR miss cycles
1231system.cpu1.dcache.demand_mshr_miss_latency::total 6729223500 # number of demand (read+write) MSHR miss cycles
1232system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6729223500 # number of overall MSHR miss cycles
1233system.cpu1.dcache.overall_mshr_miss_latency::total 6729223500 # number of overall MSHR miss cycles
1234system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169996101000 # number of ReadReq MSHR uncacheable cycles
1235system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169996101000 # number of ReadReq MSHR uncacheable cycles
1236system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17674592500 # number of WriteReq MSHR uncacheable cycles
1237system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17674592500 # number of WriteReq MSHR uncacheable cycles
1238system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 187670693500 # number of overall MSHR uncacheable cycles
1239system.cpu1.dcache.overall_mshr_uncacheable_latency::total 187670693500 # number of overall MSHR uncacheable cycles
1240system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025015 # mshr miss rate for ReadReq accesses
1241system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025015 # mshr miss rate for ReadReq accesses
1242system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses
1243system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses
1244system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.105151 # mshr miss rate for LoadLockedReq accesses
1245system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.105151 # mshr miss rate for LoadLockedReq accesses
1246system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.087730 # mshr miss rate for StoreCondReq accesses
1247system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.087730 # mshr miss rate for StoreCondReq accesses
1248system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for demand accesses
1249system.cpu1.dcache.demand_mshr_miss_rate::total 0.026491 # mshr miss rate for demand accesses
1250system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026491 # mshr miss rate for overall accesses
1251system.cpu1.dcache.overall_mshr_miss_rate::total 0.026491 # mshr miss rate for overall accesses
1252system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10738.492987 # average ReadReq mshr miss latency
1253system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10738.492987 # average ReadReq mshr miss latency
1254system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.525014 # average WriteReq mshr miss latency
1255system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.525014 # average WriteReq mshr miss latency
1256system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6746.395250 # average LoadLockedReq mshr miss latency
1257system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6746.395250 # average LoadLockedReq mshr miss latency
1258system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3138.046796 # average StoreCondReq mshr miss latency
1259system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3138.046796 # average StoreCondReq mshr miss latency
1260system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1261system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1262system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
1263system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
1264system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18068.570485 # average overall mshr miss latency
1265system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18068.570485 # average overall mshr miss latency
1266system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1267system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1268system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1269system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1270system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1271system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1272system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1273system.iocache.replacements 0 # number of replacements

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1279system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1280system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1281system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1282system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1283system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1284system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1285system.iocache.fast_writes 0 # number of fast writes performed
1286system.iocache.cache_copies 0 # number of cache copies performed
1287system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509652310593 # number of ReadReq MSHR uncacheable cycles
1288system.iocache.ReadReq_mshr_uncacheable_latency::total 509652310593 # number of ReadReq MSHR uncacheable cycles
1289system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509652310593 # number of overall MSHR uncacheable cycles
1290system.iocache.overall_mshr_uncacheable_latency::total 509652310593 # number of overall MSHR uncacheable cycles
1291system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1292system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1293system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1294system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1295system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1296
1297---------- End Simulation Statistics ----------