1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.169707 # Number of seconds simulated
4sim_ticks 1169707043000 # Number of ticks simulated
5final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 754175 # Simulator instruction rate (inst/s)
8host_op_rate 964493 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 14598169556 # Simulator tick rate (ticks/s)
10host_mem_usage 379804 # Number of bytes of host memory used
11host_seconds 80.13 # Real time elapsed on the host
12sim_insts 60429704 # Number of instructions simulated
13sim_ops 77281862 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 61898788 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 10078928 # Number of bytes written to this memory
17system.physmem.num_reads 6478591 # Number of read requests responded to by this memory
18system.physmem.num_writes 867017 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s)
24system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
25system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
27system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory
28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
30system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s)
32system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s)
33system.l2c.replacements 125934 # number of replacements
34system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use
35system.l2c.total_refs 1500548 # Total number of references to valid blocks.
36system.l2c.sampled_refs 155551 # Sample count of references to valid blocks.
37system.l2c.avg_refs 9.646663 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor
--- 165 unchanged lines hidden (view full) ---
206system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for ReadReq accesses
207system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002264 # miss rate for ReadReq accesses
208system.l2c.ReadReq_miss_rate::cpu0.inst 0.019500 # miss rate for ReadReq accesses
209system.l2c.ReadReq_miss_rate::cpu0.data 0.052112 # miss rate for ReadReq accesses
210system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for ReadReq accesses
211system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses
212system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses
213system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses
214system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses
215system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses
216system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses
217system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses
218system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses
219system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses
220system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses
221system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses
222system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses
223system.l2c.demand_miss_rate::cpu0.data 0.240912 # miss rate for demand accesses
224system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for demand accesses
225system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses
226system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses
227system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses
228system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses
229system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses
230system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses
231system.l2c.overall_miss_rate::cpu0.data 0.240912 # miss rate for overall accesses
232system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for overall accesses
233system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses
234system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses
235system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses
236system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency
237system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency
238system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency
239system.l2c.ReadReq_avg_miss_latency::cpu0.data 52082.081640 # average ReadReq miss latency
240system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average ReadReq miss latency
241system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
242system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency
243system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency
244system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency
245system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency
246system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency
247system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency
248system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency
249system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency
250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
252system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
253system.l2c.demand_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
254system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
255system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
256system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
257system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
258system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
259system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
260system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
261system.l2c.overall_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
264system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
265system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
269system.l2c.blocked::no_targets 0 # number of cycles access was blocked
270system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
271system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
272system.l2c.fast_writes 0 # number of fast writes performed
273system.l2c.cache_copies 0 # number of cache copies performed
--- 93 unchanged lines hidden (view full) ---
367system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for ReadReq accesses
368system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for ReadReq accesses
369system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for ReadReq accesses
370system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.052112 # mshr miss rate for ReadReq accesses
371system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for ReadReq accesses
372system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses
373system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses
374system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses
375system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses
376system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses
377system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses
378system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses
379system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses
380system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses
381system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses
382system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses
383system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses
384system.l2c.demand_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for demand accesses
385system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for demand accesses
386system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses
387system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses
388system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses
389system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses
390system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses
391system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses
392system.l2c.overall_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for overall accesses
393system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for overall accesses
394system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses
395system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses
396system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses
397system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
398system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
399system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency
400system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40082.081640 # average ReadReq mshr miss latency
401system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average ReadReq mshr miss latency
402system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
403system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency
404system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency
405system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency
406system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency
407system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency
408system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency
409system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency
410system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency
411system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
412system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
413system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
414system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
415system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
416system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
417system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
418system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
419system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
420system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
421system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
422system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
423system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
424system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
425system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
426system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
427system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
428system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
429system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
430system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
431system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
432system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
433system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
434system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
435system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
436system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
437system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
438system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
439system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
440system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
441system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
442system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
443system.cf0.dma_write_txs 0 # Number of DMA write transactions.
444system.cpu0.dtb.inst_hits 0 # ITB inst hits
--- 91 unchanged lines hidden (view full) ---
536system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles
537system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses)
538system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses)
539system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses
540system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses
541system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses
542system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses
543system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses
544system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses
545system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses
546system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency
547system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
548system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
549system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
550system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
551system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
552system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
553system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
554system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
555system.cpu0.icache.fast_writes 0 # number of fast writes performed
556system.cpu0.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
568system.cpu0.icache.demand_mshr_miss_latency::total 4832163500 # number of demand (read+write) MSHR miss cycles
569system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles
570system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles
571system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
572system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
573system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
574system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
575system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses
576system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses
577system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses
578system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency
579system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
580system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
581system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
582system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
583system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
584system.cpu0.dcache.replacements 335831 # number of replacements
585system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use
586system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks.
587system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks.
588system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks.
589system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
590system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor
--- 43 unchanged lines hidden (view full) ---
634system.cpu0.dcache.LoadLockedReq_accesses::total 157222 # number of LoadLockedReq accesses(hits+misses)
635system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157159 # number of StoreCondReq accesses(hits+misses)
636system.cpu0.dcache.StoreCondReq_accesses::total 157159 # number of StoreCondReq accesses(hits+misses)
637system.cpu0.dcache.demand_accesses::cpu0.data 12319714 # number of demand (read+write) accesses
638system.cpu0.dcache.demand_accesses::total 12319714 # number of demand (read+write) accesses
639system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses
640system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses
641system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses
642system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses
643system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses
644system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses
645system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses
646system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses
647system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency
648system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency
649system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency
650system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency
651system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
652system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
653system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
654system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
655system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
656system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
657system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
658system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
659system.cpu0.dcache.fast_writes 0 # number of fast writes performed
660system.cpu0.dcache.cache_copies 0 # number of cache copies performed
--- 25 unchanged lines hidden (view full) ---
686system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles
687system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles
688system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles
689system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles
690system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles
691system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles
692system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles
693system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses
694system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses
695system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses
696system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses
697system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses
698system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses
699system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency
700system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency
701system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency
702system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency
703system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
704system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
705system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
706system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
707system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
708system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
709system.cpu1.dtb.inst_hits 0 # ITB inst hits
710system.cpu1.dtb.inst_misses 0 # ITB inst misses
711system.cpu1.dtb.read_hits 8313009 # DTB read hits
712system.cpu1.dtb.read_misses 3663 # DTB read misses
713system.cpu1.dtb.write_hits 5829499 # DTB write hits
714system.cpu1.dtb.write_misses 1439 # DTB write misses
715system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
--- 85 unchanged lines hidden (view full) ---
801system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles
802system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses)
803system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses)
804system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses
805system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses
806system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses
807system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses
808system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses
809system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses
810system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses
811system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency
812system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
813system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
814system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
815system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
816system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
817system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
818system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
819system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
820system.cpu1.icache.fast_writes 0 # number of fast writes performed
821system.cpu1.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
833system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles
834system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles
835system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles
836system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
837system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
838system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
839system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
840system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses
841system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses
842system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses
843system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency
844system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
845system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
846system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
847system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
848system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
849system.cpu1.dcache.replacements 294642 # number of replacements
850system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use
851system.cpu1.dcache.total_refs 11964721 # Total number of references to valid blocks.
852system.cpu1.dcache.sampled_refs 295088 # Sample count of references to valid blocks.
853system.cpu1.dcache.avg_refs 40.546281 # Average number of references to valid blocks.
854system.cpu1.dcache.warmup_cycle 89831748000 # Cycle when the warmup percentage was hit.
855system.cpu1.dcache.occ_blocks::cpu1.data 457.752328 # Average occupied blocks per requestor
--- 43 unchanged lines hidden (view full) ---
899system.cpu1.dcache.LoadLockedReq_accesses::total 92899 # number of LoadLockedReq accesses(hits+misses)
900system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92826 # number of StoreCondReq accesses(hits+misses)
901system.cpu1.dcache.StoreCondReq_accesses::total 92826 # number of StoreCondReq accesses(hits+misses)
902system.cpu1.dcache.demand_accesses::cpu1.data 12098117 # number of demand (read+write) accesses
903system.cpu1.dcache.demand_accesses::total 12098117 # number of demand (read+write) accesses
904system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses
905system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses
906system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses
907system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses
908system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses
909system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses
910system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses
911system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses
912system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency
913system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency
914system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency
915system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency
916system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
917system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
918system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
919system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
920system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
921system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
922system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
923system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
924system.cpu1.dcache.fast_writes 0 # number of fast writes performed
925system.cpu1.dcache.cache_copies 0 # number of cache copies performed
--- 25 unchanged lines hidden (view full) ---
951system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles
952system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles
953system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles
954system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles
955system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles
956system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles
957system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles
958system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses
959system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses
960system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses
961system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses
962system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses
963system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses
964system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency
965system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency
966system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency
967system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency
968system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
969system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
970system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
971system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
972system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
973system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
974system.iocache.replacements 0 # number of replacements
975system.iocache.tagsinuse 0 # Cycle average of tags in use
976system.iocache.total_refs 0 # Total number of references to valid blocks.
977system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
978system.iocache.avg_refs nan # Average number of references to valid blocks.
979system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
980system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
--- 4 unchanged lines hidden (view full) ---
985system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
986system.iocache.fast_writes 0 # number of fast writes performed
987system.iocache.cache_copies 0 # number of cache copies performed
988system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles
989system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles
990system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles
991system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles
992system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
993system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
994system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
995
996---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.169707 # Number of seconds simulated
4sim_ticks 1169707043000 # Number of ticks simulated
5final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 754175 # Simulator instruction rate (inst/s)
8host_op_rate 964493 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 14598169556 # Simulator tick rate (ticks/s)
10host_mem_usage 379804 # Number of bytes of host memory used
11host_seconds 80.13 # Real time elapsed on the host
12sim_insts 60429704 # Number of instructions simulated
13sim_ops 77281862 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 61898788 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 10078928 # Number of bytes written to this memory
17system.physmem.num_reads 6478591 # Number of read requests responded to by this memory
18system.physmem.num_writes 867017 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s)
24system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory
25system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory
27system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory
28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory
29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory
30system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s)
31system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s)
32system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s)
33system.l2c.replacements 125934 # number of replacements
34system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use
35system.l2c.total_refs 1500548 # Total number of references to valid blocks.
36system.l2c.sampled_refs 155551 # Sample count of references to valid blocks.
37system.l2c.avg_refs 9.646663 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor
40system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor
--- 165 unchanged lines hidden (view full) ---
206system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for ReadReq accesses
207system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.002264 # miss rate for ReadReq accesses
208system.l2c.ReadReq_miss_rate::cpu0.inst 0.019500 # miss rate for ReadReq accesses
209system.l2c.ReadReq_miss_rate::cpu0.data 0.052112 # miss rate for ReadReq accesses
210system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for ReadReq accesses
211system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002559 # miss rate for ReadReq accesses
212system.l2c.ReadReq_miss_rate::cpu1.inst 0.016188 # miss rate for ReadReq accesses
213system.l2c.ReadReq_miss_rate::cpu1.data 0.055681 # miss rate for ReadReq accesses
214system.l2c.UpgradeReq_miss_rate::cpu0.data 0.797203 # miss rate for UpgradeReq accesses
215system.l2c.UpgradeReq_miss_rate::cpu1.data 0.868377 # miss rate for UpgradeReq accesses
216system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.717722 # miss rate for SCUpgradeReq accesses
217system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.700775 # miss rate for SCUpgradeReq accesses
218system.l2c.ReadExReq_miss_rate::cpu0.data 0.569136 # miss rate for ReadExReq accesses
219system.l2c.ReadExReq_miss_rate::cpu1.data 0.605340 # miss rate for ReadExReq accesses
220system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for demand accesses
221system.l2c.demand_miss_rate::cpu0.itb.walker 0.002264 # miss rate for demand accesses
222system.l2c.demand_miss_rate::cpu0.inst 0.019500 # miss rate for demand accesses
223system.l2c.demand_miss_rate::cpu0.data 0.240912 # miss rate for demand accesses
224system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for demand accesses
225system.l2c.demand_miss_rate::cpu1.itb.walker 0.002559 # miss rate for demand accesses
226system.l2c.demand_miss_rate::cpu1.inst 0.016188 # miss rate for demand accesses
227system.l2c.demand_miss_rate::cpu1.data 0.307390 # miss rate for demand accesses
228system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002435 # miss rate for overall accesses
229system.l2c.overall_miss_rate::cpu0.itb.walker 0.002264 # miss rate for overall accesses
230system.l2c.overall_miss_rate::cpu0.inst 0.019500 # miss rate for overall accesses
231system.l2c.overall_miss_rate::cpu0.data 0.240912 # miss rate for overall accesses
232system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003159 # miss rate for overall accesses
233system.l2c.overall_miss_rate::cpu1.itb.walker 0.002559 # miss rate for overall accesses
234system.l2c.overall_miss_rate::cpu1.inst 0.016188 # miss rate for overall accesses
235system.l2c.overall_miss_rate::cpu1.data 0.307390 # miss rate for overall accesses
236system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52000 # average ReadReq miss latency
237system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52125 # average ReadReq miss latency
238system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52148.829010 # average ReadReq miss latency
239system.l2c.ReadReq_avg_miss_latency::cpu0.data 52082.081640 # average ReadReq miss latency
240system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average ReadReq miss latency
241system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency
242system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.290656 # average ReadReq miss latency
243system.l2c.ReadReq_avg_miss_latency::cpu1.data 52145.584869 # average ReadReq miss latency
244system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6548.352589 # average UpgradeReq miss latency
245system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 8411.374931 # average UpgradeReq miss latency
246system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7160.493827 # average SCUpgradeReq miss latency
247system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11161.504425 # average SCUpgradeReq miss latency
248system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52045.653366 # average ReadExReq miss latency
249system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52117.289052 # average ReadExReq miss latency
250system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
251system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
252system.l2c.demand_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
253system.l2c.demand_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
254system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
255system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
256system.l2c.demand_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
257system.l2c.demand_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
258system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
259system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52125 # average overall miss latency
260system.l2c.overall_avg_miss_latency::cpu0.inst 52148.829010 # average overall miss latency
261system.l2c.overall_avg_miss_latency::cpu0.data 52050.655795 # average overall miss latency
262system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52222.222222 # average overall miss latency
263system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency
264system.l2c.overall_avg_miss_latency::cpu1.inst 52273.290656 # average overall miss latency
265system.l2c.overall_avg_miss_latency::cpu1.data 52120.067424 # average overall miss latency
266system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
267system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
268system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
269system.l2c.blocked::no_targets 0 # number of cycles access was blocked
270system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
271system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
272system.l2c.fast_writes 0 # number of fast writes performed
273system.l2c.cache_copies 0 # number of cache copies performed
--- 93 unchanged lines hidden (view full) ---
367system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for ReadReq accesses
368system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for ReadReq accesses
369system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for ReadReq accesses
370system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.052112 # mshr miss rate for ReadReq accesses
371system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for ReadReq accesses
372system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for ReadReq accesses
373system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for ReadReq accesses
374system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.055681 # mshr miss rate for ReadReq accesses
375system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.797203 # mshr miss rate for UpgradeReq accesses
376system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.868377 # mshr miss rate for UpgradeReq accesses
377system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.717722 # mshr miss rate for SCUpgradeReq accesses
378system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.700775 # mshr miss rate for SCUpgradeReq accesses
379system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569136 # mshr miss rate for ReadExReq accesses
380system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.605340 # mshr miss rate for ReadExReq accesses
381system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for demand accesses
382system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for demand accesses
383system.l2c.demand_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for demand accesses
384system.l2c.demand_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for demand accesses
385system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for demand accesses
386system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for demand accesses
387system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for demand accesses
388system.l2c.demand_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for demand accesses
389system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.002435 # mshr miss rate for overall accesses
390system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.002264 # mshr miss rate for overall accesses
391system.l2c.overall_mshr_miss_rate::cpu0.inst 0.019497 # mshr miss rate for overall accesses
392system.l2c.overall_mshr_miss_rate::cpu0.data 0.240912 # mshr miss rate for overall accesses
393system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.003159 # mshr miss rate for overall accesses
394system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002559 # mshr miss rate for overall accesses
395system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016188 # mshr miss rate for overall accesses
396system.l2c.overall_mshr_miss_rate::cpu1.data 0.307390 # mshr miss rate for overall accesses
397system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
398system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
399system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average ReadReq mshr miss latency
400system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40082.081640 # average ReadReq mshr miss latency
401system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average ReadReq mshr miss latency
402system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
403system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average ReadReq mshr miss latency
404system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40145.524636 # average ReadReq mshr miss latency
405system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.506205 # average UpgradeReq mshr miss latency
406system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.881281 # average UpgradeReq mshr miss latency
407system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.582011 # average SCUpgradeReq mshr miss latency
408system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.221239 # average SCUpgradeReq mshr miss latency
409system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40045.653366 # average ReadExReq mshr miss latency
410system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40117.289052 # average ReadExReq mshr miss latency
411system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
412system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
413system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
414system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
415system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
416system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
417system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
418system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
419system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
420system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
421system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency
422system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency
423system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency
424system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
425system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency
426system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency
427system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
428system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
429system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
430system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
431system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
432system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
433system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
434system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
435system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
436system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
437system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
438system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
439system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
440system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
441system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
442system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
443system.cf0.dma_write_txs 0 # Number of DMA write transactions.
444system.cpu0.dtb.inst_hits 0 # ITB inst hits
--- 91 unchanged lines hidden (view full) ---
536system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles
537system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses)
538system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses)
539system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses
540system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses
541system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses
542system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses
543system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses
544system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses
545system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses
546system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency
547system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
548system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency
549system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
550system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
551system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
552system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
553system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
554system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
555system.cpu0.icache.fast_writes 0 # number of fast writes performed
556system.cpu0.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
568system.cpu0.icache.demand_mshr_miss_latency::total 4832163500 # number of demand (read+write) MSHR miss cycles
569system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles
570system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles
571system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
572system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
573system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
574system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
575system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses
576system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses
577system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses
578system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency
579system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
580system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency
581system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
582system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
583system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
584system.cpu0.dcache.replacements 335831 # number of replacements
585system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use
586system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks.
587system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks.
588system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks.
589system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
590system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor
--- 43 unchanged lines hidden (view full) ---
634system.cpu0.dcache.LoadLockedReq_accesses::total 157222 # number of LoadLockedReq accesses(hits+misses)
635system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157159 # number of StoreCondReq accesses(hits+misses)
636system.cpu0.dcache.StoreCondReq_accesses::total 157159 # number of StoreCondReq accesses(hits+misses)
637system.cpu0.dcache.demand_accesses::cpu0.data 12319714 # number of demand (read+write) accesses
638system.cpu0.dcache.demand_accesses::total 12319714 # number of demand (read+write) accesses
639system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses
640system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses
641system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses
642system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses
643system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses
644system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses
645system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses
646system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses
647system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency
648system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency
649system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency
650system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency
651system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
652system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency
653system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
654system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
655system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
656system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
657system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
658system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
659system.cpu0.dcache.fast_writes 0 # number of fast writes performed
660system.cpu0.dcache.cache_copies 0 # number of cache copies performed
--- 25 unchanged lines hidden (view full) ---
686system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles
687system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles
688system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles
689system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles
690system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles
691system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles
692system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles
693system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses
694system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses
695system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses
696system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses
697system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses
698system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses
699system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency
700system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency
701system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency
702system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency
703system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
704system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency
705system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
706system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
707system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
708system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
709system.cpu1.dtb.inst_hits 0 # ITB inst hits
710system.cpu1.dtb.inst_misses 0 # ITB inst misses
711system.cpu1.dtb.read_hits 8313009 # DTB read hits
712system.cpu1.dtb.read_misses 3663 # DTB read misses
713system.cpu1.dtb.write_hits 5829499 # DTB write hits
714system.cpu1.dtb.write_misses 1439 # DTB write misses
715system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
--- 85 unchanged lines hidden (view full) ---
801system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles
802system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses)
803system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses)
804system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses
805system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses
806system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses
807system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses
808system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses
809system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses
810system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses
811system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency
812system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
813system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency
814system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
815system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
816system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
817system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
818system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
819system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
820system.cpu1.icache.fast_writes 0 # number of fast writes performed
821system.cpu1.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
833system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles
834system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles
835system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles
836system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
837system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
838system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
839system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
840system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses
841system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses
842system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses
843system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency
844system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
845system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency
846system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
847system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
848system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
849system.cpu1.dcache.replacements 294642 # number of replacements
850system.cpu1.dcache.tagsinuse 457.752328 # Cycle average of tags in use
851system.cpu1.dcache.total_refs 11964721 # Total number of references to valid blocks.
852system.cpu1.dcache.sampled_refs 295088 # Sample count of references to valid blocks.
853system.cpu1.dcache.avg_refs 40.546281 # Average number of references to valid blocks.
854system.cpu1.dcache.warmup_cycle 89831748000 # Cycle when the warmup percentage was hit.
855system.cpu1.dcache.occ_blocks::cpu1.data 457.752328 # Average occupied blocks per requestor
--- 43 unchanged lines hidden (view full) ---
899system.cpu1.dcache.LoadLockedReq_accesses::total 92899 # number of LoadLockedReq accesses(hits+misses)
900system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92826 # number of StoreCondReq accesses(hits+misses)
901system.cpu1.dcache.StoreCondReq_accesses::total 92826 # number of StoreCondReq accesses(hits+misses)
902system.cpu1.dcache.demand_accesses::cpu1.data 12098117 # number of demand (read+write) accesses
903system.cpu1.dcache.demand_accesses::total 12098117 # number of demand (read+write) accesses
904system.cpu1.dcache.overall_accesses::cpu1.data 12098117 # number of overall (read+write) accesses
905system.cpu1.dcache.overall_accesses::total 12098117 # number of overall (read+write) accesses
906system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.024175 # miss rate for ReadReq accesses
907system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030209 # miss rate for WriteReq accesses
908system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119732 # miss rate for LoadLockedReq accesses
909system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104658 # miss rate for StoreCondReq accesses
910system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026659 # miss rate for demand accesses
911system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026659 # miss rate for overall accesses
912system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14503.858110 # average ReadReq miss latency
913system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35153.999575 # average WriteReq miss latency
914system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11199.721298 # average LoadLockedReq miss latency
915system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7579.207411 # average StoreCondReq miss latency
916system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
917system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency
918system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
919system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
920system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
921system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
922system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
923system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
924system.cpu1.dcache.fast_writes 0 # number of fast writes performed
925system.cpu1.dcache.cache_copies 0 # number of cache copies performed
--- 25 unchanged lines hidden (view full) ---
951system.cpu1.dcache.overall_mshr_miss_latency::total 6816193500 # number of overall MSHR miss cycles
952system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136553272000 # number of ReadReq MSHR uncacheable cycles
953system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136553272000 # number of ReadReq MSHR uncacheable cycles
954system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39714562000 # number of WriteReq MSHR uncacheable cycles
955system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39714562000 # number of WriteReq MSHR uncacheable cycles
956system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176267834000 # number of overall MSHR uncacheable cycles
957system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles
958system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses
959system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses
960system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses
961system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses
962system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses
963system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses
964system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency
965system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency
966system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency
967system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency
968system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
969system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency
970system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
971system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
972system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
973system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
974system.iocache.replacements 0 # number of replacements
975system.iocache.tagsinuse 0 # Cycle average of tags in use
976system.iocache.total_refs 0 # Total number of references to valid blocks.
977system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
978system.iocache.avg_refs nan # Average number of references to valid blocks.
979system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
980system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
--- 4 unchanged lines hidden (view full) ---
985system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
986system.iocache.fast_writes 0 # number of fast writes performed
987system.iocache.cache_copies 0 # number of cache copies performed
988system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles
989system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles
990system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles
991system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles
992system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
993system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
994system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
995
996---------- End Simulation Statistics ----------