1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.869797 # Number of seconds simulated
4sim_ticks 2869796829000 # Number of ticks simulated
5final_tick 2869796829000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 478807 # Simulator instruction rate (inst/s)
8host_op_rate 579136 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 10450673539 # Simulator tick rate (ticks/s)
10host_mem_usage 612484 # Number of bytes of host memory used
11host_seconds 274.60 # Real time elapsed on the host
12sim_insts 131482259 # Number of instructions simulated
13sim_ops 159033076 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 1151908 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 1242084 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu0.l2cache.prefetcher 8334784 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 147092 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 510612 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.l2cache.prefetcher 354880 # Number of bytes read from this memory
25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
26system.physmem.bytes_read::total 11742896 # Number of bytes read from this memory
27system.physmem.bytes_inst_read::cpu0.inst 1151908 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu1.inst 147092 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 1299000 # Number of instructions bytes read from this memory
30system.physmem.bytes_written::writebacks 8345408 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
33system.physmem.bytes_written::total 8362972 # Number of bytes written to this memory
34system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.inst 26452 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.data 19927 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.l2cache.prefetcher 130231 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.inst 2453 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.data 7999 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.l2cache.prefetcher 5545 # Number of read requests responded to by this memory
42system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
43system.physmem.num_reads::total 192631 # Number of read requests responded to by this memory
44system.physmem.num_writes::writebacks 130397 # Number of write requests responded to by this memory
45system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
46system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
47system.physmem.num_writes::total 134788 # Number of write requests responded to by this memory
48system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.inst 401390 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.data 432813 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.l2cache.prefetcher 2904312 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.inst 51255 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.data 177926 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.l2cache.prefetcher 123660 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::total 4091891 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_inst_read::cpu0.inst 401390 # Instruction read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::cpu1.inst 51255 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_inst_read::total 452645 # Instruction read bandwidth from this memory (bytes/s)
61system.physmem.bw_write::writebacks 2908014 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_write::total 2914134 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_total::writebacks 2908014 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.inst 401390 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.data 438919 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu0.l2cache.prefetcher 2904312 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.inst 51255 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu1.data 177940 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu1.l2cache.prefetcher 123660 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::total 7006025 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.readReqs 192631 # Number of read requests accepted
77system.physmem.writeReqs 134788 # Number of write requests accepted
78system.physmem.readBursts 192631 # Number of DRAM read bursts, including those serviced by the write queue
79system.physmem.writeBursts 134788 # Number of DRAM write bursts, including those merged in the write queue
80system.physmem.bytesReadDRAM 12319616 # Total number of bytes read from DRAM
81system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
82system.physmem.bytesWritten 8376000 # Total number of bytes written to DRAM
83system.physmem.bytesReadSys 11742896 # Total read bytes from the system interface side
84system.physmem.bytesWrittenSys 8362972 # Total written bytes from the system interface side
85system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
86system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
87system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
88system.physmem.perBankRdBursts::0 11574 # Per bank write bursts
89system.physmem.perBankRdBursts::1 11705 # Per bank write bursts
90system.physmem.perBankRdBursts::2 12139 # Per bank write bursts
91system.physmem.perBankRdBursts::3 12297 # Per bank write bursts
92system.physmem.perBankRdBursts::4 20811 # Per bank write bursts
93system.physmem.perBankRdBursts::5 12493 # Per bank write bursts
94system.physmem.perBankRdBursts::6 11636 # Per bank write bursts
95system.physmem.perBankRdBursts::7 11627 # Per bank write bursts
96system.physmem.perBankRdBursts::8 11518 # Per bank write bursts
97system.physmem.perBankRdBursts::9 11803 # Per bank write bursts
98system.physmem.perBankRdBursts::10 10854 # Per bank write bursts
99system.physmem.perBankRdBursts::11 10225 # Per bank write bursts
100system.physmem.perBankRdBursts::12 10900 # Per bank write bursts
101system.physmem.perBankRdBursts::13 11460 # Per bank write bursts
102system.physmem.perBankRdBursts::14 10649 # Per bank write bursts
103system.physmem.perBankRdBursts::15 10803 # Per bank write bursts
104system.physmem.perBankWrBursts::0 8359 # Per bank write bursts
105system.physmem.perBankWrBursts::1 8644 # Per bank write bursts
106system.physmem.perBankWrBursts::2 9057 # Per bank write bursts
107system.physmem.perBankWrBursts::3 8858 # Per bank write bursts
108system.physmem.perBankWrBursts::4 8408 # Per bank write bursts
109system.physmem.perBankWrBursts::5 8900 # Per bank write bursts
110system.physmem.perBankWrBursts::6 8435 # Per bank write bursts
111system.physmem.perBankWrBursts::7 8166 # Per bank write bursts
112system.physmem.perBankWrBursts::8 8021 # Per bank write bursts
113system.physmem.perBankWrBursts::9 8475 # Per bank write bursts
114system.physmem.perBankWrBursts::10 7798 # Per bank write bursts
115system.physmem.perBankWrBursts::11 7415 # Per bank write bursts
116system.physmem.perBankWrBursts::12 7820 # Per bank write bursts
117system.physmem.perBankWrBursts::13 7815 # Per bank write bursts
118system.physmem.perBankWrBursts::14 7421 # Per bank write bursts
119system.physmem.perBankWrBursts::15 7283 # Per bank write bursts
120system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
121system.physmem.numWrRetry 25 # Number of times write queue was full causing retry
122system.physmem.totGap 2869796310500 # Total gap between requests
123system.physmem.readPktSize::0 0 # Read request sizes (log2)
124system.physmem.readPktSize::1 0 # Read request sizes (log2)
125system.physmem.readPktSize::2 9732 # Read request sizes (log2)
126system.physmem.readPktSize::3 28 # Read request sizes (log2)
127system.physmem.readPktSize::4 0 # Read request sizes (log2)
128system.physmem.readPktSize::5 0 # Read request sizes (log2)
129system.physmem.readPktSize::6 182871 # Read request sizes (log2)
130system.physmem.writePktSize::0 0 # Write request sizes (log2)
131system.physmem.writePktSize::1 0 # Write request sizes (log2)
132system.physmem.writePktSize::2 4391 # Write request sizes (log2)
133system.physmem.writePktSize::3 0 # Write request sizes (log2)
134system.physmem.writePktSize::4 0 # Write request sizes (log2)
135system.physmem.writePktSize::5 0 # Write request sizes (log2)
136system.physmem.writePktSize::6 130397 # Write request sizes (log2)
137system.physmem.rdQLenPdf::0 135454 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::1 15340 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::2 9792 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::3 8297 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::4 6685 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::5 5269 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::6 4441 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::7 3740 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::8 3238 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::9 102 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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176system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::15 2678 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::16 3664 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::17 4461 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::18 5463 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::19 6253 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::20 6327 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::21 7016 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::22 7318 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::23 8250 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::24 8142 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::25 9382 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::27 8225 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::28 8155 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::29 9383 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::30 7846 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::31 7230 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::32 7002 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::33 418 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::34 384 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::35 322 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::36 221 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::37 168 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::38 161 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::39 150 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::42 166 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::43 133 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::44 148 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::46 147 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::50 103 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::51 132 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::52 135 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::54 98 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::55 83 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::57 78 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::61 44 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::63 97 # What write queue length does an incoming req see
233system.physmem.bytesPerActivate::samples 85101 # Bytes accessed per row activation
234system.physmem.bytesPerActivate::mean 243.188118 # Bytes accessed per row activation
235system.physmem.bytesPerActivate::gmean 136.988063 # Bytes accessed per row activation
236system.physmem.bytesPerActivate::stdev 305.573889 # Bytes accessed per row activation
237system.physmem.bytesPerActivate::0-127 45210 53.13% 53.13% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::128-255 16886 19.84% 72.97% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::256-383 5688 6.68% 79.65% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::384-511 3460 4.07% 83.72% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::512-639 2293 2.69% 86.41% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::640-767 1445 1.70% 88.11% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::768-895 997 1.17% 89.28% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::896-1023 929 1.09% 90.37% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::1024-1151 8193 9.63% 100.00% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::total 85101 # Bytes accessed per row activation
247system.physmem.rdPerTurnAround::samples 6403 # Reads before turning the bus around for writes
248system.physmem.rdPerTurnAround::mean 30.062939 # Reads before turning the bus around for writes
249system.physmem.rdPerTurnAround::stdev 590.633185 # Reads before turning the bus around for writes
250system.physmem.rdPerTurnAround::0-2047 6402 99.98% 99.98% # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::total 6403 # Reads before turning the bus around for writes
253system.physmem.wrPerTurnAround::samples 6403 # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::mean 20.439638 # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::gmean 18.792302 # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::stdev 13.006159 # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::16-19 5407 84.44% 84.44% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::20-23 293 4.58% 89.02% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::24-27 63 0.98% 90.00% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::28-31 46 0.72% 90.72% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::32-35 252 3.94% 94.66% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::36-39 29 0.45% 95.11% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::40-43 22 0.34% 95.46% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::44-47 17 0.27% 95.72% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::48-51 14 0.22% 95.94% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::52-55 8 0.12% 96.06% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::56-59 5 0.08% 96.14% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::60-63 12 0.19% 96.33% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::64-67 163 2.55% 98.88% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::68-71 4 0.06% 98.94% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::72-75 10 0.16% 99.09% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::76-79 4 0.06% 99.16% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::80-83 10 0.16% 99.31% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::84-87 2 0.03% 99.34% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::88-91 1 0.02% 99.36% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::92-95 4 0.06% 99.42% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::96-99 4 0.06% 99.48% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::100-103 2 0.03% 99.52% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::104-107 3 0.05% 99.56% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::108-111 5 0.08% 99.64% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::124-127 1 0.02% 99.66% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::128-131 9 0.14% 99.80% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::132-135 1 0.02% 99.81% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::140-143 3 0.05% 99.86% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::144-147 2 0.03% 99.89% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::148-151 1 0.02% 99.91% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::156-159 2 0.03% 99.94% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::160-163 1 0.02% 99.95% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::172-175 1 0.02% 99.97% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::180-183 2 0.03% 100.00% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::total 6403 # Writes before turning the bus around for reads
292system.physmem.totQLat 4388531068 # Total ticks spent queuing
293system.physmem.totMemAccLat 7997793568 # Total ticks spent from burst creation until serviced by the DRAM
294system.physmem.totBusLat 962470000 # Total ticks spent in databus transfers
295system.physmem.avgQLat 22798.27 # Average queueing delay per DRAM burst
296system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
297system.physmem.avgMemAccLat 41548.27 # Average memory access latency per DRAM burst
298system.physmem.avgRdBW 4.29 # Average DRAM read bandwidth in MiByte/s
299system.physmem.avgWrBW 2.92 # Average achieved write bandwidth in MiByte/s
300system.physmem.avgRdBWSys 4.09 # Average system read bandwidth in MiByte/s
301system.physmem.avgWrBWSys 2.91 # Average system write bandwidth in MiByte/s
302system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
303system.physmem.busUtil 0.06 # Data bus utilization in percentage
304system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
305system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
306system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing
307system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing
308system.physmem.readRowHits 160943 # Number of row buffer hits during reads
309system.physmem.writeRowHits 77324 # Number of row buffer hits during writes
310system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads
311system.physmem.writeRowHitRate 59.07 # Row buffer hit rate for writes
312system.physmem.avgGap 8764904.63 # Average gap between requests
313system.physmem.pageHitRate 73.68 # Row buffer hit rate, read and write combined
314system.physmem_0.actEnergy 343133280 # Energy for activate commands per rank (pJ)
315system.physmem_0.preEnergy 187225500 # Energy for precharge commands per rank (pJ)
316system.physmem_0.readEnergy 813391800 # Energy for read commands per rank (pJ)
317system.physmem_0.writeEnergy 445998960 # Energy for write commands per rank (pJ)
318system.physmem_0.refreshEnergy 187440976320 # Energy for refresh commands per rank (pJ)
319system.physmem_0.actBackEnergy 84650934555 # Energy for active background per rank (pJ)
320system.physmem_0.preBackEnergy 1647621183000 # Energy for precharge background per rank (pJ)
321system.physmem_0.totalEnergy 1921502843415 # Total energy per rank (pJ)
322system.physmem_0.averagePower 669.561249 # Core power per rank (mW)
323system.physmem_0.memoryStateTime::IDLE 2740835391788 # Time in different power states
324system.physmem_0.memoryStateTime::REF 95828720000 # Time in different power states
325system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
326system.physmem_0.memoryStateTime::ACT 33132603712 # Time in different power states
327system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
328system.physmem_1.actEnergy 300230280 # Energy for activate commands per rank (pJ)
329system.physmem_1.preEnergy 163816125 # Energy for precharge commands per rank (pJ)
330system.physmem_1.readEnergy 688053600 # Energy for read commands per rank (pJ)
331system.physmem_1.writeEnergy 402071040 # Energy for write commands per rank (pJ)
332system.physmem_1.refreshEnergy 187440976320 # Energy for refresh commands per rank (pJ)
333system.physmem_1.actBackEnergy 83039782815 # Energy for active background per rank (pJ)
334system.physmem_1.preBackEnergy 1649034474000 # Energy for precharge background per rank (pJ)
335system.physmem_1.totalEnergy 1921069404180 # Total energy per rank (pJ)
336system.physmem_1.averagePower 669.410214 # Core power per rank (mW)
337system.physmem_1.memoryStateTime::IDLE 2743194226190 # Time in different power states
338system.physmem_1.memoryStateTime::REF 95828720000 # Time in different power states
339system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
340system.physmem_1.memoryStateTime::ACT 30771048810 # Time in different power states
341system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
342system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
343system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
344system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
345system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
346system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
347system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
348system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
349system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
350system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
351system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
352system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
353system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
354system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
355system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
356system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
357system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
358system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
359system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
360system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
361system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
362system.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
363system.bridge.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
364system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
365system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
366system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
367system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
368system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
369system.cf0.dma_write_txs 631 # Number of DMA write transactions.
370system.cpu_clk_domain.clock 500 # Clock period in ticks
371system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
372system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

393system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
394system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
395system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
396system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
397system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
398system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
399system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
400system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
401system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
402system.cpu0.dtb.walker.walks 7605 # Table walker walks requested
403system.cpu0.dtb.walker.walksShort 7605 # Table walker walks initiated with short descriptors
404system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1343 # Level at which table walker walks with short descriptors terminate
405system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate
406system.cpu0.dtb.walker.walkWaitTime::samples 7605 # Table walker wait (enqueue to first request) latency
407system.cpu0.dtb.walker.walkWaitTime::0 7605 100.00% 100.00% # Table walker wait (enqueue to first request) latency
408system.cpu0.dtb.walker.walkWaitTime::total 7605 # Table walker wait (enqueue to first request) latency
409system.cpu0.dtb.walker.walkCompletionTime::samples 6211 # Table walker service (enqueue to completion) latency
410system.cpu0.dtb.walker.walkCompletionTime::mean 12321.365320 # Table walker service (enqueue to completion) latency
411system.cpu0.dtb.walker.walkCompletionTime::gmean 11473.330493 # Table walker service (enqueue to completion) latency
412system.cpu0.dtb.walker.walkCompletionTime::stdev 5604.476225 # Table walker service (enqueue to completion) latency
413system.cpu0.dtb.walker.walkCompletionTime::0-16383 5759 92.72% 92.72% # Table walker service (enqueue to completion) latency
414system.cpu0.dtb.walker.walkCompletionTime::16384-32767 412 6.63% 99.36% # Table walker service (enqueue to completion) latency
415system.cpu0.dtb.walker.walkCompletionTime::32768-49151 31 0.50% 99.86% # Table walker service (enqueue to completion) latency
416system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.92% # Table walker service (enqueue to completion) latency
417system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.95% # Table walker service (enqueue to completion) latency
418system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency
419system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
420system.cpu0.dtb.walker.walkCompletionTime::total 6211 # Table walker service (enqueue to completion) latency
421system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution
422system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution
423system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution
424system.cpu0.dtb.walker.walkPageSizes::4K 4907 79.00% 79.00% # Table walker page sizes translated
425system.cpu0.dtb.walker.walkPageSizes::1M 1304 21.00% 100.00% # Table walker page sizes translated
426system.cpu0.dtb.walker.walkPageSizes::total 6211 # Table walker page sizes translated
427system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7605 # Table walker requests started/completed, data/inst
428system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
429system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7605 # Table walker requests started/completed, data/inst
430system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6211 # Table walker requests started/completed, data/inst
431system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
432system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6211 # Table walker requests started/completed, data/inst
433system.cpu0.dtb.walker.walkRequestOrigin::total 13816 # Table walker requests started/completed, data/inst
434system.cpu0.dtb.inst_hits 0 # ITB inst hits
435system.cpu0.dtb.inst_misses 0 # ITB inst misses
436system.cpu0.dtb.read_hits 22785353 # DTB read hits
437system.cpu0.dtb.read_misses 6506 # DTB read misses
438system.cpu0.dtb.write_hits 17536845 # DTB write hits
439system.cpu0.dtb.write_misses 1099 # DTB write misses
440system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
441system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
442system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
443system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
444system.cpu0.dtb.flush_entries 3343 # Number of entries that have been flushed from TLB
445system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
446system.cpu0.dtb.prefetch_faults 1756 # Number of TLB faults due to prefetch
447system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
448system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
449system.cpu0.dtb.read_accesses 22791859 # DTB read accesses
450system.cpu0.dtb.write_accesses 17537944 # DTB write accesses
451system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
452system.cpu0.dtb.hits 40322198 # DTB hits
453system.cpu0.dtb.misses 7605 # DTB misses
454system.cpu0.dtb.accesses 40329803 # DTB accesses
455system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
456system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
460system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
461system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
462system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
463system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

477system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
478system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
479system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
480system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
481system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
482system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
483system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
484system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
485system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
486system.cpu0.itb.walker.walks 3349 # Table walker walks requested
487system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors
488system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate
489system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate
490system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency
491system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency
492system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency
493system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency
494system.cpu0.itb.walker.walkCompletionTime::mean 12840.762966 # Table walker service (enqueue to completion) latency
495system.cpu0.itb.walker.walkCompletionTime::gmean 12002.591700 # Table walker service (enqueue to completion) latency
496system.cpu0.itb.walker.walkCompletionTime::stdev 5837.643760 # Table walker service (enqueue to completion) latency
497system.cpu0.itb.walker.walkCompletionTime::0-8191 347 14.87% 14.87% # Table walker service (enqueue to completion) latency
498system.cpu0.itb.walker.walkCompletionTime::8192-16383 1703 73.00% 87.87% # Table walker service (enqueue to completion) latency
499system.cpu0.itb.walker.walkCompletionTime::16384-24575 210 9.00% 96.87% # Table walker service (enqueue to completion) latency
500system.cpu0.itb.walker.walkCompletionTime::24576-32767 26 1.11% 97.99% # Table walker service (enqueue to completion) latency
501system.cpu0.itb.walker.walkCompletionTime::32768-40959 42 1.80% 99.79% # Table walker service (enqueue to completion) latency
502system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.09% 99.87% # Table walker service (enqueue to completion) latency
503system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.91% # Table walker service (enqueue to completion) latency
504system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
505system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
506system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency
507system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution
508system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution
509system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution
510system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated
511system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated
512system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated
513system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
514system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst
515system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst
516system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
517system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst
518system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst
519system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst
520system.cpu0.itb.inst_hits 108479195 # ITB inst hits
521system.cpu0.itb.inst_misses 3349 # ITB inst misses
522system.cpu0.itb.read_hits 0 # DTB read hits
523system.cpu0.itb.read_misses 0 # DTB read misses
524system.cpu0.itb.write_hits 0 # DTB write hits
525system.cpu0.itb.write_misses 0 # DTB write misses
526system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
527system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
528system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
529system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
530system.cpu0.itb.flush_entries 2087 # Number of entries that have been flushed from TLB
531system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
532system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
533system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
534system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
535system.cpu0.itb.read_accesses 0 # DTB read accesses
536system.cpu0.itb.write_accesses 0 # DTB write accesses
537system.cpu0.itb.inst_accesses 108482544 # ITB inst accesses
538system.cpu0.itb.hits 108479195 # DTB hits
539system.cpu0.itb.misses 3349 # DTB misses
540system.cpu0.itb.accesses 108482544 # DTB accesses
541system.cpu0.numPwrStateTransitions 3748 # Number of power state transitions
542system.cpu0.pwrStateClkGateDist::samples 1874 # Distribution of time spent in the clock gated state
543system.cpu0.pwrStateClkGateDist::mean 1464520585.209178 # Distribution of time spent in the clock gated state
544system.cpu0.pwrStateClkGateDist::stdev 23650117166.731750 # Distribution of time spent in the clock gated state
545system.cpu0.pwrStateClkGateDist::underflows 1082 57.74% 57.74% # Distribution of time spent in the clock gated state
546system.cpu0.pwrStateClkGateDist::1000-5e+10 787 42.00% 99.73% # Distribution of time spent in the clock gated state
547system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.79% # Distribution of time spent in the clock gated state
548system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.21% 100.00% # Distribution of time spent in the clock gated state
549system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
550system.cpu0.pwrStateClkGateDist::max_value 499966342824 # Distribution of time spent in the clock gated state
551system.cpu0.pwrStateClkGateDist::total 1874 # Distribution of time spent in the clock gated state
552system.cpu0.pwrStateResidencyTicks::ON 125285252318 # Cumulative time (in ticks) in various power states
553system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744511576682 # Cumulative time (in ticks) in various power states
554system.cpu0.numCycles 5739593658 # number of cpu cycles simulated
555system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
556system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
557system.cpu0.kern.inst.arm 0 # number of arm instructions executed
558system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed
559system.cpu0.committedInsts 105397426 # Number of instructions committed
560system.cpu0.committedOps 127063433 # Number of ops (including micro ops) committed
561system.cpu0.num_int_alu_accesses 112192231 # Number of integer alu accesses
562system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses
563system.cpu0.num_func_calls 10407708 # number of times a function call or return occured
564system.cpu0.num_conditional_control_insts 14566669 # number of instructions that are conditional controls
565system.cpu0.num_int_insts 112192231 # number of integer instructions
566system.cpu0.num_fp_insts 9820 # number of float instructions
567system.cpu0.num_int_register_reads 204833184 # number of times the integer registers were read
568system.cpu0.num_int_register_writes 77435370 # number of times the integer registers were written
569system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read
570system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
571system.cpu0.num_cc_register_reads 459130085 # number of times the CC registers were read
572system.cpu0.num_cc_register_writes 48875384 # number of times the CC registers were written
573system.cpu0.num_mem_refs 41457196 # number of memory refs
574system.cpu0.num_load_insts 23036367 # Number of load instructions
575system.cpu0.num_store_insts 18420829 # Number of store instructions
576system.cpu0.num_idle_cycles 5489023153.362087 # Number of idle cycles
577system.cpu0.num_busy_cycles 250570504.637913 # Number of busy cycles
578system.cpu0.not_idle_fraction 0.043656 # Percentage of non-idle cycles
579system.cpu0.idle_fraction 0.956344 # Percentage of idle cycles
580system.cpu0.Branches 25689353 # Number of branches fetched
581system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
582system.cpu0.op_class::IntAlu 88685820 68.09% 68.09% # Class of executed instruction
583system.cpu0.op_class::IntMult 91693 0.07% 68.16% # Class of executed instruction
584system.cpu0.op_class::IntDiv 0 0.00% 68.16% # Class of executed instruction
585system.cpu0.op_class::FloatAdd 0 0.00% 68.16% # Class of executed instruction
586system.cpu0.op_class::FloatCmp 0 0.00% 68.16% # Class of executed instruction
587system.cpu0.op_class::FloatCvt 0 0.00% 68.16% # Class of executed instruction
588system.cpu0.op_class::FloatMult 0 0.00% 68.16% # Class of executed instruction
589system.cpu0.op_class::FloatDiv 0 0.00% 68.16% # Class of executed instruction
590system.cpu0.op_class::FloatSqrt 0 0.00% 68.16% # Class of executed instruction
591system.cpu0.op_class::SimdAdd 0 0.00% 68.16% # Class of executed instruction
592system.cpu0.op_class::SimdAddAcc 0 0.00% 68.16% # Class of executed instruction
593system.cpu0.op_class::SimdAlu 0 0.00% 68.16% # Class of executed instruction
594system.cpu0.op_class::SimdCmp 0 0.00% 68.16% # Class of executed instruction
595system.cpu0.op_class::SimdCvt 0 0.00% 68.16% # Class of executed instruction
596system.cpu0.op_class::SimdMisc 0 0.00% 68.16% # Class of executed instruction
597system.cpu0.op_class::SimdMult 0 0.00% 68.16% # Class of executed instruction
598system.cpu0.op_class::SimdMultAcc 0 0.00% 68.16% # Class of executed instruction
599system.cpu0.op_class::SimdShift 0 0.00% 68.16% # Class of executed instruction
600system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.16% # Class of executed instruction
601system.cpu0.op_class::SimdSqrt 0 0.00% 68.16% # Class of executed instruction
602system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.16% # Class of executed instruction
603system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.16% # Class of executed instruction
604system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.16% # Class of executed instruction
605system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.16% # Class of executed instruction
606system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.16% # Class of executed instruction
607system.cpu0.op_class::SimdFloatMisc 8209 0.01% 68.17% # Class of executed instruction
608system.cpu0.op_class::SimdFloatMult 0 0.00% 68.17% # Class of executed instruction
609system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.17% # Class of executed instruction
610system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.17% # Class of executed instruction
611system.cpu0.op_class::MemRead 23036367 17.69% 85.86% # Class of executed instruction
612system.cpu0.op_class::MemWrite 18420829 14.14% 100.00% # Class of executed instruction
613system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
614system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
615system.cpu0.op_class::total 130245191 # Class of executed instruction
616system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
617system.cpu0.dcache.tags.replacements 690306 # number of replacements
618system.cpu0.dcache.tags.tagsinuse 490.313655 # Cycle average of tags in use
619system.cpu0.dcache.tags.total_refs 39473136 # Total number of references to valid blocks.
620system.cpu0.dcache.tags.sampled_refs 690818 # Sample count of references to valid blocks.
621system.cpu0.dcache.tags.avg_refs 57.139704 # Average number of references to valid blocks.
622system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit.
623system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.313655 # Average occupied blocks per requestor
624system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957644 # Average percentage of cache occupancy
625system.cpu0.dcache.tags.occ_percent::total 0.957644 # Average percentage of cache occupancy
626system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
627system.cpu0.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
628system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
629system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
630system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
631system.cpu0.dcache.tags.tag_accesses 81317769 # Number of tag accesses
632system.cpu0.dcache.tags.data_accesses 81317769 # Number of data accesses
633system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
634system.cpu0.dcache.ReadReq_hits::cpu0.data 21536394 # number of ReadReq hits
635system.cpu0.dcache.ReadReq_hits::total 21536394 # number of ReadReq hits
636system.cpu0.dcache.WriteReq_hits::cpu0.data 16814376 # number of WriteReq hits
637system.cpu0.dcache.WriteReq_hits::total 16814376 # number of WriteReq hits
638system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319053 # number of SoftPFReq hits
639system.cpu0.dcache.SoftPFReq_hits::total 319053 # number of SoftPFReq hits
640system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365550 # number of LoadLockedReq hits
641system.cpu0.dcache.LoadLockedReq_hits::total 365550 # number of LoadLockedReq hits
642system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362389 # number of StoreCondReq hits
643system.cpu0.dcache.StoreCondReq_hits::total 362389 # number of StoreCondReq hits
644system.cpu0.dcache.demand_hits::cpu0.data 38350770 # number of demand (read+write) hits
645system.cpu0.dcache.demand_hits::total 38350770 # number of demand (read+write) hits
646system.cpu0.dcache.overall_hits::cpu0.data 38669823 # number of overall hits
647system.cpu0.dcache.overall_hits::total 38669823 # number of overall hits
648system.cpu0.dcache.ReadReq_misses::cpu0.data 394644 # number of ReadReq misses
649system.cpu0.dcache.ReadReq_misses::total 394644 # number of ReadReq misses
650system.cpu0.dcache.WriteReq_misses::cpu0.data 324668 # number of WriteReq misses
651system.cpu0.dcache.WriteReq_misses::total 324668 # number of WriteReq misses
652system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127577 # number of SoftPFReq misses
653system.cpu0.dcache.SoftPFReq_misses::total 127577 # number of SoftPFReq misses
654system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21580 # number of LoadLockedReq misses
655system.cpu0.dcache.LoadLockedReq_misses::total 21580 # number of LoadLockedReq misses
656system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19821 # number of StoreCondReq misses
657system.cpu0.dcache.StoreCondReq_misses::total 19821 # number of StoreCondReq misses
658system.cpu0.dcache.demand_misses::cpu0.data 719312 # number of demand (read+write) misses
659system.cpu0.dcache.demand_misses::total 719312 # number of demand (read+write) misses
660system.cpu0.dcache.overall_misses::cpu0.data 846889 # number of overall misses
661system.cpu0.dcache.overall_misses::total 846889 # number of overall misses
662system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5059230000 # number of ReadReq miss cycles
663system.cpu0.dcache.ReadReq_miss_latency::total 5059230000 # number of ReadReq miss cycles
664system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5720917500 # number of WriteReq miss cycles
665system.cpu0.dcache.WriteReq_miss_latency::total 5720917500 # number of WriteReq miss cycles
666system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 328019500 # number of LoadLockedReq miss cycles
667system.cpu0.dcache.LoadLockedReq_miss_latency::total 328019500 # number of LoadLockedReq miss cycles
668system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473718500 # number of StoreCondReq miss cycles
669system.cpu0.dcache.StoreCondReq_miss_latency::total 473718500 # number of StoreCondReq miss cycles
670system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1421500 # number of StoreCondFailReq miss cycles
671system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1421500 # number of StoreCondFailReq miss cycles
672system.cpu0.dcache.demand_miss_latency::cpu0.data 10780147500 # number of demand (read+write) miss cycles
673system.cpu0.dcache.demand_miss_latency::total 10780147500 # number of demand (read+write) miss cycles
674system.cpu0.dcache.overall_miss_latency::cpu0.data 10780147500 # number of overall miss cycles
675system.cpu0.dcache.overall_miss_latency::total 10780147500 # number of overall miss cycles
676system.cpu0.dcache.ReadReq_accesses::cpu0.data 21931038 # number of ReadReq accesses(hits+misses)
677system.cpu0.dcache.ReadReq_accesses::total 21931038 # number of ReadReq accesses(hits+misses)
678system.cpu0.dcache.WriteReq_accesses::cpu0.data 17139044 # number of WriteReq accesses(hits+misses)
679system.cpu0.dcache.WriteReq_accesses::total 17139044 # number of WriteReq accesses(hits+misses)
680system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446630 # number of SoftPFReq accesses(hits+misses)
681system.cpu0.dcache.SoftPFReq_accesses::total 446630 # number of SoftPFReq accesses(hits+misses)
682system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387130 # number of LoadLockedReq accesses(hits+misses)
683system.cpu0.dcache.LoadLockedReq_accesses::total 387130 # number of LoadLockedReq accesses(hits+misses)
684system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382210 # number of StoreCondReq accesses(hits+misses)
685system.cpu0.dcache.StoreCondReq_accesses::total 382210 # number of StoreCondReq accesses(hits+misses)
686system.cpu0.dcache.demand_accesses::cpu0.data 39070082 # number of demand (read+write) accesses
687system.cpu0.dcache.demand_accesses::total 39070082 # number of demand (read+write) accesses
688system.cpu0.dcache.overall_accesses::cpu0.data 39516712 # number of overall (read+write) accesses
689system.cpu0.dcache.overall_accesses::total 39516712 # number of overall (read+write) accesses
690system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017995 # miss rate for ReadReq accesses
691system.cpu0.dcache.ReadReq_miss_rate::total 0.017995 # miss rate for ReadReq accesses
692system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018943 # miss rate for WriteReq accesses
693system.cpu0.dcache.WriteReq_miss_rate::total 0.018943 # miss rate for WriteReq accesses
694system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285644 # miss rate for SoftPFReq accesses
695system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285644 # miss rate for SoftPFReq accesses
696system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055744 # miss rate for LoadLockedReq accesses
697system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055744 # miss rate for LoadLockedReq accesses
698system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051859 # miss rate for StoreCondReq accesses
699system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051859 # miss rate for StoreCondReq accesses
700system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018411 # miss rate for demand accesses
701system.cpu0.dcache.demand_miss_rate::total 0.018411 # miss rate for demand accesses
702system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021431 # miss rate for overall accesses
703system.cpu0.dcache.overall_miss_rate::total 0.021431 # miss rate for overall accesses
704system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12819.731201 # average ReadReq miss latency
705system.cpu0.dcache.ReadReq_avg_miss_latency::total 12819.731201 # average ReadReq miss latency
706system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17620.823426 # average WriteReq miss latency
707system.cpu0.dcache.WriteReq_avg_miss_latency::total 17620.823426 # average WriteReq miss latency
708system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15200.162187 # average LoadLockedReq miss latency
709system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15200.162187 # average LoadLockedReq miss latency
710system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23899.828465 # average StoreCondReq miss latency
711system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23899.828465 # average StoreCondReq miss latency
712system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
713system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
714system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14986.747753 # average overall miss latency
715system.cpu0.dcache.demand_avg_miss_latency::total 14986.747753 # average overall miss latency
716system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12729.115032 # average overall miss latency
717system.cpu0.dcache.overall_avg_miss_latency::total 12729.115032 # average overall miss latency
718system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
719system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
720system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
721system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
722system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
723system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
724system.cpu0.dcache.writebacks::writebacks 690306 # number of writebacks
725system.cpu0.dcache.writebacks::total 690306 # number of writebacks
726system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25258 # number of ReadReq MSHR hits
727system.cpu0.dcache.ReadReq_mshr_hits::total 25258 # number of ReadReq MSHR hits
728system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14953 # number of LoadLockedReq MSHR hits
729system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14953 # number of LoadLockedReq MSHR hits
730system.cpu0.dcache.demand_mshr_hits::cpu0.data 25258 # number of demand (read+write) MSHR hits
731system.cpu0.dcache.demand_mshr_hits::total 25258 # number of demand (read+write) MSHR hits
732system.cpu0.dcache.overall_mshr_hits::cpu0.data 25258 # number of overall MSHR hits
733system.cpu0.dcache.overall_mshr_hits::total 25258 # number of overall MSHR hits
734system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369386 # number of ReadReq MSHR misses
735system.cpu0.dcache.ReadReq_mshr_misses::total 369386 # number of ReadReq MSHR misses
736system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324668 # number of WriteReq MSHR misses
737system.cpu0.dcache.WriteReq_mshr_misses::total 324668 # number of WriteReq MSHR misses
738system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100493 # number of SoftPFReq MSHR misses
739system.cpu0.dcache.SoftPFReq_mshr_misses::total 100493 # number of SoftPFReq MSHR misses
740system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6627 # number of LoadLockedReq MSHR misses
741system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6627 # number of LoadLockedReq MSHR misses
742system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19821 # number of StoreCondReq MSHR misses
743system.cpu0.dcache.StoreCondReq_mshr_misses::total 19821 # number of StoreCondReq MSHR misses
744system.cpu0.dcache.demand_mshr_misses::cpu0.data 694054 # number of demand (read+write) MSHR misses
745system.cpu0.dcache.demand_mshr_misses::total 694054 # number of demand (read+write) MSHR misses
746system.cpu0.dcache.overall_mshr_misses::cpu0.data 794547 # number of overall MSHR misses
747system.cpu0.dcache.overall_mshr_misses::total 794547 # number of overall MSHR misses
748system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable
749system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21106 # number of ReadReq MSHR uncacheable
750system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable
751system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19680 # number of WriteReq MSHR uncacheable
752system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses
753system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40786 # number of overall MSHR uncacheable misses
754system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4295278500 # number of ReadReq MSHR miss cycles
755system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4295278500 # number of ReadReq MSHR miss cycles
756system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5396249500 # number of WriteReq MSHR miss cycles
757system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5396249500 # number of WriteReq MSHR miss cycles
758system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1609240500 # number of SoftPFReq MSHR miss cycles
759system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1609240500 # number of SoftPFReq MSHR miss cycles
760system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 98443000 # number of LoadLockedReq MSHR miss cycles
761system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98443000 # number of LoadLockedReq MSHR miss cycles
762system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 453938500 # number of StoreCondReq MSHR miss cycles
763system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 453938500 # number of StoreCondReq MSHR miss cycles
764system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1380500 # number of StoreCondFailReq MSHR miss cycles
765system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1380500 # number of StoreCondFailReq MSHR miss cycles
766system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9691528000 # number of demand (read+write) MSHR miss cycles
767system.cpu0.dcache.demand_mshr_miss_latency::total 9691528000 # number of demand (read+write) MSHR miss cycles
768system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11300768500 # number of overall MSHR miss cycles
769system.cpu0.dcache.overall_mshr_miss_latency::total 11300768500 # number of overall MSHR miss cycles
770system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4679128000 # number of ReadReq MSHR uncacheable cycles
771system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4679128000 # number of ReadReq MSHR uncacheable cycles
772system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4679128000 # number of overall MSHR uncacheable cycles
773system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4679128000 # number of overall MSHR uncacheable cycles
774system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016843 # mshr miss rate for ReadReq accesses
775system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016843 # mshr miss rate for ReadReq accesses
776system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018943 # mshr miss rate for WriteReq accesses
777system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses
778system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225003 # mshr miss rate for SoftPFReq accesses
779system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225003 # mshr miss rate for SoftPFReq accesses
780system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017118 # mshr miss rate for LoadLockedReq accesses
781system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017118 # mshr miss rate for LoadLockedReq accesses
782system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051859 # mshr miss rate for StoreCondReq accesses
783system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051859 # mshr miss rate for StoreCondReq accesses
784system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017764 # mshr miss rate for demand accesses
785system.cpu0.dcache.demand_mshr_miss_rate::total 0.017764 # mshr miss rate for demand accesses
786system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020107 # mshr miss rate for overall accesses
787system.cpu0.dcache.overall_mshr_miss_rate::total 0.020107 # mshr miss rate for overall accesses
788system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11628.157266 # average ReadReq mshr miss latency
789system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11628.157266 # average ReadReq mshr miss latency
790system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16620.823426 # average WriteReq mshr miss latency
791system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16620.823426 # average WriteReq mshr miss latency
792system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16013.458649 # average SoftPFReq mshr miss latency
793system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16013.458649 # average SoftPFReq mshr miss latency
794system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14854.836276 # average LoadLockedReq mshr miss latency
795system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14854.836276 # average LoadLockedReq mshr miss latency
796system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22901.896978 # average StoreCondReq mshr miss latency
797system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22901.896978 # average StoreCondReq mshr miss latency
798system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
799system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
800system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13963.651243 # average overall mshr miss latency
801system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13963.651243 # average overall mshr miss latency
802system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14222.907518 # average overall mshr miss latency
803system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14222.907518 # average overall mshr miss latency
804system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221696.579172 # average ReadReq mshr uncacheable latency
805system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221696.579172 # average ReadReq mshr uncacheable latency
806system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 114723.875840 # average overall mshr uncacheable latency
807system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 114723.875840 # average overall mshr uncacheable latency
808system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
809system.cpu0.icache.tags.replacements 1101713 # number of replacements
810system.cpu0.icache.tags.tagsinuse 511.449165 # Cycle average of tags in use
811system.cpu0.icache.tags.total_refs 107376961 # Total number of references to valid blocks.
812system.cpu0.icache.tags.sampled_refs 1102225 # Sample count of references to valid blocks.
813system.cpu0.icache.tags.avg_refs 97.418368 # Average number of references to valid blocks.
814system.cpu0.icache.tags.warmup_cycle 14058108000 # Cycle when the warmup percentage was hit.
815system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.449165 # Average occupied blocks per requestor
816system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998924 # Average percentage of cache occupancy
817system.cpu0.icache.tags.occ_percent::total 0.998924 # Average percentage of cache occupancy
818system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
819system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
820system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id
821system.cpu0.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id
822system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
823system.cpu0.icache.tags.tag_accesses 218060624 # Number of tag accesses
824system.cpu0.icache.tags.data_accesses 218060624 # Number of data accesses
825system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
826system.cpu0.icache.ReadReq_hits::cpu0.inst 107376961 # number of ReadReq hits
827system.cpu0.icache.ReadReq_hits::total 107376961 # number of ReadReq hits
828system.cpu0.icache.demand_hits::cpu0.inst 107376961 # number of demand (read+write) hits
829system.cpu0.icache.demand_hits::total 107376961 # number of demand (read+write) hits
830system.cpu0.icache.overall_hits::cpu0.inst 107376961 # number of overall hits
831system.cpu0.icache.overall_hits::total 107376961 # number of overall hits
832system.cpu0.icache.ReadReq_misses::cpu0.inst 1102234 # number of ReadReq misses
833system.cpu0.icache.ReadReq_misses::total 1102234 # number of ReadReq misses
834system.cpu0.icache.demand_misses::cpu0.inst 1102234 # number of demand (read+write) misses
835system.cpu0.icache.demand_misses::total 1102234 # number of demand (read+write) misses
836system.cpu0.icache.overall_misses::cpu0.inst 1102234 # number of overall misses
837system.cpu0.icache.overall_misses::total 1102234 # number of overall misses
838system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10984481500 # number of ReadReq miss cycles
839system.cpu0.icache.ReadReq_miss_latency::total 10984481500 # number of ReadReq miss cycles
840system.cpu0.icache.demand_miss_latency::cpu0.inst 10984481500 # number of demand (read+write) miss cycles
841system.cpu0.icache.demand_miss_latency::total 10984481500 # number of demand (read+write) miss cycles
842system.cpu0.icache.overall_miss_latency::cpu0.inst 10984481500 # number of overall miss cycles
843system.cpu0.icache.overall_miss_latency::total 10984481500 # number of overall miss cycles
844system.cpu0.icache.ReadReq_accesses::cpu0.inst 108479195 # number of ReadReq accesses(hits+misses)
845system.cpu0.icache.ReadReq_accesses::total 108479195 # number of ReadReq accesses(hits+misses)
846system.cpu0.icache.demand_accesses::cpu0.inst 108479195 # number of demand (read+write) accesses
847system.cpu0.icache.demand_accesses::total 108479195 # number of demand (read+write) accesses
848system.cpu0.icache.overall_accesses::cpu0.inst 108479195 # number of overall (read+write) accesses
849system.cpu0.icache.overall_accesses::total 108479195 # number of overall (read+write) accesses
850system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010161 # miss rate for ReadReq accesses
851system.cpu0.icache.ReadReq_miss_rate::total 0.010161 # miss rate for ReadReq accesses
852system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010161 # miss rate for demand accesses
853system.cpu0.icache.demand_miss_rate::total 0.010161 # miss rate for demand accesses
854system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010161 # miss rate for overall accesses
855system.cpu0.icache.overall_miss_rate::total 0.010161 # miss rate for overall accesses
856system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9965.652938 # average ReadReq miss latency
857system.cpu0.icache.ReadReq_avg_miss_latency::total 9965.652938 # average ReadReq miss latency
858system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9965.652938 # average overall miss latency
859system.cpu0.icache.demand_avg_miss_latency::total 9965.652938 # average overall miss latency
860system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9965.652938 # average overall miss latency
861system.cpu0.icache.overall_avg_miss_latency::total 9965.652938 # average overall miss latency
862system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
863system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
864system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
865system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
866system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
867system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
868system.cpu0.icache.writebacks::writebacks 1101713 # number of writebacks
869system.cpu0.icache.writebacks::total 1101713 # number of writebacks
870system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1102234 # number of ReadReq MSHR misses
871system.cpu0.icache.ReadReq_mshr_misses::total 1102234 # number of ReadReq MSHR misses
872system.cpu0.icache.demand_mshr_misses::cpu0.inst 1102234 # number of demand (read+write) MSHR misses
873system.cpu0.icache.demand_mshr_misses::total 1102234 # number of demand (read+write) MSHR misses
874system.cpu0.icache.overall_mshr_misses::cpu0.inst 1102234 # number of overall MSHR misses
875system.cpu0.icache.overall_mshr_misses::total 1102234 # number of overall MSHR misses
876system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
877system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
878system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
879system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
880system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10433364500 # number of ReadReq MSHR miss cycles
881system.cpu0.icache.ReadReq_mshr_miss_latency::total 10433364500 # number of ReadReq MSHR miss cycles
882system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10433364500 # number of demand (read+write) MSHR miss cycles
883system.cpu0.icache.demand_mshr_miss_latency::total 10433364500 # number of demand (read+write) MSHR miss cycles
884system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10433364500 # number of overall MSHR miss cycles
885system.cpu0.icache.overall_mshr_miss_latency::total 10433364500 # number of overall MSHR miss cycles
886system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 811416500 # number of ReadReq MSHR uncacheable cycles
887system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles
888system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles
889system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles
890system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for ReadReq accesses
891system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010161 # mshr miss rate for ReadReq accesses
892system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for demand accesses
893system.cpu0.icache.demand_mshr_miss_rate::total 0.010161 # mshr miss rate for demand accesses
894system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010161 # mshr miss rate for overall accesses
895system.cpu0.icache.overall_mshr_miss_rate::total 0.010161 # mshr miss rate for overall accesses
896system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average ReadReq mshr miss latency
897system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9465.652938 # average ReadReq mshr miss latency
898system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average overall mshr miss latency
899system.cpu0.icache.demand_avg_mshr_miss_latency::total 9465.652938 # average overall mshr miss latency
900system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9465.652938 # average overall mshr miss latency
901system.cpu0.icache.overall_avg_mshr_miss_latency::total 9465.652938 # average overall mshr miss latency
902system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency
903system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency
904system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency
905system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency
906system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
907system.cpu0.l2cache.prefetcher.num_hwpf_issued 1850136 # number of hwpf issued
908system.cpu0.l2cache.prefetcher.pfIdentified 1850170 # number of prefetch candidates identified
909system.cpu0.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue
910system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
911system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
912system.cpu0.l2cache.prefetcher.pfSpanPage 236334 # number of prefetches not generated due to page crossing
913system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
914system.cpu0.l2cache.tags.replacements 266149 # number of replacements
915system.cpu0.l2cache.tags.tagsinuse 16069.328191 # Cycle average of tags in use
916system.cpu0.l2cache.tags.total_refs 2918942 # Total number of references to valid blocks.
917system.cpu0.l2cache.tags.sampled_refs 282232 # Sample count of references to valid blocks.
918system.cpu0.l2cache.tags.avg_refs 10.342350 # Average number of references to valid blocks.
919system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
920system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.612326 # Average occupied blocks per requestor
921system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.486543 # Average occupied blocks per requestor
922system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.157051 # Average occupied blocks per requestor
923system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1554.072270 # Average occupied blocks per requestor
924system.cpu0.l2cache.tags.occ_percent::writebacks 0.885902 # Average percentage of cache occupancy
925system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
926system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy
927system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.094853 # Average percentage of cache occupancy
928system.cpu0.l2cache.tags.occ_percent::total 0.980794 # Average percentage of cache occupancy
929system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1018 # Occupied blocks per task id
930system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
931system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15059 # Occupied blocks per task id
932system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
933system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 235 # Occupied blocks per task id
934system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 358 # Occupied blocks per task id
935system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id
936system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
937system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
938system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
939system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
940system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id
941system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3210 # Occupied blocks per task id
942system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7726 # Occupied blocks per task id
943system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3842 # Occupied blocks per task id
944system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062134 # Percentage of cache occupancy per task id
945system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
946system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.919128 # Percentage of cache occupancy per task id
947system.cpu0.l2cache.tags.tag_accesses 59974635 # Number of tag accesses
948system.cpu0.l2cache.tags.data_accesses 59974635 # Number of data accesses
949system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
950system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 9773 # number of ReadReq hits
951system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4523 # number of ReadReq hits
952system.cpu0.l2cache.ReadReq_hits::total 14296 # number of ReadReq hits
953system.cpu0.l2cache.WritebackDirty_hits::writebacks 475089 # number of WritebackDirty hits
954system.cpu0.l2cache.WritebackDirty_hits::total 475089 # number of WritebackDirty hits
955system.cpu0.l2cache.WritebackClean_hits::writebacks 1289020 # number of WritebackClean hits
956system.cpu0.l2cache.WritebackClean_hits::total 1289020 # number of WritebackClean hits
957system.cpu0.l2cache.ReadExReq_hits::cpu0.data 224372 # number of ReadExReq hits
958system.cpu0.l2cache.ReadExReq_hits::total 224372 # number of ReadExReq hits
959system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1057524 # number of ReadCleanReq hits
960system.cpu0.l2cache.ReadCleanReq_hits::total 1057524 # number of ReadCleanReq hits
961system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 382410 # number of ReadSharedReq hits
962system.cpu0.l2cache.ReadSharedReq_hits::total 382410 # number of ReadSharedReq hits
963system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 9773 # number of demand (read+write) hits
964system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4523 # number of demand (read+write) hits
965system.cpu0.l2cache.demand_hits::cpu0.inst 1057524 # number of demand (read+write) hits
966system.cpu0.l2cache.demand_hits::cpu0.data 606782 # number of demand (read+write) hits
967system.cpu0.l2cache.demand_hits::total 1678602 # number of demand (read+write) hits
968system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 9773 # number of overall hits
969system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4523 # number of overall hits
970system.cpu0.l2cache.overall_hits::cpu0.inst 1057524 # number of overall hits
971system.cpu0.l2cache.overall_hits::cpu0.data 606782 # number of overall hits
972system.cpu0.l2cache.overall_hits::total 1678602 # number of overall hits
973system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 217 # number of ReadReq misses
974system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 146 # number of ReadReq misses
975system.cpu0.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
976system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55553 # number of UpgradeReq misses
977system.cpu0.l2cache.UpgradeReq_misses::total 55553 # number of UpgradeReq misses
978system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19821 # number of SCUpgradeReq misses
979system.cpu0.l2cache.SCUpgradeReq_misses::total 19821 # number of SCUpgradeReq misses
980system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44743 # number of ReadExReq misses
981system.cpu0.l2cache.ReadExReq_misses::total 44743 # number of ReadExReq misses
982system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 44710 # number of ReadCleanReq misses
983system.cpu0.l2cache.ReadCleanReq_misses::total 44710 # number of ReadCleanReq misses
984system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94096 # number of ReadSharedReq misses
985system.cpu0.l2cache.ReadSharedReq_misses::total 94096 # number of ReadSharedReq misses
986system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 217 # number of demand (read+write) misses
987system.cpu0.l2cache.demand_misses::cpu0.itb.walker 146 # number of demand (read+write) misses
988system.cpu0.l2cache.demand_misses::cpu0.inst 44710 # number of demand (read+write) misses
989system.cpu0.l2cache.demand_misses::cpu0.data 138839 # number of demand (read+write) misses
990system.cpu0.l2cache.demand_misses::total 183912 # number of demand (read+write) misses
991system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 217 # number of overall misses
992system.cpu0.l2cache.overall_misses::cpu0.itb.walker 146 # number of overall misses
993system.cpu0.l2cache.overall_misses::cpu0.inst 44710 # number of overall misses
994system.cpu0.l2cache.overall_misses::cpu0.data 138839 # number of overall misses
995system.cpu0.l2cache.overall_misses::total 183912 # number of overall misses
996system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5274500 # number of ReadReq miss cycles
997system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3487000 # number of ReadReq miss cycles
998system.cpu0.l2cache.ReadReq_miss_latency::total 8761500 # number of ReadReq miss cycles
999system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 99258500 # number of UpgradeReq miss cycles
1000system.cpu0.l2cache.UpgradeReq_miss_latency::total 99258500 # number of UpgradeReq miss cycles
1001system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 22708000 # number of SCUpgradeReq miss cycles
1002system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 22708000 # number of SCUpgradeReq miss cycles
1003system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1319000 # number of SCUpgradeFailReq miss cycles
1004system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1319000 # number of SCUpgradeFailReq miss cycles
1005system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2047288500 # number of ReadExReq miss cycles
1006system.cpu0.l2cache.ReadExReq_miss_latency::total 2047288500 # number of ReadExReq miss cycles
1007system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2385299500 # number of ReadCleanReq miss cycles
1008system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2385299500 # number of ReadCleanReq miss cycles
1009system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2791991500 # number of ReadSharedReq miss cycles
1010system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2791991500 # number of ReadSharedReq miss cycles
1011system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5274500 # number of demand (read+write) miss cycles
1012system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3487000 # number of demand (read+write) miss cycles
1013system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2385299500 # number of demand (read+write) miss cycles
1014system.cpu0.l2cache.demand_miss_latency::cpu0.data 4839280000 # number of demand (read+write) miss cycles
1015system.cpu0.l2cache.demand_miss_latency::total 7233341000 # number of demand (read+write) miss cycles
1016system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5274500 # number of overall miss cycles
1017system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3487000 # number of overall miss cycles
1018system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2385299500 # number of overall miss cycles
1019system.cpu0.l2cache.overall_miss_latency::cpu0.data 4839280000 # number of overall miss cycles
1020system.cpu0.l2cache.overall_miss_latency::total 7233341000 # number of overall miss cycles
1021system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 9990 # number of ReadReq accesses(hits+misses)
1022system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4669 # number of ReadReq accesses(hits+misses)
1023system.cpu0.l2cache.ReadReq_accesses::total 14659 # number of ReadReq accesses(hits+misses)
1024system.cpu0.l2cache.WritebackDirty_accesses::writebacks 475089 # number of WritebackDirty accesses(hits+misses)
1025system.cpu0.l2cache.WritebackDirty_accesses::total 475089 # number of WritebackDirty accesses(hits+misses)
1026system.cpu0.l2cache.WritebackClean_accesses::writebacks 1289020 # number of WritebackClean accesses(hits+misses)
1027system.cpu0.l2cache.WritebackClean_accesses::total 1289020 # number of WritebackClean accesses(hits+misses)
1028system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55553 # number of UpgradeReq accesses(hits+misses)
1029system.cpu0.l2cache.UpgradeReq_accesses::total 55553 # number of UpgradeReq accesses(hits+misses)
1030system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19821 # number of SCUpgradeReq accesses(hits+misses)
1031system.cpu0.l2cache.SCUpgradeReq_accesses::total 19821 # number of SCUpgradeReq accesses(hits+misses)
1032system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269115 # number of ReadExReq accesses(hits+misses)
1033system.cpu0.l2cache.ReadExReq_accesses::total 269115 # number of ReadExReq accesses(hits+misses)
1034system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1102234 # number of ReadCleanReq accesses(hits+misses)
1035system.cpu0.l2cache.ReadCleanReq_accesses::total 1102234 # number of ReadCleanReq accesses(hits+misses)
1036system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 476506 # number of ReadSharedReq accesses(hits+misses)
1037system.cpu0.l2cache.ReadSharedReq_accesses::total 476506 # number of ReadSharedReq accesses(hits+misses)
1038system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 9990 # number of demand (read+write) accesses
1039system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4669 # number of demand (read+write) accesses
1040system.cpu0.l2cache.demand_accesses::cpu0.inst 1102234 # number of demand (read+write) accesses
1041system.cpu0.l2cache.demand_accesses::cpu0.data 745621 # number of demand (read+write) accesses
1042system.cpu0.l2cache.demand_accesses::total 1862514 # number of demand (read+write) accesses
1043system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 9990 # number of overall (read+write) accesses
1044system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4669 # number of overall (read+write) accesses
1045system.cpu0.l2cache.overall_accesses::cpu0.inst 1102234 # number of overall (read+write) accesses
1046system.cpu0.l2cache.overall_accesses::cpu0.data 745621 # number of overall (read+write) accesses
1047system.cpu0.l2cache.overall_accesses::total 1862514 # number of overall (read+write) accesses
1048system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021722 # miss rate for ReadReq accesses
1049system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031270 # miss rate for ReadReq accesses
1050system.cpu0.l2cache.ReadReq_miss_rate::total 0.024763 # miss rate for ReadReq accesses
1051system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1052system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1053system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1054system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1055system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.166260 # miss rate for ReadExReq accesses
1056system.cpu0.l2cache.ReadExReq_miss_rate::total 0.166260 # miss rate for ReadExReq accesses
1057system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040563 # miss rate for ReadCleanReq accesses
1058system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040563 # miss rate for ReadCleanReq accesses
1059system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.197471 # miss rate for ReadSharedReq accesses
1060system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.197471 # miss rate for ReadSharedReq accesses
1061system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021722 # miss rate for demand accesses
1062system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031270 # miss rate for demand accesses
1063system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040563 # miss rate for demand accesses
1064system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.186206 # miss rate for demand accesses
1065system.cpu0.l2cache.demand_miss_rate::total 0.098744 # miss rate for demand accesses
1066system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021722 # miss rate for overall accesses
1067system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031270 # miss rate for overall accesses
1068system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040563 # miss rate for overall accesses
1069system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.186206 # miss rate for overall accesses
1070system.cpu0.l2cache.overall_miss_rate::total 0.098744 # miss rate for overall accesses
1071system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24306.451613 # average ReadReq miss latency
1072system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23883.561644 # average ReadReq miss latency
1073system.cpu0.l2cache.ReadReq_avg_miss_latency::total 24136.363636 # average ReadReq miss latency
1074system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 1786.735190 # average UpgradeReq miss latency
1075system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 1786.735190 # average UpgradeReq miss latency
1076system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1145.653600 # average SCUpgradeReq miss latency
1077system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1145.653600 # average SCUpgradeReq miss latency
1078system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
1079system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
1080system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45756.621147 # average ReadExReq miss latency
1081system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45756.621147 # average ReadExReq miss latency
1082system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 53350.469694 # average ReadCleanReq miss latency
1083system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 53350.469694 # average ReadCleanReq miss latency
1084system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29671.734186 # average ReadSharedReq miss latency
1085system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29671.734186 # average ReadSharedReq miss latency
1086system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24306.451613 # average overall miss latency
1087system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23883.561644 # average overall miss latency
1088system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 53350.469694 # average overall miss latency
1089system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34855.336037 # average overall miss latency
1090system.cpu0.l2cache.demand_avg_miss_latency::total 39330.446083 # average overall miss latency
1091system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24306.451613 # average overall miss latency
1092system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23883.561644 # average overall miss latency
1093system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 53350.469694 # average overall miss latency
1094system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34855.336037 # average overall miss latency
1095system.cpu0.l2cache.overall_avg_miss_latency::total 39330.446083 # average overall miss latency
1096system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1097system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1098system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1099system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1100system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1101system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1102system.cpu0.l2cache.unused_prefetches 11148 # number of HardPF blocks evicted w/o reference
1103system.cpu0.l2cache.writebacks::writebacks 227538 # number of writebacks
1104system.cpu0.l2cache.writebacks::total 227538 # number of writebacks
1105system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1132 # number of ReadExReq MSHR hits
1106system.cpu0.l2cache.ReadExReq_mshr_hits::total 1132 # number of ReadExReq MSHR hits
1107system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 31 # number of ReadSharedReq MSHR hits
1108system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 31 # number of ReadSharedReq MSHR hits
1109system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1163 # number of demand (read+write) MSHR hits
1110system.cpu0.l2cache.demand_mshr_hits::total 1163 # number of demand (read+write) MSHR hits
1111system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1163 # number of overall MSHR hits
1112system.cpu0.l2cache.overall_mshr_hits::total 1163 # number of overall MSHR hits
1113system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 217 # number of ReadReq MSHR misses
1114system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 146 # number of ReadReq MSHR misses
1115system.cpu0.l2cache.ReadReq_mshr_misses::total 363 # number of ReadReq MSHR misses
1116system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 258758 # number of HardPFReq MSHR misses
1117system.cpu0.l2cache.HardPFReq_mshr_misses::total 258758 # number of HardPFReq MSHR misses
1118system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55553 # number of UpgradeReq MSHR misses
1119system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55553 # number of UpgradeReq MSHR misses
1120system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19821 # number of SCUpgradeReq MSHR misses
1121system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19821 # number of SCUpgradeReq MSHR misses
1122system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 43611 # number of ReadExReq MSHR misses
1123system.cpu0.l2cache.ReadExReq_mshr_misses::total 43611 # number of ReadExReq MSHR misses
1124system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 44710 # number of ReadCleanReq MSHR misses
1125system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 44710 # number of ReadCleanReq MSHR misses
1126system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94065 # number of ReadSharedReq MSHR misses
1127system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94065 # number of ReadSharedReq MSHR misses
1128system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 217 # number of demand (read+write) MSHR misses
1129system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 146 # number of demand (read+write) MSHR misses
1130system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 44710 # number of demand (read+write) MSHR misses
1131system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137676 # number of demand (read+write) MSHR misses
1132system.cpu0.l2cache.demand_mshr_misses::total 182749 # number of demand (read+write) MSHR misses
1133system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 217 # number of overall MSHR misses
1134system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 146 # number of overall MSHR misses
1135system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 44710 # number of overall MSHR misses
1136system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137676 # number of overall MSHR misses
1137system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 258758 # number of overall MSHR misses
1138system.cpu0.l2cache.overall_mshr_misses::total 441507 # number of overall MSHR misses
1139system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
1140system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable
1141system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 30128 # number of ReadReq MSHR uncacheable
1142system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable
1143system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19680 # number of WriteReq MSHR uncacheable
1144system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
1145system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses
1146system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 49808 # number of overall MSHR uncacheable misses
1147system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3972500 # number of ReadReq MSHR miss cycles
1148system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2611000 # number of ReadReq MSHR miss cycles
1149system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6583500 # number of ReadReq MSHR miss cycles
1150system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13423934365 # number of HardPFReq MSHR miss cycles
1151system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13423934365 # number of HardPFReq MSHR miss cycles
1152system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1067977500 # number of UpgradeReq MSHR miss cycles
1153system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1067977500 # number of UpgradeReq MSHR miss cycles
1154system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 305529500 # number of SCUpgradeReq MSHR miss cycles
1155system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 305529500 # number of SCUpgradeReq MSHR miss cycles
1156system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1073000 # number of SCUpgradeFailReq MSHR miss cycles
1157system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1073000 # number of SCUpgradeFailReq MSHR miss cycles
1158system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1676618000 # number of ReadExReq MSHR miss cycles
1159system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1676618000 # number of ReadExReq MSHR miss cycles
1160system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2117039500 # number of ReadCleanReq MSHR miss cycles
1161system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2117039500 # number of ReadCleanReq MSHR miss cycles
1162system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2223147000 # number of ReadSharedReq MSHR miss cycles
1163system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2223147000 # number of ReadSharedReq MSHR miss cycles
1164system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3972500 # number of demand (read+write) MSHR miss cycles
1165system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2611000 # number of demand (read+write) MSHR miss cycles
1166system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2117039500 # number of demand (read+write) MSHR miss cycles
1167system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3899765000 # number of demand (read+write) MSHR miss cycles
1168system.cpu0.l2cache.demand_mshr_miss_latency::total 6023388000 # number of demand (read+write) MSHR miss cycles
1169system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3972500 # number of overall MSHR miss cycles
1170system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2611000 # number of overall MSHR miss cycles
1171system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2117039500 # number of overall MSHR miss cycles
1172system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3899765000 # number of overall MSHR miss cycles
1173system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13423934365 # number of overall MSHR miss cycles
1174system.cpu0.l2cache.overall_mshr_miss_latency::total 19447322365 # number of overall MSHR miss cycles
1175system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 743751500 # number of ReadReq MSHR uncacheable cycles
1176system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4509867000 # number of ReadReq MSHR uncacheable cycles
1177system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5253618500 # number of ReadReq MSHR uncacheable cycles
1178system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 743751500 # number of overall MSHR uncacheable cycles
1179system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4509867000 # number of overall MSHR uncacheable cycles
1180system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 5253618500 # number of overall MSHR uncacheable cycles
1181system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for ReadReq accesses
1182system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for ReadReq accesses
1183system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024763 # mshr miss rate for ReadReq accesses
1184system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1185system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1186system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1187system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1188system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1189system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1190system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.162053 # mshr miss rate for ReadExReq accesses
1191system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.162053 # mshr miss rate for ReadExReq accesses
1192system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for ReadCleanReq accesses
1193system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040563 # mshr miss rate for ReadCleanReq accesses
1194system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.197406 # mshr miss rate for ReadSharedReq accesses
1195system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.197406 # mshr miss rate for ReadSharedReq accesses
1196system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for demand accesses
1197system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for demand accesses
1198system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for demand accesses
1199system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184646 # mshr miss rate for demand accesses
1200system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098120 # mshr miss rate for demand accesses
1201system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021722 # mshr miss rate for overall accesses
1202system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031270 # mshr miss rate for overall accesses
1203system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040563 # mshr miss rate for overall accesses
1204system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184646 # mshr miss rate for overall accesses
1205system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1206system.cpu0.l2cache.overall_mshr_miss_rate::total 0.237049 # mshr miss rate for overall accesses
1207system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average ReadReq mshr miss latency
1208system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average ReadReq mshr miss latency
1209system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18136.363636 # average ReadReq mshr miss latency
1210system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51878.335607 # average HardPFReq mshr miss latency
1211system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 51878.335607 # average HardPFReq mshr miss latency
1212system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19224.479326 # average UpgradeReq mshr miss latency
1213system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19224.479326 # average UpgradeReq mshr miss latency
1214system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15414.434186 # average SCUpgradeReq mshr miss latency
1215system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15414.434186 # average SCUpgradeReq mshr miss latency
1216system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
1217system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
1218system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38444.841898 # average ReadExReq mshr miss latency
1219system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38444.841898 # average ReadExReq mshr miss latency
1220system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average ReadCleanReq mshr miss latency
1221system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47350.469694 # average ReadCleanReq mshr miss latency
1222system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23634.157232 # average ReadSharedReq mshr miss latency
1223system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23634.157232 # average ReadSharedReq mshr miss latency
1224system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average overall mshr miss latency
1225system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average overall mshr miss latency
1226system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average overall mshr miss latency
1227system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28325.670415 # average overall mshr miss latency
1228system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32959.895813 # average overall mshr miss latency
1229system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18306.451613 # average overall mshr miss latency
1230system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17883.561644 # average overall mshr miss latency
1231system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47350.469694 # average overall mshr miss latency
1232system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28325.670415 # average overall mshr miss latency
1233system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 51878.335607 # average overall mshr miss latency
1234system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44047.596901 # average overall mshr miss latency
1235system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency
1236system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 213677.011276 # average ReadReq mshr uncacheable latency
1237system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174376.609798 # average ReadReq mshr uncacheable latency
1238system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency
1239system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 110573.897906 # average overall mshr uncacheable latency
1240system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 105477.403228 # average overall mshr uncacheable latency
1241system.cpu0.toL2Bus.snoop_filter.tot_requests 3727432 # Total number of requests made to the snoop filter.
1242system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1879617 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1243system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1244system.cpu0.toL2Bus.snoop_filter.tot_snoops 314429 # Total number of snoops made to the snoop filter.
1245system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 310730 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1246system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3699 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1247system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1248system.cpu0.toL2Bus.trans_dist::ReadReq 50409 # Transaction distribution
1249system.cpu0.toL2Bus.trans_dist::ReadResp 1677085 # Transaction distribution
1250system.cpu0.toL2Bus.trans_dist::WriteReq 19680 # Transaction distribution
1251system.cpu0.toL2Bus.trans_dist::WriteResp 19680 # Transaction distribution
1252system.cpu0.toL2Bus.trans_dist::WritebackDirty 702838 # Transaction distribution
1253system.cpu0.toL2Bus.trans_dist::WritebackClean 1316929 # Transaction distribution
1254system.cpu0.toL2Bus.trans_dist::CleanEvict 184068 # Transaction distribution
1255system.cpu0.toL2Bus.trans_dist::HardPFReq 307004 # Transaction distribution
1256system.cpu0.toL2Bus.trans_dist::UpgradeReq 88013 # Transaction distribution
1257system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42167 # Transaction distribution
1258system.cpu0.toL2Bus.trans_dist::UpgradeResp 112831 # Transaction distribution
1259system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
1260system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution
1261system.cpu0.toL2Bus.trans_dist::ReadExReq 288284 # Transaction distribution
1262system.cpu0.toL2Bus.trans_dist::ReadExResp 284624 # Transaction distribution
1263system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1102234 # Transaction distribution
1264system.cpu0.toL2Bus.trans_dist::ReadSharedReq 554693 # Transaction distribution
1265system.cpu0.toL2Bus.trans_dist::InvalidateReq 3303 # Transaction distribution
1266system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3324225 # Packet count per connected master and slave (bytes)
1267system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2514874 # Packet count per connected master and slave (bytes)
1268system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11068 # Packet count per connected master and slave (bytes)
1269system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23857 # Packet count per connected master and slave (bytes)
1270system.cpu0.toL2Bus.pkt_count::total 5874024 # Packet count per connected master and slave (bytes)
1271system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141088696 # Cumulative packet size per connected master and slave (bytes)
1272system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96080240 # Cumulative packet size per connected master and slave (bytes)
1273system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18676 # Cumulative packet size per connected master and slave (bytes)
1274system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 39960 # Cumulative packet size per connected master and slave (bytes)
1275system.cpu0.toL2Bus.pkt_size::total 237227572 # Cumulative packet size per connected master and slave (bytes)
1276system.cpu0.toL2Bus.snoops 980964 # Total snoops (count)
1277system.cpu0.toL2Bus.snoopTraffic 18662568 # Total snoop traffic (bytes)
1278system.cpu0.toL2Bus.snoop_fanout::samples 2867653 # Request fanout histogram
1279system.cpu0.toL2Bus.snoop_fanout::mean 0.124927 # Request fanout histogram
1280system.cpu0.toL2Bus.snoop_fanout::stdev 0.334515 # Request fanout histogram
1281system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1282system.cpu0.toL2Bus.snoop_fanout::0 2513105 87.64% 87.64% # Request fanout histogram
1283system.cpu0.toL2Bus.snoop_fanout::1 350849 12.23% 99.87% # Request fanout histogram
1284system.cpu0.toL2Bus.snoop_fanout::2 3699 0.13% 100.00% # Request fanout histogram
1285system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1286system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1287system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1288system.cpu0.toL2Bus.snoop_fanout::total 2867653 # Request fanout histogram
1289system.cpu0.toL2Bus.reqLayer0.occupancy 3694518500 # Layer occupancy (ticks)
1290system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1291system.cpu0.toL2Bus.snoopLayer0.occupancy 114067456 # Layer occupancy (ticks)
1292system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1293system.cpu0.toL2Bus.respLayer0.occupancy 1662373000 # Layer occupancy (ticks)
1294system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1295system.cpu0.toL2Bus.respLayer1.occupancy 1187117482 # Layer occupancy (ticks)
1296system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1297system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
1298system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1299system.cpu0.toL2Bus.respLayer3.occupancy 13871990 # Layer occupancy (ticks)
1300system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1301system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1302system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1303system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1304system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1305system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1306system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1307system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1308system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1309system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1323system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1324system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1325system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1326system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1327system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1328system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1329system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1330system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1331system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1332system.cpu1.dtb.walker.walks 3295 # Table walker walks requested
1333system.cpu1.dtb.walker.walksShort 3295 # Table walker walks initiated with short descriptors
1334system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 621 # Level at which table walker walks with short descriptors terminate
1335system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2674 # Level at which table walker walks with short descriptors terminate
1336system.cpu1.dtb.walker.walkWaitTime::samples 3295 # Table walker wait (enqueue to first request) latency
1337system.cpu1.dtb.walker.walkWaitTime::0 3295 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1338system.cpu1.dtb.walker.walkWaitTime::total 3295 # Table walker wait (enqueue to first request) latency
1339system.cpu1.dtb.walker.walkCompletionTime::samples 2525 # Table walker service (enqueue to completion) latency
1340system.cpu1.dtb.walker.walkCompletionTime::mean 11832.673267 # Table walker service (enqueue to completion) latency
1341system.cpu1.dtb.walker.walkCompletionTime::gmean 11118.852324 # Table walker service (enqueue to completion) latency
1342system.cpu1.dtb.walker.walkCompletionTime::stdev 4722.323425 # Table walker service (enqueue to completion) latency
1343system.cpu1.dtb.walker.walkCompletionTime::0-4095 1 0.04% 0.04% # Table walker service (enqueue to completion) latency
1344system.cpu1.dtb.walker.walkCompletionTime::4096-8191 600 23.76% 23.80% # Table walker service (enqueue to completion) latency
1345system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1197 47.41% 71.21% # Table walker service (enqueue to completion) latency
1346system.cpu1.dtb.walker.walkCompletionTime::12288-16383 525 20.79% 92.00% # Table walker service (enqueue to completion) latency
1347system.cpu1.dtb.walker.walkCompletionTime::16384-20479 78 3.09% 95.09% # Table walker service (enqueue to completion) latency
1348system.cpu1.dtb.walker.walkCompletionTime::20480-24575 55 2.18% 97.27% # Table walker service (enqueue to completion) latency
1349system.cpu1.dtb.walker.walkCompletionTime::24576-28671 34 1.35% 98.61% # Table walker service (enqueue to completion) latency
1350system.cpu1.dtb.walker.walkCompletionTime::28672-32767 21 0.83% 99.45% # Table walker service (enqueue to completion) latency
1351system.cpu1.dtb.walker.walkCompletionTime::32768-36863 5 0.20% 99.64% # Table walker service (enqueue to completion) latency
1352system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.76% # Table walker service (enqueue to completion) latency
1353system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency
1354system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 99.92% # Table walker service (enqueue to completion) latency
1355system.cpu1.dtb.walker.walkCompletionTime::49152-53247 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
1356system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
1357system.cpu1.dtb.walker.walkCompletionTime::total 2525 # Table walker service (enqueue to completion) latency
1358system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution
1359system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution
1360system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution
1361system.cpu1.dtb.walker.walkPageSizes::4K 1912 75.72% 75.72% # Table walker page sizes translated
1362system.cpu1.dtb.walker.walkPageSizes::1M 613 24.28% 100.00% # Table walker page sizes translated
1363system.cpu1.dtb.walker.walkPageSizes::total 2525 # Table walker page sizes translated
1364system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3295 # Table walker requests started/completed, data/inst
1365system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1366system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3295 # Table walker requests started/completed, data/inst
1367system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2525 # Table walker requests started/completed, data/inst
1368system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1369system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2525 # Table walker requests started/completed, data/inst
1370system.cpu1.dtb.walker.walkRequestOrigin::total 5820 # Table walker requests started/completed, data/inst
1371system.cpu1.dtb.inst_hits 0 # ITB inst hits
1372system.cpu1.dtb.inst_misses 0 # ITB inst misses
1373system.cpu1.dtb.read_hits 6294037 # DTB read hits
1374system.cpu1.dtb.read_misses 2780 # DTB read misses
1375system.cpu1.dtb.write_hits 4620410 # DTB write hits
1376system.cpu1.dtb.write_misses 515 # DTB write misses
1377system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1378system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1379system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1380system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1381system.cpu1.dtb.flush_entries 1950 # Number of entries that have been flushed from TLB
1382system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1383system.cpu1.dtb.prefetch_faults 345 # Number of TLB faults due to prefetch
1384system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1385system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
1386system.cpu1.dtb.read_accesses 6296817 # DTB read accesses
1387system.cpu1.dtb.write_accesses 4620925 # DTB write accesses
1388system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1389system.cpu1.dtb.hits 10914447 # DTB hits
1390system.cpu1.dtb.misses 3295 # DTB misses
1391system.cpu1.dtb.accesses 10917742 # DTB accesses
1392system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1393system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1394system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1395system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1396system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1397system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1398system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1399system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1400system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1414system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1415system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1416system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1417system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1418system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1419system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1420system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1421system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1422system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1423system.cpu1.itb.walker.walks 1746 # Table walker walks requested
1424system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors
1425system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate
1426system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate
1427system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency
1428system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1429system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency
1430system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency
1431system.cpu1.itb.walker.walkCompletionTime::mean 12387.082204 # Table walker service (enqueue to completion) latency
1432system.cpu1.itb.walker.walkCompletionTime::gmean 11535.325922 # Table walker service (enqueue to completion) latency
1433system.cpu1.itb.walker.walkCompletionTime::stdev 5801.640137 # Table walker service (enqueue to completion) latency
1434system.cpu1.itb.walker.walkCompletionTime::4096-8191 173 15.63% 15.63% # Table walker service (enqueue to completion) latency
1435system.cpu1.itb.walker.walkCompletionTime::8192-12287 662 59.80% 75.43% # Table walker service (enqueue to completion) latency
1436system.cpu1.itb.walker.walkCompletionTime::12288-16383 167 15.09% 90.51% # Table walker service (enqueue to completion) latency
1437system.cpu1.itb.walker.walkCompletionTime::16384-20479 48 4.34% 94.85% # Table walker service (enqueue to completion) latency
1438system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.18% 95.03% # Table walker service (enqueue to completion) latency
1439system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 1.99% 97.02% # Table walker service (enqueue to completion) latency
1440system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.81% 97.83% # Table walker service (enqueue to completion) latency
1441system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 98.01% # Table walker service (enqueue to completion) latency
1442system.cpu1.itb.walker.walkCompletionTime::36864-40959 17 1.54% 99.55% # Table walker service (enqueue to completion) latency
1443system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.82% # Table walker service (enqueue to completion) latency
1444system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 99.91% # Table walker service (enqueue to completion) latency
1445system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
1446system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency
1447system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution
1448system.cpu1.itb.walker.walksPending::0 -2078939828 100.00% 100.00% # Table walker pending requests distribution
1449system.cpu1.itb.walker.walksPending::total -2078939828 # Table walker pending requests distribution
1450system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated
1451system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated
1452system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated
1453system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1454system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst
1455system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst
1456system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1457system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst
1458system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst
1459system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst
1460system.cpu1.itb.inst_hits 27022574 # ITB inst hits
1461system.cpu1.itb.inst_misses 1746 # ITB inst misses
1462system.cpu1.itb.read_hits 0 # DTB read hits
1463system.cpu1.itb.read_misses 0 # DTB read misses
1464system.cpu1.itb.write_hits 0 # DTB write hits
1465system.cpu1.itb.write_misses 0 # DTB write misses
1466system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1467system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1468system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1469system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1470system.cpu1.itb.flush_entries 1084 # Number of entries that have been flushed from TLB
1471system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1472system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1473system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1474system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1475system.cpu1.itb.read_accesses 0 # DTB read accesses
1476system.cpu1.itb.write_accesses 0 # DTB write accesses
1477system.cpu1.itb.inst_accesses 27024320 # ITB inst accesses
1478system.cpu1.itb.hits 27022574 # DTB hits
1479system.cpu1.itb.misses 1746 # DTB misses
1480system.cpu1.itb.accesses 27024320 # DTB accesses
1481system.cpu1.numPwrStateTransitions 5545 # Number of power state transitions
1482system.cpu1.pwrStateClkGateDist::samples 2773 # Distribution of time spent in the clock gated state
1483system.cpu1.pwrStateClkGateDist::mean 1021169708.427335 # Distribution of time spent in the clock gated state
1484system.cpu1.pwrStateClkGateDist::stdev 25639051633.019150 # Distribution of time spent in the clock gated state
1485system.cpu1.pwrStateClkGateDist::underflows 1969 71.01% 71.01% # Distribution of time spent in the clock gated state
1486system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.78% 99.78% # Distribution of time spent in the clock gated state
1487system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state
1488system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state
1489system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state
1490system.cpu1.pwrStateClkGateDist::8e+11-8.5e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state
1491system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state
1492system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1493system.cpu1.pwrStateClkGateDist::max_value 929980591792 # Distribution of time spent in the clock gated state
1494system.cpu1.pwrStateClkGateDist::total 2773 # Distribution of time spent in the clock gated state
1495system.cpu1.pwrStateResidencyTicks::ON 38093227531 # Cumulative time (in ticks) in various power states
1496system.cpu1.pwrStateResidencyTicks::CLK_GATED 2831703601469 # Cumulative time (in ticks) in various power states
1497system.cpu1.numCycles 5738665817 # number of cpu cycles simulated
1498system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1499system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1500system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1501system.cpu1.kern.inst.quiesce 2773 # number of quiesce instructions executed
1502system.cpu1.committedInsts 26084833 # Number of instructions committed
1503system.cpu1.committedOps 31969643 # Number of ops (including micro ops) committed
1504system.cpu1.num_int_alu_accesses 28891717 # Number of integer alu accesses
1505system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses
1506system.cpu1.num_func_calls 3291352 # number of times a function call or return occured
1507system.cpu1.num_conditional_control_insts 2940246 # number of instructions that are conditional controls
1508system.cpu1.num_int_insts 28891717 # number of integer instructions
1509system.cpu1.num_fp_insts 1857 # number of float instructions
1510system.cpu1.num_int_register_reads 54405566 # number of times the integer registers were read
1511system.cpu1.num_int_register_writes 20702345 # number of times the integer registers were written
1512system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read
1513system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
1514system.cpu1.num_cc_register_reads 117659728 # number of times the CC registers were read
1515system.cpu1.num_cc_register_writes 9804030 # number of times the CC registers were written
1516system.cpu1.num_mem_refs 11150743 # number of memory refs
1517system.cpu1.num_load_insts 6405542 # Number of load instructions
1518system.cpu1.num_store_insts 4745201 # Number of store instructions
1519system.cpu1.num_idle_cycles 5662491677.952167 # Number of idle cycles
1520system.cpu1.num_busy_cycles 76174139.047833 # Number of busy cycles
1521system.cpu1.not_idle_fraction 0.013274 # Percentage of non-idle cycles
1522system.cpu1.idle_fraction 0.986726 # Percentage of idle cycles
1523system.cpu1.Branches 6334050 # Number of branches fetched
1524system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
1525system.cpu1.op_class::IntAlu 21707276 65.97% 65.97% # Class of executed instruction
1526system.cpu1.op_class::IntMult 42869 0.13% 66.10% # Class of executed instruction
1527system.cpu1.op_class::IntDiv 0 0.00% 66.10% # Class of executed instruction
1528system.cpu1.op_class::FloatAdd 0 0.00% 66.10% # Class of executed instruction
1529system.cpu1.op_class::FloatCmp 0 0.00% 66.10% # Class of executed instruction
1530system.cpu1.op_class::FloatCvt 0 0.00% 66.10% # Class of executed instruction
1531system.cpu1.op_class::FloatMult 0 0.00% 66.10% # Class of executed instruction
1532system.cpu1.op_class::FloatDiv 0 0.00% 66.10% # Class of executed instruction
1533system.cpu1.op_class::FloatSqrt 0 0.00% 66.10% # Class of executed instruction
1534system.cpu1.op_class::SimdAdd 0 0.00% 66.10% # Class of executed instruction
1535system.cpu1.op_class::SimdAddAcc 0 0.00% 66.10% # Class of executed instruction
1536system.cpu1.op_class::SimdAlu 0 0.00% 66.10% # Class of executed instruction
1537system.cpu1.op_class::SimdCmp 0 0.00% 66.10% # Class of executed instruction
1538system.cpu1.op_class::SimdCvt 0 0.00% 66.10% # Class of executed instruction
1539system.cpu1.op_class::SimdMisc 0 0.00% 66.10% # Class of executed instruction
1540system.cpu1.op_class::SimdMult 0 0.00% 66.10% # Class of executed instruction
1541system.cpu1.op_class::SimdMultAcc 0 0.00% 66.10% # Class of executed instruction
1542system.cpu1.op_class::SimdShift 0 0.00% 66.10% # Class of executed instruction
1543system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.10% # Class of executed instruction
1544system.cpu1.op_class::SimdSqrt 0 0.00% 66.10% # Class of executed instruction
1545system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.10% # Class of executed instruction
1546system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.10% # Class of executed instruction
1547system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.10% # Class of executed instruction
1548system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.10% # Class of executed instruction
1549system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.10% # Class of executed instruction
1550system.cpu1.op_class::SimdFloatMisc 3317 0.01% 66.11% # Class of executed instruction
1551system.cpu1.op_class::SimdFloatMult 0 0.00% 66.11% # Class of executed instruction
1552system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.11% # Class of executed instruction
1553system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.11% # Class of executed instruction
1554system.cpu1.op_class::MemRead 6405542 19.47% 85.58% # Class of executed instruction
1555system.cpu1.op_class::MemWrite 4745201 14.42% 100.00% # Class of executed instruction
1556system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1557system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1558system.cpu1.op_class::total 32904271 # Class of executed instruction
1559system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1560system.cpu1.dcache.tags.replacements 184968 # number of replacements
1561system.cpu1.dcache.tags.tagsinuse 463.748200 # Cycle average of tags in use
1562system.cpu1.dcache.tags.total_refs 10628914 # Total number of references to valid blocks.
1563system.cpu1.dcache.tags.sampled_refs 185317 # Sample count of references to valid blocks.
1564system.cpu1.dcache.tags.avg_refs 57.355310 # Average number of references to valid blocks.
1565system.cpu1.dcache.tags.warmup_cycle 117456056000 # Cycle when the warmup percentage was hit.
1566system.cpu1.dcache.tags.occ_blocks::cpu1.data 463.748200 # Average occupied blocks per requestor
1567system.cpu1.dcache.tags.occ_percent::cpu1.data 0.905758 # Average percentage of cache occupancy
1568system.cpu1.dcache.tags.occ_percent::total 0.905758 # Average percentage of cache occupancy
1569system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id
1570system.cpu1.dcache.tags.age_task_id_blocks_1024::2 279 # Occupied blocks per task id
1571system.cpu1.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id
1572system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id
1573system.cpu1.dcache.tags.tag_accesses 22007267 # Number of tag accesses
1574system.cpu1.dcache.tags.data_accesses 22007267 # Number of data accesses
1575system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1576system.cpu1.dcache.ReadReq_hits::cpu1.data 5972632 # number of ReadReq hits
1577system.cpu1.dcache.ReadReq_hits::total 5972632 # number of ReadReq hits
1578system.cpu1.dcache.WriteReq_hits::cpu1.data 4424329 # number of WriteReq hits
1579system.cpu1.dcache.WriteReq_hits::total 4424329 # number of WriteReq hits
1580system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48799 # number of SoftPFReq hits
1581system.cpu1.dcache.SoftPFReq_hits::total 48799 # number of SoftPFReq hits
1582system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78725 # number of LoadLockedReq hits
1583system.cpu1.dcache.LoadLockedReq_hits::total 78725 # number of LoadLockedReq hits
1584system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70549 # number of StoreCondReq hits
1585system.cpu1.dcache.StoreCondReq_hits::total 70549 # number of StoreCondReq hits
1586system.cpu1.dcache.demand_hits::cpu1.data 10396961 # number of demand (read+write) hits
1587system.cpu1.dcache.demand_hits::total 10396961 # number of demand (read+write) hits
1588system.cpu1.dcache.overall_hits::cpu1.data 10445760 # number of overall hits
1589system.cpu1.dcache.overall_hits::total 10445760 # number of overall hits
1590system.cpu1.dcache.ReadReq_misses::cpu1.data 132851 # number of ReadReq misses
1591system.cpu1.dcache.ReadReq_misses::total 132851 # number of ReadReq misses
1592system.cpu1.dcache.WriteReq_misses::cpu1.data 90720 # number of WriteReq misses
1593system.cpu1.dcache.WriteReq_misses::total 90720 # number of WriteReq misses
1594system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30243 # number of SoftPFReq misses
1595system.cpu1.dcache.SoftPFReq_misses::total 30243 # number of SoftPFReq misses
1596system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17042 # number of LoadLockedReq misses
1597system.cpu1.dcache.LoadLockedReq_misses::total 17042 # number of LoadLockedReq misses
1598system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23391 # number of StoreCondReq misses
1599system.cpu1.dcache.StoreCondReq_misses::total 23391 # number of StoreCondReq misses
1600system.cpu1.dcache.demand_misses::cpu1.data 223571 # number of demand (read+write) misses
1601system.cpu1.dcache.demand_misses::total 223571 # number of demand (read+write) misses
1602system.cpu1.dcache.overall_misses::cpu1.data 253814 # number of overall misses
1603system.cpu1.dcache.overall_misses::total 253814 # number of overall misses
1604system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1953731000 # number of ReadReq miss cycles
1605system.cpu1.dcache.ReadReq_miss_latency::total 1953731000 # number of ReadReq miss cycles
1606system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2328640500 # number of WriteReq miss cycles
1607system.cpu1.dcache.WriteReq_miss_latency::total 2328640500 # number of WriteReq miss cycles
1608system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317134000 # number of LoadLockedReq miss cycles
1609system.cpu1.dcache.LoadLockedReq_miss_latency::total 317134000 # number of LoadLockedReq miss cycles
1610system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572176500 # number of StoreCondReq miss cycles
1611system.cpu1.dcache.StoreCondReq_miss_latency::total 572176500 # number of StoreCondReq miss cycles
1612system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2893000 # number of StoreCondFailReq miss cycles
1613system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2893000 # number of StoreCondFailReq miss cycles
1614system.cpu1.dcache.demand_miss_latency::cpu1.data 4282371500 # number of demand (read+write) miss cycles
1615system.cpu1.dcache.demand_miss_latency::total 4282371500 # number of demand (read+write) miss cycles
1616system.cpu1.dcache.overall_miss_latency::cpu1.data 4282371500 # number of overall miss cycles
1617system.cpu1.dcache.overall_miss_latency::total 4282371500 # number of overall miss cycles
1618system.cpu1.dcache.ReadReq_accesses::cpu1.data 6105483 # number of ReadReq accesses(hits+misses)
1619system.cpu1.dcache.ReadReq_accesses::total 6105483 # number of ReadReq accesses(hits+misses)
1620system.cpu1.dcache.WriteReq_accesses::cpu1.data 4515049 # number of WriteReq accesses(hits+misses)
1621system.cpu1.dcache.WriteReq_accesses::total 4515049 # number of WriteReq accesses(hits+misses)
1622system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79042 # number of SoftPFReq accesses(hits+misses)
1623system.cpu1.dcache.SoftPFReq_accesses::total 79042 # number of SoftPFReq accesses(hits+misses)
1624system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95767 # number of LoadLockedReq accesses(hits+misses)
1625system.cpu1.dcache.LoadLockedReq_accesses::total 95767 # number of LoadLockedReq accesses(hits+misses)
1626system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93940 # number of StoreCondReq accesses(hits+misses)
1627system.cpu1.dcache.StoreCondReq_accesses::total 93940 # number of StoreCondReq accesses(hits+misses)
1628system.cpu1.dcache.demand_accesses::cpu1.data 10620532 # number of demand (read+write) accesses
1629system.cpu1.dcache.demand_accesses::total 10620532 # number of demand (read+write) accesses
1630system.cpu1.dcache.overall_accesses::cpu1.data 10699574 # number of overall (read+write) accesses
1631system.cpu1.dcache.overall_accesses::total 10699574 # number of overall (read+write) accesses
1632system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.021759 # miss rate for ReadReq accesses
1633system.cpu1.dcache.ReadReq_miss_rate::total 0.021759 # miss rate for ReadReq accesses
1634system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.020093 # miss rate for WriteReq accesses
1635system.cpu1.dcache.WriteReq_miss_rate::total 0.020093 # miss rate for WriteReq accesses
1636system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382619 # miss rate for SoftPFReq accesses
1637system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382619 # miss rate for SoftPFReq accesses
1638system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177953 # miss rate for LoadLockedReq accesses
1639system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177953 # miss rate for LoadLockedReq accesses
1640system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248999 # miss rate for StoreCondReq accesses
1641system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248999 # miss rate for StoreCondReq accesses
1642system.cpu1.dcache.demand_miss_rate::cpu1.data 0.021051 # miss rate for demand accesses
1643system.cpu1.dcache.demand_miss_rate::total 0.021051 # miss rate for demand accesses
1644system.cpu1.dcache.overall_miss_rate::cpu1.data 0.023722 # miss rate for overall accesses
1645system.cpu1.dcache.overall_miss_rate::total 0.023722 # miss rate for overall accesses
1646system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14706.182114 # average ReadReq miss latency
1647system.cpu1.dcache.ReadReq_avg_miss_latency::total 14706.182114 # average ReadReq miss latency
1648system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25668.435847 # average WriteReq miss latency
1649system.cpu1.dcache.WriteReq_avg_miss_latency::total 25668.435847 # average WriteReq miss latency
1650system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18608.966084 # average LoadLockedReq miss latency
1651system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18608.966084 # average LoadLockedReq miss latency
1652system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24461.395408 # average StoreCondReq miss latency
1653system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24461.395408 # average StoreCondReq miss latency
1654system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1655system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1656system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19154.414034 # average overall miss latency
1657system.cpu1.dcache.demand_avg_miss_latency::total 19154.414034 # average overall miss latency
1658system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16872.085464 # average overall miss latency
1659system.cpu1.dcache.overall_avg_miss_latency::total 16872.085464 # average overall miss latency
1660system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1661system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1662system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1663system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1664system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1665system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1666system.cpu1.dcache.writebacks::writebacks 184968 # number of writebacks
1667system.cpu1.dcache.writebacks::total 184968 # number of writebacks
1668system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 261 # number of ReadReq MSHR hits
1669system.cpu1.dcache.ReadReq_mshr_hits::total 261 # number of ReadReq MSHR hits
1670system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11955 # number of LoadLockedReq MSHR hits
1671system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11955 # number of LoadLockedReq MSHR hits
1672system.cpu1.dcache.demand_mshr_hits::cpu1.data 261 # number of demand (read+write) MSHR hits
1673system.cpu1.dcache.demand_mshr_hits::total 261 # number of demand (read+write) MSHR hits
1674system.cpu1.dcache.overall_mshr_hits::cpu1.data 261 # number of overall MSHR hits
1675system.cpu1.dcache.overall_mshr_hits::total 261 # number of overall MSHR hits
1676system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 132590 # number of ReadReq MSHR misses
1677system.cpu1.dcache.ReadReq_mshr_misses::total 132590 # number of ReadReq MSHR misses
1678system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90720 # number of WriteReq MSHR misses
1679system.cpu1.dcache.WriteReq_mshr_misses::total 90720 # number of WriteReq MSHR misses
1680system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29532 # number of SoftPFReq MSHR misses
1681system.cpu1.dcache.SoftPFReq_mshr_misses::total 29532 # number of SoftPFReq MSHR misses
1682system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5087 # number of LoadLockedReq MSHR misses
1683system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5087 # number of LoadLockedReq MSHR misses
1684system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23391 # number of StoreCondReq MSHR misses
1685system.cpu1.dcache.StoreCondReq_mshr_misses::total 23391 # number of StoreCondReq MSHR misses
1686system.cpu1.dcache.demand_mshr_misses::cpu1.data 223310 # number of demand (read+write) MSHR misses
1687system.cpu1.dcache.demand_mshr_misses::total 223310 # number of demand (read+write) MSHR misses
1688system.cpu1.dcache.overall_mshr_misses::cpu1.data 252842 # number of overall MSHR misses
1689system.cpu1.dcache.overall_mshr_misses::total 252842 # number of overall MSHR misses
1690system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 13772 # number of ReadReq MSHR uncacheable
1691system.cpu1.dcache.ReadReq_mshr_uncacheable::total 13772 # number of ReadReq MSHR uncacheable
1692system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable
1693system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11224 # number of WriteReq MSHR uncacheable
1694system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 24996 # number of overall MSHR uncacheable misses
1695system.cpu1.dcache.overall_mshr_uncacheable_misses::total 24996 # number of overall MSHR uncacheable misses
1696system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1815324500 # number of ReadReq MSHR miss cycles
1697system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1815324500 # number of ReadReq MSHR miss cycles
1698system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2237920500 # number of WriteReq MSHR miss cycles
1699system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2237920500 # number of WriteReq MSHR miss cycles
1700system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 484982000 # number of SoftPFReq MSHR miss cycles
1701system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 484982000 # number of SoftPFReq MSHR miss cycles
1702system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85050000 # number of LoadLockedReq MSHR miss cycles
1703system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85050000 # number of LoadLockedReq MSHR miss cycles
1704system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548834500 # number of StoreCondReq MSHR miss cycles
1705system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548834500 # number of StoreCondReq MSHR miss cycles
1706system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2844000 # number of StoreCondFailReq MSHR miss cycles
1707system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2844000 # number of StoreCondFailReq MSHR miss cycles
1708system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4053245000 # number of demand (read+write) MSHR miss cycles
1709system.cpu1.dcache.demand_mshr_miss_latency::total 4053245000 # number of demand (read+write) MSHR miss cycles
1710system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4538227000 # number of overall MSHR miss cycles
1711system.cpu1.dcache.overall_mshr_miss_latency::total 4538227000 # number of overall MSHR miss cycles
1712system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2392670000 # number of ReadReq MSHR uncacheable cycles
1713system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2392670000 # number of ReadReq MSHR uncacheable cycles
1714system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2392670000 # number of overall MSHR uncacheable cycles
1715system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2392670000 # number of overall MSHR uncacheable cycles
1716system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.021717 # mshr miss rate for ReadReq accesses
1717system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.021717 # mshr miss rate for ReadReq accesses
1718system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.020093 # mshr miss rate for WriteReq accesses
1719system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.020093 # mshr miss rate for WriteReq accesses
1720system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.373624 # mshr miss rate for SoftPFReq accesses
1721system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.373624 # mshr miss rate for SoftPFReq accesses
1722system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053119 # mshr miss rate for LoadLockedReq accesses
1723system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053119 # mshr miss rate for LoadLockedReq accesses
1724system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248999 # mshr miss rate for StoreCondReq accesses
1725system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248999 # mshr miss rate for StoreCondReq accesses
1726system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.021026 # mshr miss rate for demand accesses
1727system.cpu1.dcache.demand_mshr_miss_rate::total 0.021026 # mshr miss rate for demand accesses
1728system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.023631 # mshr miss rate for overall accesses
1729system.cpu1.dcache.overall_mshr_miss_rate::total 0.023631 # mshr miss rate for overall accesses
1730system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13691.262539 # average ReadReq mshr miss latency
1731system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13691.262539 # average ReadReq mshr miss latency
1732system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24668.435847 # average WriteReq mshr miss latency
1733system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24668.435847 # average WriteReq mshr miss latency
1734system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16422.253826 # average SoftPFReq mshr miss latency
1735system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16422.253826 # average SoftPFReq mshr miss latency
1736system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16719.087871 # average LoadLockedReq mshr miss latency
1737system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16719.087871 # average LoadLockedReq mshr miss latency
1738system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23463.490231 # average StoreCondReq mshr miss latency
1739system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23463.490231 # average StoreCondReq mshr miss latency
1740system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1741system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1742system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18150.754556 # average overall mshr miss latency
1743system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18150.754556 # average overall mshr miss latency
1744system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17948.865299 # average overall mshr miss latency
1745system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17948.865299 # average overall mshr miss latency
1746system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173734.388615 # average ReadReq mshr uncacheable latency
1747system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173734.388615 # average ReadReq mshr uncacheable latency
1748system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95722.115538 # average overall mshr uncacheable latency
1749system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95722.115538 # average overall mshr uncacheable latency
1750system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1751system.cpu1.icache.tags.replacements 504074 # number of replacements
1752system.cpu1.icache.tags.tagsinuse 498.478768 # Cycle average of tags in use
1753system.cpu1.icache.tags.total_refs 26517983 # Total number of references to valid blocks.
1754system.cpu1.icache.tags.sampled_refs 504586 # Sample count of references to valid blocks.
1755system.cpu1.icache.tags.avg_refs 52.553941 # Average number of references to valid blocks.
1756system.cpu1.icache.tags.warmup_cycle 85269939000 # Cycle when the warmup percentage was hit.
1757system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478768 # Average occupied blocks per requestor
1758system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy
1759system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy
1760system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1761system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
1762system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id
1763system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
1764system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1765system.cpu1.icache.tags.tag_accesses 54549724 # Number of tag accesses
1766system.cpu1.icache.tags.data_accesses 54549724 # Number of data accesses
1767system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1768system.cpu1.icache.ReadReq_hits::cpu1.inst 26517983 # number of ReadReq hits
1769system.cpu1.icache.ReadReq_hits::total 26517983 # number of ReadReq hits
1770system.cpu1.icache.demand_hits::cpu1.inst 26517983 # number of demand (read+write) hits
1771system.cpu1.icache.demand_hits::total 26517983 # number of demand (read+write) hits
1772system.cpu1.icache.overall_hits::cpu1.inst 26517983 # number of overall hits
1773system.cpu1.icache.overall_hits::total 26517983 # number of overall hits
1774system.cpu1.icache.ReadReq_misses::cpu1.inst 504586 # number of ReadReq misses
1775system.cpu1.icache.ReadReq_misses::total 504586 # number of ReadReq misses
1776system.cpu1.icache.demand_misses::cpu1.inst 504586 # number of demand (read+write) misses
1777system.cpu1.icache.demand_misses::total 504586 # number of demand (read+write) misses
1778system.cpu1.icache.overall_misses::cpu1.inst 504586 # number of overall misses
1779system.cpu1.icache.overall_misses::total 504586 # number of overall misses
1780system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4509196500 # number of ReadReq miss cycles
1781system.cpu1.icache.ReadReq_miss_latency::total 4509196500 # number of ReadReq miss cycles
1782system.cpu1.icache.demand_miss_latency::cpu1.inst 4509196500 # number of demand (read+write) miss cycles
1783system.cpu1.icache.demand_miss_latency::total 4509196500 # number of demand (read+write) miss cycles
1784system.cpu1.icache.overall_miss_latency::cpu1.inst 4509196500 # number of overall miss cycles
1785system.cpu1.icache.overall_miss_latency::total 4509196500 # number of overall miss cycles
1786system.cpu1.icache.ReadReq_accesses::cpu1.inst 27022569 # number of ReadReq accesses(hits+misses)
1787system.cpu1.icache.ReadReq_accesses::total 27022569 # number of ReadReq accesses(hits+misses)
1788system.cpu1.icache.demand_accesses::cpu1.inst 27022569 # number of demand (read+write) accesses
1789system.cpu1.icache.demand_accesses::total 27022569 # number of demand (read+write) accesses
1790system.cpu1.icache.overall_accesses::cpu1.inst 27022569 # number of overall (read+write) accesses
1791system.cpu1.icache.overall_accesses::total 27022569 # number of overall (read+write) accesses
1792system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018673 # miss rate for ReadReq accesses
1793system.cpu1.icache.ReadReq_miss_rate::total 0.018673 # miss rate for ReadReq accesses
1794system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018673 # miss rate for demand accesses
1795system.cpu1.icache.demand_miss_rate::total 0.018673 # miss rate for demand accesses
1796system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018673 # miss rate for overall accesses
1797system.cpu1.icache.overall_miss_rate::total 0.018673 # miss rate for overall accesses
1798system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8936.428082 # average ReadReq miss latency
1799system.cpu1.icache.ReadReq_avg_miss_latency::total 8936.428082 # average ReadReq miss latency
1800system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8936.428082 # average overall miss latency
1801system.cpu1.icache.demand_avg_miss_latency::total 8936.428082 # average overall miss latency
1802system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8936.428082 # average overall miss latency
1803system.cpu1.icache.overall_avg_miss_latency::total 8936.428082 # average overall miss latency
1804system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1805system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1806system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1807system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1808system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1809system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1810system.cpu1.icache.writebacks::writebacks 504074 # number of writebacks
1811system.cpu1.icache.writebacks::total 504074 # number of writebacks
1812system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 504586 # number of ReadReq MSHR misses
1813system.cpu1.icache.ReadReq_mshr_misses::total 504586 # number of ReadReq MSHR misses
1814system.cpu1.icache.demand_mshr_misses::cpu1.inst 504586 # number of demand (read+write) MSHR misses
1815system.cpu1.icache.demand_mshr_misses::total 504586 # number of demand (read+write) MSHR misses
1816system.cpu1.icache.overall_mshr_misses::cpu1.inst 504586 # number of overall MSHR misses
1817system.cpu1.icache.overall_mshr_misses::total 504586 # number of overall MSHR misses
1818system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
1819system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
1820system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
1821system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
1822system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4256903500 # number of ReadReq MSHR miss cycles
1823system.cpu1.icache.ReadReq_mshr_miss_latency::total 4256903500 # number of ReadReq MSHR miss cycles
1824system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4256903500 # number of demand (read+write) MSHR miss cycles
1825system.cpu1.icache.demand_mshr_miss_latency::total 4256903500 # number of demand (read+write) MSHR miss cycles
1826system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4256903500 # number of overall MSHR miss cycles
1827system.cpu1.icache.overall_mshr_miss_latency::total 4256903500 # number of overall MSHR miss cycles
1828system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # number of ReadReq MSHR uncacheable cycles
1829system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15776500 # number of ReadReq MSHR uncacheable cycles
1830system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15776500 # number of overall MSHR uncacheable cycles
1831system.cpu1.icache.overall_mshr_uncacheable_latency::total 15776500 # number of overall MSHR uncacheable cycles
1832system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018673 # mshr miss rate for ReadReq accesses
1833system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018673 # mshr miss rate for ReadReq accesses
1834system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018673 # mshr miss rate for demand accesses
1835system.cpu1.icache.demand_mshr_miss_rate::total 0.018673 # mshr miss rate for demand accesses
1836system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018673 # mshr miss rate for overall accesses
1837system.cpu1.icache.overall_mshr_miss_rate::total 0.018673 # mshr miss rate for overall accesses
1838system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average ReadReq mshr miss latency
1839system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8436.428082 # average ReadReq mshr miss latency
1840system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average overall mshr miss latency
1841system.cpu1.icache.demand_avg_mshr_miss_latency::total 8436.428082 # average overall mshr miss latency
1842system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8436.428082 # average overall mshr miss latency
1843system.cpu1.icache.overall_avg_mshr_miss_latency::total 8436.428082 # average overall mshr miss latency
1844system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency
1845system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency
1846system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency
1847system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency
1848system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1849system.cpu1.l2cache.prefetcher.num_hwpf_issued 194200 # number of hwpf issued
1850system.cpu1.l2cache.prefetcher.pfIdentified 194208 # number of prefetch candidates identified
1851system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
1852system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1853system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1854system.cpu1.l2cache.prefetcher.pfSpanPage 58064 # number of prefetches not generated due to page crossing
1855system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1856system.cpu1.l2cache.tags.replacements 39025 # number of replacements
1857system.cpu1.l2cache.tags.tagsinuse 14524.719643 # Cycle average of tags in use
1858system.cpu1.l2cache.tags.total_refs 1158959 # Total number of references to valid blocks.
1859system.cpu1.l2cache.tags.sampled_refs 53669 # Sample count of references to valid blocks.
1860system.cpu1.l2cache.tags.avg_refs 21.594570 # Average number of references to valid blocks.
1861system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1862system.cpu1.l2cache.tags.occ_blocks::writebacks 14059.725770 # Average occupied blocks per requestor
1863system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 5.138677 # Average occupied blocks per requestor
1864system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.073426 # Average occupied blocks per requestor
1865system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 457.781770 # Average occupied blocks per requestor
1866system.cpu1.l2cache.tags.occ_percent::writebacks 0.858138 # Average percentage of cache occupancy
1867system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000314 # Average percentage of cache occupancy
1868system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy
1869system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027941 # Average percentage of cache occupancy
1870system.cpu1.l2cache.tags.occ_percent::total 0.886519 # Average percentage of cache occupancy
1871system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1036 # Occupied blocks per task id
1872system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id
1873system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13588 # Occupied blocks per task id
1874system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id
1875system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 48 # Occupied blocks per task id
1876system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 987 # Occupied blocks per task id
1877system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
1878system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
1879system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
1880system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id
1881system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1629 # Occupied blocks per task id
1882system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11648 # Occupied blocks per task id
1883system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.063232 # Percentage of cache occupancy per task id
1884system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id
1885system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.829346 # Percentage of cache occupancy per task id
1886system.cpu1.l2cache.tags.tag_accesses 23678541 # Number of tag accesses
1887system.cpu1.l2cache.tags.data_accesses 23678541 # Number of data accesses
1888system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
1889system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3677 # number of ReadReq hits
1890system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1997 # number of ReadReq hits
1891system.cpu1.l2cache.ReadReq_hits::total 5674 # number of ReadReq hits
1892system.cpu1.l2cache.WritebackDirty_hits::writebacks 113054 # number of WritebackDirty hits
1893system.cpu1.l2cache.WritebackDirty_hits::total 113054 # number of WritebackDirty hits
1894system.cpu1.l2cache.WritebackClean_hits::writebacks 564912 # number of WritebackClean hits
1895system.cpu1.l2cache.WritebackClean_hits::total 564912 # number of WritebackClean hits
1896system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27115 # number of ReadExReq hits
1897system.cpu1.l2cache.ReadExReq_hits::total 27115 # number of ReadExReq hits
1898system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 491676 # number of ReadCleanReq hits
1899system.cpu1.l2cache.ReadCleanReq_hits::total 491676 # number of ReadCleanReq hits
1900system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 100094 # number of ReadSharedReq hits
1901system.cpu1.l2cache.ReadSharedReq_hits::total 100094 # number of ReadSharedReq hits
1902system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3677 # number of demand (read+write) hits
1903system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1997 # number of demand (read+write) hits
1904system.cpu1.l2cache.demand_hits::cpu1.inst 491676 # number of demand (read+write) hits
1905system.cpu1.l2cache.demand_hits::cpu1.data 127209 # number of demand (read+write) hits
1906system.cpu1.l2cache.demand_hits::total 624559 # number of demand (read+write) hits
1907system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3677 # number of overall hits
1908system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1997 # number of overall hits
1909system.cpu1.l2cache.overall_hits::cpu1.inst 491676 # number of overall hits
1910system.cpu1.l2cache.overall_hits::cpu1.data 127209 # number of overall hits
1911system.cpu1.l2cache.overall_hits::total 624559 # number of overall hits
1912system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses
1913system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses
1914system.cpu1.l2cache.ReadReq_misses::total 588 # number of ReadReq misses
1915system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29273 # number of UpgradeReq misses
1916system.cpu1.l2cache.UpgradeReq_misses::total 29273 # number of UpgradeReq misses
1917system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23388 # number of SCUpgradeReq misses
1918system.cpu1.l2cache.SCUpgradeReq_misses::total 23388 # number of SCUpgradeReq misses
1919system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
1920system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
1921system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34332 # number of ReadExReq misses
1922system.cpu1.l2cache.ReadExReq_misses::total 34332 # number of ReadExReq misses
1923system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12910 # number of ReadCleanReq misses
1924system.cpu1.l2cache.ReadCleanReq_misses::total 12910 # number of ReadCleanReq misses
1925system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 67115 # number of ReadSharedReq misses
1926system.cpu1.l2cache.ReadSharedReq_misses::total 67115 # number of ReadSharedReq misses
1927system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 321 # number of demand (read+write) misses
1928system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses
1929system.cpu1.l2cache.demand_misses::cpu1.inst 12910 # number of demand (read+write) misses
1930system.cpu1.l2cache.demand_misses::cpu1.data 101447 # number of demand (read+write) misses
1931system.cpu1.l2cache.demand_misses::total 114945 # number of demand (read+write) misses
1932system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 321 # number of overall misses
1933system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses
1934system.cpu1.l2cache.overall_misses::cpu1.inst 12910 # number of overall misses
1935system.cpu1.l2cache.overall_misses::cpu1.data 101447 # number of overall misses
1936system.cpu1.l2cache.overall_misses::total 114945 # number of overall misses
1937system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6521000 # number of ReadReq miss cycles
1938system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5470500 # number of ReadReq miss cycles
1939system.cpu1.l2cache.ReadReq_miss_latency::total 11991500 # number of ReadReq miss cycles
1940system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64762500 # number of UpgradeReq miss cycles
1941system.cpu1.l2cache.UpgradeReq_miss_latency::total 64762500 # number of UpgradeReq miss cycles
1942system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 33901000 # number of SCUpgradeReq miss cycles
1943system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 33901000 # number of SCUpgradeReq miss cycles
1944system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2768998 # number of SCUpgradeFailReq miss cycles
1945system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2768998 # number of SCUpgradeFailReq miss cycles
1946system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1261050000 # number of ReadExReq miss cycles
1947system.cpu1.l2cache.ReadExReq_miss_latency::total 1261050000 # number of ReadExReq miss cycles
1948system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 523740500 # number of ReadCleanReq miss cycles
1949system.cpu1.l2cache.ReadCleanReq_miss_latency::total 523740500 # number of ReadCleanReq miss cycles
1950system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1479063500 # number of ReadSharedReq miss cycles
1951system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1479063500 # number of ReadSharedReq miss cycles
1952system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6521000 # number of demand (read+write) miss cycles
1953system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5470500 # number of demand (read+write) miss cycles
1954system.cpu1.l2cache.demand_miss_latency::cpu1.inst 523740500 # number of demand (read+write) miss cycles
1955system.cpu1.l2cache.demand_miss_latency::cpu1.data 2740113500 # number of demand (read+write) miss cycles
1956system.cpu1.l2cache.demand_miss_latency::total 3275845500 # number of demand (read+write) miss cycles
1957system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6521000 # number of overall miss cycles
1958system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5470500 # number of overall miss cycles
1959system.cpu1.l2cache.overall_miss_latency::cpu1.inst 523740500 # number of overall miss cycles
1960system.cpu1.l2cache.overall_miss_latency::cpu1.data 2740113500 # number of overall miss cycles
1961system.cpu1.l2cache.overall_miss_latency::total 3275845500 # number of overall miss cycles
1962system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3998 # number of ReadReq accesses(hits+misses)
1963system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2264 # number of ReadReq accesses(hits+misses)
1964system.cpu1.l2cache.ReadReq_accesses::total 6262 # number of ReadReq accesses(hits+misses)
1965system.cpu1.l2cache.WritebackDirty_accesses::writebacks 113054 # number of WritebackDirty accesses(hits+misses)
1966system.cpu1.l2cache.WritebackDirty_accesses::total 113054 # number of WritebackDirty accesses(hits+misses)
1967system.cpu1.l2cache.WritebackClean_accesses::writebacks 564912 # number of WritebackClean accesses(hits+misses)
1968system.cpu1.l2cache.WritebackClean_accesses::total 564912 # number of WritebackClean accesses(hits+misses)
1969system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29273 # number of UpgradeReq accesses(hits+misses)
1970system.cpu1.l2cache.UpgradeReq_accesses::total 29273 # number of UpgradeReq accesses(hits+misses)
1971system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23388 # number of SCUpgradeReq accesses(hits+misses)
1972system.cpu1.l2cache.SCUpgradeReq_accesses::total 23388 # number of SCUpgradeReq accesses(hits+misses)
1973system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
1974system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
1975system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61447 # number of ReadExReq accesses(hits+misses)
1976system.cpu1.l2cache.ReadExReq_accesses::total 61447 # number of ReadExReq accesses(hits+misses)
1977system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 504586 # number of ReadCleanReq accesses(hits+misses)
1978system.cpu1.l2cache.ReadCleanReq_accesses::total 504586 # number of ReadCleanReq accesses(hits+misses)
1979system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 167209 # number of ReadSharedReq accesses(hits+misses)
1980system.cpu1.l2cache.ReadSharedReq_accesses::total 167209 # number of ReadSharedReq accesses(hits+misses)
1981system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3998 # number of demand (read+write) accesses
1982system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2264 # number of demand (read+write) accesses
1983system.cpu1.l2cache.demand_accesses::cpu1.inst 504586 # number of demand (read+write) accesses
1984system.cpu1.l2cache.demand_accesses::cpu1.data 228656 # number of demand (read+write) accesses
1985system.cpu1.l2cache.demand_accesses::total 739504 # number of demand (read+write) accesses
1986system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3998 # number of overall (read+write) accesses
1987system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2264 # number of overall (read+write) accesses
1988system.cpu1.l2cache.overall_accesses::cpu1.inst 504586 # number of overall (read+write) accesses
1989system.cpu1.l2cache.overall_accesses::cpu1.data 228656 # number of overall (read+write) accesses
1990system.cpu1.l2cache.overall_accesses::total 739504 # number of overall (read+write) accesses
1991system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.080290 # miss rate for ReadReq accesses
1992system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.117933 # miss rate for ReadReq accesses
1993system.cpu1.l2cache.ReadReq_miss_rate::total 0.093900 # miss rate for ReadReq accesses
1994system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1995system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1996system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1997system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1998system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1999system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2000system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.558725 # miss rate for ReadExReq accesses
2001system.cpu1.l2cache.ReadExReq_miss_rate::total 0.558725 # miss rate for ReadExReq accesses
2002system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025585 # miss rate for ReadCleanReq accesses
2003system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025585 # miss rate for ReadCleanReq accesses
2004system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.401384 # miss rate for ReadSharedReq accesses
2005system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.401384 # miss rate for ReadSharedReq accesses
2006system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.080290 # miss rate for demand accesses
2007system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.117933 # miss rate for demand accesses
2008system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025585 # miss rate for demand accesses
2009system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443666 # miss rate for demand accesses
2010system.cpu1.l2cache.demand_miss_rate::total 0.155435 # miss rate for demand accesses
2011system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.080290 # miss rate for overall accesses
2012system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.117933 # miss rate for overall accesses
2013system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025585 # miss rate for overall accesses
2014system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443666 # miss rate for overall accesses
2015system.cpu1.l2cache.overall_miss_rate::total 0.155435 # miss rate for overall accesses
2016system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20314.641745 # average ReadReq miss latency
2017system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20488.764045 # average ReadReq miss latency
2018system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20393.707483 # average ReadReq miss latency
2019system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2212.362928 # average UpgradeReq miss latency
2020system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2212.362928 # average UpgradeReq miss latency
2021system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1449.504019 # average SCUpgradeReq miss latency
2022system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1449.504019 # average SCUpgradeReq miss latency
2023system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 922999.333333 # average SCUpgradeFailReq miss latency
2024system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 922999.333333 # average SCUpgradeFailReq miss latency
2025system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36731.038099 # average ReadExReq miss latency
2026system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36731.038099 # average ReadExReq miss latency
2027system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40568.590240 # average ReadCleanReq miss latency
2028system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40568.590240 # average ReadCleanReq miss latency
2029system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22037.748640 # average ReadSharedReq miss latency
2030system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22037.748640 # average ReadSharedReq miss latency
2031system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20314.641745 # average overall miss latency
2032system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20488.764045 # average overall miss latency
2033system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40568.590240 # average overall miss latency
2034system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27010.296017 # average overall miss latency
2035system.cpu1.l2cache.demand_avg_miss_latency::total 28499.243116 # average overall miss latency
2036system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20314.641745 # average overall miss latency
2037system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20488.764045 # average overall miss latency
2038system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40568.590240 # average overall miss latency
2039system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27010.296017 # average overall miss latency
2040system.cpu1.l2cache.overall_avg_miss_latency::total 28499.243116 # average overall miss latency
2041system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2042system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2043system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2044system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2045system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2046system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2047system.cpu1.l2cache.unused_prefetches 741 # number of HardPF blocks evicted w/o reference
2048system.cpu1.l2cache.writebacks::writebacks 28109 # number of writebacks
2049system.cpu1.l2cache.writebacks::total 28109 # number of writebacks
2050system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 75 # number of ReadExReq MSHR hits
2051system.cpu1.l2cache.ReadExReq_mshr_hits::total 75 # number of ReadExReq MSHR hits
2052system.cpu1.l2cache.demand_mshr_hits::cpu1.data 75 # number of demand (read+write) MSHR hits
2053system.cpu1.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
2054system.cpu1.l2cache.overall_mshr_hits::cpu1.data 75 # number of overall MSHR hits
2055system.cpu1.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
2056system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 321 # number of ReadReq MSHR misses
2057system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 267 # number of ReadReq MSHR misses
2058system.cpu1.l2cache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses
2059system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23341 # number of HardPFReq MSHR misses
2060system.cpu1.l2cache.HardPFReq_mshr_misses::total 23341 # number of HardPFReq MSHR misses
2061system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29273 # number of UpgradeReq MSHR misses
2062system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29273 # number of UpgradeReq MSHR misses
2063system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23388 # number of SCUpgradeReq MSHR misses
2064system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23388 # number of SCUpgradeReq MSHR misses
2065system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
2066system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
2067system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34257 # number of ReadExReq MSHR misses
2068system.cpu1.l2cache.ReadExReq_mshr_misses::total 34257 # number of ReadExReq MSHR misses
2069system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 12910 # number of ReadCleanReq MSHR misses
2070system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 12910 # number of ReadCleanReq MSHR misses
2071system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 67115 # number of ReadSharedReq MSHR misses
2072system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 67115 # number of ReadSharedReq MSHR misses
2073system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 321 # number of demand (read+write) MSHR misses
2074system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 267 # number of demand (read+write) MSHR misses
2075system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 12910 # number of demand (read+write) MSHR misses
2076system.cpu1.l2cache.demand_mshr_misses::cpu1.data 101372 # number of demand (read+write) MSHR misses
2077system.cpu1.l2cache.demand_mshr_misses::total 114870 # number of demand (read+write) MSHR misses
2078system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 321 # number of overall MSHR misses
2079system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 267 # number of overall MSHR misses
2080system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 12910 # number of overall MSHR misses
2081system.cpu1.l2cache.overall_mshr_misses::cpu1.data 101372 # number of overall MSHR misses
2082system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23341 # number of overall MSHR misses
2083system.cpu1.l2cache.overall_mshr_misses::total 138211 # number of overall MSHR misses
2084system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2085system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 13772 # number of ReadReq MSHR uncacheable
2086system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 13949 # number of ReadReq MSHR uncacheable
2087system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable
2088system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11224 # number of WriteReq MSHR uncacheable
2089system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2090system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 24996 # number of overall MSHR uncacheable misses
2091system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 25173 # number of overall MSHR uncacheable misses
2092system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4595000 # number of ReadReq MSHR miss cycles
2093system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3868500 # number of ReadReq MSHR miss cycles
2094system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8463500 # number of ReadReq MSHR miss cycles
2095system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 732704788 # number of HardPFReq MSHR miss cycles
2096system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 732704788 # number of HardPFReq MSHR miss cycles
2097system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 486199500 # number of UpgradeReq MSHR miss cycles
2098system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 486199500 # number of UpgradeReq MSHR miss cycles
2099system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 373432500 # number of SCUpgradeReq MSHR miss cycles
2100system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 373432500 # number of SCUpgradeReq MSHR miss cycles
2101system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2474998 # number of SCUpgradeFailReq MSHR miss cycles
2102system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2474998 # number of SCUpgradeFailReq MSHR miss cycles
2103system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1046225500 # number of ReadExReq MSHR miss cycles
2104system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1046225500 # number of ReadExReq MSHR miss cycles
2105system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 446280500 # number of ReadCleanReq MSHR miss cycles
2106system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 446280500 # number of ReadCleanReq MSHR miss cycles
2107system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1076373500 # number of ReadSharedReq MSHR miss cycles
2108system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1076373500 # number of ReadSharedReq MSHR miss cycles
2109system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4595000 # number of demand (read+write) MSHR miss cycles
2110system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3868500 # number of demand (read+write) MSHR miss cycles
2111system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 446280500 # number of demand (read+write) MSHR miss cycles
2112system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2122599000 # number of demand (read+write) MSHR miss cycles
2113system.cpu1.l2cache.demand_mshr_miss_latency::total 2577343000 # number of demand (read+write) MSHR miss cycles
2114system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4595000 # number of overall MSHR miss cycles
2115system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3868500 # number of overall MSHR miss cycles
2116system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 446280500 # number of overall MSHR miss cycles
2117system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2122599000 # number of overall MSHR miss cycles
2118system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 732704788 # number of overall MSHR miss cycles
2119system.cpu1.l2cache.overall_mshr_miss_latency::total 3310047788 # number of overall MSHR miss cycles
2120system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14449000 # number of ReadReq MSHR uncacheable cycles
2121system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2282145500 # number of ReadReq MSHR uncacheable cycles
2122system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2296594500 # number of ReadReq MSHR uncacheable cycles
2123system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14449000 # number of overall MSHR uncacheable cycles
2124system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2282145500 # number of overall MSHR uncacheable cycles
2125system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2296594500 # number of overall MSHR uncacheable cycles
2126system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.080290 # mshr miss rate for ReadReq accesses
2127system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.117933 # mshr miss rate for ReadReq accesses
2128system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.093900 # mshr miss rate for ReadReq accesses
2129system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2130system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2131system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2132system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2133system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2134system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2135system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2136system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2137system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.557505 # mshr miss rate for ReadExReq accesses
2138system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.557505 # mshr miss rate for ReadExReq accesses
2139system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.025585 # mshr miss rate for ReadCleanReq accesses
2140system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.025585 # mshr miss rate for ReadCleanReq accesses
2141system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.401384 # mshr miss rate for ReadSharedReq accesses
2142system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.401384 # mshr miss rate for ReadSharedReq accesses
2143system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.080290 # mshr miss rate for demand accesses
2144system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.117933 # mshr miss rate for demand accesses
2145system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025585 # mshr miss rate for demand accesses
2146system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443338 # mshr miss rate for demand accesses
2147system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155334 # mshr miss rate for demand accesses
2148system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.080290 # mshr miss rate for overall accesses
2149system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.117933 # mshr miss rate for overall accesses
2150system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025585 # mshr miss rate for overall accesses
2151system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443338 # mshr miss rate for overall accesses
2152system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2153system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186897 # mshr miss rate for overall accesses
2154system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average ReadReq mshr miss latency
2155system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average ReadReq mshr miss latency
2156system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14393.707483 # average ReadReq mshr miss latency
2157system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31391.319481 # average HardPFReq mshr miss latency
2158system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31391.319481 # average HardPFReq mshr miss latency
2159system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16609.144946 # average UpgradeReq mshr miss latency
2160system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16609.144946 # average UpgradeReq mshr miss latency
2161system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15966.841970 # average SCUpgradeReq mshr miss latency
2162system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15966.841970 # average SCUpgradeReq mshr miss latency
2163system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 824999.333333 # average SCUpgradeFailReq mshr miss latency
2164system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 824999.333333 # average SCUpgradeFailReq mshr miss latency
2165system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30540.488075 # average ReadExReq mshr miss latency
2166system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30540.488075 # average ReadExReq mshr miss latency
2167system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average ReadCleanReq mshr miss latency
2168system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34568.590240 # average ReadCleanReq mshr miss latency
2169system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16037.748640 # average ReadSharedReq mshr miss latency
2170system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16037.748640 # average ReadSharedReq mshr miss latency
2171system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average overall mshr miss latency
2172system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average overall mshr miss latency
2173system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average overall mshr miss latency
2174system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20938.710887 # average overall mshr miss latency
2175system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22437.041873 # average overall mshr miss latency
2176system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14314.641745 # average overall mshr miss latency
2177system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14488.764045 # average overall mshr miss latency
2178system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34568.590240 # average overall mshr miss latency
2179system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20938.710887 # average overall mshr miss latency
2180system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31391.319481 # average overall mshr miss latency
2181system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23949.235502 # average overall mshr miss latency
2182system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency
2183system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165709.083648 # average ReadReq mshr uncacheable latency
2184system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164642.232418 # average ReadReq mshr uncacheable latency
2185system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency
2186system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91300.428068 # average overall mshr uncacheable latency
2187system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91232.451436 # average overall mshr uncacheable latency
2188system.cpu1.toL2Bus.snoop_filter.tot_requests 1481374 # Total number of requests made to the snoop filter.
2189system.cpu1.toL2Bus.snoop_filter.hit_single_requests 748184 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2190system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11076 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2191system.cpu1.toL2Bus.snoop_filter.tot_snoops 177406 # Total number of snoops made to the snoop filter.
2192system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 174791 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2193system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2615 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2194system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2195system.cpu1.toL2Bus.trans_dist::ReadReq 23242 # Transaction distribution
2196system.cpu1.toL2Bus.trans_dist::ReadResp 733434 # Transaction distribution
2197system.cpu1.toL2Bus.trans_dist::WriteReq 11224 # Transaction distribution
2198system.cpu1.toL2Bus.trans_dist::WriteResp 11224 # Transaction distribution
2199system.cpu1.toL2Bus.trans_dist::WritebackDirty 142093 # Transaction distribution
2200system.cpu1.toL2Bus.trans_dist::WritebackClean 575988 # Transaction distribution
2201system.cpu1.toL2Bus.trans_dist::CleanEvict 98729 # Transaction distribution
2202system.cpu1.toL2Bus.trans_dist::HardPFReq 27772 # Transaction distribution
2203system.cpu1.toL2Bus.trans_dist::UpgradeReq 72921 # Transaction distribution
2204system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41250 # Transaction distribution
2205system.cpu1.toL2Bus.trans_dist::UpgradeResp 85602 # Transaction distribution
2206system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
2207system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution
2208system.cpu1.toL2Bus.trans_dist::ReadExReq 69150 # Transaction distribution
2209system.cpu1.toL2Bus.trans_dist::ReadExResp 66171 # Transaction distribution
2210system.cpu1.toL2Bus.trans_dist::ReadCleanReq 504586 # Transaction distribution
2211system.cpu1.toL2Bus.trans_dist::ReadSharedReq 246891 # Transaction distribution
2212system.cpu1.toL2Bus.trans_dist::InvalidateReq 241 # Transaction distribution
2213system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1513600 # Packet count per connected master and slave (bytes)
2214system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 873749 # Packet count per connected master and slave (bytes)
2215system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5588 # Packet count per connected master and slave (bytes)
2216system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9967 # Packet count per connected master and slave (bytes)
2217system.cpu1.toL2Bus.pkt_count::total 2402904 # Packet count per connected master and slave (bytes)
2218system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64554948 # Cumulative packet size per connected master and slave (bytes)
2219system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29333690 # Cumulative packet size per connected master and slave (bytes)
2220system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9056 # Cumulative packet size per connected master and slave (bytes)
2221system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 15992 # Cumulative packet size per connected master and slave (bytes)
2222system.cpu1.toL2Bus.pkt_size::total 93913686 # Cumulative packet size per connected master and slave (bytes)
2223system.cpu1.toL2Bus.snoops 383897 # Total snoops (count)
2224system.cpu1.toL2Bus.snoopTraffic 4632988 # Total snoop traffic (bytes)
2225system.cpu1.toL2Bus.snoop_fanout::samples 1125089 # Request fanout histogram
2226system.cpu1.toL2Bus.snoop_fanout::mean 0.175565 # Request fanout histogram
2227system.cpu1.toL2Bus.snoop_fanout::stdev 0.386511 # Request fanout histogram
2228system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2229system.cpu1.toL2Bus.snoop_fanout::0 930178 82.68% 82.68% # Request fanout histogram
2230system.cpu1.toL2Bus.snoop_fanout::1 192296 17.09% 99.77% # Request fanout histogram
2231system.cpu1.toL2Bus.snoop_fanout::2 2615 0.23% 100.00% # Request fanout histogram
2232system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2233system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2234system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2235system.cpu1.toL2Bus.snoop_fanout::total 1125089 # Request fanout histogram
2236system.cpu1.toL2Bus.reqLayer0.occupancy 1449361998 # Layer occupancy (ticks)
2237system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2238system.cpu1.toL2Bus.snoopLayer0.occupancy 81273182 # Layer occupancy (ticks)
2239system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2240system.cpu1.toL2Bus.respLayer0.occupancy 757056000 # Layer occupancy (ticks)
2241system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2242system.cpu1.toL2Bus.respLayer1.occupancy 388749000 # Layer occupancy (ticks)
2243system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2244system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks)
2245system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2246system.cpu1.toL2Bus.respLayer3.occupancy 5969499 # Layer occupancy (ticks)
2247system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2248system.iobus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2249system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
2250system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
2251system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
2252system.iobus.trans_dist::WriteResp 59421 # Transaction distribution
2253system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
2254system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2255system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2256system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2257system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2258system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2259system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2260system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2261system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2262system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2263system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2264system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2265system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2266system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2267system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2268system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2269system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2270system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2271system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2272system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes)
2273system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
2274system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
2275system.iobus.pkt_count::total 180872 # Packet count per connected master and slave (bytes)
2276system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
2277system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2278system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2279system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2280system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2281system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2282system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2283system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2284system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2285system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2286system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2287system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2288system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2289system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2290system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2291system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2292system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2293system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2294system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2295system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
2296system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
2297system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
2298system.iobus.pkt_size::total 2484066 # Cumulative packet size per connected master and slave (bytes)
2299system.iobus.reqLayer0.occupancy 48725500 # Layer occupancy (ticks)
2300system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2301system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks)
2302system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2303system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks)
2304system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2305system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks)
2306system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2307system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks)
2308system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2309system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks)
2310system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2311system.iobus.reqLayer8.occupancy 599000 # Layer occupancy (ticks)
2312system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2313system.iobus.reqLayer10.occupancy 23000 # Layer occupancy (ticks)
2314system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2315system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks)
2316system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2317system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks)
2318system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2319system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks)
2320system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2321system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks)
2322system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2323system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
2324system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2325system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
2326system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2327system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2328system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2329system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2330system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2331system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks)
2332system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2333system.iobus.reqLayer23.occupancy 6153000 # Layer occupancy (ticks)
2334system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2335system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks)
2336system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2337system.iobus.reqLayer25.occupancy 187736829 # Layer occupancy (ticks)
2338system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2339system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks)
2340system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2341system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
2342system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2343system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2344system.iocache.tags.replacements 36445 # number of replacements
2345system.iocache.tags.tagsinuse 14.386581 # Cycle average of tags in use
2346system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2347system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
2348system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2349system.iocache.tags.warmup_cycle 289188615000 # Cycle when the warmup percentage was hit.
2350system.iocache.tags.occ_blocks::realview.ide 14.386581 # Average occupied blocks per requestor
2351system.iocache.tags.occ_percent::realview.ide 0.899161 # Average percentage of cache occupancy
2352system.iocache.tags.occ_percent::total 0.899161 # Average percentage of cache occupancy
2353system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2354system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2355system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2356system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2357system.iocache.tags.data_accesses 328311 # Number of data accesses
2358system.iocache.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2359system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2360system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2361system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2362system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2363system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
2364system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
2365system.iocache.overall_misses::realview.ide 36479 # number of overall misses
2366system.iocache.overall_misses::total 36479 # number of overall misses
2367system.iocache.ReadReq_miss_latency::realview.ide 35445377 # number of ReadReq miss cycles
2368system.iocache.ReadReq_miss_latency::total 35445377 # number of ReadReq miss cycles
2369system.iocache.WriteLineReq_miss_latency::realview.ide 4303608452 # number of WriteLineReq miss cycles
2370system.iocache.WriteLineReq_miss_latency::total 4303608452 # number of WriteLineReq miss cycles
2371system.iocache.demand_miss_latency::realview.ide 4339053829 # number of demand (read+write) miss cycles
2372system.iocache.demand_miss_latency::total 4339053829 # number of demand (read+write) miss cycles
2373system.iocache.overall_miss_latency::realview.ide 4339053829 # number of overall miss cycles
2374system.iocache.overall_miss_latency::total 4339053829 # number of overall miss cycles
2375system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2376system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2377system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2378system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2379system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
2380system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
2381system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
2382system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
2383system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2384system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2385system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2386system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2387system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2388system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2389system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2390system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2391system.iocache.ReadReq_avg_miss_latency::realview.ide 139001.478431 # average ReadReq miss latency
2392system.iocache.ReadReq_avg_miss_latency::total 139001.478431 # average ReadReq miss latency
2393system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.445340 # average WriteLineReq miss latency
2394system.iocache.WriteLineReq_avg_miss_latency::total 118805.445340 # average WriteLineReq miss latency
2395system.iocache.demand_avg_miss_latency::realview.ide 118946.622139 # average overall miss latency
2396system.iocache.demand_avg_miss_latency::total 118946.622139 # average overall miss latency
2397system.iocache.overall_avg_miss_latency::realview.ide 118946.622139 # average overall miss latency
2398system.iocache.overall_avg_miss_latency::total 118946.622139 # average overall miss latency
2399system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked
2400system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2401system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked
2402system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2403system.iocache.avg_blocked_cycles::no_mshrs 3.750000 # average number of cycles each access was blocked
2404system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2405system.iocache.writebacks::writebacks 36190 # number of writebacks
2406system.iocache.writebacks::total 36190 # number of writebacks
2407system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2408system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2409system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2410system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2411system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
2412system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
2413system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
2414system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
2415system.iocache.ReadReq_mshr_miss_latency::realview.ide 22695377 # number of ReadReq MSHR miss cycles
2416system.iocache.ReadReq_mshr_miss_latency::total 22695377 # number of ReadReq MSHR miss cycles
2417system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490051224 # number of WriteLineReq MSHR miss cycles
2418system.iocache.WriteLineReq_mshr_miss_latency::total 2490051224 # number of WriteLineReq MSHR miss cycles
2419system.iocache.demand_mshr_miss_latency::realview.ide 2512746601 # number of demand (read+write) MSHR miss cycles
2420system.iocache.demand_mshr_miss_latency::total 2512746601 # number of demand (read+write) MSHR miss cycles
2421system.iocache.overall_mshr_miss_latency::realview.ide 2512746601 # number of overall MSHR miss cycles
2422system.iocache.overall_mshr_miss_latency::total 2512746601 # number of overall MSHR miss cycles
2423system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2424system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2425system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2426system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2427system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2428system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2429system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2430system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2431system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 89001.478431 # average ReadReq mshr miss latency
2432system.iocache.ReadReq_avg_mshr_miss_latency::total 89001.478431 # average ReadReq mshr miss latency
2433system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.371687 # average WriteLineReq mshr miss latency
2434system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.371687 # average WriteLineReq mshr miss latency
2435system.iocache.demand_avg_mshr_miss_latency::realview.ide 68882.003372 # average overall mshr miss latency
2436system.iocache.demand_avg_mshr_miss_latency::total 68882.003372 # average overall mshr miss latency
2437system.iocache.overall_avg_mshr_miss_latency::realview.ide 68882.003372 # average overall mshr miss latency
2438system.iocache.overall_avg_mshr_miss_latency::total 68882.003372 # average overall mshr miss latency
2439system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2440system.l2c.tags.replacements 119266 # number of replacements
2441system.l2c.tags.tagsinuse 63150.928665 # Cycle average of tags in use
2442system.l2c.tags.total_refs 419498 # Total number of references to valid blocks.
2443system.l2c.tags.sampled_refs 183131 # Sample count of references to valid blocks.
2444system.l2c.tags.avg_refs 2.290699 # Average number of references to valid blocks.
2445system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2446system.l2c.tags.occ_blocks::writebacks 13441.811145 # Average occupied blocks per requestor
2447system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.006326 # Average occupied blocks per requestor
2448system.l2c.tags.occ_blocks::cpu0.itb.walker 0.055729 # Average occupied blocks per requestor
2449system.l2c.tags.occ_blocks::cpu0.inst 7581.242495 # Average occupied blocks per requestor
2450system.l2c.tags.occ_blocks::cpu0.data 2905.326286 # Average occupied blocks per requestor
2451system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35913.296254 # Average occupied blocks per requestor
2452system.l2c.tags.occ_blocks::cpu1.inst 1514.615308 # Average occupied blocks per requestor
2453system.l2c.tags.occ_blocks::cpu1.data 303.672578 # Average occupied blocks per requestor
2454system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1486.902543 # Average occupied blocks per requestor
2455system.l2c.tags.occ_percent::writebacks 0.205106 # Average percentage of cache occupancy
2456system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy
2457system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2458system.l2c.tags.occ_percent::cpu0.inst 0.115681 # Average percentage of cache occupancy
2459system.l2c.tags.occ_percent::cpu0.data 0.044332 # Average percentage of cache occupancy
2460system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.547993 # Average percentage of cache occupancy
2461system.l2c.tags.occ_percent::cpu1.inst 0.023111 # Average percentage of cache occupancy
2462system.l2c.tags.occ_percent::cpu1.data 0.004634 # Average percentage of cache occupancy
2463system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022688 # Average percentage of cache occupancy
2464system.l2c.tags.occ_percent::total 0.963607 # Average percentage of cache occupancy
2465system.l2c.tags.occ_task_id_blocks::1022 30886 # Occupied blocks per task id
2466system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
2467system.l2c.tags.occ_task_id_blocks::1024 32974 # Occupied blocks per task id
2468system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
2469system.l2c.tags.age_task_id_blocks_1022::2 76 # Occupied blocks per task id
2470system.l2c.tags.age_task_id_blocks_1022::3 4718 # Occupied blocks per task id
2471system.l2c.tags.age_task_id_blocks_1022::4 26088 # Occupied blocks per task id
2472system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
2473system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
2474system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
2475system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id
2476system.l2c.tags.age_task_id_blocks_1024::3 2232 # Occupied blocks per task id
2477system.l2c.tags.age_task_id_blocks_1024::4 30425 # Occupied blocks per task id
2478system.l2c.tags.occ_task_id_percent::1022 0.471283 # Percentage of cache occupancy per task id
2479system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
2480system.l2c.tags.occ_task_id_percent::1024 0.503143 # Percentage of cache occupancy per task id
2481system.l2c.tags.tag_accesses 5778594 # Number of tag accesses
2482system.l2c.tags.data_accesses 5778594 # Number of data accesses
2483system.l2c.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2484system.l2c.WritebackDirty_hits::writebacks 255647 # number of WritebackDirty hits
2485system.l2c.WritebackDirty_hits::total 255647 # number of WritebackDirty hits
2486system.l2c.UpgradeReq_hits::cpu0.data 32152 # number of UpgradeReq hits
2487system.l2c.UpgradeReq_hits::cpu1.data 2169 # number of UpgradeReq hits
2488system.l2c.UpgradeReq_hits::total 34321 # number of UpgradeReq hits
2489system.l2c.SCUpgradeReq_hits::cpu0.data 2017 # number of SCUpgradeReq hits
2490system.l2c.SCUpgradeReq_hits::cpu1.data 1011 # number of SCUpgradeReq hits
2491system.l2c.SCUpgradeReq_hits::total 3028 # number of SCUpgradeReq hits
2492system.l2c.ReadExReq_hits::cpu0.data 4187 # number of ReadExReq hits
2493system.l2c.ReadExReq_hits::cpu1.data 1790 # number of ReadExReq hits
2494system.l2c.ReadExReq_hits::total 5977 # number of ReadExReq hits
2495system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 77 # number of ReadSharedReq hits
2496system.l2c.ReadSharedReq_hits::cpu0.itb.walker 85 # number of ReadSharedReq hits
2497system.l2c.ReadSharedReq_hits::cpu0.inst 27265 # number of ReadSharedReq hits
2498system.l2c.ReadSharedReq_hits::cpu0.data 45372 # number of ReadSharedReq hits
2499system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46765 # number of ReadSharedReq hits
2500system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 37 # number of ReadSharedReq hits
2501system.l2c.ReadSharedReq_hits::cpu1.itb.walker 32 # number of ReadSharedReq hits
2502system.l2c.ReadSharedReq_hits::cpu1.inst 10614 # number of ReadSharedReq hits
2503system.l2c.ReadSharedReq_hits::cpu1.data 8420 # number of ReadSharedReq hits
2504system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4646 # number of ReadSharedReq hits
2505system.l2c.ReadSharedReq_hits::total 143313 # number of ReadSharedReq hits
2506system.l2c.demand_hits::cpu0.dtb.walker 77 # number of demand (read+write) hits
2507system.l2c.demand_hits::cpu0.itb.walker 85 # number of demand (read+write) hits
2508system.l2c.demand_hits::cpu0.inst 27265 # number of demand (read+write) hits
2509system.l2c.demand_hits::cpu0.data 49559 # number of demand (read+write) hits
2510system.l2c.demand_hits::cpu0.l2cache.prefetcher 46765 # number of demand (read+write) hits
2511system.l2c.demand_hits::cpu1.dtb.walker 37 # number of demand (read+write) hits
2512system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits
2513system.l2c.demand_hits::cpu1.inst 10614 # number of demand (read+write) hits
2514system.l2c.demand_hits::cpu1.data 10210 # number of demand (read+write) hits
2515system.l2c.demand_hits::cpu1.l2cache.prefetcher 4646 # number of demand (read+write) hits
2516system.l2c.demand_hits::total 149290 # number of demand (read+write) hits
2517system.l2c.overall_hits::cpu0.dtb.walker 77 # number of overall hits
2518system.l2c.overall_hits::cpu0.itb.walker 85 # number of overall hits
2519system.l2c.overall_hits::cpu0.inst 27265 # number of overall hits
2520system.l2c.overall_hits::cpu0.data 49559 # number of overall hits
2521system.l2c.overall_hits::cpu0.l2cache.prefetcher 46765 # number of overall hits
2522system.l2c.overall_hits::cpu1.dtb.walker 37 # number of overall hits
2523system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits
2524system.l2c.overall_hits::cpu1.inst 10614 # number of overall hits
2525system.l2c.overall_hits::cpu1.data 10210 # number of overall hits
2526system.l2c.overall_hits::cpu1.l2cache.prefetcher 4646 # number of overall hits
2527system.l2c.overall_hits::total 149290 # number of overall hits
2528system.l2c.UpgradeReq_misses::cpu0.data 8829 # number of UpgradeReq misses
2529system.l2c.UpgradeReq_misses::cpu1.data 2766 # number of UpgradeReq misses
2530system.l2c.UpgradeReq_misses::total 11595 # number of UpgradeReq misses
2531system.l2c.SCUpgradeReq_misses::cpu0.data 562 # number of SCUpgradeReq misses
2532system.l2c.SCUpgradeReq_misses::cpu1.data 1350 # number of SCUpgradeReq misses
2533system.l2c.SCUpgradeReq_misses::total 1912 # number of SCUpgradeReq misses
2534system.l2c.ReadExReq_misses::cpu0.data 10910 # number of ReadExReq misses
2535system.l2c.ReadExReq_misses::cpu1.data 7277 # number of ReadExReq misses
2536system.l2c.ReadExReq_misses::total 18187 # number of ReadExReq misses
2537system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses
2538system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
2539system.l2c.ReadSharedReq_misses::cpu0.inst 17445 # number of ReadSharedReq misses
2540system.l2c.ReadSharedReq_misses::cpu0.data 8731 # number of ReadSharedReq misses
2541system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130401 # number of ReadSharedReq misses
2542system.l2c.ReadSharedReq_misses::cpu1.inst 2296 # number of ReadSharedReq misses
2543system.l2c.ReadSharedReq_misses::cpu1.data 718 # number of ReadSharedReq misses
2544system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5545 # number of ReadSharedReq misses
2545system.l2c.ReadSharedReq_misses::total 165145 # number of ReadSharedReq misses
2546system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
2547system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
2548system.l2c.demand_misses::cpu0.inst 17445 # number of demand (read+write) misses
2549system.l2c.demand_misses::cpu0.data 19641 # number of demand (read+write) misses
2550system.l2c.demand_misses::cpu0.l2cache.prefetcher 130401 # number of demand (read+write) misses
2551system.l2c.demand_misses::cpu1.inst 2296 # number of demand (read+write) misses
2552system.l2c.demand_misses::cpu1.data 7995 # number of demand (read+write) misses
2553system.l2c.demand_misses::cpu1.l2cache.prefetcher 5545 # number of demand (read+write) misses
2554system.l2c.demand_misses::total 183332 # number of demand (read+write) misses
2555system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
2556system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
2557system.l2c.overall_misses::cpu0.inst 17445 # number of overall misses
2558system.l2c.overall_misses::cpu0.data 19641 # number of overall misses
2559system.l2c.overall_misses::cpu0.l2cache.prefetcher 130401 # number of overall misses
2560system.l2c.overall_misses::cpu1.inst 2296 # number of overall misses
2561system.l2c.overall_misses::cpu1.data 7995 # number of overall misses
2562system.l2c.overall_misses::cpu1.l2cache.prefetcher 5545 # number of overall misses
2563system.l2c.overall_misses::total 183332 # number of overall misses
2564system.l2c.UpgradeReq_miss_latency::cpu0.data 14927000 # number of UpgradeReq miss cycles
2565system.l2c.UpgradeReq_miss_latency::cpu1.data 2436000 # number of UpgradeReq miss cycles
2566system.l2c.UpgradeReq_miss_latency::total 17363000 # number of UpgradeReq miss cycles
2567system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1977500 # number of SCUpgradeReq miss cycles
2568system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1602000 # number of SCUpgradeReq miss cycles
2569system.l2c.SCUpgradeReq_miss_latency::total 3579500 # number of SCUpgradeReq miss cycles
2570system.l2c.ReadExReq_miss_latency::cpu0.data 1046073500 # number of ReadExReq miss cycles
2571system.l2c.ReadExReq_miss_latency::cpu1.data 591480500 # number of ReadExReq miss cycles
2572system.l2c.ReadExReq_miss_latency::total 1637554000 # number of ReadExReq miss cycles
2573system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 605500 # number of ReadSharedReq miss cycles
2574system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 174000 # number of ReadSharedReq miss cycles
2575system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1424566500 # number of ReadSharedReq miss cycles
2576system.l2c.ReadSharedReq_miss_latency::cpu0.data 766776000 # number of ReadSharedReq miss cycles
2577system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12582000643 # number of ReadSharedReq miss cycles
2578system.l2c.ReadSharedReq_miss_latency::cpu1.inst 188965500 # number of ReadSharedReq miss cycles
2579system.l2c.ReadSharedReq_miss_latency::cpu1.data 64274000 # number of ReadSharedReq miss cycles
2580system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 624236555 # number of ReadSharedReq miss cycles
2581system.l2c.ReadSharedReq_miss_latency::total 15651598698 # number of ReadSharedReq miss cycles
2582system.l2c.demand_miss_latency::cpu0.dtb.walker 605500 # number of demand (read+write) miss cycles
2583system.l2c.demand_miss_latency::cpu0.itb.walker 174000 # number of demand (read+write) miss cycles
2584system.l2c.demand_miss_latency::cpu0.inst 1424566500 # number of demand (read+write) miss cycles
2585system.l2c.demand_miss_latency::cpu0.data 1812849500 # number of demand (read+write) miss cycles
2586system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12582000643 # number of demand (read+write) miss cycles
2587system.l2c.demand_miss_latency::cpu1.inst 188965500 # number of demand (read+write) miss cycles
2588system.l2c.demand_miss_latency::cpu1.data 655754500 # number of demand (read+write) miss cycles
2589system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 624236555 # number of demand (read+write) miss cycles
2590system.l2c.demand_miss_latency::total 17289152698 # number of demand (read+write) miss cycles
2591system.l2c.overall_miss_latency::cpu0.dtb.walker 605500 # number of overall miss cycles
2592system.l2c.overall_miss_latency::cpu0.itb.walker 174000 # number of overall miss cycles
2593system.l2c.overall_miss_latency::cpu0.inst 1424566500 # number of overall miss cycles
2594system.l2c.overall_miss_latency::cpu0.data 1812849500 # number of overall miss cycles
2595system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12582000643 # number of overall miss cycles
2596system.l2c.overall_miss_latency::cpu1.inst 188965500 # number of overall miss cycles
2597system.l2c.overall_miss_latency::cpu1.data 655754500 # number of overall miss cycles
2598system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 624236555 # number of overall miss cycles
2599system.l2c.overall_miss_latency::total 17289152698 # number of overall miss cycles
2600system.l2c.WritebackDirty_accesses::writebacks 255647 # number of WritebackDirty accesses(hits+misses)
2601system.l2c.WritebackDirty_accesses::total 255647 # number of WritebackDirty accesses(hits+misses)
2602system.l2c.UpgradeReq_accesses::cpu0.data 40981 # number of UpgradeReq accesses(hits+misses)
2603system.l2c.UpgradeReq_accesses::cpu1.data 4935 # number of UpgradeReq accesses(hits+misses)
2604system.l2c.UpgradeReq_accesses::total 45916 # number of UpgradeReq accesses(hits+misses)
2605system.l2c.SCUpgradeReq_accesses::cpu0.data 2579 # number of SCUpgradeReq accesses(hits+misses)
2606system.l2c.SCUpgradeReq_accesses::cpu1.data 2361 # number of SCUpgradeReq accesses(hits+misses)
2607system.l2c.SCUpgradeReq_accesses::total 4940 # number of SCUpgradeReq accesses(hits+misses)
2608system.l2c.ReadExReq_accesses::cpu0.data 15097 # number of ReadExReq accesses(hits+misses)
2609system.l2c.ReadExReq_accesses::cpu1.data 9067 # number of ReadExReq accesses(hits+misses)
2610system.l2c.ReadExReq_accesses::total 24164 # number of ReadExReq accesses(hits+misses)
2611system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 84 # number of ReadSharedReq accesses(hits+misses)
2612system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 87 # number of ReadSharedReq accesses(hits+misses)
2613system.l2c.ReadSharedReq_accesses::cpu0.inst 44710 # number of ReadSharedReq accesses(hits+misses)
2614system.l2c.ReadSharedReq_accesses::cpu0.data 54103 # number of ReadSharedReq accesses(hits+misses)
2615system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177166 # number of ReadSharedReq accesses(hits+misses)
2616system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 37 # number of ReadSharedReq accesses(hits+misses)
2617system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 32 # number of ReadSharedReq accesses(hits+misses)
2618system.l2c.ReadSharedReq_accesses::cpu1.inst 12910 # number of ReadSharedReq accesses(hits+misses)
2619system.l2c.ReadSharedReq_accesses::cpu1.data 9138 # number of ReadSharedReq accesses(hits+misses)
2620system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 10191 # number of ReadSharedReq accesses(hits+misses)
2621system.l2c.ReadSharedReq_accesses::total 308458 # number of ReadSharedReq accesses(hits+misses)
2622system.l2c.demand_accesses::cpu0.dtb.walker 84 # number of demand (read+write) accesses
2623system.l2c.demand_accesses::cpu0.itb.walker 87 # number of demand (read+write) accesses
2624system.l2c.demand_accesses::cpu0.inst 44710 # number of demand (read+write) accesses
2625system.l2c.demand_accesses::cpu0.data 69200 # number of demand (read+write) accesses
2626system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177166 # number of demand (read+write) accesses
2627system.l2c.demand_accesses::cpu1.dtb.walker 37 # number of demand (read+write) accesses
2628system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses
2629system.l2c.demand_accesses::cpu1.inst 12910 # number of demand (read+write) accesses
2630system.l2c.demand_accesses::cpu1.data 18205 # number of demand (read+write) accesses
2631system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10191 # number of demand (read+write) accesses
2632system.l2c.demand_accesses::total 332622 # number of demand (read+write) accesses
2633system.l2c.overall_accesses::cpu0.dtb.walker 84 # number of overall (read+write) accesses
2634system.l2c.overall_accesses::cpu0.itb.walker 87 # number of overall (read+write) accesses
2635system.l2c.overall_accesses::cpu0.inst 44710 # number of overall (read+write) accesses
2636system.l2c.overall_accesses::cpu0.data 69200 # number of overall (read+write) accesses
2637system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177166 # number of overall (read+write) accesses
2638system.l2c.overall_accesses::cpu1.dtb.walker 37 # number of overall (read+write) accesses
2639system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses
2640system.l2c.overall_accesses::cpu1.inst 12910 # number of overall (read+write) accesses
2641system.l2c.overall_accesses::cpu1.data 18205 # number of overall (read+write) accesses
2642system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10191 # number of overall (read+write) accesses
2643system.l2c.overall_accesses::total 332622 # number of overall (read+write) accesses
2644system.l2c.UpgradeReq_miss_rate::cpu0.data 0.215441 # miss rate for UpgradeReq accesses
2645system.l2c.UpgradeReq_miss_rate::cpu1.data 0.560486 # miss rate for UpgradeReq accesses
2646system.l2c.UpgradeReq_miss_rate::total 0.252526 # miss rate for UpgradeReq accesses
2647system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.217914 # miss rate for SCUpgradeReq accesses
2648system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.571792 # miss rate for SCUpgradeReq accesses
2649system.l2c.SCUpgradeReq_miss_rate::total 0.387045 # miss rate for SCUpgradeReq accesses
2650system.l2c.ReadExReq_miss_rate::cpu0.data 0.722660 # miss rate for ReadExReq accesses
2651system.l2c.ReadExReq_miss_rate::cpu1.data 0.802581 # miss rate for ReadExReq accesses
2652system.l2c.ReadExReq_miss_rate::total 0.752649 # miss rate for ReadExReq accesses
2653system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.083333 # miss rate for ReadSharedReq accesses
2654system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.022989 # miss rate for ReadSharedReq accesses
2655system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.390181 # miss rate for ReadSharedReq accesses
2656system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.161377 # miss rate for ReadSharedReq accesses
2657system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.736039 # miss rate for ReadSharedReq accesses
2658system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.177847 # miss rate for ReadSharedReq accesses
2659system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.078573 # miss rate for ReadSharedReq accesses
2660system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.544108 # miss rate for ReadSharedReq accesses
2661system.l2c.ReadSharedReq_miss_rate::total 0.535389 # miss rate for ReadSharedReq accesses
2662system.l2c.demand_miss_rate::cpu0.dtb.walker 0.083333 # miss rate for demand accesses
2663system.l2c.demand_miss_rate::cpu0.itb.walker 0.022989 # miss rate for demand accesses
2664system.l2c.demand_miss_rate::cpu0.inst 0.390181 # miss rate for demand accesses
2665system.l2c.demand_miss_rate::cpu0.data 0.283829 # miss rate for demand accesses
2666system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.736039 # miss rate for demand accesses
2667system.l2c.demand_miss_rate::cpu1.inst 0.177847 # miss rate for demand accesses
2668system.l2c.demand_miss_rate::cpu1.data 0.439165 # miss rate for demand accesses
2669system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.544108 # miss rate for demand accesses
2670system.l2c.demand_miss_rate::total 0.551172 # miss rate for demand accesses
2671system.l2c.overall_miss_rate::cpu0.dtb.walker 0.083333 # miss rate for overall accesses
2672system.l2c.overall_miss_rate::cpu0.itb.walker 0.022989 # miss rate for overall accesses
2673system.l2c.overall_miss_rate::cpu0.inst 0.390181 # miss rate for overall accesses
2674system.l2c.overall_miss_rate::cpu0.data 0.283829 # miss rate for overall accesses
2675system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.736039 # miss rate for overall accesses
2676system.l2c.overall_miss_rate::cpu1.inst 0.177847 # miss rate for overall accesses
2677system.l2c.overall_miss_rate::cpu1.data 0.439165 # miss rate for overall accesses
2678system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.544108 # miss rate for overall accesses
2679system.l2c.overall_miss_rate::total 0.551172 # miss rate for overall accesses
2680system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1690.678446 # average UpgradeReq miss latency
2681system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 880.694143 # average UpgradeReq miss latency
2682system.l2c.UpgradeReq_avg_miss_latency::total 1497.455800 # average UpgradeReq miss latency
2683system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3518.683274 # average SCUpgradeReq miss latency
2684system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1186.666667 # average SCUpgradeReq miss latency
2685system.l2c.SCUpgradeReq_avg_miss_latency::total 1872.123431 # average SCUpgradeReq miss latency
2686system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95882.080660 # average ReadExReq miss latency
2687system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81280.816270 # average ReadExReq miss latency
2688system.l2c.ReadExReq_avg_miss_latency::total 90039.808655 # average ReadExReq miss latency
2689system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 86500 # average ReadSharedReq miss latency
2690system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 87000 # average ReadSharedReq miss latency
2691system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 81660.447120 # average ReadSharedReq miss latency
2692system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87822.242584 # average ReadSharedReq miss latency
2693system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96486.995061 # average ReadSharedReq miss latency
2694system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 82302.047038 # average ReadSharedReq miss latency
2695system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 89518.105850 # average ReadSharedReq miss latency
2696system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 112576.475203 # average ReadSharedReq miss latency
2697system.l2c.ReadSharedReq_avg_miss_latency::total 94774.886905 # average ReadSharedReq miss latency
2698system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 86500 # average overall miss latency
2699system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
2700system.l2c.demand_avg_miss_latency::cpu0.inst 81660.447120 # average overall miss latency
2701system.l2c.demand_avg_miss_latency::cpu0.data 92299.246474 # average overall miss latency
2702system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96486.995061 # average overall miss latency
2703system.l2c.demand_avg_miss_latency::cpu1.inst 82302.047038 # average overall miss latency
2704system.l2c.demand_avg_miss_latency::cpu1.data 82020.575360 # average overall miss latency
2705system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 112576.475203 # average overall miss latency
2706system.l2c.demand_avg_miss_latency::total 94305.155117 # average overall miss latency
2707system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 86500 # average overall miss latency
2708system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87000 # average overall miss latency
2709system.l2c.overall_avg_miss_latency::cpu0.inst 81660.447120 # average overall miss latency
2710system.l2c.overall_avg_miss_latency::cpu0.data 92299.246474 # average overall miss latency
2711system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96486.995061 # average overall miss latency
2712system.l2c.overall_avg_miss_latency::cpu1.inst 82302.047038 # average overall miss latency
2713system.l2c.overall_avg_miss_latency::cpu1.data 82020.575360 # average overall miss latency
2714system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 112576.475203 # average overall miss latency
2715system.l2c.overall_avg_miss_latency::total 94305.155117 # average overall miss latency
2716system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2717system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2718system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2719system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2720system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2721system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2722system.l2c.writebacks::writebacks 94207 # number of writebacks
2723system.l2c.writebacks::total 94207 # number of writebacks
2724system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 8 # number of ReadSharedReq MSHR hits
2725system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 8 # number of ReadSharedReq MSHR hits
2726system.l2c.ReadSharedReq_mshr_hits::total 16 # number of ReadSharedReq MSHR hits
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2728system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
2729system.l2c.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits
2730system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits
2731system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
2732system.l2c.overall_mshr_hits::total 16 # number of overall MSHR hits
2733system.l2c.CleanEvict_mshr_misses::writebacks 2843 # number of CleanEvict MSHR misses
2734system.l2c.CleanEvict_mshr_misses::total 2843 # number of CleanEvict MSHR misses
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2736system.l2c.UpgradeReq_mshr_misses::cpu1.data 2766 # number of UpgradeReq MSHR misses
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2738system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 562 # number of SCUpgradeReq MSHR misses
2739system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1350 # number of SCUpgradeReq MSHR misses
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2748system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130401 # number of ReadSharedReq MSHR misses
2749system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2288 # number of ReadSharedReq MSHR misses
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2751system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5545 # number of ReadSharedReq MSHR misses
2752system.l2c.ReadSharedReq_mshr_misses::total 165129 # number of ReadSharedReq MSHR misses
2753system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses
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2757system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130401 # number of demand (read+write) MSHR misses
2758system.l2c.demand_mshr_misses::cpu1.inst 2288 # number of demand (read+write) MSHR misses
2759system.l2c.demand_mshr_misses::cpu1.data 7995 # number of demand (read+write) MSHR misses
2760system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5545 # number of demand (read+write) MSHR misses
2761system.l2c.demand_mshr_misses::total 183316 # number of demand (read+write) MSHR misses
2762system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses
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2766system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130401 # number of overall MSHR misses
2767system.l2c.overall_mshr_misses::cpu1.inst 2288 # number of overall MSHR misses
2768system.l2c.overall_mshr_misses::cpu1.data 7995 # number of overall MSHR misses
2769system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5545 # number of overall MSHR misses
2770system.l2c.overall_mshr_misses::total 183316 # number of overall MSHR misses
2771system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
2772system.l2c.ReadReq_mshr_uncacheable::cpu0.data 21106 # number of ReadReq MSHR uncacheable
2773system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2774system.l2c.ReadReq_mshr_uncacheable::cpu1.data 13769 # number of ReadReq MSHR uncacheable
2775system.l2c.ReadReq_mshr_uncacheable::total 44074 # number of ReadReq MSHR uncacheable
2776system.l2c.WriteReq_mshr_uncacheable::cpu0.data 19680 # number of WriteReq MSHR uncacheable
2777system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11224 # number of WriteReq MSHR uncacheable
2778system.l2c.WriteReq_mshr_uncacheable::total 30904 # number of WriteReq MSHR uncacheable
2779system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
2780system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40786 # number of overall MSHR uncacheable misses
2781system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2782system.l2c.overall_mshr_uncacheable_misses::cpu1.data 24993 # number of overall MSHR uncacheable misses
2783system.l2c.overall_mshr_uncacheable_misses::total 74978 # number of overall MSHR uncacheable misses
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2785system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 63038000 # number of UpgradeReq MSHR miss cycles
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2787system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 14501000 # number of SCUpgradeReq MSHR miss cycles
2788system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 33544500 # number of SCUpgradeReq MSHR miss cycles
2789system.l2c.SCUpgradeReq_mshr_miss_latency::total 48045500 # number of SCUpgradeReq MSHR miss cycles
2790system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 936973500 # number of ReadExReq MSHR miss cycles
2791system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 518710500 # number of ReadExReq MSHR miss cycles
2792system.l2c.ReadExReq_mshr_miss_latency::total 1455684000 # number of ReadExReq MSHR miss cycles
2793system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 535500 # number of ReadSharedReq MSHR miss cycles
2794system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 154000 # number of ReadSharedReq MSHR miss cycles
2795system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1249680003 # number of ReadSharedReq MSHR miss cycles
2796system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 679466000 # number of ReadSharedReq MSHR miss cycles
2797system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11277986652 # number of ReadSharedReq MSHR miss cycles
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2799system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 57094000 # number of ReadSharedReq MSHR miss cycles
2800system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 568784560 # number of ReadSharedReq MSHR miss cycles
2801system.l2c.ReadSharedReq_mshr_miss_latency::total 13999360715 # number of ReadSharedReq MSHR miss cycles
2802system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 535500 # number of demand (read+write) MSHR miss cycles
2803system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 154000 # number of demand (read+write) MSHR miss cycles
2804system.l2c.demand_mshr_miss_latency::cpu0.inst 1249680003 # number of demand (read+write) MSHR miss cycles
2805system.l2c.demand_mshr_miss_latency::cpu0.data 1616439500 # number of demand (read+write) MSHR miss cycles
2806system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11277986652 # number of demand (read+write) MSHR miss cycles
2807system.l2c.demand_mshr_miss_latency::cpu1.inst 165660000 # number of demand (read+write) MSHR miss cycles
2808system.l2c.demand_mshr_miss_latency::cpu1.data 575804500 # number of demand (read+write) MSHR miss cycles
2809system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 568784560 # number of demand (read+write) MSHR miss cycles
2810system.l2c.demand_mshr_miss_latency::total 15455044715 # number of demand (read+write) MSHR miss cycles
2811system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 535500 # number of overall MSHR miss cycles
2812system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 154000 # number of overall MSHR miss cycles
2813system.l2c.overall_mshr_miss_latency::cpu0.inst 1249680003 # number of overall MSHR miss cycles
2814system.l2c.overall_mshr_miss_latency::cpu0.data 1616439500 # number of overall MSHR miss cycles
2815system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11277986652 # number of overall MSHR miss cycles
2816system.l2c.overall_mshr_miss_latency::cpu1.inst 165660000 # number of overall MSHR miss cycles
2817system.l2c.overall_mshr_miss_latency::cpu1.data 575804500 # number of overall MSHR miss cycles
2818system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 568784560 # number of overall MSHR miss cycles
2819system.l2c.overall_mshr_miss_latency::total 15455044715 # number of overall MSHR miss cycles
2820system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 581355000 # number of ReadReq MSHR uncacheable cycles
2821system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4129945000 # number of ReadReq MSHR uncacheable cycles
2822system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11263000 # number of ReadReq MSHR uncacheable cycles
2823system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2034246500 # number of ReadReq MSHR uncacheable cycles
2824system.l2c.ReadReq_mshr_uncacheable_latency::total 6756809500 # number of ReadReq MSHR uncacheable cycles
2825system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 581355000 # number of overall MSHR uncacheable cycles
2826system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4129945000 # number of overall MSHR uncacheable cycles
2827system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11263000 # number of overall MSHR uncacheable cycles
2828system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2034246500 # number of overall MSHR uncacheable cycles
2829system.l2c.overall_mshr_uncacheable_latency::total 6756809500 # number of overall MSHR uncacheable cycles
2830system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2831system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2832system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.215441 # mshr miss rate for UpgradeReq accesses
2833system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.560486 # mshr miss rate for UpgradeReq accesses
2834system.l2c.UpgradeReq_mshr_miss_rate::total 0.252526 # mshr miss rate for UpgradeReq accesses
2835system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.217914 # mshr miss rate for SCUpgradeReq accesses
2836system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.571792 # mshr miss rate for SCUpgradeReq accesses
2837system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.387045 # mshr miss rate for SCUpgradeReq accesses
2838system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.722660 # mshr miss rate for ReadExReq accesses
2839system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.802581 # mshr miss rate for ReadExReq accesses
2840system.l2c.ReadExReq_mshr_miss_rate::total 0.752649 # mshr miss rate for ReadExReq accesses
2841system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for ReadSharedReq accesses
2842system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for ReadSharedReq accesses
2843system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for ReadSharedReq accesses
2844system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161377 # mshr miss rate for ReadSharedReq accesses
2845system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for ReadSharedReq accesses
2846system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for ReadSharedReq accesses
2847system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.078573 # mshr miss rate for ReadSharedReq accesses
2848system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for ReadSharedReq accesses
2849system.l2c.ReadSharedReq_mshr_miss_rate::total 0.535337 # mshr miss rate for ReadSharedReq accesses
2850system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for demand accesses
2851system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for demand accesses
2852system.l2c.demand_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for demand accesses
2853system.l2c.demand_mshr_miss_rate::cpu0.data 0.283829 # mshr miss rate for demand accesses
2854system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for demand accesses
2855system.l2c.demand_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for demand accesses
2856system.l2c.demand_mshr_miss_rate::cpu1.data 0.439165 # mshr miss rate for demand accesses
2857system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for demand accesses
2858system.l2c.demand_mshr_miss_rate::total 0.551124 # mshr miss rate for demand accesses
2859system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.083333 # mshr miss rate for overall accesses
2860system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.022989 # mshr miss rate for overall accesses
2861system.l2c.overall_mshr_miss_rate::cpu0.inst 0.390002 # mshr miss rate for overall accesses
2862system.l2c.overall_mshr_miss_rate::cpu0.data 0.283829 # mshr miss rate for overall accesses
2863system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.736039 # mshr miss rate for overall accesses
2864system.l2c.overall_mshr_miss_rate::cpu1.inst 0.177227 # mshr miss rate for overall accesses
2865system.l2c.overall_mshr_miss_rate::cpu1.data 0.439165 # mshr miss rate for overall accesses
2866system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.544108 # mshr miss rate for overall accesses
2867system.l2c.overall_mshr_miss_rate::total 0.551124 # mshr miss rate for overall accesses
2868system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23927.681504 # average UpgradeReq mshr miss latency
2869system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22790.310918 # average UpgradeReq mshr miss latency
2870system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23656.360500 # average UpgradeReq mshr miss latency
2871system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25802.491103 # average SCUpgradeReq mshr miss latency
2872system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24847.777778 # average SCUpgradeReq mshr miss latency
2873system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25128.399582 # average SCUpgradeReq mshr miss latency
2874system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85882.080660 # average ReadExReq mshr miss latency
2875system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71280.816270 # average ReadExReq mshr miss latency
2876system.l2c.ReadExReq_avg_mshr_miss_latency::total 80039.808655 # average ReadExReq mshr miss latency
2877system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average ReadSharedReq mshr miss latency
2878system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency
2879system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average ReadSharedReq mshr miss latency
2880system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77822.242584 # average ReadSharedReq mshr miss latency
2881system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average ReadSharedReq mshr miss latency
2882system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average ReadSharedReq mshr miss latency
2883system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 79518.105850 # average ReadSharedReq mshr miss latency
2884system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average ReadSharedReq mshr miss latency
2885system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84778.329155 # average ReadSharedReq mshr miss latency
2886system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average overall mshr miss latency
2887system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
2888system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average overall mshr miss latency
2889system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82299.246474 # average overall mshr miss latency
2890system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average overall mshr miss latency
2891system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average overall mshr miss latency
2892system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72020.575360 # average overall mshr miss latency
2893system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average overall mshr miss latency
2894system.l2c.demand_avg_mshr_miss_latency::total 84308.214858 # average overall mshr miss latency
2895system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76500 # average overall mshr miss latency
2896system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency
2897system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71668.291736 # average overall mshr miss latency
2898system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82299.246474 # average overall mshr miss latency
2899system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86486.964456 # average overall mshr miss latency
2900system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72403.846154 # average overall mshr miss latency
2901system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72020.575360 # average overall mshr miss latency
2902system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 102576.115419 # average overall mshr miss latency
2903system.l2c.overall_avg_mshr_miss_latency::total 84308.214858 # average overall mshr miss latency
2904system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency
2905system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 195676.347958 # average ReadReq mshr uncacheable latency
2906system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency
2907system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 147741.048733 # average ReadReq mshr uncacheable latency
2908system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153306.019422 # average ReadReq mshr uncacheable latency
2909system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency
2910system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101258.887854 # average overall mshr uncacheable latency
2911system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency
2912system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81392.649942 # average overall mshr uncacheable latency
2913system.l2c.overall_avg_mshr_uncacheable_latency::total 90117.227720 # average overall mshr uncacheable latency
2914system.membus.snoop_filter.tot_requests 502889 # Total number of requests made to the snoop filter.
2915system.membus.snoop_filter.hit_single_requests 289010 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2916system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2917system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
2918system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2919system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2920system.membus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2921system.membus.trans_dist::ReadReq 44074 # Transaction distribution
2922system.membus.trans_dist::ReadResp 209458 # Transaction distribution
2923system.membus.trans_dist::WriteReq 30904 # Transaction distribution
2924system.membus.trans_dist::WriteResp 30904 # Transaction distribution
2925system.membus.trans_dist::WritebackDirty 130397 # Transaction distribution
2926system.membus.trans_dist::CleanEvict 14501 # Transaction distribution
2927system.membus.trans_dist::UpgradeReq 77693 # Transaction distribution
2928system.membus.trans_dist::SCUpgradeReq 40094 # Transaction distribution
2929system.membus.trans_dist::UpgradeResp 16 # Transaction distribution
2930system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
2931system.membus.trans_dist::ReadExReq 38557 # Transaction distribution
2932system.membus.trans_dist::ReadExResp 18075 # Transaction distribution
2933system.membus.trans_dist::ReadSharedReq 165384 # Transaction distribution
2934system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2935system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes)
2936system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
2937system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13706 # Packet count per connected master and slave (bytes)
2938system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641086 # Packet count per connected master and slave (bytes)
2939system.membus.pkt_count_system.l2c.mem_side::total 762740 # Packet count per connected master and slave (bytes)
2940system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes)
2941system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes)
2942system.membus.pkt_count::total 835679 # Packet count per connected master and slave (bytes)
2943system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
2944system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
2945system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27412 # Cumulative packet size per connected master and slave (bytes)
2946system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17788748 # Cumulative packet size per connected master and slave (bytes)
2947system.membus.pkt_size_system.l2c.mem_side::total 17979022 # Cumulative packet size per connected master and slave (bytes)
2948system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
2949system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2950system.membus.pkt_size::total 20296142 # Cumulative packet size per connected master and slave (bytes)
2951system.membus.snoops 125256 # Total snoops (count)
2952system.membus.snoopTraffic 37632 # Total snoop traffic (bytes)
2953system.membus.snoop_fanout::samples 432932 # Request fanout histogram
2954system.membus.snoop_fanout::mean 0.012007 # Request fanout histogram
2955system.membus.snoop_fanout::stdev 0.108915 # Request fanout histogram
2956system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2957system.membus.snoop_fanout::0 427734 98.80% 98.80% # Request fanout histogram
2958system.membus.snoop_fanout::1 5198 1.20% 100.00% # Request fanout histogram
2959system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2960system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2961system.membus.snoop_fanout::min_value 0 # Request fanout histogram
2962system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2963system.membus.snoop_fanout::total 432932 # Request fanout histogram
2964system.membus.reqLayer0.occupancy 88248500 # Layer occupancy (ticks)
2965system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2966system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks)
2967system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2968system.membus.reqLayer2.occupancy 11302499 # Layer occupancy (ticks)
2969system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2970system.membus.reqLayer5.occupancy 949242954 # Layer occupancy (ticks)
2971system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2972system.membus.respLayer2.occupancy 1079420372 # Layer occupancy (ticks)
2973system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2974system.membus.respLayer3.occupancy 1341881 # Layer occupancy (ticks)
2975system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2976system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2977system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2978system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2979system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2980system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2981system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2982system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2983system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
2984system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
2985system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
2986system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
2987system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
2988system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2989system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2990system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
2991system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2992system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2993system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2994system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2995system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2996system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2997system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
2998system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

3014system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
3015system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3016system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3017system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
3018system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3019system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
3020system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
3021system.realview.ethernet.droppedPackets 0 # number of packets dropped
3022system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3023system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3024system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3025system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3026system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3027system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3028system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3029system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3030system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3031system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3032system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3033system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3034system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3035system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3036system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3037system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3038system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3039system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3040system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3041system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3042system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3043system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3044system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3045system.toL2Bus.snoop_filter.tot_requests 971913 # Total number of requests made to the snoop filter.
3046system.toL2Bus.snoop_filter.hit_single_requests 526665 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3047system.toL2Bus.snoop_filter.hit_multi_requests 151758 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3048system.toL2Bus.snoop_filter.tot_snoops 18562 # Total number of snoops made to the snoop filter.
3049system.toL2Bus.snoop_filter.hit_single_snoops 17727 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3050system.toL2Bus.snoop_filter.hit_multi_snoops 835 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3051system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2869796829000 # Cumulative time (in ticks) in various power states
3052system.toL2Bus.trans_dist::ReadReq 44077 # Transaction distribution
3053system.toL2Bus.trans_dist::ReadResp 473751 # Transaction distribution
3054system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution
3055system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution
3056system.toL2Bus.trans_dist::WritebackDirty 349854 # Transaction distribution
3057system.toL2Bus.trans_dist::CleanEvict 105962 # Transaction distribution
3058system.toL2Bus.trans_dist::UpgradeReq 111902 # Transaction distribution
3059system.toL2Bus.trans_dist::SCUpgradeReq 43122 # Transaction distribution
3060system.toL2Bus.trans_dist::UpgradeResp 155024 # Transaction distribution
3061system.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution
3062system.toL2Bus.trans_dist::UpgradeFailResp 90 # Transaction distribution
3063system.toL2Bus.trans_dist::ReadExReq 50816 # Transaction distribution
3064system.toL2Bus.trans_dist::ReadExResp 50816 # Transaction distribution
3065system.toL2Bus.trans_dist::ReadSharedReq 429676 # Transaction distribution
3066system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution
3067system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1183270 # Packet count per connected master and slave (bytes)
3068system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 322305 # Packet count per connected master and slave (bytes)
3069system.toL2Bus.pkt_count::total 1505575 # Packet count per connected master and slave (bytes)
3070system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33366812 # Cumulative packet size per connected master and slave (bytes)
3071system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4544754 # Cumulative packet size per connected master and slave (bytes)
3072system.toL2Bus.pkt_size::total 37911566 # Cumulative packet size per connected master and slave (bytes)
3073system.toL2Bus.snoops 376245 # Total snoops (count)
3074system.toL2Bus.snoopTraffic 15498572 # Total snoop traffic (bytes)
3075system.toL2Bus.snoop_fanout::samples 834461 # Request fanout histogram
3076system.toL2Bus.snoop_fanout::mean 0.383881 # Request fanout histogram
3077system.toL2Bus.snoop_fanout::stdev 0.488383 # Request fanout histogram
3078system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3079system.toL2Bus.snoop_fanout::0 514962 61.71% 61.71% # Request fanout histogram
3080system.toL2Bus.snoop_fanout::1 318664 38.19% 99.90% # Request fanout histogram
3081system.toL2Bus.snoop_fanout::2 835 0.10% 100.00% # Request fanout histogram
3082system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3083system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3084system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3085system.toL2Bus.snoop_fanout::total 834461 # Request fanout histogram
3086system.toL2Bus.reqLayer0.occupancy 867249813 # Layer occupancy (ticks)
3087system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3088system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks)
3089system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3090system.toL2Bus.respLayer0.occupancy 626009420 # Layer occupancy (ticks)
3091system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3092system.toL2Bus.respLayer1.occupancy 234312270 # Layer occupancy (ticks)
3093system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3094
3095---------- End Simulation Statistics ----------