1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.871806 # Number of seconds simulated
4sim_ticks 2871806231000 # Number of ticks simulated
5final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 937604 # Simulator instruction rate (inst/s)
8host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 20478123685 # Simulator tick rate (ticks/s)
10host_mem_usage 614632 # Number of bytes of host memory used
11host_seconds 140.24 # Real time elapsed on the host
12sim_insts 131483712 # Number of instructions simulated
13sim_ops 159036662 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1158756 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1268260 # Number of bytes read from this memory
--- 662 unchanged lines hidden (view full) ---
682system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14153.803140 # average overall miss latency
683system.cpu0.dcache.overall_avg_miss_latency::total 14153.803140 # average overall miss latency
684system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
685system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
686system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
687system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
688system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
689system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
690system.cpu0.dcache.fast_writes 0 # number of fast writes performed
691system.cpu0.dcache.cache_copies 0 # number of cache copies performed
692system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks
693system.cpu0.dcache.writebacks::total 733230 # number of writebacks
694system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25285 # number of ReadReq MSHR hits
695system.cpu0.dcache.ReadReq_mshr_hits::total 25285 # number of ReadReq MSHR hits
696system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits
697system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
698system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15695 # number of LoadLockedReq MSHR hits
699system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15695 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
734system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1800000 # number of StoreCondFailReq MSHR miss cycles
735system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1800000 # number of StoreCondFailReq MSHR miss cycles
736system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432714000 # number of demand (read+write) MSHR miss cycles
737system.cpu0.dcache.demand_mshr_miss_latency::total 11432714000 # number of demand (read+write) MSHR miss cycles
738system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000 # number of overall MSHR miss cycles
739system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles
740system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles
741system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles
742system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400920500 # number of WriteReq MSHR uncacheable cycles
743system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400920500 # number of WriteReq MSHR uncacheable cycles
744system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029763500 # number of overall MSHR uncacheable cycles
745system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029763500 # number of overall MSHR uncacheable cycles
746system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses
747system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses
748system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses
749system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017926 # mshr miss rate for WriteReq accesses
750system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231342 # mshr miss rate for SoftPFReq accesses
751system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231342 # mshr miss rate for SoftPFReq accesses
752system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016916 # mshr miss rate for LoadLockedReq accesses
753system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016916 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
770system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
771system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
772system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15641.111446 # average overall mshr miss latency
773system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15641.111446 # average overall mshr miss latency
774system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260 # average overall mshr miss latency
775system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # average overall mshr miss latency
776system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161 # average ReadReq mshr uncacheable latency
777system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161 # average ReadReq mshr uncacheable latency
778system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022 # average WriteReq mshr uncacheable latency
779system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022 # average WriteReq mshr uncacheable latency
780system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605 # average overall mshr uncacheable latency
781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605 # average overall mshr uncacheable latency
782system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
783system.cpu0.icache.tags.replacements 1147026 # number of replacements
784system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use
785system.cpu0.icache.tags.total_refs 120430031 # Total number of references to valid blocks.
786system.cpu0.icache.tags.sampled_refs 1147538 # Sample count of references to valid blocks.
787system.cpu0.icache.tags.avg_refs 104.946443 # Average number of references to valid blocks.
788system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit.
789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor
790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10667.958262 # average overall miss latency
834system.cpu0.icache.overall_avg_miss_latency::total 10667.958262 # average overall miss latency
835system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
839system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
841system.cpu0.icache.fast_writes 0 # number of fast writes performed
842system.cpu0.icache.cache_copies 0 # number of cache copies performed
843system.cpu0.icache.writebacks::writebacks 1147026 # number of writebacks
844system.cpu0.icache.writebacks::total 1147026 # number of writebacks
845system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147547 # number of ReadReq MSHR misses
846system.cpu0.icache.ReadReq_mshr_misses::total 1147547 # number of ReadReq MSHR misses
847system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147547 # number of demand (read+write) MSHR misses
848system.cpu0.icache.demand_mshr_misses::total 1147547 # number of demand (read+write) MSHR misses
849system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147547 # number of overall MSHR misses
850system.cpu0.icache.overall_mshr_misses::total 1147547 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
873system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency
874system.cpu0.icache.demand_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency
875system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency
876system.cpu0.icache.overall_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency
877system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency
878system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency
879system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency
880system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency
881system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
882system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935584 # number of hwpf issued
883system.cpu0.l2cache.prefetcher.pfIdentified 1935659 # number of prefetch candidates identified
884system.cpu0.l2cache.prefetcher.pfBufferHit 66 # number of redundant prefetches already in prefetch queue
885system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
886system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
887system.cpu0.l2cache.prefetcher.pfSpanPage 246453 # number of prefetches not generated due to page crossing
888system.cpu0.l2cache.tags.replacements 273594 # number of replacements
889system.cpu0.l2cache.tags.tagsinuse 16077.204583 # Cycle average of tags in use
--- 185 unchanged lines hidden (view full) ---
1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43698.326879 # average overall miss latency
1076system.cpu0.l2cache.overall_avg_miss_latency::total 50634.109884 # average overall miss latency
1077system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1078system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1079system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1080system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1081system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1082system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1083system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1084system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1085system.cpu0.l2cache.unused_prefetches 10692 # number of HardPF blocks evicted w/o reference
1086system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks
1087system.cpu0.l2cache.writebacks::total 231848 # number of writebacks
1088system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1793 # number of ReadExReq MSHR hits
1089system.cpu0.l2cache.ReadExReq_mshr_hits::total 1793 # number of ReadExReq MSHR hits
1090system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 59 # number of ReadSharedReq MSHR hits
1091system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 59 # number of ReadSharedReq MSHR hits
1092system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1852 # number of demand (read+write) MSHR hits
--- 62 unchanged lines hidden (view full) ---
1155system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1575500 # number of overall MSHR miss cycles
1156system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3008596500 # number of overall MSHR miss cycles
1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5022496500 # number of overall MSHR miss cycles
1158system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20425308140 # number of overall MSHR miss cycles
1159system.cpu0.l2cache.overall_mshr_miss_latency::total 28461338140 # number of overall MSHR miss cycles
1160system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles
1161system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373893500 # number of ReadReq MSHR uncacheable cycles
1162system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560105000 # number of ReadReq MSHR uncacheable cycles
1163system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187056500 # number of WriteReq MSHR uncacheable cycles
1164system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187056500 # number of WriteReq MSHR uncacheable cycles
1165system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles
1166system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11560950000 # number of overall MSHR uncacheable cycles
1167system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747161500 # number of overall MSHR uncacheable cycles
1168system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for ReadReq accesses
1169system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for ReadReq accesses
1170system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014117 # mshr miss rate for ReadReq accesses
1171system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1172system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1173system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1174system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1175system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 43 unchanged lines hidden (view full) ---
1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency
1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency
1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency
1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average overall mshr miss latency
1223system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 # average overall mshr miss latency
1224system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency
1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency
1226system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency
1227system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency
1228system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency
1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency
1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency
1231system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency
1232system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1233system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter.
1234system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1235system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1236system.cpu0.toL2Bus.snoop_filter.tot_snoops 319838 # Total number of snoops made to the snoop filter.
1237system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316964 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1238system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2874 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1239system.cpu0.toL2Bus.trans_dist::ReadReq 63699 # Transaction distribution
1240system.cpu0.toL2Bus.trans_dist::ReadResp 1766064 # Transaction distribution
--- 383 unchanged lines hidden (view full) ---
1624system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20616.095936 # average overall miss latency
1625system.cpu1.dcache.overall_avg_miss_latency::total 20616.095936 # average overall miss latency
1626system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1627system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1628system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1629system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1630system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1631system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1632system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1633system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1634system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks
1635system.cpu1.dcache.writebacks::total 148452 # number of writebacks
1636system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits
1637system.cpu1.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
1638system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11671 # number of LoadLockedReq MSHR hits
1639system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11671 # number of LoadLockedReq MSHR hits
1640system.cpu1.dcache.demand_mshr_hits::cpu1.data 223 # number of demand (read+write) MSHR hits
1641system.cpu1.dcache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits
--- 32 unchanged lines hidden (view full) ---
1674system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4985000 # number of StoreCondFailReq MSHR miss cycles
1675system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4985000 # number of StoreCondFailReq MSHR miss cycles
1676system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4262527500 # number of demand (read+write) MSHR miss cycles
1677system.cpu1.dcache.demand_mshr_miss_latency::total 4262527500 # number of demand (read+write) MSHR miss cycles
1678system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000 # number of overall MSHR miss cycles
1679system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles
1680system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles
1681system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles
1682system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303136500 # number of WriteReq MSHR uncacheable cycles
1683system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303136500 # number of WriteReq MSHR uncacheable cycles
1684system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742664000 # number of overall MSHR uncacheable cycles
1685system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742664000 # number of overall MSHR uncacheable cycles
1686system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses
1687system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses
1688system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses
1689system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028102 # mshr miss rate for WriteReq accesses
1690system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360930 # mshr miss rate for SoftPFReq accesses
1691system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360930 # mshr miss rate for SoftPFReq accesses
1692system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056993 # mshr miss rate for LoadLockedReq accesses
1693system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056993 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
1710system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1711system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1712system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22182.525227 # average overall mshr miss latency
1713system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22182.525227 # average overall mshr miss latency
1714system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355 # average overall mshr miss latency
1715system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency
1716system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency
1717system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency
1718system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061 # average WriteReq mshr uncacheable latency
1719system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061 # average WriteReq mshr uncacheable latency
1720system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295 # average overall mshr uncacheable latency
1721system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295 # average overall mshr uncacheable latency
1722system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1723system.cpu1.icache.tags.replacements 463484 # number of replacements
1724system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use
1725system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks.
1726system.cpu1.icache.tags.sampled_refs 463996 # Sample count of references to valid blocks.
1727system.cpu1.icache.tags.avg_refs 29.004039 # Average number of references to valid blocks.
1728system.cpu1.icache.tags.warmup_cycle 106358922000 # Cycle when the warmup percentage was hit.
1729system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310914 # Average occupied blocks per requestor
1730system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
1773system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency
1774system.cpu1.icache.overall_avg_miss_latency::total 9082.120320 # average overall miss latency
1775system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1776system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1777system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1778system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1779system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1780system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1781system.cpu1.icache.fast_writes 0 # number of fast writes performed
1782system.cpu1.icache.cache_copies 0 # number of cache copies performed
1783system.cpu1.icache.writebacks::writebacks 463484 # number of writebacks
1784system.cpu1.icache.writebacks::total 463484 # number of writebacks
1785system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463996 # number of ReadReq MSHR misses
1786system.cpu1.icache.ReadReq_mshr_misses::total 463996 # number of ReadReq MSHR misses
1787system.cpu1.icache.demand_mshr_misses::cpu1.inst 463996 # number of demand (read+write) MSHR misses
1788system.cpu1.icache.demand_mshr_misses::total 463996 # number of demand (read+write) MSHR misses
1789system.cpu1.icache.overall_mshr_misses::cpu1.inst 463996 # number of overall MSHR misses
1790system.cpu1.icache.overall_mshr_misses::total 463996 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
1813system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency
1814system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency
1815system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency
1816system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency
1817system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency
1818system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency
1819system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency
1820system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency
1821system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1822system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued
1823system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified
1824system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue
1825system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1826system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1827system.cpu1.l2cache.prefetcher.pfSpanPage 50208 # number of prefetches not generated due to page crossing
1828system.cpu1.l2cache.tags.replacements 31332 # number of replacements
1829system.cpu1.l2cache.tags.tagsinuse 14956.481117 # Cycle average of tags in use
--- 180 unchanged lines hidden (view full) ---
2010system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32054.155988 # average overall miss latency
2011system.cpu1.l2cache.overall_avg_miss_latency::total 34329.100414 # average overall miss latency
2012system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2013system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2015system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2017system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2018system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2019system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2020system.cpu1.l2cache.unused_prefetches 502 # number of HardPF blocks evicted w/o reference
2021system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks
2022system.cpu1.l2cache.writebacks::total 26072 # number of writebacks
2023system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 73 # number of ReadExReq MSHR hits
2024system.cpu1.l2cache.ReadExReq_mshr_hits::total 73 # number of ReadExReq MSHR hits
2025system.cpu1.l2cache.demand_mshr_hits::cpu1.data 73 # number of demand (read+write) MSHR hits
2026system.cpu1.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
2027system.cpu1.l2cache.overall_mshr_hits::cpu1.data 73 # number of overall MSHR hits
--- 60 unchanged lines hidden (view full) ---
2088system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4155500 # number of overall MSHR miss cycles
2089system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 476217500 # number of overall MSHR miss cycles
2090system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2493275000 # number of overall MSHR miss cycles
2091system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 927478543 # number of overall MSHR miss cycles
2092system.cpu1.l2cache.overall_mshr_miss_latency::total 3906024043 # number of overall MSHR miss cycles
2093system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles
2094system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414523000 # number of ReadReq MSHR uncacheable cycles
2095system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436742000 # number of ReadReq MSHR uncacheable cycles
2096system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284955500 # number of WriteReq MSHR uncacheable cycles
2097system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284955500 # number of WriteReq MSHR uncacheable cycles
2098system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles
2099system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699478500 # number of overall MSHR uncacheable cycles
2100system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721697500 # number of overall MSHR uncacheable cycles
2101system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses
2102system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses
2103system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses
2104system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2105system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2106system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2107system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2108system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 43 unchanged lines hidden (view full) ---
2152system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency
2153system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency
2154system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency
2155system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average overall mshr miss latency
2156system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 # average overall mshr miss latency
2157system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency
2158system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency
2159system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency
2160system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency
2161system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency
2162system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency
2163system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency
2164system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency
2165system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2166system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter.
2167system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2168system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2169system.cpu1.toL2Bus.snoop_filter.tot_snoops 168501 # Total number of snoops made to the snoop filter.
2170system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166697 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2171system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1804 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2172system.cpu1.toL2Bus.trans_dist::ReadReq 10096 # Transaction distribution
2173system.cpu1.toL2Bus.trans_dist::ReadResp 652859 # Transaction distribution
--- 154 unchanged lines hidden (view full) ---
2328system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2329system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2330system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2331system.iocache.tags.data_accesses 328311 # Number of data accesses
2332system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2333system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2334system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2335system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2336system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
2337system.iocache.demand_misses::total 255 # number of demand (read+write) misses
2338system.iocache.overall_misses::realview.ide 255 # number of overall misses
2339system.iocache.overall_misses::total 255 # number of overall misses
2340system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles
2341system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles
2342system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles
2343system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles
2344system.iocache.demand_miss_latency::realview.ide 32883377 # number of demand (read+write) miss cycles
2345system.iocache.demand_miss_latency::total 32883377 # number of demand (read+write) miss cycles
2346system.iocache.overall_miss_latency::realview.ide 32883377 # number of overall miss cycles
2347system.iocache.overall_miss_latency::total 32883377 # number of overall miss cycles
2348system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2349system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2350system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2351system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2352system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
2353system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
2354system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
2355system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
2356system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2357system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2358system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2359system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2360system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2361system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2362system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2363system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2364system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608 # average ReadReq miss latency
2365system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency
2366system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency
2367system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency
2368system.iocache.demand_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
2369system.iocache.demand_avg_miss_latency::total 128954.419608 # average overall miss latency
2370system.iocache.overall_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
2371system.iocache.overall_avg_miss_latency::total 128954.419608 # average overall miss latency
2372system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked
2373system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2374system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
2375system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2376system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
2377system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2378system.iocache.fast_writes 0 # number of fast writes performed
2379system.iocache.cache_copies 0 # number of cache copies performed
2380system.iocache.writebacks::writebacks 36206 # number of writebacks
2381system.iocache.writebacks::total 36206 # number of writebacks
2382system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2383system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2384system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2385system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2386system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
2387system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
2388system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
2389system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
2390system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles
2391system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles
2392system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles
2393system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles
2394system.iocache.demand_mshr_miss_latency::realview.ide 20133377 # number of demand (read+write) MSHR miss cycles
2395system.iocache.demand_mshr_miss_latency::total 20133377 # number of demand (read+write) MSHR miss cycles
2396system.iocache.overall_mshr_miss_latency::realview.ide 20133377 # number of overall MSHR miss cycles
2397system.iocache.overall_mshr_miss_latency::total 20133377 # number of overall MSHR miss cycles
2398system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2399system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2400system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2401system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2402system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2403system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2404system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2405system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2406system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608 # average ReadReq mshr miss latency
2407system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency
2408system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency
2409system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency
2410system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
2411system.iocache.demand_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
2412system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
2413system.iocache.overall_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
2414system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2415system.l2c.tags.replacements 124374 # number of replacements
2416system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use
2417system.l2c.tags.total_refs 421293 # Total number of references to valid blocks.
2418system.l2c.tags.sampled_refs 188431 # Sample count of references to valid blocks.
2419system.l2c.tags.avg_refs 2.235795 # Average number of references to valid blocks.
2420system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2421system.l2c.tags.occ_blocks::writebacks 13456.936548 # Average occupied blocks per requestor
2422system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.884029 # Average occupied blocks per requestor
--- 265 unchanged lines hidden (view full) ---
2688system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957 # average overall miss latency
2689system.l2c.overall_avg_miss_latency::total 143055.948758 # average overall miss latency
2690system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2691system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2692system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2693system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2694system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2695system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2696system.l2c.fast_writes 0 # number of fast writes performed
2697system.l2c.cache_copies 0 # number of cache copies performed
2698system.l2c.writebacks::writebacks 97172 # number of writebacks
2699system.l2c.writebacks::total 97172 # number of writebacks
2700system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits
2701system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits
2702system.l2c.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits
2703system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
2704system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
2705system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
--- 87 unchanged lines hidden (view full) ---
2793system.l2c.overall_mshr_miss_latency::cpu1.data 1047597021 # number of overall MSHR miss cycles
2794system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 796678627 # number of overall MSHR miss cycles
2795system.l2c.overall_mshr_miss_latency::total 25144697820 # number of overall MSHR miss cycles
2796system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles
2797system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801182501 # number of ReadReq MSHR uncacheable cycles
2798system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles
2799system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359054501 # number of ReadReq MSHR uncacheable cycles
2800system.l2c.ReadReq_mshr_uncacheable_latency::total 7203084502 # number of ReadReq MSHR uncacheable cycles
2801system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702546001 # number of WriteReq MSHR uncacheable cycles
2802system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243701000 # number of WriteReq MSHR uncacheable cycles
2803system.l2c.WriteReq_mshr_uncacheable_latency::total 4946247001 # number of WriteReq MSHR uncacheable cycles
2804system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles
2805system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503728502 # number of overall MSHR uncacheable cycles
2806system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles
2807system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602755501 # number of overall MSHR uncacheable cycles
2808system.l2c.overall_mshr_uncacheable_latency::total 12149331503 # number of overall MSHR uncacheable cycles
2809system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2810system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2811system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.224375 # mshr miss rate for UpgradeReq accesses
2812system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.533969 # mshr miss rate for UpgradeReq accesses
2813system.l2c.UpgradeReq_mshr_miss_rate::total 0.252741 # mshr miss rate for UpgradeReq accesses
2814system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.224278 # mshr miss rate for SCUpgradeReq accesses
2815system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.576698 # mshr miss rate for SCUpgradeReq accesses
2816system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.383350 # mshr miss rate for SCUpgradeReq accesses
--- 63 unchanged lines hidden (view full) ---
2880system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency
2881system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency
2882system.l2c.overall_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency
2883system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency
2884system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847 # average ReadReq mshr uncacheable latency
2885system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency
2886system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency
2887system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency
2888system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency
2889system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency
2890system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency
2891system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency
2892system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency
2893system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency
2894system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency
2895system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency
2896system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2897system.membus.trans_dist::ReadReq 44095 # Transaction distribution
2898system.membus.trans_dist::ReadResp 214453 # Transaction distribution
2899system.membus.trans_dist::WriteReq 30922 # Transaction distribution
2900system.membus.trans_dist::WriteResp 30922 # Transaction distribution
2901system.membus.trans_dist::WritebackDirty 133378 # Transaction distribution
2902system.membus.trans_dist::CleanEvict 14958 # Transaction distribution
2903system.membus.trans_dist::UpgradeReq 73332 # Transaction distribution
2904system.membus.trans_dist::SCUpgradeReq 39852 # Transaction distribution
--- 136 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.871806 # Number of seconds simulated
4sim_ticks 2871806231000 # Number of ticks simulated
5final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 937604 # Simulator instruction rate (inst/s)
8host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 20478123685 # Simulator tick rate (ticks/s)
10host_mem_usage 614632 # Number of bytes of host memory used
11host_seconds 140.24 # Real time elapsed on the host
12sim_insts 131483712 # Number of instructions simulated
13sim_ops 159036662 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1158756 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1268260 # Number of bytes read from this memory
--- 662 unchanged lines hidden (view full) ---
682system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14153.803140 # average overall miss latency
683system.cpu0.dcache.overall_avg_miss_latency::total 14153.803140 # average overall miss latency
684system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
685system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
686system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
687system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
688system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
689system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
690system.cpu0.dcache.fast_writes 0 # number of fast writes performed
691system.cpu0.dcache.cache_copies 0 # number of cache copies performed
692system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks
693system.cpu0.dcache.writebacks::total 733230 # number of writebacks
694system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25285 # number of ReadReq MSHR hits
695system.cpu0.dcache.ReadReq_mshr_hits::total 25285 # number of ReadReq MSHR hits
696system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits
697system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
698system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15695 # number of LoadLockedReq MSHR hits
699system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15695 # number of LoadLockedReq MSHR hits
--- 34 unchanged lines hidden (view full) ---
734system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1800000 # number of StoreCondFailReq MSHR miss cycles
735system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1800000 # number of StoreCondFailReq MSHR miss cycles
736system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432714000 # number of demand (read+write) MSHR miss cycles
737system.cpu0.dcache.demand_mshr_miss_latency::total 11432714000 # number of demand (read+write) MSHR miss cycles
738system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000 # number of overall MSHR miss cycles
739system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles
740system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles
741system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles
742system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400920500 # number of WriteReq MSHR uncacheable cycles
743system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400920500 # number of WriteReq MSHR uncacheable cycles
744system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029763500 # number of overall MSHR uncacheable cycles
745system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029763500 # number of overall MSHR uncacheable cycles
746system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses
747system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses
748system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses
749system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017926 # mshr miss rate for WriteReq accesses
750system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231342 # mshr miss rate for SoftPFReq accesses
751system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231342 # mshr miss rate for SoftPFReq accesses
752system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016916 # mshr miss rate for LoadLockedReq accesses
753system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016916 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
770system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
771system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
772system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15641.111446 # average overall mshr miss latency
773system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15641.111446 # average overall mshr miss latency
774system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260 # average overall mshr miss latency
775system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # average overall mshr miss latency
776system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161 # average ReadReq mshr uncacheable latency
777system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161 # average ReadReq mshr uncacheable latency
778system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189512.632022 # average WriteReq mshr uncacheable latency
779system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189512.632022 # average WriteReq mshr uncacheable latency
780system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199445.644605 # average overall mshr uncacheable latency
781system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199445.644605 # average overall mshr uncacheable latency
782system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
783system.cpu0.icache.tags.replacements 1147026 # number of replacements
784system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use
785system.cpu0.icache.tags.total_refs 120430031 # Total number of references to valid blocks.
786system.cpu0.icache.tags.sampled_refs 1147538 # Sample count of references to valid blocks.
787system.cpu0.icache.tags.avg_refs 104.946443 # Average number of references to valid blocks.
788system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit.
789system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor
790system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
833system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10667.958262 # average overall miss latency
834system.cpu0.icache.overall_avg_miss_latency::total 10667.958262 # average overall miss latency
835system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
836system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
837system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
838system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
839system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
840system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
841system.cpu0.icache.fast_writes 0 # number of fast writes performed
842system.cpu0.icache.cache_copies 0 # number of cache copies performed
843system.cpu0.icache.writebacks::writebacks 1147026 # number of writebacks
844system.cpu0.icache.writebacks::total 1147026 # number of writebacks
845system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147547 # number of ReadReq MSHR misses
846system.cpu0.icache.ReadReq_mshr_misses::total 1147547 # number of ReadReq MSHR misses
847system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147547 # number of demand (read+write) MSHR misses
848system.cpu0.icache.demand_mshr_misses::total 1147547 # number of demand (read+write) MSHR misses
849system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147547 # number of overall MSHR misses
850system.cpu0.icache.overall_mshr_misses::total 1147547 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
873system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency
874system.cpu0.icache.demand_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency
875system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency
876system.cpu0.icache.overall_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency
877system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency
878system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency
879system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency
880system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency
881system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
882system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935584 # number of hwpf issued
883system.cpu0.l2cache.prefetcher.pfIdentified 1935659 # number of prefetch candidates identified
884system.cpu0.l2cache.prefetcher.pfBufferHit 66 # number of redundant prefetches already in prefetch queue
885system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
886system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
887system.cpu0.l2cache.prefetcher.pfSpanPage 246453 # number of prefetches not generated due to page crossing
888system.cpu0.l2cache.tags.replacements 273594 # number of replacements
889system.cpu0.l2cache.tags.tagsinuse 16077.204583 # Cycle average of tags in use
--- 185 unchanged lines hidden (view full) ---
1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43698.326879 # average overall miss latency
1076system.cpu0.l2cache.overall_avg_miss_latency::total 50634.109884 # average overall miss latency
1077system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1078system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1079system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1080system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1081system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1082system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1083system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1084system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1085system.cpu0.l2cache.unused_prefetches 10692 # number of HardPF blocks evicted w/o reference
1086system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks
1087system.cpu0.l2cache.writebacks::total 231848 # number of writebacks
1088system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1793 # number of ReadExReq MSHR hits
1089system.cpu0.l2cache.ReadExReq_mshr_hits::total 1793 # number of ReadExReq MSHR hits
1090system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 59 # number of ReadSharedReq MSHR hits
1091system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 59 # number of ReadSharedReq MSHR hits
1092system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1852 # number of demand (read+write) MSHR hits
--- 62 unchanged lines hidden (view full) ---
1155system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1575500 # number of overall MSHR miss cycles
1156system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3008596500 # number of overall MSHR miss cycles
1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5022496500 # number of overall MSHR miss cycles
1158system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20425308140 # number of overall MSHR miss cycles
1159system.cpu0.l2cache.overall_mshr_miss_latency::total 28461338140 # number of overall MSHR miss cycles
1160system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles
1161system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373893500 # number of ReadReq MSHR uncacheable cycles
1162system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560105000 # number of ReadReq MSHR uncacheable cycles
1163system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187056500 # number of WriteReq MSHR uncacheable cycles
1164system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187056500 # number of WriteReq MSHR uncacheable cycles
1165system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles
1166system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11560950000 # number of overall MSHR uncacheable cycles
1167system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747161500 # number of overall MSHR uncacheable cycles
1168system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for ReadReq accesses
1169system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for ReadReq accesses
1170system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014117 # mshr miss rate for ReadReq accesses
1171system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1172system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1173system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1174system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1175system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 43 unchanged lines hidden (view full) ---
1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency
1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency
1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency
1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average overall mshr miss latency
1223system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 # average overall mshr miss latency
1224system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency
1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency
1226system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency
1227system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182008.368715 # average WriteReq mshr uncacheable latency
1228system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182008.368715 # average WriteReq mshr uncacheable latency
1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency
1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191673.022084 # average overall mshr uncacheable latency
1231system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183840.916958 # average overall mshr uncacheable latency
1232system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1233system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter.
1234system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1235system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1236system.cpu0.toL2Bus.snoop_filter.tot_snoops 319838 # Total number of snoops made to the snoop filter.
1237system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316964 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1238system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2874 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1239system.cpu0.toL2Bus.trans_dist::ReadReq 63699 # Transaction distribution
1240system.cpu0.toL2Bus.trans_dist::ReadResp 1766064 # Transaction distribution
--- 383 unchanged lines hidden (view full) ---
1624system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20616.095936 # average overall miss latency
1625system.cpu1.dcache.overall_avg_miss_latency::total 20616.095936 # average overall miss latency
1626system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1627system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1628system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1629system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1630system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1631system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1632system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1633system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1634system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks
1635system.cpu1.dcache.writebacks::total 148452 # number of writebacks
1636system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits
1637system.cpu1.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
1638system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11671 # number of LoadLockedReq MSHR hits
1639system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11671 # number of LoadLockedReq MSHR hits
1640system.cpu1.dcache.demand_mshr_hits::cpu1.data 223 # number of demand (read+write) MSHR hits
1641system.cpu1.dcache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits
--- 32 unchanged lines hidden (view full) ---
1674system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4985000 # number of StoreCondFailReq MSHR miss cycles
1675system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4985000 # number of StoreCondFailReq MSHR miss cycles
1676system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4262527500 # number of demand (read+write) MSHR miss cycles
1677system.cpu1.dcache.demand_mshr_miss_latency::total 4262527500 # number of demand (read+write) MSHR miss cycles
1678system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000 # number of overall MSHR miss cycles
1679system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles
1680system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles
1681system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles
1682system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303136500 # number of WriteReq MSHR uncacheable cycles
1683system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303136500 # number of WriteReq MSHR uncacheable cycles
1684system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742664000 # number of overall MSHR uncacheable cycles
1685system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742664000 # number of overall MSHR uncacheable cycles
1686system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses
1687system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses
1688system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses
1689system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028102 # mshr miss rate for WriteReq accesses
1690system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360930 # mshr miss rate for SoftPFReq accesses
1691system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360930 # mshr miss rate for SoftPFReq accesses
1692system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056993 # mshr miss rate for LoadLockedReq accesses
1693system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056993 # mshr miss rate for LoadLockedReq accesses
--- 16 unchanged lines hidden (view full) ---
1710system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1711system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1712system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22182.525227 # average overall mshr miss latency
1713system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22182.525227 # average overall mshr miss latency
1714system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355 # average overall mshr miss latency
1715system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency
1716system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency
1717system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency
1718system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125107.924061 # average WriteReq mshr uncacheable latency
1719system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125107.924061 # average WriteReq mshr uncacheable latency
1720system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134907.175295 # average overall mshr uncacheable latency
1721system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134907.175295 # average overall mshr uncacheable latency
1722system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1723system.cpu1.icache.tags.replacements 463484 # number of replacements
1724system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use
1725system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks.
1726system.cpu1.icache.tags.sampled_refs 463996 # Sample count of references to valid blocks.
1727system.cpu1.icache.tags.avg_refs 29.004039 # Average number of references to valid blocks.
1728system.cpu1.icache.tags.warmup_cycle 106358922000 # Cycle when the warmup percentage was hit.
1729system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310914 # Average occupied blocks per requestor
1730system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy
--- 42 unchanged lines hidden (view full) ---
1773system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency
1774system.cpu1.icache.overall_avg_miss_latency::total 9082.120320 # average overall miss latency
1775system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1776system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1777system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1778system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1779system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1780system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1781system.cpu1.icache.fast_writes 0 # number of fast writes performed
1782system.cpu1.icache.cache_copies 0 # number of cache copies performed
1783system.cpu1.icache.writebacks::writebacks 463484 # number of writebacks
1784system.cpu1.icache.writebacks::total 463484 # number of writebacks
1785system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463996 # number of ReadReq MSHR misses
1786system.cpu1.icache.ReadReq_mshr_misses::total 463996 # number of ReadReq MSHR misses
1787system.cpu1.icache.demand_mshr_misses::cpu1.inst 463996 # number of demand (read+write) MSHR misses
1788system.cpu1.icache.demand_mshr_misses::total 463996 # number of demand (read+write) MSHR misses
1789system.cpu1.icache.overall_mshr_misses::cpu1.inst 463996 # number of overall MSHR misses
1790system.cpu1.icache.overall_mshr_misses::total 463996 # number of overall MSHR misses
--- 22 unchanged lines hidden (view full) ---
1813system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency
1814system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency
1815system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency
1816system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency
1817system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency
1818system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency
1819system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency
1820system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency
1821system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1822system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued
1823system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified
1824system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue
1825system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1826system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1827system.cpu1.l2cache.prefetcher.pfSpanPage 50208 # number of prefetches not generated due to page crossing
1828system.cpu1.l2cache.tags.replacements 31332 # number of replacements
1829system.cpu1.l2cache.tags.tagsinuse 14956.481117 # Cycle average of tags in use
--- 180 unchanged lines hidden (view full) ---
2010system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32054.155988 # average overall miss latency
2011system.cpu1.l2cache.overall_avg_miss_latency::total 34329.100414 # average overall miss latency
2012system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2013system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2014system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2015system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2016system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2017system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2018system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2019system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2020system.cpu1.l2cache.unused_prefetches 502 # number of HardPF blocks evicted w/o reference
2021system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks
2022system.cpu1.l2cache.writebacks::total 26072 # number of writebacks
2023system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 73 # number of ReadExReq MSHR hits
2024system.cpu1.l2cache.ReadExReq_mshr_hits::total 73 # number of ReadExReq MSHR hits
2025system.cpu1.l2cache.demand_mshr_hits::cpu1.data 73 # number of demand (read+write) MSHR hits
2026system.cpu1.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
2027system.cpu1.l2cache.overall_mshr_hits::cpu1.data 73 # number of overall MSHR hits
--- 60 unchanged lines hidden (view full) ---
2088system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4155500 # number of overall MSHR miss cycles
2089system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 476217500 # number of overall MSHR miss cycles
2090system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2493275000 # number of overall MSHR miss cycles
2091system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 927478543 # number of overall MSHR miss cycles
2092system.cpu1.l2cache.overall_mshr_miss_latency::total 3906024043 # number of overall MSHR miss cycles
2093system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles
2094system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414523000 # number of ReadReq MSHR uncacheable cycles
2095system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436742000 # number of ReadReq MSHR uncacheable cycles
2096system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284955500 # number of WriteReq MSHR uncacheable cycles
2097system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284955500 # number of WriteReq MSHR uncacheable cycles
2098system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles
2099system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699478500 # number of overall MSHR uncacheable cycles
2100system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721697500 # number of overall MSHR uncacheable cycles
2101system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses
2102system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses
2103system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses
2104system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2105system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2106system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2107system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2108system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
--- 43 unchanged lines hidden (view full) ---
2152system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency
2153system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency
2154system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency
2155system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average overall mshr miss latency
2156system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 # average overall mshr miss latency
2157system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency
2158system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency
2159system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency
2160system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117604.416013 # average WriteReq mshr uncacheable latency
2161system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117604.416013 # average WriteReq mshr uncacheable latency
2162system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency
2163system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127062.397820 # average overall mshr uncacheable latency
2164system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127014.695530 # average overall mshr uncacheable latency
2165system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2166system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter.
2167system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2168system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2169system.cpu1.toL2Bus.snoop_filter.tot_snoops 168501 # Total number of snoops made to the snoop filter.
2170system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166697 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2171system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1804 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2172system.cpu1.toL2Bus.trans_dist::ReadReq 10096 # Transaction distribution
2173system.cpu1.toL2Bus.trans_dist::ReadResp 652859 # Transaction distribution
--- 154 unchanged lines hidden (view full) ---
2328system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2329system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2330system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2331system.iocache.tags.data_accesses 328311 # Number of data accesses
2332system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2333system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2334system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2335system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2336system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
2337system.iocache.demand_misses::total 255 # number of demand (read+write) misses
2338system.iocache.overall_misses::realview.ide 255 # number of overall misses
2339system.iocache.overall_misses::total 255 # number of overall misses
2340system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles
2341system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles
2342system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles
2343system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles
2344system.iocache.demand_miss_latency::realview.ide 32883377 # number of demand (read+write) miss cycles
2345system.iocache.demand_miss_latency::total 32883377 # number of demand (read+write) miss cycles
2346system.iocache.overall_miss_latency::realview.ide 32883377 # number of overall miss cycles
2347system.iocache.overall_miss_latency::total 32883377 # number of overall miss cycles
2348system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2349system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2350system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2351system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2352system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
2353system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
2354system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
2355system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
2356system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2357system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2358system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2359system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2360system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2361system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2362system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2363system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2364system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608 # average ReadReq miss latency
2365system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency
2366system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency
2367system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency
2368system.iocache.demand_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
2369system.iocache.demand_avg_miss_latency::total 128954.419608 # average overall miss latency
2370system.iocache.overall_avg_miss_latency::realview.ide 128954.419608 # average overall miss latency
2371system.iocache.overall_avg_miss_latency::total 128954.419608 # average overall miss latency
2372system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked
2373system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2374system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
2375system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2376system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
2377system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2378system.iocache.fast_writes 0 # number of fast writes performed
2379system.iocache.cache_copies 0 # number of cache copies performed
2380system.iocache.writebacks::writebacks 36206 # number of writebacks
2381system.iocache.writebacks::total 36206 # number of writebacks
2382system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2383system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2384system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2385system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2386system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
2387system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
2388system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
2389system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
2390system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles
2391system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles
2392system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles
2393system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles
2394system.iocache.demand_mshr_miss_latency::realview.ide 20133377 # number of demand (read+write) MSHR miss cycles
2395system.iocache.demand_mshr_miss_latency::total 20133377 # number of demand (read+write) MSHR miss cycles
2396system.iocache.overall_mshr_miss_latency::realview.ide 20133377 # number of overall MSHR miss cycles
2397system.iocache.overall_mshr_miss_latency::total 20133377 # number of overall MSHR miss cycles
2398system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2399system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2400system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2401system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2402system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2403system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2404system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2405system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2406system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608 # average ReadReq mshr miss latency
2407system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency
2408system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency
2409system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency
2410system.iocache.demand_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
2411system.iocache.demand_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
2412system.iocache.overall_avg_mshr_miss_latency::realview.ide 78954.419608 # average overall mshr miss latency
2413system.iocache.overall_avg_mshr_miss_latency::total 78954.419608 # average overall mshr miss latency
2414system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2415system.l2c.tags.replacements 124374 # number of replacements
2416system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use
2417system.l2c.tags.total_refs 421293 # Total number of references to valid blocks.
2418system.l2c.tags.sampled_refs 188431 # Sample count of references to valid blocks.
2419system.l2c.tags.avg_refs 2.235795 # Average number of references to valid blocks.
2420system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2421system.l2c.tags.occ_blocks::writebacks 13456.936548 # Average occupied blocks per requestor
2422system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.884029 # Average occupied blocks per requestor
--- 265 unchanged lines hidden (view full) ---
2688system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957 # average overall miss latency
2689system.l2c.overall_avg_miss_latency::total 143055.948758 # average overall miss latency
2690system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2691system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2692system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2693system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2694system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2695system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2696system.l2c.fast_writes 0 # number of fast writes performed
2697system.l2c.cache_copies 0 # number of cache copies performed
2698system.l2c.writebacks::writebacks 97172 # number of writebacks
2699system.l2c.writebacks::total 97172 # number of writebacks
2700system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits
2701system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits
2702system.l2c.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits
2703system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
2704system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
2705system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
--- 87 unchanged lines hidden (view full) ---
2793system.l2c.overall_mshr_miss_latency::cpu1.data 1047597021 # number of overall MSHR miss cycles
2794system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 796678627 # number of overall MSHR miss cycles
2795system.l2c.overall_mshr_miss_latency::total 25144697820 # number of overall MSHR miss cycles
2796system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles
2797system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801182501 # number of ReadReq MSHR uncacheable cycles
2798system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles
2799system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359054501 # number of ReadReq MSHR uncacheable cycles
2800system.l2c.ReadReq_mshr_uncacheable_latency::total 7203084502 # number of ReadReq MSHR uncacheable cycles
2801system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702546001 # number of WriteReq MSHR uncacheable cycles
2802system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243701000 # number of WriteReq MSHR uncacheable cycles
2803system.l2c.WriteReq_mshr_uncacheable_latency::total 4946247001 # number of WriteReq MSHR uncacheable cycles
2804system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles
2805system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503728502 # number of overall MSHR uncacheable cycles
2806system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles
2807system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602755501 # number of overall MSHR uncacheable cycles
2808system.l2c.overall_mshr_uncacheable_latency::total 12149331503 # number of overall MSHR uncacheable cycles
2809system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2810system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2811system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.224375 # mshr miss rate for UpgradeReq accesses
2812system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.533969 # mshr miss rate for UpgradeReq accesses
2813system.l2c.UpgradeReq_mshr_miss_rate::total 0.252741 # mshr miss rate for UpgradeReq accesses
2814system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.224278 # mshr miss rate for SCUpgradeReq accesses
2815system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.576698 # mshr miss rate for SCUpgradeReq accesses
2816system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.383350 # mshr miss rate for SCUpgradeReq accesses
--- 63 unchanged lines hidden (view full) ---
2880system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency
2881system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency
2882system.l2c.overall_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency
2883system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency
2884system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847 # average ReadReq mshr uncacheable latency
2885system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency
2886system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency
2887system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency
2888system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165007.403804 # average WriteReq mshr uncacheable latency
2889system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100578.208832 # average WriteReq mshr uncacheable latency
2890system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159958.831932 # average WriteReq mshr uncacheable latency
2891system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency
2892system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174144.978148 # average overall mshr uncacheable latency
2893system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency
2894system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109552.072156 # average overall mshr uncacheable latency
2895system.l2c.overall_avg_mshr_uncacheable_latency::total 161954.377048 # average overall mshr uncacheable latency
2896system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2897system.membus.trans_dist::ReadReq 44095 # Transaction distribution
2898system.membus.trans_dist::ReadResp 214453 # Transaction distribution
2899system.membus.trans_dist::WriteReq 30922 # Transaction distribution
2900system.membus.trans_dist::WriteResp 30922 # Transaction distribution
2901system.membus.trans_dist::WritebackDirty 133378 # Transaction distribution
2902system.membus.trans_dist::CleanEvict 14958 # Transaction distribution
2903system.membus.trans_dist::UpgradeReq 73332 # Transaction distribution
2904system.membus.trans_dist::SCUpgradeReq 39852 # Transaction distribution
--- 136 unchanged lines hidden ---