1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.868749 # Number of seconds simulated
4sim_ticks 2868748596000 # Number of ticks simulated
5final_tick 2868748596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 740337 # Simulator instruction rate (inst/s)
8host_op_rate 895502 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 16150564794 # Simulator tick rate (ticks/s)
10host_mem_usage 599396 # Number of bytes of host memory used
11host_seconds 177.63 # Real time elapsed on the host
12sim_insts 131502488 # Number of instructions simulated
13sim_ops 159063828 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1184036 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1278116 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8584576 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.inst 111060 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.data 568976 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.l2cache.prefetcher 412800 # Number of bytes read from this memory
24system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
25system.physmem.bytes_read::total 12141100 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 1184036 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 111060 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::total 1295096 # Number of instructions bytes read from this memory
29system.physmem.bytes_written::writebacks 8715904 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
32system.physmem.bytes_written::total 8733468 # Number of bytes written to this memory
33system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.inst 26954 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.data 20490 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.l2cache.prefetcher 134134 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.inst 1890 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.data 8910 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.l2cache.prefetcher 6450 # Number of read requests responded to by this memory
41system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 198852 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 136186 # Number of write requests responded to by this memory
44system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
45system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
46system.physmem.num_writes::total 140577 # Number of write requests responded to by this memory
47system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.inst 412736 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.data 445531 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.l2cache.prefetcher 2992446 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.inst 38714 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.data 198336 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.l2cache.prefetcher 143895 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::total 4232194 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_inst_read::cpu0.inst 412736 # Instruction read bandwidth from this memory (bytes/s)
58system.physmem.bw_inst_read::cpu1.inst 38714 # Instruction read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::total 451450 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_write::writebacks 3038225 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::total 3044348 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_total::writebacks 3038225 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.inst 412736 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.data 451639 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.l2cache.prefetcher 2992446 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.inst 38714 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.data 198350 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu1.l2cache.prefetcher 143895 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::total 7276541 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.readReqs 198852 # Number of read requests accepted
76system.physmem.writeReqs 140577 # Number of write requests accepted
77system.physmem.readBursts 198852 # Number of DRAM read bursts, including those serviced by the write queue
78system.physmem.writeBursts 140577 # Number of DRAM write bursts, including those merged in the write queue
79system.physmem.bytesReadDRAM 12717568 # Total number of bytes read from DRAM
80system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue
81system.physmem.bytesWritten 8745536 # Total number of bytes written to DRAM
82system.physmem.bytesReadSys 12141100 # Total read bytes from the system interface side
83system.physmem.bytesWrittenSys 8733468 # Total written bytes from the system interface side
84system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue
85system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
86system.physmem.neitherReadNorWriteReqs 48892 # Number of requests that are neither read nor write
87system.physmem.perBankRdBursts::0 12039 # Per bank write bursts
88system.physmem.perBankRdBursts::1 11932 # Per bank write bursts
89system.physmem.perBankRdBursts::2 12219 # Per bank write bursts
90system.physmem.perBankRdBursts::3 12193 # Per bank write bursts
91system.physmem.perBankRdBursts::4 20606 # Per bank write bursts
92system.physmem.perBankRdBursts::5 12429 # Per bank write bursts
93system.physmem.perBankRdBursts::6 12151 # Per bank write bursts
94system.physmem.perBankRdBursts::7 12313 # Per bank write bursts
95system.physmem.perBankRdBursts::8 12521 # Per bank write bursts
96system.physmem.perBankRdBursts::9 12643 # Per bank write bursts
97system.physmem.perBankRdBursts::10 11981 # Per bank write bursts
98system.physmem.perBankRdBursts::11 11107 # Per bank write bursts
99system.physmem.perBankRdBursts::12 11212 # Per bank write bursts
100system.physmem.perBankRdBursts::13 11639 # Per bank write bursts
101system.physmem.perBankRdBursts::14 10708 # Per bank write bursts
102system.physmem.perBankRdBursts::15 11019 # Per bank write bursts
103system.physmem.perBankWrBursts::0 8788 # Per bank write bursts
104system.physmem.perBankWrBursts::1 8813 # Per bank write bursts
105system.physmem.perBankWrBursts::2 9145 # Per bank write bursts
106system.physmem.perBankWrBursts::3 8891 # Per bank write bursts
107system.physmem.perBankWrBursts::4 8356 # Per bank write bursts
108system.physmem.perBankWrBursts::5 8969 # Per bank write bursts
109system.physmem.perBankWrBursts::6 8864 # Per bank write bursts
110system.physmem.perBankWrBursts::7 8722 # Per bank write bursts
111system.physmem.perBankWrBursts::8 9036 # Per bank write bursts
112system.physmem.perBankWrBursts::9 9148 # Per bank write bursts
113system.physmem.perBankWrBursts::10 8611 # Per bank write bursts
114system.physmem.perBankWrBursts::11 8177 # Per bank write bursts
115system.physmem.perBankWrBursts::12 8063 # Per bank write bursts
116system.physmem.perBankWrBursts::13 7981 # Per bank write bursts
117system.physmem.perBankWrBursts::14 7509 # Per bank write bursts
118system.physmem.perBankWrBursts::15 7576 # Per bank write bursts
119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
120system.physmem.numWrRetry 39 # Number of times write queue was full causing retry
121system.physmem.totGap 2868748135500 # Total gap between requests
122system.physmem.readPktSize::0 0 # Read request sizes (log2)
123system.physmem.readPktSize::1 0 # Read request sizes (log2)
124system.physmem.readPktSize::2 9731 # Read request sizes (log2)
125system.physmem.readPktSize::3 28 # Read request sizes (log2)
126system.physmem.readPktSize::4 0 # Read request sizes (log2)
127system.physmem.readPktSize::5 0 # Read request sizes (log2)
128system.physmem.readPktSize::6 189093 # Read request sizes (log2)
129system.physmem.writePktSize::0 0 # Write request sizes (log2)
130system.physmem.writePktSize::1 0 # Write request sizes (log2)
131system.physmem.writePktSize::2 4391 # Write request sizes (log2)
132system.physmem.writePktSize::3 0 # Write request sizes (log2)
133system.physmem.writePktSize::4 0 # Write request sizes (log2)
134system.physmem.writePktSize::5 0 # Write request sizes (log2)
135system.physmem.writePktSize::6 136186 # Write request sizes (log2)
136system.physmem.rdQLenPdf::0 138565 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::1 16001 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::2 10431 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::3 8838 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::4 7035 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::5 5529 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::6 4705 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::7 3918 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::8 3439 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::9 106 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::10 73 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
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155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::15 2660 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::16 3121 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::17 4817 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::18 5889 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::19 6298 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::20 6719 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::21 6977 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::22 8373 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::24 9929 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::25 9268 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::26 9147 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::27 8525 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::28 8846 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::29 10151 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::30 8179 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::31 7567 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::32 7217 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::33 283 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::35 252 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::40 245 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::42 148 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::44 165 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::45 127 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::46 158 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::47 160 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::49 144 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::52 118 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::53 128 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::55 153 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::56 79 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::59 49 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::62 60 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::63 133 # What write queue length does an incoming req see
232system.physmem.bytesPerActivate::samples 88033 # Bytes accessed per row activation
233system.physmem.bytesPerActivate::mean 243.806754 # Bytes accessed per row activation
234system.physmem.bytesPerActivate::gmean 138.095781 # Bytes accessed per row activation
235system.physmem.bytesPerActivate::stdev 304.392225 # Bytes accessed per row activation
236system.physmem.bytesPerActivate::0-127 45989 52.24% 52.24% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::128-255 18103 20.56% 72.80% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::256-383 5912 6.72% 79.52% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::384-511 3673 4.17% 83.69% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::512-639 2470 2.81% 86.50% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::640-767 1565 1.78% 88.28% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::768-895 995 1.13% 89.41% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::896-1023 958 1.09% 90.49% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::1024-1151 8368 9.51% 100.00% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::total 88033 # Bytes accessed per row activation
246system.physmem.rdPerTurnAround::samples 6795 # Reads before turning the bus around for writes
247system.physmem.rdPerTurnAround::mean 29.243709 # Reads before turning the bus around for writes
248system.physmem.rdPerTurnAround::stdev 545.811163 # Reads before turning the bus around for writes
249system.physmem.rdPerTurnAround::0-2047 6793 99.97% 99.97% # Reads before turning the bus around for writes
250system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::total 6795 # Reads before turning the bus around for writes
253system.physmem.wrPerTurnAround::samples 6795 # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::mean 20.110228 # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::gmean 18.616765 # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::stdev 12.492638 # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::16-19 5748 84.59% 84.59% # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::20-23 291 4.28% 88.87% # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::24-27 178 2.62% 91.49% # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::28-31 60 0.88% 92.38% # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::32-35 79 1.16% 93.54% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::36-39 156 2.30% 95.84% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::40-43 28 0.41% 96.25% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::44-47 7 0.10% 96.35% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::48-51 12 0.18% 96.53% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::52-55 7 0.10% 96.63% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::56-59 9 0.13% 96.76% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::60-63 7 0.10% 96.87% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::64-67 161 2.37% 99.23% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::68-71 3 0.04% 99.28% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::72-75 4 0.06% 99.34% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::76-79 11 0.16% 99.50% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::80-83 3 0.04% 99.54% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::92-95 2 0.03% 99.59% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::112-115 1 0.01% 99.60% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::116-119 1 0.01% 99.62% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::124-127 3 0.04% 99.66% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::128-131 11 0.16% 99.82% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::140-143 1 0.01% 99.84% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::164-167 4 0.06% 99.90% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::172-175 1 0.01% 99.91% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::176-179 5 0.07% 99.99% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::total 6795 # Writes before turning the bus around for reads
286system.physmem.totQLat 4722732900 # Total ticks spent queuing
287system.physmem.totMemAccLat 8448582900 # Total ticks spent from burst creation until serviced by the DRAM
288system.physmem.totBusLat 993560000 # Total ticks spent in databus transfers
289system.physmem.avgQLat 23766.72 # Average queueing delay per DRAM burst
290system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
291system.physmem.avgMemAccLat 42516.72 # Average memory access latency per DRAM burst
292system.physmem.avgRdBW 4.43 # Average DRAM read bandwidth in MiByte/s
293system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s
294system.physmem.avgRdBWSys 4.23 # Average system read bandwidth in MiByte/s
295system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s
296system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
297system.physmem.busUtil 0.06 # Data bus utilization in percentage
298system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
299system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
300system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
301system.physmem.avgWrQLen 22.76 # Average write queue length when enqueuing
302system.physmem.readRowHits 166188 # Number of row buffer hits during reads
303system.physmem.writeRowHits 81139 # Number of row buffer hits during writes
304system.physmem.readRowHitRate 83.63 # Row buffer hit rate for reads
305system.physmem.writeRowHitRate 59.36 # Row buffer hit rate for writes
306system.physmem.avgGap 8451688.38 # Average gap between requests
307system.physmem.pageHitRate 73.74 # Row buffer hit rate, read and write combined
308system.physmem_0.actEnergy 346580640 # Energy for activate commands per rank (pJ)
309system.physmem_0.preEnergy 189106500 # Energy for precharge commands per rank (pJ)
310system.physmem_0.readEnergy 825871800 # Energy for read commands per rank (pJ)
311system.physmem_0.writeEnergy 457151040 # Energy for write commands per rank (pJ)
312system.physmem_0.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ)
313system.physmem_0.actBackEnergy 84248156880 # Energy for active background per rank (pJ)
314system.physmem_0.preBackEnergy 1647343810500 # Energy for precharge background per rank (pJ)
315system.physmem_0.totalEnergy 1920782998080 # Total energy per rank (pJ)
316system.physmem_0.averagePower 669.555658 # Core power per rank (mW)
317system.physmem_0.memoryStateTime::IDLE 2740372132788 # Time in different power states
318system.physmem_0.memoryStateTime::REF 95793620000 # Time in different power states
319system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
320system.physmem_0.memoryStateTime::ACT 32582747712 # Time in different power states
321system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
322system.physmem_1.actEnergy 318948840 # Energy for activate commands per rank (pJ)
323system.physmem_1.preEnergy 174029625 # Energy for precharge commands per rank (pJ)
324system.physmem_1.readEnergy 724074000 # Energy for read commands per rank (pJ)
325system.physmem_1.writeEnergy 428334480 # Energy for write commands per rank (pJ)
326system.physmem_1.refreshEnergy 187372320720 # Energy for refresh commands per rank (pJ)
327system.physmem_1.actBackEnergy 83576818575 # Energy for active background per rank (pJ)
328system.physmem_1.preBackEnergy 1647932703750 # Energy for precharge background per rank (pJ)
329system.physmem_1.totalEnergy 1920527229990 # Total energy per rank (pJ)
330system.physmem_1.averagePower 669.466501 # Core power per rank (mW)
331system.physmem_1.memoryStateTime::IDLE 2741353761866 # Time in different power states
332system.physmem_1.memoryStateTime::REF 95793620000 # Time in different power states
333system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
334system.physmem_1.memoryStateTime::ACT 31595469384 # Time in different power states
335system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
336system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
337system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
338system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
339system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
340system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
341system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
342system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory

--- 39 unchanged lines hidden (view full) ---

382system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
383system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
384system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
385system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
386system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
387system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
388system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
389system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
390system.cpu0.dtb.walker.walks 7824 # Table walker walks requested
391system.cpu0.dtb.walker.walksShort 7824 # Table walker walks initiated with short descriptors
392system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1442 # Level at which table walker walks with short descriptors terminate
393system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6382 # Level at which table walker walks with short descriptors terminate
394system.cpu0.dtb.walker.walkWaitTime::samples 7824 # Table walker wait (enqueue to first request) latency
395system.cpu0.dtb.walker.walkWaitTime::0 7824 100.00% 100.00% # Table walker wait (enqueue to first request) latency
396system.cpu0.dtb.walker.walkWaitTime::total 7824 # Table walker wait (enqueue to first request) latency
397system.cpu0.dtb.walker.walkCompletionTime::samples 6430 # Table walker service (enqueue to completion) latency
398system.cpu0.dtb.walker.walkCompletionTime::mean 10325.194401 # Table walker service (enqueue to completion) latency
399system.cpu0.dtb.walker.walkCompletionTime::gmean 9252.413387 # Table walker service (enqueue to completion) latency
400system.cpu0.dtb.walker.walkCompletionTime::stdev 6597.669693 # Table walker service (enqueue to completion) latency
401system.cpu0.dtb.walker.walkCompletionTime::0-32767 6417 99.80% 99.80% # Table walker service (enqueue to completion) latency
402system.cpu0.dtb.walker.walkCompletionTime::32768-65535 7 0.11% 99.91% # Table walker service (enqueue to completion) latency
403system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency
404system.cpu0.dtb.walker.walkCompletionTime::98304-131071 3 0.05% 99.98% # Table walker service (enqueue to completion) latency
405system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
406system.cpu0.dtb.walker.walkCompletionTime::total 6430 # Table walker service (enqueue to completion) latency
407system.cpu0.dtb.walker.walksPending::samples 1109412500 # Table walker pending requests distribution
408system.cpu0.dtb.walker.walksPending::0 1109412500 100.00% 100.00% # Table walker pending requests distribution
409system.cpu0.dtb.walker.walksPending::total 1109412500 # Table walker pending requests distribution
410system.cpu0.dtb.walker.walkPageSizes::4K 5027 78.18% 78.18% # Table walker page sizes translated
411system.cpu0.dtb.walker.walkPageSizes::1M 1403 21.82% 100.00% # Table walker page sizes translated
412system.cpu0.dtb.walker.walkPageSizes::total 6430 # Table walker page sizes translated
413system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7824 # Table walker requests started/completed, data/inst
414system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
415system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7824 # Table walker requests started/completed, data/inst
416system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6430 # Table walker requests started/completed, data/inst
417system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
418system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6430 # Table walker requests started/completed, data/inst
419system.cpu0.dtb.walker.walkRequestOrigin::total 14254 # Table walker requests started/completed, data/inst
420system.cpu0.dtb.inst_hits 0 # ITB inst hits
421system.cpu0.dtb.inst_misses 0 # ITB inst misses
422system.cpu0.dtb.read_hits 25236580 # DTB read hits
423system.cpu0.dtb.read_misses 6707 # DTB read misses
424system.cpu0.dtb.write_hits 18793560 # DTB write hits
425system.cpu0.dtb.write_misses 1117 # DTB write misses
426system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
427system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
428system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
429system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
430system.cpu0.dtb.flush_entries 3444 # Number of entries that have been flushed from TLB
431system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
432system.cpu0.dtb.prefetch_faults 1747 # Number of TLB faults due to prefetch
433system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
434system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
435system.cpu0.dtb.read_accesses 25243287 # DTB read accesses
436system.cpu0.dtb.write_accesses 18794677 # DTB write accesses
437system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
438system.cpu0.dtb.hits 44030140 # DTB hits
439system.cpu0.dtb.misses 7824 # DTB misses
440system.cpu0.dtb.accesses 44037964 # DTB accesses
441system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
442system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
443system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
444system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
445system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
446system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
447system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

462system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
463system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
464system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
465system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
466system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
467system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
468system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
469system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
470system.cpu0.itb.walker.walks 3348 # Table walker walks requested
471system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors
472system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate
473system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate
474system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency
475system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency
476system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency
477system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency
478system.cpu0.itb.walker.walkCompletionTime::mean 10655.874786 # Table walker service (enqueue to completion) latency
479system.cpu0.itb.walker.walkCompletionTime::gmean 9465.333686 # Table walker service (enqueue to completion) latency
480system.cpu0.itb.walker.walkCompletionTime::stdev 5846.917058 # Table walker service (enqueue to completion) latency
481system.cpu0.itb.walker.walkCompletionTime::0-8191 920 39.45% 39.45% # Table walker service (enqueue to completion) latency
482system.cpu0.itb.walker.walkCompletionTime::8192-16383 1284 55.06% 94.51% # Table walker service (enqueue to completion) latency
483system.cpu0.itb.walker.walkCompletionTime::16384-24575 84 3.60% 98.11% # Table walker service (enqueue to completion) latency
484system.cpu0.itb.walker.walkCompletionTime::24576-32767 34 1.46% 99.57% # Table walker service (enqueue to completion) latency
485system.cpu0.itb.walker.walkCompletionTime::32768-40959 8 0.34% 99.91% # Table walker service (enqueue to completion) latency
486system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
487system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
488system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency
489system.cpu0.itb.walker.walksPending::samples 1109040500 # Table walker pending requests distribution
490system.cpu0.itb.walker.walksPending::0 1109040500 100.00% 100.00% # Table walker pending requests distribution
491system.cpu0.itb.walker.walksPending::total 1109040500 # Table walker pending requests distribution
492system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated
493system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated
494system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated
495system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
496system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst
497system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst
498system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
499system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst
500system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst
501system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst
502system.cpu0.itb.inst_hits 119342617 # ITB inst hits
503system.cpu0.itb.inst_misses 3348 # ITB inst misses
504system.cpu0.itb.read_hits 0 # DTB read hits
505system.cpu0.itb.read_misses 0 # DTB read misses
506system.cpu0.itb.write_hits 0 # DTB write hits
507system.cpu0.itb.write_misses 0 # DTB write misses
508system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
509system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
510system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
511system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
512system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB
513system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
514system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
515system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
516system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
517system.cpu0.itb.read_accesses 0 # DTB read accesses
518system.cpu0.itb.write_accesses 0 # DTB write accesses
519system.cpu0.itb.inst_accesses 119345965 # ITB inst accesses
520system.cpu0.itb.hits 119342617 # DTB hits
521system.cpu0.itb.misses 3348 # DTB misses
522system.cpu0.itb.accesses 119345965 # DTB accesses
523system.cpu0.numCycles 5737497192 # number of cpu cycles simulated
524system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
525system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
526system.cpu0.committedInsts 115654281 # Number of instructions committed
527system.cpu0.committedOps 139770289 # Number of ops (including micro ops) committed
528system.cpu0.num_int_alu_accesses 123734710 # Number of integer alu accesses
529system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses
530system.cpu0.num_func_calls 12768418 # number of times a function call or return occured
531system.cpu0.num_conditional_control_insts 15718242 # number of instructions that are conditional controls
532system.cpu0.num_int_insts 123734710 # number of integer instructions
533system.cpu0.num_fp_insts 9820 # number of float instructions
534system.cpu0.num_int_register_reads 227859200 # number of times the integer registers were read
535system.cpu0.num_int_register_writes 85998639 # number of times the integer registers were written
536system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read
537system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
538system.cpu0.num_cc_register_reads 506429091 # number of times the CC registers were read
539system.cpu0.num_cc_register_writes 52352971 # number of times the CC registers were written
540system.cpu0.num_mem_refs 45168124 # number of memory refs
541system.cpu0.num_load_insts 25488908 # Number of load instructions
542system.cpu0.num_store_insts 19679216 # Number of store instructions
543system.cpu0.num_idle_cycles 5463941135.084096 # Number of idle cycles
544system.cpu0.num_busy_cycles 273556056.915905 # Number of busy cycles
545system.cpu0.not_idle_fraction 0.047679 # Percentage of non-idle cycles
546system.cpu0.idle_fraction 0.952321 # Percentage of idle cycles
547system.cpu0.Branches 29223626 # Number of branches fetched
548system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
549system.cpu0.op_class::IntAlu 98271812 68.45% 68.45% # Class of executed instruction
550system.cpu0.op_class::IntMult 109732 0.08% 68.53% # Class of executed instruction
551system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction
552system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction
553system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction
554system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction
555system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
556system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction
557system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction
558system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction
559system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction
560system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction
561system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction
562system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction
563system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction
564system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction
565system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction
566system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction
567system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction
568system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction
569system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction
570system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction
571system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction
572system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction
573system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction
574system.cpu0.op_class::SimdFloatMisc 8207 0.01% 68.54% # Class of executed instruction
575system.cpu0.op_class::SimdFloatMult 0 0.00% 68.54% # Class of executed instruction
576system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.54% # Class of executed instruction
577system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.54% # Class of executed instruction
578system.cpu0.op_class::MemRead 25488908 17.75% 86.29% # Class of executed instruction
579system.cpu0.op_class::MemWrite 19679216 13.71% 100.00% # Class of executed instruction
580system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
581system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
582system.cpu0.op_class::total 143560148 # Class of executed instruction
583system.cpu0.kern.inst.arm 0 # number of arm instructions executed
584system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed
585system.cpu0.dcache.tags.replacements 696532 # number of replacements
586system.cpu0.dcache.tags.tagsinuse 491.305468 # Cycle average of tags in use
587system.cpu0.dcache.tags.total_refs 43154174 # Total number of references to valid blocks.
588system.cpu0.dcache.tags.sampled_refs 697044 # Sample count of references to valid blocks.
589system.cpu0.dcache.tags.avg_refs 61.910258 # Average number of references to valid blocks.
590system.cpu0.dcache.tags.warmup_cycle 1135377000 # Cycle when the warmup percentage was hit.
591system.cpu0.dcache.tags.occ_blocks::cpu0.data 491.305468 # Average occupied blocks per requestor
592system.cpu0.dcache.tags.occ_percent::cpu0.data 0.959581 # Average percentage of cache occupancy
593system.cpu0.dcache.tags.occ_percent::total 0.959581 # Average percentage of cache occupancy
594system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
595system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
596system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
597system.cpu0.dcache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id
598system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
599system.cpu0.dcache.tags.tag_accesses 88699037 # Number of tag accesses
600system.cpu0.dcache.tags.data_accesses 88699037 # Number of data accesses
601system.cpu0.dcache.ReadReq_hits::cpu0.data 23972048 # number of ReadReq hits
602system.cpu0.dcache.ReadReq_hits::total 23972048 # number of ReadReq hits
603system.cpu0.dcache.WriteReq_hits::cpu0.data 18061887 # number of WriteReq hits
604system.cpu0.dcache.WriteReq_hits::total 18061887 # number of WriteReq hits
605system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318120 # number of SoftPFReq hits
606system.cpu0.dcache.SoftPFReq_hits::total 318120 # number of SoftPFReq hits
607system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365603 # number of LoadLockedReq hits
608system.cpu0.dcache.LoadLockedReq_hits::total 365603 # number of LoadLockedReq hits
609system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362648 # number of StoreCondReq hits
610system.cpu0.dcache.StoreCondReq_hits::total 362648 # number of StoreCondReq hits
611system.cpu0.dcache.demand_hits::cpu0.data 42033935 # number of demand (read+write) hits
612system.cpu0.dcache.demand_hits::total 42033935 # number of demand (read+write) hits
613system.cpu0.dcache.overall_hits::cpu0.data 42352055 # number of overall hits
614system.cpu0.dcache.overall_hits::total 42352055 # number of overall hits
615system.cpu0.dcache.ReadReq_misses::cpu0.data 398676 # number of ReadReq misses
616system.cpu0.dcache.ReadReq_misses::total 398676 # number of ReadReq misses
617system.cpu0.dcache.WriteReq_misses::cpu0.data 324664 # number of WriteReq misses
618system.cpu0.dcache.WriteReq_misses::total 324664 # number of WriteReq misses
619system.cpu0.dcache.SoftPFReq_misses::cpu0.data 128643 # number of SoftPFReq misses
620system.cpu0.dcache.SoftPFReq_misses::total 128643 # number of SoftPFReq misses
621system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21706 # number of LoadLockedReq misses
622system.cpu0.dcache.LoadLockedReq_misses::total 21706 # number of LoadLockedReq misses
623system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19707 # number of StoreCondReq misses
624system.cpu0.dcache.StoreCondReq_misses::total 19707 # number of StoreCondReq misses
625system.cpu0.dcache.demand_misses::cpu0.data 723340 # number of demand (read+write) misses
626system.cpu0.dcache.demand_misses::total 723340 # number of demand (read+write) misses
627system.cpu0.dcache.overall_misses::cpu0.data 851983 # number of overall misses
628system.cpu0.dcache.overall_misses::total 851983 # number of overall misses
629system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5067389500 # number of ReadReq miss cycles
630system.cpu0.dcache.ReadReq_miss_latency::total 5067389500 # number of ReadReq miss cycles
631system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5162627000 # number of WriteReq miss cycles
632system.cpu0.dcache.WriteReq_miss_latency::total 5162627000 # number of WriteReq miss cycles
633system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330228000 # number of LoadLockedReq miss cycles
634system.cpu0.dcache.LoadLockedReq_miss_latency::total 330228000 # number of LoadLockedReq miss cycles
635system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435506500 # number of StoreCondReq miss cycles
636system.cpu0.dcache.StoreCondReq_miss_latency::total 435506500 # number of StoreCondReq miss cycles
637system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1585500 # number of StoreCondFailReq miss cycles
638system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1585500 # number of StoreCondFailReq miss cycles
639system.cpu0.dcache.demand_miss_latency::cpu0.data 10230016500 # number of demand (read+write) miss cycles
640system.cpu0.dcache.demand_miss_latency::total 10230016500 # number of demand (read+write) miss cycles
641system.cpu0.dcache.overall_miss_latency::cpu0.data 10230016500 # number of overall miss cycles
642system.cpu0.dcache.overall_miss_latency::total 10230016500 # number of overall miss cycles
643system.cpu0.dcache.ReadReq_accesses::cpu0.data 24370724 # number of ReadReq accesses(hits+misses)
644system.cpu0.dcache.ReadReq_accesses::total 24370724 # number of ReadReq accesses(hits+misses)
645system.cpu0.dcache.WriteReq_accesses::cpu0.data 18386551 # number of WriteReq accesses(hits+misses)
646system.cpu0.dcache.WriteReq_accesses::total 18386551 # number of WriteReq accesses(hits+misses)
647system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446763 # number of SoftPFReq accesses(hits+misses)
648system.cpu0.dcache.SoftPFReq_accesses::total 446763 # number of SoftPFReq accesses(hits+misses)
649system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387309 # number of LoadLockedReq accesses(hits+misses)
650system.cpu0.dcache.LoadLockedReq_accesses::total 387309 # number of LoadLockedReq accesses(hits+misses)
651system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382355 # number of StoreCondReq accesses(hits+misses)
652system.cpu0.dcache.StoreCondReq_accesses::total 382355 # number of StoreCondReq accesses(hits+misses)
653system.cpu0.dcache.demand_accesses::cpu0.data 42757275 # number of demand (read+write) accesses
654system.cpu0.dcache.demand_accesses::total 42757275 # number of demand (read+write) accesses
655system.cpu0.dcache.overall_accesses::cpu0.data 43204038 # number of overall (read+write) accesses
656system.cpu0.dcache.overall_accesses::total 43204038 # number of overall (read+write) accesses
657system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016359 # miss rate for ReadReq accesses
658system.cpu0.dcache.ReadReq_miss_rate::total 0.016359 # miss rate for ReadReq accesses
659system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017658 # miss rate for WriteReq accesses
660system.cpu0.dcache.WriteReq_miss_rate::total 0.017658 # miss rate for WriteReq accesses
661system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.287945 # miss rate for SoftPFReq accesses
662system.cpu0.dcache.SoftPFReq_miss_rate::total 0.287945 # miss rate for SoftPFReq accesses
663system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056043 # miss rate for LoadLockedReq accesses
664system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056043 # miss rate for LoadLockedReq accesses
665system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051541 # miss rate for StoreCondReq accesses
666system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051541 # miss rate for StoreCondReq accesses
667system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016917 # miss rate for demand accesses
668system.cpu0.dcache.demand_miss_rate::total 0.016917 # miss rate for demand accesses
669system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019720 # miss rate for overall accesses
670system.cpu0.dcache.overall_miss_rate::total 0.019720 # miss rate for overall accesses
671system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12710.545656 # average ReadReq miss latency
672system.cpu0.dcache.ReadReq_avg_miss_latency::total 12710.545656 # average ReadReq miss latency
673system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15901.445802 # average WriteReq miss latency
674system.cpu0.dcache.WriteReq_avg_miss_latency::total 15901.445802 # average WriteReq miss latency
675system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15213.673639 # average LoadLockedReq miss latency
676system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15213.673639 # average LoadLockedReq miss latency
677system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22099.076470 # average StoreCondReq miss latency
678system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22099.076470 # average StoreCondReq miss latency
679system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
680system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
681system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14142.749606 # average overall miss latency
682system.cpu0.dcache.demand_avg_miss_latency::total 14142.749606 # average overall miss latency
683system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12007.301202 # average overall miss latency
684system.cpu0.dcache.overall_avg_miss_latency::total 12007.301202 # average overall miss latency
685system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
686system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
687system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
688system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
689system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
690system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
691system.cpu0.dcache.fast_writes 0 # number of fast writes performed
692system.cpu0.dcache.cache_copies 0 # number of cache copies performed
693system.cpu0.dcache.writebacks::writebacks 508357 # number of writebacks
694system.cpu0.dcache.writebacks::total 508357 # number of writebacks
695system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25412 # number of ReadReq MSHR hits
696system.cpu0.dcache.ReadReq_mshr_hits::total 25412 # number of ReadReq MSHR hits
697system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15099 # number of LoadLockedReq MSHR hits
698system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15099 # number of LoadLockedReq MSHR hits
699system.cpu0.dcache.demand_mshr_hits::cpu0.data 25412 # number of demand (read+write) MSHR hits
700system.cpu0.dcache.demand_mshr_hits::total 25412 # number of demand (read+write) MSHR hits
701system.cpu0.dcache.overall_mshr_hits::cpu0.data 25412 # number of overall MSHR hits
702system.cpu0.dcache.overall_mshr_hits::total 25412 # number of overall MSHR hits
703system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 373264 # number of ReadReq MSHR misses
704system.cpu0.dcache.ReadReq_mshr_misses::total 373264 # number of ReadReq MSHR misses
705system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324664 # number of WriteReq MSHR misses
706system.cpu0.dcache.WriteReq_mshr_misses::total 324664 # number of WriteReq MSHR misses
707system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101205 # number of SoftPFReq MSHR misses
708system.cpu0.dcache.SoftPFReq_mshr_misses::total 101205 # number of SoftPFReq MSHR misses
709system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6607 # number of LoadLockedReq MSHR misses
710system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6607 # number of LoadLockedReq MSHR misses
711system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19707 # number of StoreCondReq MSHR misses
712system.cpu0.dcache.StoreCondReq_mshr_misses::total 19707 # number of StoreCondReq MSHR misses
713system.cpu0.dcache.demand_mshr_misses::cpu0.data 697928 # number of demand (read+write) MSHR misses
714system.cpu0.dcache.demand_mshr_misses::total 697928 # number of demand (read+write) MSHR misses
715system.cpu0.dcache.overall_mshr_misses::cpu0.data 799133 # number of overall MSHR misses
716system.cpu0.dcache.overall_mshr_misses::total 799133 # number of overall MSHR misses
717system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32335 # number of ReadReq MSHR uncacheable
718system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32335 # number of ReadReq MSHR uncacheable
719system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28719 # number of WriteReq MSHR uncacheable
720system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28719 # number of WriteReq MSHR uncacheable
721system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 61054 # number of overall MSHR uncacheable misses
722system.cpu0.dcache.overall_mshr_uncacheable_misses::total 61054 # number of overall MSHR uncacheable misses
723system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4299217000 # number of ReadReq MSHR miss cycles
724system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4299217000 # number of ReadReq MSHR miss cycles
725system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4837963000 # number of WriteReq MSHR miss cycles
726system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4837963000 # number of WriteReq MSHR miss cycles
727system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1611370000 # number of SoftPFReq MSHR miss cycles
728system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1611370000 # number of SoftPFReq MSHR miss cycles
729system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 100016000 # number of LoadLockedReq MSHR miss cycles
730system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100016000 # number of LoadLockedReq MSHR miss cycles
731system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 415846500 # number of StoreCondReq MSHR miss cycles
732system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 415846500 # number of StoreCondReq MSHR miss cycles
733system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1538500 # number of StoreCondFailReq MSHR miss cycles
734system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1538500 # number of StoreCondFailReq MSHR miss cycles
735system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9137180000 # number of demand (read+write) MSHR miss cycles
736system.cpu0.dcache.demand_mshr_miss_latency::total 9137180000 # number of demand (read+write) MSHR miss cycles
737system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10748550000 # number of overall MSHR miss cycles
738system.cpu0.dcache.overall_mshr_miss_latency::total 10748550000 # number of overall MSHR miss cycles
739system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6362298500 # number of ReadReq MSHR uncacheable cycles
740system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6362298500 # number of ReadReq MSHR uncacheable cycles
741system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4936759500 # number of WriteReq MSHR uncacheable cycles
742system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4936759500 # number of WriteReq MSHR uncacheable cycles
743system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11299058000 # number of overall MSHR uncacheable cycles
744system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11299058000 # number of overall MSHR uncacheable cycles
745system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015316 # mshr miss rate for ReadReq accesses
746system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015316 # mshr miss rate for ReadReq accesses
747system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017658 # mshr miss rate for WriteReq accesses
748system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017658 # mshr miss rate for WriteReq accesses
749system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226530 # mshr miss rate for SoftPFReq accesses
750system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226530 # mshr miss rate for SoftPFReq accesses
751system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017059 # mshr miss rate for LoadLockedReq accesses
752system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017059 # mshr miss rate for LoadLockedReq accesses
753system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051541 # mshr miss rate for StoreCondReq accesses
754system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051541 # mshr miss rate for StoreCondReq accesses
755system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016323 # mshr miss rate for demand accesses
756system.cpu0.dcache.demand_mshr_miss_rate::total 0.016323 # mshr miss rate for demand accesses
757system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018497 # mshr miss rate for overall accesses
758system.cpu0.dcache.overall_mshr_miss_rate::total 0.018497 # mshr miss rate for overall accesses
759system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11517.898860 # average ReadReq mshr miss latency
760system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11517.898860 # average ReadReq mshr miss latency
761system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14901.445802 # average WriteReq mshr miss latency
762system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14901.445802 # average WriteReq mshr miss latency
763system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15921.841806 # average SoftPFReq mshr miss latency
764system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15921.841806 # average SoftPFReq mshr miss latency
765system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15137.884062 # average LoadLockedReq mshr miss latency
766system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15137.884062 # average LoadLockedReq mshr miss latency
767system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21101.461410 # average StoreCondReq mshr miss latency
768system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21101.461410 # average StoreCondReq mshr miss latency
769system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
770system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
771system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13091.866210 # average overall mshr miss latency
772system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13091.866210 # average overall mshr miss latency
773system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13450.264224 # average overall mshr miss latency
774system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13450.264224 # average overall mshr miss latency
775system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196761.976187 # average ReadReq mshr uncacheable latency
776system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196761.976187 # average ReadReq mshr uncacheable latency
777system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171898.725582 # average WriteReq mshr uncacheable latency
778system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171898.725582 # average WriteReq mshr uncacheable latency
779system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185066.629541 # average overall mshr uncacheable latency
780system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 185066.629541 # average overall mshr uncacheable latency
781system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
782system.cpu0.icache.tags.replacements 1105972 # number of replacements
783system.cpu0.icache.tags.tagsinuse 511.454897 # Cycle average of tags in use
784system.cpu0.icache.tags.total_refs 118236124 # Total number of references to valid blocks.
785system.cpu0.icache.tags.sampled_refs 1106484 # Sample count of references to valid blocks.
786system.cpu0.icache.tags.avg_refs 106.857509 # Average number of references to valid blocks.
787system.cpu0.icache.tags.warmup_cycle 13516114000 # Cycle when the warmup percentage was hit.
788system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.454897 # Average occupied blocks per requestor
789system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998935 # Average percentage of cache occupancy
790system.cpu0.icache.tags.occ_percent::total 0.998935 # Average percentage of cache occupancy
791system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
792system.cpu0.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
793system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
794system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id
795system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
796system.cpu0.icache.tags.tag_accesses 239791727 # Number of tag accesses
797system.cpu0.icache.tags.data_accesses 239791727 # Number of data accesses
798system.cpu0.icache.ReadReq_hits::cpu0.inst 118236124 # number of ReadReq hits
799system.cpu0.icache.ReadReq_hits::total 118236124 # number of ReadReq hits
800system.cpu0.icache.demand_hits::cpu0.inst 118236124 # number of demand (read+write) hits
801system.cpu0.icache.demand_hits::total 118236124 # number of demand (read+write) hits
802system.cpu0.icache.overall_hits::cpu0.inst 118236124 # number of overall hits
803system.cpu0.icache.overall_hits::total 118236124 # number of overall hits
804system.cpu0.icache.ReadReq_misses::cpu0.inst 1106493 # number of ReadReq misses
805system.cpu0.icache.ReadReq_misses::total 1106493 # number of ReadReq misses
806system.cpu0.icache.demand_misses::cpu0.inst 1106493 # number of demand (read+write) misses
807system.cpu0.icache.demand_misses::total 1106493 # number of demand (read+write) misses
808system.cpu0.icache.overall_misses::cpu0.inst 1106493 # number of overall misses
809system.cpu0.icache.overall_misses::total 1106493 # number of overall misses
810system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10938029500 # number of ReadReq miss cycles
811system.cpu0.icache.ReadReq_miss_latency::total 10938029500 # number of ReadReq miss cycles
812system.cpu0.icache.demand_miss_latency::cpu0.inst 10938029500 # number of demand (read+write) miss cycles
813system.cpu0.icache.demand_miss_latency::total 10938029500 # number of demand (read+write) miss cycles
814system.cpu0.icache.overall_miss_latency::cpu0.inst 10938029500 # number of overall miss cycles
815system.cpu0.icache.overall_miss_latency::total 10938029500 # number of overall miss cycles
816system.cpu0.icache.ReadReq_accesses::cpu0.inst 119342617 # number of ReadReq accesses(hits+misses)
817system.cpu0.icache.ReadReq_accesses::total 119342617 # number of ReadReq accesses(hits+misses)
818system.cpu0.icache.demand_accesses::cpu0.inst 119342617 # number of demand (read+write) accesses
819system.cpu0.icache.demand_accesses::total 119342617 # number of demand (read+write) accesses
820system.cpu0.icache.overall_accesses::cpu0.inst 119342617 # number of overall (read+write) accesses
821system.cpu0.icache.overall_accesses::total 119342617 # number of overall (read+write) accesses
822system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009272 # miss rate for ReadReq accesses
823system.cpu0.icache.ReadReq_miss_rate::total 0.009272 # miss rate for ReadReq accesses
824system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009272 # miss rate for demand accesses
825system.cpu0.icache.demand_miss_rate::total 0.009272 # miss rate for demand accesses
826system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009272 # miss rate for overall accesses
827system.cpu0.icache.overall_miss_rate::total 0.009272 # miss rate for overall accesses
828system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9885.312876 # average ReadReq miss latency
829system.cpu0.icache.ReadReq_avg_miss_latency::total 9885.312876 # average ReadReq miss latency
830system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9885.312876 # average overall miss latency
831system.cpu0.icache.demand_avg_miss_latency::total 9885.312876 # average overall miss latency
832system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9885.312876 # average overall miss latency
833system.cpu0.icache.overall_avg_miss_latency::total 9885.312876 # average overall miss latency
834system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
835system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
836system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
837system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
838system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
839system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
840system.cpu0.icache.fast_writes 0 # number of fast writes performed
841system.cpu0.icache.cache_copies 0 # number of cache copies performed
842system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1106493 # number of ReadReq MSHR misses
843system.cpu0.icache.ReadReq_mshr_misses::total 1106493 # number of ReadReq MSHR misses
844system.cpu0.icache.demand_mshr_misses::cpu0.inst 1106493 # number of demand (read+write) MSHR misses
845system.cpu0.icache.demand_mshr_misses::total 1106493 # number of demand (read+write) MSHR misses
846system.cpu0.icache.overall_mshr_misses::cpu0.inst 1106493 # number of overall MSHR misses
847system.cpu0.icache.overall_mshr_misses::total 1106493 # number of overall MSHR misses
848system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
849system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
850system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
851system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
852system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10384783000 # number of ReadReq MSHR miss cycles
853system.cpu0.icache.ReadReq_mshr_miss_latency::total 10384783000 # number of ReadReq MSHR miss cycles
854system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10384783000 # number of demand (read+write) MSHR miss cycles
855system.cpu0.icache.demand_mshr_miss_latency::total 10384783000 # number of demand (read+write) MSHR miss cycles
856system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10384783000 # number of overall MSHR miss cycles
857system.cpu0.icache.overall_mshr_miss_latency::total 10384783000 # number of overall MSHR miss cycles
858system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 800795500 # number of ReadReq MSHR uncacheable cycles
859system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 800795500 # number of ReadReq MSHR uncacheable cycles
860system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 800795500 # number of overall MSHR uncacheable cycles
861system.cpu0.icache.overall_mshr_uncacheable_latency::total 800795500 # number of overall MSHR uncacheable cycles
862system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for ReadReq accesses
863system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009272 # mshr miss rate for ReadReq accesses
864system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for demand accesses
865system.cpu0.icache.demand_mshr_miss_rate::total 0.009272 # mshr miss rate for demand accesses
866system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009272 # mshr miss rate for overall accesses
867system.cpu0.icache.overall_mshr_miss_rate::total 0.009272 # mshr miss rate for overall accesses
868system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average ReadReq mshr miss latency
869system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9385.312876 # average ReadReq mshr miss latency
870system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average overall mshr miss latency
871system.cpu0.icache.demand_avg_mshr_miss_latency::total 9385.312876 # average overall mshr miss latency
872system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9385.312876 # average overall mshr miss latency
873system.cpu0.icache.overall_avg_mshr_miss_latency::total 9385.312876 # average overall mshr miss latency
874system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average ReadReq mshr uncacheable latency
875system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88760.308136 # average ReadReq mshr uncacheable latency
876system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88760.308136 # average overall mshr uncacheable latency
877system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88760.308136 # average overall mshr uncacheable latency
878system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
879system.cpu0.l2cache.prefetcher.num_hwpf_issued 1841098 # number of hwpf issued
880system.cpu0.l2cache.prefetcher.pfIdentified 1841106 # number of prefetch candidates identified
881system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue
882system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
883system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
884system.cpu0.l2cache.prefetcher.pfSpanPage 237750 # number of prefetches not generated due to page crossing
885system.cpu0.l2cache.tags.replacements 269395 # number of replacements
886system.cpu0.l2cache.tags.tagsinuse 16110.328705 # Cycle average of tags in use
887system.cpu0.l2cache.tags.total_refs 3241181 # Total number of references to valid blocks.
888system.cpu0.l2cache.tags.sampled_refs 285612 # Sample count of references to valid blocks.
889system.cpu0.l2cache.tags.avg_refs 11.348196 # Average number of references to valid blocks.
890system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
891system.cpu0.l2cache.tags.occ_blocks::writebacks 7729.941983 # Average occupied blocks per requestor
892system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.543117 # Average occupied blocks per requestor
893system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.104661 # Average occupied blocks per requestor
894system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4692.501202 # Average occupied blocks per requestor
895system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1977.796502 # Average occupied blocks per requestor
896system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1707.441239 # Average occupied blocks per requestor
897system.cpu0.l2cache.tags.occ_percent::writebacks 0.471798 # Average percentage of cache occupancy
898system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000155 # Average percentage of cache occupancy
899system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy
900system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.286408 # Average percentage of cache occupancy
901system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.120715 # Average percentage of cache occupancy
902system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104214 # Average percentage of cache occupancy
903system.cpu0.l2cache.tags.occ_percent::total 0.983296 # Average percentage of cache occupancy
904system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1097 # Occupied blocks per task id
905system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
906system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15114 # Occupied blocks per task id
907system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
908system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 275 # Occupied blocks per task id
909system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 382 # Occupied blocks per task id
910system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 431 # Occupied blocks per task id
911system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
912system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
913system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
914system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
915system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3320 # Occupied blocks per task id
916system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7689 # Occupied blocks per task id
917system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3966 # Occupied blocks per task id
918system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.066956 # Percentage of cache occupancy per task id
919system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
920system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922485 # Percentage of cache occupancy per task id
921system.cpu0.l2cache.tags.tag_accesses 60150726 # Number of tag accesses
922system.cpu0.l2cache.tags.data_accesses 60150726 # Number of data accesses
923system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7925 # number of ReadReq hits
924system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3539 # number of ReadReq hits
925system.cpu0.l2cache.ReadReq_hits::total 11464 # number of ReadReq hits
926system.cpu0.l2cache.Writeback_hits::writebacks 508356 # number of Writeback hits
927system.cpu0.l2cache.Writeback_hits::total 508356 # number of Writeback hits
928system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28387 # number of UpgradeReq hits
929system.cpu0.l2cache.UpgradeReq_hits::total 28387 # number of UpgradeReq hits
930system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1736 # number of SCUpgradeReq hits
931system.cpu0.l2cache.SCUpgradeReq_hits::total 1736 # number of SCUpgradeReq hits
932system.cpu0.l2cache.ReadExReq_hits::cpu0.data 229125 # number of ReadExReq hits
933system.cpu0.l2cache.ReadExReq_hits::total 229125 # number of ReadExReq hits
934system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1058458 # number of ReadCleanReq hits
935system.cpu0.l2cache.ReadCleanReq_hits::total 1058458 # number of ReadCleanReq hits
936system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 386565 # number of ReadSharedReq hits
937system.cpu0.l2cache.ReadSharedReq_hits::total 386565 # number of ReadSharedReq hits
938system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7925 # number of demand (read+write) hits
939system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3539 # number of demand (read+write) hits
940system.cpu0.l2cache.demand_hits::cpu0.inst 1058458 # number of demand (read+write) hits
941system.cpu0.l2cache.demand_hits::cpu0.data 615690 # number of demand (read+write) hits
942system.cpu0.l2cache.demand_hits::total 1685612 # number of demand (read+write) hits
943system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7925 # number of overall hits
944system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3539 # number of overall hits
945system.cpu0.l2cache.overall_hits::cpu0.inst 1058458 # number of overall hits
946system.cpu0.l2cache.overall_hits::cpu0.data 615690 # number of overall hits
947system.cpu0.l2cache.overall_hits::total 1685612 # number of overall hits
948system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 220 # number of ReadReq misses
949system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 114 # number of ReadReq misses
950system.cpu0.l2cache.ReadReq_misses::total 334 # number of ReadReq misses
951system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 25774 # number of UpgradeReq misses
952system.cpu0.l2cache.UpgradeReq_misses::total 25774 # number of UpgradeReq misses
953system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17960 # number of SCUpgradeReq misses
954system.cpu0.l2cache.SCUpgradeReq_misses::total 17960 # number of SCUpgradeReq misses
955system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses
956system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses
957system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41378 # number of ReadExReq misses
958system.cpu0.l2cache.ReadExReq_misses::total 41378 # number of ReadExReq misses
959system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 48035 # number of ReadCleanReq misses
960system.cpu0.l2cache.ReadCleanReq_misses::total 48035 # number of ReadCleanReq misses
961system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94511 # number of ReadSharedReq misses
962system.cpu0.l2cache.ReadSharedReq_misses::total 94511 # number of ReadSharedReq misses
963system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 220 # number of demand (read+write) misses
964system.cpu0.l2cache.demand_misses::cpu0.itb.walker 114 # number of demand (read+write) misses
965system.cpu0.l2cache.demand_misses::cpu0.inst 48035 # number of demand (read+write) misses
966system.cpu0.l2cache.demand_misses::cpu0.data 135889 # number of demand (read+write) misses
967system.cpu0.l2cache.demand_misses::total 184258 # number of demand (read+write) misses
968system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 220 # number of overall misses
969system.cpu0.l2cache.overall_misses::cpu0.itb.walker 114 # number of overall misses
970system.cpu0.l2cache.overall_misses::cpu0.inst 48035 # number of overall misses
971system.cpu0.l2cache.overall_misses::cpu0.data 135889 # number of overall misses
972system.cpu0.l2cache.overall_misses::total 184258 # number of overall misses
973system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5406500 # number of ReadReq miss cycles
974system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2600000 # number of ReadReq miss cycles
975system.cpu0.l2cache.ReadReq_miss_latency::total 8006500 # number of ReadReq miss cycles
976system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 476714500 # number of UpgradeReq miss cycles
977system.cpu0.l2cache.UpgradeReq_miss_latency::total 476714500 # number of UpgradeReq miss cycles
978system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365472000 # number of SCUpgradeReq miss cycles
979system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365472000 # number of SCUpgradeReq miss cycles
980system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1464493 # number of SCUpgradeFailReq miss cycles
981system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1464493 # number of SCUpgradeFailReq miss cycles
982system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2004346000 # number of ReadExReq miss cycles
983system.cpu0.l2cache.ReadExReq_miss_latency::total 2004346000 # number of ReadExReq miss cycles
984system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2385304000 # number of ReadCleanReq miss cycles
985system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2385304000 # number of ReadCleanReq miss cycles
986system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2775342500 # number of ReadSharedReq miss cycles
987system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2775342500 # number of ReadSharedReq miss cycles
988system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5406500 # number of demand (read+write) miss cycles
989system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2600000 # number of demand (read+write) miss cycles
990system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2385304000 # number of demand (read+write) miss cycles
991system.cpu0.l2cache.demand_miss_latency::cpu0.data 4779688500 # number of demand (read+write) miss cycles
992system.cpu0.l2cache.demand_miss_latency::total 7172999000 # number of demand (read+write) miss cycles
993system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5406500 # number of overall miss cycles
994system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2600000 # number of overall miss cycles
995system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2385304000 # number of overall miss cycles
996system.cpu0.l2cache.overall_miss_latency::cpu0.data 4779688500 # number of overall miss cycles
997system.cpu0.l2cache.overall_miss_latency::total 7172999000 # number of overall miss cycles
998system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8145 # number of ReadReq accesses(hits+misses)
999system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3653 # number of ReadReq accesses(hits+misses)
1000system.cpu0.l2cache.ReadReq_accesses::total 11798 # number of ReadReq accesses(hits+misses)
1001system.cpu0.l2cache.Writeback_accesses::writebacks 508356 # number of Writeback accesses(hits+misses)
1002system.cpu0.l2cache.Writeback_accesses::total 508356 # number of Writeback accesses(hits+misses)
1003system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54161 # number of UpgradeReq accesses(hits+misses)
1004system.cpu0.l2cache.UpgradeReq_accesses::total 54161 # number of UpgradeReq accesses(hits+misses)
1005system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19696 # number of SCUpgradeReq accesses(hits+misses)
1006system.cpu0.l2cache.SCUpgradeReq_accesses::total 19696 # number of SCUpgradeReq accesses(hits+misses)
1007system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses)
1008system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses)
1009system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270503 # number of ReadExReq accesses(hits+misses)
1010system.cpu0.l2cache.ReadExReq_accesses::total 270503 # number of ReadExReq accesses(hits+misses)
1011system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1106493 # number of ReadCleanReq accesses(hits+misses)
1012system.cpu0.l2cache.ReadCleanReq_accesses::total 1106493 # number of ReadCleanReq accesses(hits+misses)
1013system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 481076 # number of ReadSharedReq accesses(hits+misses)
1014system.cpu0.l2cache.ReadSharedReq_accesses::total 481076 # number of ReadSharedReq accesses(hits+misses)
1015system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8145 # number of demand (read+write) accesses
1016system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3653 # number of demand (read+write) accesses
1017system.cpu0.l2cache.demand_accesses::cpu0.inst 1106493 # number of demand (read+write) accesses
1018system.cpu0.l2cache.demand_accesses::cpu0.data 751579 # number of demand (read+write) accesses
1019system.cpu0.l2cache.demand_accesses::total 1869870 # number of demand (read+write) accesses
1020system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8145 # number of overall (read+write) accesses
1021system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3653 # number of overall (read+write) accesses
1022system.cpu0.l2cache.overall_accesses::cpu0.inst 1106493 # number of overall (read+write) accesses
1023system.cpu0.l2cache.overall_accesses::cpu0.data 751579 # number of overall (read+write) accesses
1024system.cpu0.l2cache.overall_accesses::total 1869870 # number of overall (read+write) accesses
1025system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027010 # miss rate for ReadReq accesses
1026system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031207 # miss rate for ReadReq accesses
1027system.cpu0.l2cache.ReadReq_miss_rate::total 0.028310 # miss rate for ReadReq accesses
1028system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.475877 # miss rate for UpgradeReq accesses
1029system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.475877 # miss rate for UpgradeReq accesses
1030system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.911860 # miss rate for SCUpgradeReq accesses
1031system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.911860 # miss rate for SCUpgradeReq accesses
1032system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1033system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1034system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.152967 # miss rate for ReadExReq accesses
1035system.cpu0.l2cache.ReadExReq_miss_rate::total 0.152967 # miss rate for ReadExReq accesses
1036system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.043412 # miss rate for ReadCleanReq accesses
1037system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.043412 # miss rate for ReadCleanReq accesses
1038system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.196458 # miss rate for ReadSharedReq accesses
1039system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.196458 # miss rate for ReadSharedReq accesses
1040system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027010 # miss rate for demand accesses
1041system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031207 # miss rate for demand accesses
1042system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.043412 # miss rate for demand accesses
1043system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.180805 # miss rate for demand accesses
1044system.cpu0.l2cache.demand_miss_rate::total 0.098541 # miss rate for demand accesses
1045system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027010 # miss rate for overall accesses
1046system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031207 # miss rate for overall accesses
1047system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.043412 # miss rate for overall accesses
1048system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.180805 # miss rate for overall accesses
1049system.cpu0.l2cache.overall_miss_rate::total 0.098541 # miss rate for overall accesses
1050system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 24575 # average ReadReq miss latency
1051system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22807.017544 # average ReadReq miss latency
1052system.cpu0.l2cache.ReadReq_avg_miss_latency::total 23971.556886 # average ReadReq miss latency
1053system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18495.945526 # average UpgradeReq miss latency
1054system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18495.945526 # average UpgradeReq miss latency
1055system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20349.220490 # average SCUpgradeReq miss latency
1056system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20349.220490 # average SCUpgradeReq miss latency
1057system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 133135.727273 # average SCUpgradeFailReq miss latency
1058system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 133135.727273 # average SCUpgradeFailReq miss latency
1059system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 48439.895597 # average ReadExReq miss latency
1060system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 48439.895597 # average ReadExReq miss latency
1061system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 49657.624649 # average ReadCleanReq miss latency
1062system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 49657.624649 # average ReadCleanReq miss latency
1063system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29365.285522 # average ReadSharedReq miss latency
1064system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29365.285522 # average ReadSharedReq miss latency
1065system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 24575 # average overall miss latency
1066system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22807.017544 # average overall miss latency
1067system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49657.624649 # average overall miss latency
1068system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35173.476146 # average overall miss latency
1069system.cpu0.l2cache.demand_avg_miss_latency::total 38929.104842 # average overall miss latency
1070system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 24575 # average overall miss latency
1071system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22807.017544 # average overall miss latency
1072system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49657.624649 # average overall miss latency
1073system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35173.476146 # average overall miss latency
1074system.cpu0.l2cache.overall_avg_miss_latency::total 38929.104842 # average overall miss latency
1075system.cpu0.l2cache.blocked_cycles::no_mshrs 52 # number of cycles access was blocked
1076system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1077system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
1078system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1079system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked
1080system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1081system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1082system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1083system.cpu0.l2cache.writebacks::writebacks 196326 # number of writebacks
1084system.cpu0.l2cache.writebacks::total 196326 # number of writebacks
1085system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1152 # number of ReadExReq MSHR hits
1086system.cpu0.l2cache.ReadExReq_mshr_hits::total 1152 # number of ReadExReq MSHR hits
1087system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 31 # number of ReadSharedReq MSHR hits
1088system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 31 # number of ReadSharedReq MSHR hits
1089system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1183 # number of demand (read+write) MSHR hits
1090system.cpu0.l2cache.demand_mshr_hits::total 1183 # number of demand (read+write) MSHR hits
1091system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1183 # number of overall MSHR hits
1092system.cpu0.l2cache.overall_mshr_hits::total 1183 # number of overall MSHR hits
1093system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 220 # number of ReadReq MSHR misses
1094system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 114 # number of ReadReq MSHR misses
1095system.cpu0.l2cache.ReadReq_mshr_misses::total 334 # number of ReadReq MSHR misses
1096system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8437 # number of CleanEvict MSHR misses
1097system.cpu0.l2cache.CleanEvict_mshr_misses::total 8437 # number of CleanEvict MSHR misses
1098system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 245004 # number of HardPFReq MSHR misses
1099system.cpu0.l2cache.HardPFReq_mshr_misses::total 245004 # number of HardPFReq MSHR misses
1100system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 25774 # number of UpgradeReq MSHR misses
1101system.cpu0.l2cache.UpgradeReq_mshr_misses::total 25774 # number of UpgradeReq MSHR misses
1102system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17960 # number of SCUpgradeReq MSHR misses
1103system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17960 # number of SCUpgradeReq MSHR misses
1104system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses
1105system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses
1106system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40226 # number of ReadExReq MSHR misses
1107system.cpu0.l2cache.ReadExReq_mshr_misses::total 40226 # number of ReadExReq MSHR misses
1108system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 48035 # number of ReadCleanReq MSHR misses
1109system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 48035 # number of ReadCleanReq MSHR misses
1110system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94480 # number of ReadSharedReq MSHR misses
1111system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94480 # number of ReadSharedReq MSHR misses
1112system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 220 # number of demand (read+write) MSHR misses
1113system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 114 # number of demand (read+write) MSHR misses
1114system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 48035 # number of demand (read+write) MSHR misses
1115system.cpu0.l2cache.demand_mshr_misses::cpu0.data 134706 # number of demand (read+write) MSHR misses
1116system.cpu0.l2cache.demand_mshr_misses::total 183075 # number of demand (read+write) MSHR misses
1117system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 220 # number of overall MSHR misses
1118system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 114 # number of overall MSHR misses
1119system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 48035 # number of overall MSHR misses
1120system.cpu0.l2cache.overall_mshr_misses::cpu0.data 134706 # number of overall MSHR misses
1121system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 245004 # number of overall MSHR misses
1122system.cpu0.l2cache.overall_mshr_misses::total 428079 # number of overall MSHR misses
1123system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
1124system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32335 # number of ReadReq MSHR uncacheable
1125system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 41357 # number of ReadReq MSHR uncacheable
1126system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28719 # number of WriteReq MSHR uncacheable
1127system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28719 # number of WriteReq MSHR uncacheable
1128system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
1129system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 61054 # number of overall MSHR uncacheable misses
1130system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 70076 # number of overall MSHR uncacheable misses
1131system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4086500 # number of ReadReq MSHR miss cycles
1132system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1916000 # number of ReadReq MSHR miss cycles
1133system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 6002500 # number of ReadReq MSHR miss cycles
1134system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13739930078 # number of HardPFReq MSHR miss cycles
1135system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13739930078 # number of HardPFReq MSHR miss cycles
1136system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 517996000 # number of UpgradeReq MSHR miss cycles
1137system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 517996000 # number of UpgradeReq MSHR miss cycles
1138system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 267528500 # number of SCUpgradeReq MSHR miss cycles
1139system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 267528500 # number of SCUpgradeReq MSHR miss cycles
1140system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1182493 # number of SCUpgradeFailReq MSHR miss cycles
1141system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1182493 # number of SCUpgradeFailReq MSHR miss cycles
1142system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1648080000 # number of ReadExReq MSHR miss cycles
1143system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1648080000 # number of ReadExReq MSHR miss cycles
1144system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2097094000 # number of ReadCleanReq MSHR miss cycles
1145system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2097094000 # number of ReadCleanReq MSHR miss cycles
1146system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2203041000 # number of ReadSharedReq MSHR miss cycles
1147system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2203041000 # number of ReadSharedReq MSHR miss cycles
1148system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 4086500 # number of demand (read+write) MSHR miss cycles
1149system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1916000 # number of demand (read+write) MSHR miss cycles
1150system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2097094000 # number of demand (read+write) MSHR miss cycles
1151system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3851121000 # number of demand (read+write) MSHR miss cycles
1152system.cpu0.l2cache.demand_mshr_miss_latency::total 5954217500 # number of demand (read+write) MSHR miss cycles
1153system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 4086500 # number of overall MSHR miss cycles
1154system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1916000 # number of overall MSHR miss cycles
1155system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2097094000 # number of overall MSHR miss cycles
1156system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3851121000 # number of overall MSHR miss cycles
1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13739930078 # number of overall MSHR miss cycles
1158system.cpu0.l2cache.overall_mshr_miss_latency::total 19694147578 # number of overall MSHR miss cycles
1159system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 733130500 # number of ReadReq MSHR uncacheable cycles
1160system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6103617500 # number of ReadReq MSHR uncacheable cycles
1161system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6836748000 # number of ReadReq MSHR uncacheable cycles
1162system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4721367000 # number of WriteReq MSHR uncacheable cycles
1163system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4721367000 # number of WriteReq MSHR uncacheable cycles
1164system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 733130500 # number of overall MSHR uncacheable cycles
1165system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10824984500 # number of overall MSHR uncacheable cycles
1166system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11558115000 # number of overall MSHR uncacheable cycles
1167system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for ReadReq accesses
1168system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for ReadReq accesses
1169system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028310 # mshr miss rate for ReadReq accesses
1170system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1171system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1172system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1173system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1174system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.475877 # mshr miss rate for UpgradeReq accesses
1175system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.475877 # mshr miss rate for UpgradeReq accesses
1176system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911860 # mshr miss rate for SCUpgradeReq accesses
1177system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911860 # mshr miss rate for SCUpgradeReq accesses
1178system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1179system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1180system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148708 # mshr miss rate for ReadExReq accesses
1181system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148708 # mshr miss rate for ReadExReq accesses
1182system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for ReadCleanReq accesses
1183system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043412 # mshr miss rate for ReadCleanReq accesses
1184system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.196393 # mshr miss rate for ReadSharedReq accesses
1185system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.196393 # mshr miss rate for ReadSharedReq accesses
1186system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for demand accesses
1187system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for demand accesses
1188system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for demand accesses
1189system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.179231 # mshr miss rate for demand accesses
1190system.cpu0.l2cache.demand_mshr_miss_rate::total 0.097908 # mshr miss rate for demand accesses
1191system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027010 # mshr miss rate for overall accesses
1192system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031207 # mshr miss rate for overall accesses
1193system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.043412 # mshr miss rate for overall accesses
1194system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.179231 # mshr miss rate for overall accesses
1195system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1196system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228935 # mshr miss rate for overall accesses
1197system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average ReadReq mshr miss latency
1198system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average ReadReq mshr miss latency
1199system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 17971.556886 # average ReadReq mshr miss latency
1200system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average HardPFReq mshr miss latency
1201system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56080.431658 # average HardPFReq mshr miss latency
1202system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20097.617754 # average UpgradeReq mshr miss latency
1203system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.617754 # average UpgradeReq mshr miss latency
1204system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14895.796214 # average SCUpgradeReq mshr miss latency
1205system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14895.796214 # average SCUpgradeReq mshr miss latency
1206system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 107499.363636 # average SCUpgradeFailReq mshr miss latency
1207system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 107499.363636 # average SCUpgradeFailReq mshr miss latency
1208system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40970.516581 # average ReadExReq mshr miss latency
1209system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40970.516581 # average ReadExReq mshr miss latency
1210system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average ReadCleanReq mshr miss latency
1211system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43657.624649 # average ReadCleanReq mshr miss latency
1212system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23317.538103 # average ReadSharedReq mshr miss latency
1213system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23317.538103 # average ReadSharedReq mshr miss latency
1214system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency
1215system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency
1216system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency
1217system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency
1218system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32523.378397 # average overall mshr miss latency
1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18575 # average overall mshr miss latency
1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16807.017544 # average overall mshr miss latency
1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43657.624649 # average overall mshr miss latency
1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28589.082892 # average overall mshr miss latency
1223system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56080.431658 # average overall mshr miss latency
1224system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46005.871762 # average overall mshr miss latency
1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average ReadReq mshr uncacheable latency
1226system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188761.945261 # average ReadReq mshr uncacheable latency
1227system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165310.539933 # average ReadReq mshr uncacheable latency
1228system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164398.725582 # average WriteReq mshr uncacheable latency
1229system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164398.725582 # average WriteReq mshr uncacheable latency
1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81260.308136 # average overall mshr uncacheable latency
1231system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 177301.806597 # average overall mshr uncacheable latency
1232system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 164936.854273 # average overall mshr uncacheable latency
1233system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1234system.cpu0.toL2Bus.trans_dist::ReadReq 64646 # Transaction distribution
1235system.cpu0.toL2Bus.trans_dist::ReadResp 1697156 # Transaction distribution
1236system.cpu0.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution
1237system.cpu0.toL2Bus.trans_dist::WriteResp 28719 # Transaction distribution
1238system.cpu0.toL2Bus.trans_dist::Writeback 871288 # Transaction distribution
1239system.cpu0.toL2Bus.trans_dist::CleanEvict 1384656 # Transaction distribution
1240system.cpu0.toL2Bus.trans_dist::HardPFReq 292494 # Transaction distribution
1241system.cpu0.toL2Bus.trans_dist::UpgradeReq 87584 # Transaction distribution
1242system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42065 # Transaction distribution
1243system.cpu0.toL2Bus.trans_dist::UpgradeResp 111017 # Transaction distribution
1244system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution
1245system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution
1246system.cpu0.toL2Bus.trans_dist::ReadExReq 299003 # Transaction distribution
1247system.cpu0.toL2Bus.trans_dist::ReadExResp 286103 # Transaction distribution
1248system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1106493 # Transaction distribution
1249system.cpu0.toL2Bus.trans_dist::ReadSharedReq 579158 # Transaction distribution
1250system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
1251system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3315880 # Packet count per connected master and slave (bytes)
1252system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2563217 # Packet count per connected master and slave (bytes)
1253system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10051 # Packet count per connected master and slave (bytes)
1254system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22351 # Packet count per connected master and slave (bytes)
1255system.cpu0.toL2Bus.pkt_count::total 5911499 # Packet count per connected master and slave (bytes)
1256system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70851640 # Cumulative packet size per connected master and slave (bytes)
1257system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84881644 # Cumulative packet size per connected master and slave (bytes)
1258system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14612 # Cumulative packet size per connected master and slave (bytes)
1259system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 32580 # Cumulative packet size per connected master and slave (bytes)
1260system.cpu0.toL2Bus.pkt_size::total 155780476 # Cumulative packet size per connected master and slave (bytes)
1261system.cpu0.toL2Bus.snoops 1106596 # Total snoops (count)
1262system.cpu0.toL2Bus.snoop_fanout::samples 4822448 # Request fanout histogram
1263system.cpu0.toL2Bus.snoop_fanout::mean 1.211081 # Request fanout histogram
1264system.cpu0.toL2Bus.snoop_fanout::stdev 0.408076 # Request fanout histogram
1265system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1266system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1267system.cpu0.toL2Bus.snoop_fanout::1 3804521 78.89% 78.89% # Request fanout histogram
1268system.cpu0.toL2Bus.snoop_fanout::2 1017927 21.11% 100.00% # Request fanout histogram
1269system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1270system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1271system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1272system.cpu0.toL2Bus.snoop_fanout::total 4822448 # Request fanout histogram
1273system.cpu0.toL2Bus.reqLayer0.occupancy 2435282990 # Layer occupancy (ticks)
1274system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1275system.cpu0.toL2Bus.snoopLayer0.occupancy 113496000 # Layer occupancy (ticks)
1276system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1277system.cpu0.toL2Bus.respLayer0.occupancy 1668761500 # Layer occupancy (ticks)
1278system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1279system.cpu0.toL2Bus.respLayer1.occupancy 1211060981 # Layer occupancy (ticks)
1280system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1281system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks)
1282system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1283system.cpu0.toL2Bus.respLayer3.occupancy 14212986 # Layer occupancy (ticks)
1284system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1285system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1286system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1287system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1288system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1289system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1290system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1291system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

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1306system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1307system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1308system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1309system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1310system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1311system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1312system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1313system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1314system.cpu1.dtb.walker.walks 3357 # Table walker walks requested
1315system.cpu1.dtb.walker.walksShort 3357 # Table walker walks initiated with short descriptors
1316system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 663 # Level at which table walker walks with short descriptors terminate
1317system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate
1318system.cpu1.dtb.walker.walkWaitTime::samples 3357 # Table walker wait (enqueue to first request) latency
1319system.cpu1.dtb.walker.walkWaitTime::0 3357 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1320system.cpu1.dtb.walker.walkWaitTime::total 3357 # Table walker wait (enqueue to first request) latency
1321system.cpu1.dtb.walker.walkCompletionTime::samples 2587 # Table walker service (enqueue to completion) latency
1322system.cpu1.dtb.walker.walkCompletionTime::mean 9934.866641 # Table walker service (enqueue to completion) latency
1323system.cpu1.dtb.walker.walkCompletionTime::gmean 9080.760096 # Table walker service (enqueue to completion) latency
1324system.cpu1.dtb.walker.walkCompletionTime::stdev 4767.740714 # Table walker service (enqueue to completion) latency
1325system.cpu1.dtb.walker.walkCompletionTime::0-4095 19 0.73% 0.73% # Table walker service (enqueue to completion) latency
1326system.cpu1.dtb.walker.walkCompletionTime::4096-8191 1032 39.89% 40.63% # Table walker service (enqueue to completion) latency
1327system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1082 41.82% 82.45% # Table walker service (enqueue to completion) latency
1328system.cpu1.dtb.walker.walkCompletionTime::12288-16383 330 12.76% 95.21% # Table walker service (enqueue to completion) latency
1329system.cpu1.dtb.walker.walkCompletionTime::20480-24575 64 2.47% 97.68% # Table walker service (enqueue to completion) latency
1330system.cpu1.dtb.walker.walkCompletionTime::24576-28671 39 1.51% 99.19% # Table walker service (enqueue to completion) latency
1331system.cpu1.dtb.walker.walkCompletionTime::28672-32767 16 0.62% 99.81% # Table walker service (enqueue to completion) latency
1332system.cpu1.dtb.walker.walkCompletionTime::40960-45055 5 0.19% 100.00% # Table walker service (enqueue to completion) latency
1333system.cpu1.dtb.walker.walkCompletionTime::total 2587 # Table walker service (enqueue to completion) latency
1334system.cpu1.dtb.walker.walksPending::samples 1655632468 # Table walker pending requests distribution
1335system.cpu1.dtb.walker.walksPending::0 1655632468 100.00% 100.00% # Table walker pending requests distribution
1336system.cpu1.dtb.walker.walksPending::total 1655632468 # Table walker pending requests distribution
1337system.cpu1.dtb.walker.walkPageSizes::4K 1932 74.68% 74.68% # Table walker page sizes translated
1338system.cpu1.dtb.walker.walkPageSizes::1M 655 25.32% 100.00% # Table walker page sizes translated
1339system.cpu1.dtb.walker.walkPageSizes::total 2587 # Table walker page sizes translated
1340system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3357 # Table walker requests started/completed, data/inst
1341system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1342system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3357 # Table walker requests started/completed, data/inst
1343system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2587 # Table walker requests started/completed, data/inst
1344system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1345system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2587 # Table walker requests started/completed, data/inst
1346system.cpu1.dtb.walker.walkRequestOrigin::total 5944 # Table walker requests started/completed, data/inst
1347system.cpu1.dtb.inst_hits 0 # ITB inst hits
1348system.cpu1.dtb.inst_misses 0 # ITB inst misses
1349system.cpu1.dtb.read_hits 3844486 # DTB read hits
1350system.cpu1.dtb.read_misses 2847 # DTB read misses
1351system.cpu1.dtb.write_hits 3369243 # DTB write hits
1352system.cpu1.dtb.write_misses 510 # DTB write misses
1353system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1354system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1355system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1356system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1357system.cpu1.dtb.flush_entries 2034 # Number of entries that have been flushed from TLB
1358system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1359system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch
1360system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1361system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
1362system.cpu1.dtb.read_accesses 3847333 # DTB read accesses
1363system.cpu1.dtb.write_accesses 3369753 # DTB write accesses
1364system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1365system.cpu1.dtb.hits 7213729 # DTB hits
1366system.cpu1.dtb.misses 3357 # DTB misses
1367system.cpu1.dtb.accesses 7217086 # DTB accesses
1368system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1369system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1370system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1371system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1372system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1373system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1374system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1375system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1389system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1390system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1391system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1392system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1393system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1394system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1395system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1396system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1397system.cpu1.itb.walker.walks 1746 # Table walker walks requested
1398system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors
1399system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate
1400system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate
1401system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency
1402system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1403system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency
1404system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency
1405system.cpu1.itb.walker.walkCompletionTime::mean 10678.410117 # Table walker service (enqueue to completion) latency
1406system.cpu1.itb.walker.walkCompletionTime::gmean 9623.001262 # Table walker service (enqueue to completion) latency
1407system.cpu1.itb.walker.walkCompletionTime::stdev 5682.967955 # Table walker service (enqueue to completion) latency
1408system.cpu1.itb.walker.walkCompletionTime::4096-8191 356 32.16% 32.16% # Table walker service (enqueue to completion) latency
1409system.cpu1.itb.walker.walkCompletionTime::8192-12287 499 45.08% 77.24% # Table walker service (enqueue to completion) latency
1410system.cpu1.itb.walker.walkCompletionTime::12288-16383 181 16.35% 93.59% # Table walker service (enqueue to completion) latency
1411system.cpu1.itb.walker.walkCompletionTime::16384-20479 17 1.54% 95.12% # Table walker service (enqueue to completion) latency
1412system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.21% # Table walker service (enqueue to completion) latency
1413system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.71% 97.92% # Table walker service (enqueue to completion) latency
1414system.cpu1.itb.walker.walkCompletionTime::28672-32767 12 1.08% 99.01% # Table walker service (enqueue to completion) latency
1415system.cpu1.itb.walker.walkCompletionTime::32768-36863 5 0.45% 99.46% # Table walker service (enqueue to completion) latency
1416system.cpu1.itb.walker.walkCompletionTime::40960-45055 5 0.45% 99.91% # Table walker service (enqueue to completion) latency
1417system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
1418system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency
1419system.cpu1.itb.walker.walksPending::samples 1655094468 # Table walker pending requests distribution
1420system.cpu1.itb.walker.walksPending::0 1655094468 100.00% 100.00% # Table walker pending requests distribution
1421system.cpu1.itb.walker.walksPending::total 1655094468 # Table walker pending requests distribution
1422system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated
1423system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated
1424system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated
1425system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1426system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst
1427system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst
1428system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1429system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst
1430system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst
1431system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst
1432system.cpu1.itb.inst_hits 16180944 # ITB inst hits
1433system.cpu1.itb.inst_misses 1746 # ITB inst misses
1434system.cpu1.itb.read_hits 0 # DTB read hits
1435system.cpu1.itb.read_misses 0 # DTB read misses
1436system.cpu1.itb.write_hits 0 # DTB write hits
1437system.cpu1.itb.write_misses 0 # DTB write misses
1438system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1439system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1440system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1441system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1442system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB
1443system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1444system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1445system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1446system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1447system.cpu1.itb.read_accesses 0 # DTB read accesses
1448system.cpu1.itb.write_accesses 0 # DTB write accesses
1449system.cpu1.itb.inst_accesses 16182690 # ITB inst accesses
1450system.cpu1.itb.hits 16180944 # DTB hits
1451system.cpu1.itb.misses 1746 # DTB misses
1452system.cpu1.itb.accesses 16182690 # DTB accesses
1453system.cpu1.numCycles 5736568944 # number of cpu cycles simulated
1454system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1455system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1456system.cpu1.committedInsts 15848207 # Number of instructions committed
1457system.cpu1.committedOps 19293539 # Number of ops (including micro ops) committed
1458system.cpu1.num_int_alu_accesses 17383760 # Number of integer alu accesses
1459system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses
1460system.cpu1.num_func_calls 938177 # number of times a function call or return occured
1461system.cpu1.num_conditional_control_insts 1786282 # number of instructions that are conditional controls
1462system.cpu1.num_int_insts 17383760 # number of integer instructions
1463system.cpu1.num_fp_insts 1857 # number of float instructions
1464system.cpu1.num_int_register_reads 31469136 # number of times the integer registers were read
1465system.cpu1.num_int_register_writes 12170371 # number of times the integer registers were written
1466system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read
1467system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
1468system.cpu1.num_cc_register_reads 70461385 # number of times the CC registers were read
1469system.cpu1.num_cc_register_writes 6330901 # number of times the CC registers were written
1470system.cpu1.num_mem_refs 7446495 # number of memory refs
1471system.cpu1.num_load_insts 3955836 # Number of load instructions
1472system.cpu1.num_store_insts 3490659 # Number of store instructions
1473system.cpu1.num_idle_cycles 5686521745.715384 # Number of idle cycles
1474system.cpu1.num_busy_cycles 50047198.284615 # Number of busy cycles
1475system.cpu1.not_idle_fraction 0.008724 # Percentage of non-idle cycles
1476system.cpu1.idle_fraction 0.991276 # Percentage of idle cycles
1477system.cpu1.Branches 2803460 # Number of branches fetched
1478system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
1479system.cpu1.op_class::IntAlu 12144730 61.90% 61.90% # Class of executed instruction
1480system.cpu1.op_class::IntMult 26187 0.13% 62.03% # Class of executed instruction
1481system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction
1482system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction
1483system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction
1484system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction
1485system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction
1486system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction
1487system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction
1488system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction
1489system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction
1490system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction
1491system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction
1492system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction
1493system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction
1494system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction
1495system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction
1496system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction
1497system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction
1498system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction
1499system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction
1500system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction
1501system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction
1502system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction
1503system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction
1504system.cpu1.op_class::SimdFloatMisc 3277 0.02% 62.05% # Class of executed instruction
1505system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction
1506system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction
1507system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction
1508system.cpu1.op_class::MemRead 3955836 20.16% 82.21% # Class of executed instruction
1509system.cpu1.op_class::MemWrite 3490659 17.79% 100.00% # Class of executed instruction
1510system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1511system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1512system.cpu1.op_class::total 19620755 # Class of executed instruction
1513system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1514system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed
1515system.cpu1.dcache.tags.replacements 186869 # number of replacements
1516system.cpu1.dcache.tags.tagsinuse 468.718276 # Cycle average of tags in use
1517system.cpu1.dcache.tags.total_refs 6945303 # Total number of references to valid blocks.
1518system.cpu1.dcache.tags.sampled_refs 187221 # Sample count of references to valid blocks.
1519system.cpu1.dcache.tags.avg_refs 37.096816 # Average number of references to valid blocks.
1520system.cpu1.dcache.tags.warmup_cycle 104852682500 # Cycle when the warmup percentage was hit.
1521system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.718276 # Average occupied blocks per requestor
1522system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915465 # Average percentage of cache occupancy
1523system.cpu1.dcache.tags.occ_percent::total 0.915465 # Average percentage of cache occupancy
1524system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id
1525system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
1526system.cpu1.dcache.tags.age_task_id_blocks_1024::3 69 # Occupied blocks per task id
1527system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
1528system.cpu1.dcache.tags.tag_accesses 14648138 # Number of tag accesses
1529system.cpu1.dcache.tags.data_accesses 14648138 # Number of data accesses
1530system.cpu1.dcache.ReadReq_hits::cpu1.data 3533706 # number of ReadReq hits
1531system.cpu1.dcache.ReadReq_hits::total 3533706 # number of ReadReq hits
1532system.cpu1.dcache.WriteReq_hits::cpu1.data 3181686 # number of WriteReq hits
1533system.cpu1.dcache.WriteReq_hits::total 3181686 # number of WriteReq hits
1534system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48716 # number of SoftPFReq hits
1535system.cpu1.dcache.SoftPFReq_hits::total 48716 # number of SoftPFReq hits
1536system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78610 # number of LoadLockedReq hits
1537system.cpu1.dcache.LoadLockedReq_hits::total 78610 # number of LoadLockedReq hits
1538system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70554 # number of StoreCondReq hits
1539system.cpu1.dcache.StoreCondReq_hits::total 70554 # number of StoreCondReq hits
1540system.cpu1.dcache.demand_hits::cpu1.data 6715392 # number of demand (read+write) hits
1541system.cpu1.dcache.demand_hits::total 6715392 # number of demand (read+write) hits
1542system.cpu1.dcache.overall_hits::cpu1.data 6764108 # number of overall hits
1543system.cpu1.dcache.overall_hits::total 6764108 # number of overall hits
1544system.cpu1.dcache.ReadReq_misses::cpu1.data 133537 # number of ReadReq misses
1545system.cpu1.dcache.ReadReq_misses::total 133537 # number of ReadReq misses
1546system.cpu1.dcache.WriteReq_misses::cpu1.data 91347 # number of WriteReq misses
1547system.cpu1.dcache.WriteReq_misses::total 91347 # number of WriteReq misses
1548system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30388 # number of SoftPFReq misses
1549system.cpu1.dcache.SoftPFReq_misses::total 30388 # number of SoftPFReq misses
1550system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17048 # number of LoadLockedReq misses
1551system.cpu1.dcache.LoadLockedReq_misses::total 17048 # number of LoadLockedReq misses
1552system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23285 # number of StoreCondReq misses
1553system.cpu1.dcache.StoreCondReq_misses::total 23285 # number of StoreCondReq misses
1554system.cpu1.dcache.demand_misses::cpu1.data 224884 # number of demand (read+write) misses
1555system.cpu1.dcache.demand_misses::total 224884 # number of demand (read+write) misses
1556system.cpu1.dcache.overall_misses::cpu1.data 255272 # number of overall misses
1557system.cpu1.dcache.overall_misses::total 255272 # number of overall misses
1558system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1938354000 # number of ReadReq miss cycles
1559system.cpu1.dcache.ReadReq_miss_latency::total 1938354000 # number of ReadReq miss cycles
1560system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2351393500 # number of WriteReq miss cycles
1561system.cpu1.dcache.WriteReq_miss_latency::total 2351393500 # number of WriteReq miss cycles
1562system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319800000 # number of LoadLockedReq miss cycles
1563system.cpu1.dcache.LoadLockedReq_miss_latency::total 319800000 # number of LoadLockedReq miss cycles
1564system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 544967000 # number of StoreCondReq miss cycles
1565system.cpu1.dcache.StoreCondReq_miss_latency::total 544967000 # number of StoreCondReq miss cycles
1566system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2548000 # number of StoreCondFailReq miss cycles
1567system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2548000 # number of StoreCondFailReq miss cycles
1568system.cpu1.dcache.demand_miss_latency::cpu1.data 4289747500 # number of demand (read+write) miss cycles
1569system.cpu1.dcache.demand_miss_latency::total 4289747500 # number of demand (read+write) miss cycles
1570system.cpu1.dcache.overall_miss_latency::cpu1.data 4289747500 # number of overall miss cycles
1571system.cpu1.dcache.overall_miss_latency::total 4289747500 # number of overall miss cycles
1572system.cpu1.dcache.ReadReq_accesses::cpu1.data 3667243 # number of ReadReq accesses(hits+misses)
1573system.cpu1.dcache.ReadReq_accesses::total 3667243 # number of ReadReq accesses(hits+misses)
1574system.cpu1.dcache.WriteReq_accesses::cpu1.data 3273033 # number of WriteReq accesses(hits+misses)
1575system.cpu1.dcache.WriteReq_accesses::total 3273033 # number of WriteReq accesses(hits+misses)
1576system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79104 # number of SoftPFReq accesses(hits+misses)
1577system.cpu1.dcache.SoftPFReq_accesses::total 79104 # number of SoftPFReq accesses(hits+misses)
1578system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95658 # number of LoadLockedReq accesses(hits+misses)
1579system.cpu1.dcache.LoadLockedReq_accesses::total 95658 # number of LoadLockedReq accesses(hits+misses)
1580system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93839 # number of StoreCondReq accesses(hits+misses)
1581system.cpu1.dcache.StoreCondReq_accesses::total 93839 # number of StoreCondReq accesses(hits+misses)
1582system.cpu1.dcache.demand_accesses::cpu1.data 6940276 # number of demand (read+write) accesses
1583system.cpu1.dcache.demand_accesses::total 6940276 # number of demand (read+write) accesses
1584system.cpu1.dcache.overall_accesses::cpu1.data 7019380 # number of overall (read+write) accesses
1585system.cpu1.dcache.overall_accesses::total 7019380 # number of overall (read+write) accesses
1586system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036413 # miss rate for ReadReq accesses
1587system.cpu1.dcache.ReadReq_miss_rate::total 0.036413 # miss rate for ReadReq accesses
1588system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027909 # miss rate for WriteReq accesses
1589system.cpu1.dcache.WriteReq_miss_rate::total 0.027909 # miss rate for WriteReq accesses
1590system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.384153 # miss rate for SoftPFReq accesses
1591system.cpu1.dcache.SoftPFReq_miss_rate::total 0.384153 # miss rate for SoftPFReq accesses
1592system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178218 # miss rate for LoadLockedReq accesses
1593system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178218 # miss rate for LoadLockedReq accesses
1594system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248138 # miss rate for StoreCondReq accesses
1595system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248138 # miss rate for StoreCondReq accesses
1596system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032403 # miss rate for demand accesses
1597system.cpu1.dcache.demand_miss_rate::total 0.032403 # miss rate for demand accesses
1598system.cpu1.dcache.overall_miss_rate::cpu1.data 0.036367 # miss rate for overall accesses
1599system.cpu1.dcache.overall_miss_rate::total 0.036367 # miss rate for overall accesses
1600system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14515.482600 # average ReadReq miss latency
1601system.cpu1.dcache.ReadReq_avg_miss_latency::total 14515.482600 # average ReadReq miss latency
1602system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25741.332501 # average WriteReq miss latency
1603system.cpu1.dcache.WriteReq_avg_miss_latency::total 25741.332501 # average WriteReq miss latency
1604system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18758.798686 # average LoadLockedReq miss latency
1605system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18758.798686 # average LoadLockedReq miss latency
1606system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23404.208718 # average StoreCondReq miss latency
1607system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23404.208718 # average StoreCondReq miss latency
1608system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1609system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1610system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19075.378862 # average overall miss latency
1611system.cpu1.dcache.demand_avg_miss_latency::total 19075.378862 # average overall miss latency
1612system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16804.614294 # average overall miss latency
1613system.cpu1.dcache.overall_avg_miss_latency::total 16804.614294 # average overall miss latency
1614system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1615system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1616system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1617system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1618system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1619system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1620system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1621system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1622system.cpu1.dcache.writebacks::writebacks 116740 # number of writebacks
1623system.cpu1.dcache.writebacks::total 116740 # number of writebacks
1624system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 267 # number of ReadReq MSHR hits
1625system.cpu1.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits
1626system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11810 # number of LoadLockedReq MSHR hits
1627system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11810 # number of LoadLockedReq MSHR hits
1628system.cpu1.dcache.demand_mshr_hits::cpu1.data 267 # number of demand (read+write) MSHR hits
1629system.cpu1.dcache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits
1630system.cpu1.dcache.overall_mshr_hits::cpu1.data 267 # number of overall MSHR hits
1631system.cpu1.dcache.overall_mshr_hits::total 267 # number of overall MSHR hits
1632system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133270 # number of ReadReq MSHR misses
1633system.cpu1.dcache.ReadReq_mshr_misses::total 133270 # number of ReadReq MSHR misses
1634system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91347 # number of WriteReq MSHR misses
1635system.cpu1.dcache.WriteReq_mshr_misses::total 91347 # number of WriteReq MSHR misses
1636system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29613 # number of SoftPFReq MSHR misses
1637system.cpu1.dcache.SoftPFReq_mshr_misses::total 29613 # number of SoftPFReq MSHR misses
1638system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5238 # number of LoadLockedReq MSHR misses
1639system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5238 # number of LoadLockedReq MSHR misses
1640system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23285 # number of StoreCondReq MSHR misses
1641system.cpu1.dcache.StoreCondReq_mshr_misses::total 23285 # number of StoreCondReq MSHR misses
1642system.cpu1.dcache.demand_mshr_misses::cpu1.data 224617 # number of demand (read+write) MSHR misses
1643system.cpu1.dcache.demand_mshr_misses::total 224617 # number of demand (read+write) MSHR misses
1644system.cpu1.dcache.overall_mshr_misses::cpu1.data 254230 # number of overall MSHR misses
1645system.cpu1.dcache.overall_mshr_misses::total 254230 # number of overall MSHR misses
1646system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2508 # number of ReadReq MSHR uncacheable
1647system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2508 # number of ReadReq MSHR uncacheable
1648system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2155 # number of WriteReq MSHR uncacheable
1649system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2155 # number of WriteReq MSHR uncacheable
1650system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 4663 # number of overall MSHR uncacheable misses
1651system.cpu1.dcache.overall_mshr_uncacheable_misses::total 4663 # number of overall MSHR uncacheable misses
1652system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1799290500 # number of ReadReq MSHR miss cycles
1653system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1799290500 # number of ReadReq MSHR miss cycles
1654system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2260046500 # number of WriteReq MSHR miss cycles
1655system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2260046500 # number of WriteReq MSHR miss cycles
1656system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 487726000 # number of SoftPFReq MSHR miss cycles
1657system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 487726000 # number of SoftPFReq MSHR miss cycles
1658system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90112000 # number of LoadLockedReq MSHR miss cycles
1659system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90112000 # number of LoadLockedReq MSHR miss cycles
1660system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 521727000 # number of StoreCondReq MSHR miss cycles
1661system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 521727000 # number of StoreCondReq MSHR miss cycles
1662system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2503000 # number of StoreCondFailReq MSHR miss cycles
1663system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2503000 # number of StoreCondFailReq MSHR miss cycles
1664system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4059337000 # number of demand (read+write) MSHR miss cycles
1665system.cpu1.dcache.demand_mshr_miss_latency::total 4059337000 # number of demand (read+write) MSHR miss cycles
1666system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4547063000 # number of overall MSHR miss cycles
1667system.cpu1.dcache.overall_mshr_miss_latency::total 4547063000 # number of overall MSHR miss cycles
1668system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 302228000 # number of ReadReq MSHR uncacheable cycles
1669system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 302228000 # number of ReadReq MSHR uncacheable cycles
1670system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 224553500 # number of WriteReq MSHR uncacheable cycles
1671system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 224553500 # number of WriteReq MSHR uncacheable cycles
1672system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 526781500 # number of overall MSHR uncacheable cycles
1673system.cpu1.dcache.overall_mshr_uncacheable_latency::total 526781500 # number of overall MSHR uncacheable cycles
1674system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036341 # mshr miss rate for ReadReq accesses
1675system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036341 # mshr miss rate for ReadReq accesses
1676system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027909 # mshr miss rate for WriteReq accesses
1677system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027909 # mshr miss rate for WriteReq accesses
1678system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.374355 # mshr miss rate for SoftPFReq accesses
1679system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.374355 # mshr miss rate for SoftPFReq accesses
1680system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054758 # mshr miss rate for LoadLockedReq accesses
1681system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054758 # mshr miss rate for LoadLockedReq accesses
1682system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248138 # mshr miss rate for StoreCondReq accesses
1683system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248138 # mshr miss rate for StoreCondReq accesses
1684system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032364 # mshr miss rate for demand accesses
1685system.cpu1.dcache.demand_mshr_miss_rate::total 0.032364 # mshr miss rate for demand accesses
1686system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036218 # mshr miss rate for overall accesses
1687system.cpu1.dcache.overall_mshr_miss_rate::total 0.036218 # mshr miss rate for overall accesses
1688system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13501.091769 # average ReadReq mshr miss latency
1689system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13501.091769 # average ReadReq mshr miss latency
1690system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24741.332501 # average WriteReq mshr miss latency
1691system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24741.332501 # average WriteReq mshr miss latency
1692system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16469.996285 # average SoftPFReq mshr miss latency
1693system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16469.996285 # average SoftPFReq mshr miss latency
1694system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17203.512791 # average LoadLockedReq mshr miss latency
1695system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17203.512791 # average LoadLockedReq mshr miss latency
1696system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22406.141293 # average StoreCondReq mshr miss latency
1697system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22406.141293 # average StoreCondReq mshr miss latency
1698system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1699system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1700system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18072.260782 # average overall mshr miss latency
1701system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18072.260782 # average overall mshr miss latency
1702system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17885.627188 # average overall mshr miss latency
1703system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17885.627188 # average overall mshr miss latency
1704system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120505.582137 # average ReadReq mshr uncacheable latency
1705system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120505.582137 # average ReadReq mshr uncacheable latency
1706system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104201.160093 # average WriteReq mshr uncacheable latency
1707system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 104201.160093 # average WriteReq mshr uncacheable latency
1708system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 112970.512546 # average overall mshr uncacheable latency
1709system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 112970.512546 # average overall mshr uncacheable latency
1710system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1711system.cpu1.icache.tags.replacements 501529 # number of replacements
1712system.cpu1.icache.tags.tagsinuse 498.573325 # Cycle average of tags in use
1713system.cpu1.icache.tags.total_refs 15678898 # Total number of references to valid blocks.
1714system.cpu1.icache.tags.sampled_refs 502041 # Sample count of references to valid blocks.
1715system.cpu1.icache.tags.avg_refs 31.230314 # Average number of references to valid blocks.
1716system.cpu1.icache.tags.warmup_cycle 84707327000 # Cycle when the warmup percentage was hit.
1717system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.573325 # Average occupied blocks per requestor
1718system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973776 # Average percentage of cache occupancy
1719system.cpu1.icache.tags.occ_percent::total 0.973776 # Average percentage of cache occupancy
1720system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1721system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id
1722system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id
1723system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
1724system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1725system.cpu1.icache.tags.tag_accesses 32863919 # Number of tag accesses
1726system.cpu1.icache.tags.data_accesses 32863919 # Number of data accesses
1727system.cpu1.icache.ReadReq_hits::cpu1.inst 15678898 # number of ReadReq hits
1728system.cpu1.icache.ReadReq_hits::total 15678898 # number of ReadReq hits
1729system.cpu1.icache.demand_hits::cpu1.inst 15678898 # number of demand (read+write) hits
1730system.cpu1.icache.demand_hits::total 15678898 # number of demand (read+write) hits
1731system.cpu1.icache.overall_hits::cpu1.inst 15678898 # number of overall hits
1732system.cpu1.icache.overall_hits::total 15678898 # number of overall hits
1733system.cpu1.icache.ReadReq_misses::cpu1.inst 502041 # number of ReadReq misses
1734system.cpu1.icache.ReadReq_misses::total 502041 # number of ReadReq misses
1735system.cpu1.icache.demand_misses::cpu1.inst 502041 # number of demand (read+write) misses
1736system.cpu1.icache.demand_misses::total 502041 # number of demand (read+write) misses
1737system.cpu1.icache.overall_misses::cpu1.inst 502041 # number of overall misses
1738system.cpu1.icache.overall_misses::total 502041 # number of overall misses
1739system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4374235500 # number of ReadReq miss cycles
1740system.cpu1.icache.ReadReq_miss_latency::total 4374235500 # number of ReadReq miss cycles
1741system.cpu1.icache.demand_miss_latency::cpu1.inst 4374235500 # number of demand (read+write) miss cycles
1742system.cpu1.icache.demand_miss_latency::total 4374235500 # number of demand (read+write) miss cycles
1743system.cpu1.icache.overall_miss_latency::cpu1.inst 4374235500 # number of overall miss cycles
1744system.cpu1.icache.overall_miss_latency::total 4374235500 # number of overall miss cycles
1745system.cpu1.icache.ReadReq_accesses::cpu1.inst 16180939 # number of ReadReq accesses(hits+misses)
1746system.cpu1.icache.ReadReq_accesses::total 16180939 # number of ReadReq accesses(hits+misses)
1747system.cpu1.icache.demand_accesses::cpu1.inst 16180939 # number of demand (read+write) accesses
1748system.cpu1.icache.demand_accesses::total 16180939 # number of demand (read+write) accesses
1749system.cpu1.icache.overall_accesses::cpu1.inst 16180939 # number of overall (read+write) accesses
1750system.cpu1.icache.overall_accesses::total 16180939 # number of overall (read+write) accesses
1751system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031027 # miss rate for ReadReq accesses
1752system.cpu1.icache.ReadReq_miss_rate::total 0.031027 # miss rate for ReadReq accesses
1753system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031027 # miss rate for demand accesses
1754system.cpu1.icache.demand_miss_rate::total 0.031027 # miss rate for demand accesses
1755system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031027 # miss rate for overall accesses
1756system.cpu1.icache.overall_miss_rate::total 0.031027 # miss rate for overall accesses
1757system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8712.904922 # average ReadReq miss latency
1758system.cpu1.icache.ReadReq_avg_miss_latency::total 8712.904922 # average ReadReq miss latency
1759system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency
1760system.cpu1.icache.demand_avg_miss_latency::total 8712.904922 # average overall miss latency
1761system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8712.904922 # average overall miss latency
1762system.cpu1.icache.overall_avg_miss_latency::total 8712.904922 # average overall miss latency
1763system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1764system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1765system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1766system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1767system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1768system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1769system.cpu1.icache.fast_writes 0 # number of fast writes performed
1770system.cpu1.icache.cache_copies 0 # number of cache copies performed
1771system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 502041 # number of ReadReq MSHR misses
1772system.cpu1.icache.ReadReq_mshr_misses::total 502041 # number of ReadReq MSHR misses
1773system.cpu1.icache.demand_mshr_misses::cpu1.inst 502041 # number of demand (read+write) MSHR misses
1774system.cpu1.icache.demand_mshr_misses::total 502041 # number of demand (read+write) MSHR misses
1775system.cpu1.icache.overall_mshr_misses::cpu1.inst 502041 # number of overall MSHR misses
1776system.cpu1.icache.overall_mshr_misses::total 502041 # number of overall MSHR misses
1777system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
1778system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
1779system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
1780system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
1781system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4123215000 # number of ReadReq MSHR miss cycles
1782system.cpu1.icache.ReadReq_mshr_miss_latency::total 4123215000 # number of ReadReq MSHR miss cycles
1783system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4123215000 # number of demand (read+write) MSHR miss cycles
1784system.cpu1.icache.demand_mshr_miss_latency::total 4123215000 # number of demand (read+write) MSHR miss cycles
1785system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4123215000 # number of overall MSHR miss cycles
1786system.cpu1.icache.overall_mshr_miss_latency::total 4123215000 # number of overall MSHR miss cycles
1787system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15225000 # number of ReadReq MSHR uncacheable cycles
1788system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15225000 # number of ReadReq MSHR uncacheable cycles
1789system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15225000 # number of overall MSHR uncacheable cycles
1790system.cpu1.icache.overall_mshr_uncacheable_latency::total 15225000 # number of overall MSHR uncacheable cycles
1791system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for ReadReq accesses
1792system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.031027 # mshr miss rate for ReadReq accesses
1793system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for demand accesses
1794system.cpu1.icache.demand_mshr_miss_rate::total 0.031027 # mshr miss rate for demand accesses
1795system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.031027 # mshr miss rate for overall accesses
1796system.cpu1.icache.overall_mshr_miss_rate::total 0.031027 # mshr miss rate for overall accesses
1797system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average ReadReq mshr miss latency
1798system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8212.904922 # average ReadReq mshr miss latency
1799system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency
1800system.cpu1.icache.demand_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency
1801system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8212.904922 # average overall mshr miss latency
1802system.cpu1.icache.overall_avg_mshr_miss_latency::total 8212.904922 # average overall mshr miss latency
1803system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average ReadReq mshr uncacheable latency
1804system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86016.949153 # average ReadReq mshr uncacheable latency
1805system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86016.949153 # average overall mshr uncacheable latency
1806system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86016.949153 # average overall mshr uncacheable latency
1807system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1808system.cpu1.l2cache.prefetcher.num_hwpf_issued 199800 # number of hwpf issued
1809system.cpu1.l2cache.prefetcher.pfIdentified 199800 # number of prefetch candidates identified
1810system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
1811system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1812system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1813system.cpu1.l2cache.prefetcher.pfSpanPage 61752 # number of prefetches not generated due to page crossing
1814system.cpu1.l2cache.tags.replacements 45885 # number of replacements
1815system.cpu1.l2cache.tags.tagsinuse 14962.501141 # Cycle average of tags in use
1816system.cpu1.l2cache.tags.total_refs 1260771 # Total number of references to valid blocks.
1817system.cpu1.l2cache.tags.sampled_refs 60629 # Sample count of references to valid blocks.
1818system.cpu1.l2cache.tags.avg_refs 20.794851 # Average number of references to valid blocks.
1819system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1820system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.992983 # Average occupied blocks per requestor
1821system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.872865 # Average occupied blocks per requestor
1822system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.082863 # Average occupied blocks per requestor
1823system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2870.067957 # Average occupied blocks per requestor
1824system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2148.313714 # Average occupied blocks per requestor
1825system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 992.170760 # Average occupied blocks per requestor
1826system.cpu1.l2cache.tags.occ_percent::writebacks 0.546020 # Average percentage of cache occupancy
1827system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000236 # Average percentage of cache occupancy
1828system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy
1829system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.175175 # Average percentage of cache occupancy
1830system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.131123 # Average percentage of cache occupancy
1831system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060557 # Average percentage of cache occupancy
1832system.cpu1.l2cache.tags.occ_percent::total 0.913239 # Average percentage of cache occupancy
1833system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1179 # Occupied blocks per task id
1834system.cpu1.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id
1835system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13548 # Occupied blocks per task id
1836system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id
1837system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 28 # Occupied blocks per task id
1838system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1149 # Occupied blocks per task id
1839system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
1840system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
1841system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
1842system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id
1843system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1569 # Occupied blocks per task id
1844system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11689 # Occupied blocks per task id
1845system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.071960 # Percentage of cache occupancy per task id
1846system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001038 # Percentage of cache occupancy per task id
1847system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826904 # Percentage of cache occupancy per task id
1848system.cpu1.l2cache.tags.tag_accesses 23682241 # Number of tag accesses
1849system.cpu1.l2cache.tags.data_accesses 23682241 # Number of data accesses
1850system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3041 # number of ReadReq hits
1851system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1687 # number of ReadReq hits
1852system.cpu1.l2cache.ReadReq_hits::total 4728 # number of ReadReq hits
1853system.cpu1.l2cache.Writeback_hits::writebacks 116740 # number of Writeback hits
1854system.cpu1.l2cache.Writeback_hits::total 116740 # number of Writeback hits
1855system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1450 # number of UpgradeReq hits
1856system.cpu1.l2cache.UpgradeReq_hits::total 1450 # number of UpgradeReq hits
1857system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 871 # number of SCUpgradeReq hits
1858system.cpu1.l2cache.SCUpgradeReq_hits::total 871 # number of SCUpgradeReq hits
1859system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27883 # number of ReadExReq hits
1860system.cpu1.l2cache.ReadExReq_hits::total 27883 # number of ReadExReq hits
1861system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 488673 # number of ReadCleanReq hits
1862system.cpu1.l2cache.ReadCleanReq_hits::total 488673 # number of ReadCleanReq hits
1863system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 100414 # number of ReadSharedReq hits
1864system.cpu1.l2cache.ReadSharedReq_hits::total 100414 # number of ReadSharedReq hits
1865system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3041 # number of demand (read+write) hits
1866system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1687 # number of demand (read+write) hits
1867system.cpu1.l2cache.demand_hits::cpu1.inst 488673 # number of demand (read+write) hits
1868system.cpu1.l2cache.demand_hits::cpu1.data 128297 # number of demand (read+write) hits
1869system.cpu1.l2cache.demand_hits::total 621698 # number of demand (read+write) hits
1870system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3041 # number of overall hits
1871system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1687 # number of overall hits
1872system.cpu1.l2cache.overall_hits::cpu1.inst 488673 # number of overall hits
1873system.cpu1.l2cache.overall_hits::cpu1.data 128297 # number of overall hits
1874system.cpu1.l2cache.overall_hits::total 621698 # number of overall hits
1875system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 323 # number of ReadReq misses
1876system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 278 # number of ReadReq misses
1877system.cpu1.l2cache.ReadReq_misses::total 601 # number of ReadReq misses
1878system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27681 # number of UpgradeReq misses
1879system.cpu1.l2cache.UpgradeReq_misses::total 27681 # number of UpgradeReq misses
1880system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22412 # number of SCUpgradeReq misses
1881system.cpu1.l2cache.SCUpgradeReq_misses::total 22412 # number of SCUpgradeReq misses
1882system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
1883system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
1884system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34333 # number of ReadExReq misses
1885system.cpu1.l2cache.ReadExReq_misses::total 34333 # number of ReadExReq misses
1886system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13368 # number of ReadCleanReq misses
1887system.cpu1.l2cache.ReadCleanReq_misses::total 13368 # number of ReadCleanReq misses
1888system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 67707 # number of ReadSharedReq misses
1889system.cpu1.l2cache.ReadSharedReq_misses::total 67707 # number of ReadSharedReq misses
1890system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 323 # number of demand (read+write) misses
1891system.cpu1.l2cache.demand_misses::cpu1.itb.walker 278 # number of demand (read+write) misses
1892system.cpu1.l2cache.demand_misses::cpu1.inst 13368 # number of demand (read+write) misses
1893system.cpu1.l2cache.demand_misses::cpu1.data 102040 # number of demand (read+write) misses
1894system.cpu1.l2cache.demand_misses::total 116009 # number of demand (read+write) misses
1895system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 323 # number of overall misses
1896system.cpu1.l2cache.overall_misses::cpu1.itb.walker 278 # number of overall misses
1897system.cpu1.l2cache.overall_misses::cpu1.inst 13368 # number of overall misses
1898system.cpu1.l2cache.overall_misses::cpu1.data 102040 # number of overall misses
1899system.cpu1.l2cache.overall_misses::total 116009 # number of overall misses
1900system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6494000 # number of ReadReq miss cycles
1901system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5572000 # number of ReadReq miss cycles
1902system.cpu1.l2cache.ReadReq_miss_latency::total 12066000 # number of ReadReq miss cycles
1903system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 531615500 # number of UpgradeReq miss cycles
1904system.cpu1.l2cache.UpgradeReq_miss_latency::total 531615500 # number of UpgradeReq miss cycles
1905system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 445738000 # number of SCUpgradeReq miss cycles
1906system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 445738000 # number of SCUpgradeReq miss cycles
1907system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2435500 # number of SCUpgradeFailReq miss cycles
1908system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2435500 # number of SCUpgradeFailReq miss cycles
1909system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1319690000 # number of ReadExReq miss cycles
1910system.cpu1.l2cache.ReadExReq_miss_latency::total 1319690000 # number of ReadExReq miss cycles
1911system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 440659500 # number of ReadCleanReq miss cycles
1912system.cpu1.l2cache.ReadCleanReq_miss_latency::total 440659500 # number of ReadCleanReq miss cycles
1913system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1471913000 # number of ReadSharedReq miss cycles
1914system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1471913000 # number of ReadSharedReq miss cycles
1915system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6494000 # number of demand (read+write) miss cycles
1916system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5572000 # number of demand (read+write) miss cycles
1917system.cpu1.l2cache.demand_miss_latency::cpu1.inst 440659500 # number of demand (read+write) miss cycles
1918system.cpu1.l2cache.demand_miss_latency::cpu1.data 2791603000 # number of demand (read+write) miss cycles
1919system.cpu1.l2cache.demand_miss_latency::total 3244328500 # number of demand (read+write) miss cycles
1920system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6494000 # number of overall miss cycles
1921system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5572000 # number of overall miss cycles
1922system.cpu1.l2cache.overall_miss_latency::cpu1.inst 440659500 # number of overall miss cycles
1923system.cpu1.l2cache.overall_miss_latency::cpu1.data 2791603000 # number of overall miss cycles
1924system.cpu1.l2cache.overall_miss_latency::total 3244328500 # number of overall miss cycles
1925system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3364 # number of ReadReq accesses(hits+misses)
1926system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1965 # number of ReadReq accesses(hits+misses)
1927system.cpu1.l2cache.ReadReq_accesses::total 5329 # number of ReadReq accesses(hits+misses)
1928system.cpu1.l2cache.Writeback_accesses::writebacks 116740 # number of Writeback accesses(hits+misses)
1929system.cpu1.l2cache.Writeback_accesses::total 116740 # number of Writeback accesses(hits+misses)
1930system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29131 # number of UpgradeReq accesses(hits+misses)
1931system.cpu1.l2cache.UpgradeReq_accesses::total 29131 # number of UpgradeReq accesses(hits+misses)
1932system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23283 # number of SCUpgradeReq accesses(hits+misses)
1933system.cpu1.l2cache.SCUpgradeReq_accesses::total 23283 # number of SCUpgradeReq accesses(hits+misses)
1934system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1935system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1936system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62216 # number of ReadExReq accesses(hits+misses)
1937system.cpu1.l2cache.ReadExReq_accesses::total 62216 # number of ReadExReq accesses(hits+misses)
1938system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 502041 # number of ReadCleanReq accesses(hits+misses)
1939system.cpu1.l2cache.ReadCleanReq_accesses::total 502041 # number of ReadCleanReq accesses(hits+misses)
1940system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 168121 # number of ReadSharedReq accesses(hits+misses)
1941system.cpu1.l2cache.ReadSharedReq_accesses::total 168121 # number of ReadSharedReq accesses(hits+misses)
1942system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3364 # number of demand (read+write) accesses
1943system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1965 # number of demand (read+write) accesses
1944system.cpu1.l2cache.demand_accesses::cpu1.inst 502041 # number of demand (read+write) accesses
1945system.cpu1.l2cache.demand_accesses::cpu1.data 230337 # number of demand (read+write) accesses
1946system.cpu1.l2cache.demand_accesses::total 737707 # number of demand (read+write) accesses
1947system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3364 # number of overall (read+write) accesses
1948system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1965 # number of overall (read+write) accesses
1949system.cpu1.l2cache.overall_accesses::cpu1.inst 502041 # number of overall (read+write) accesses
1950system.cpu1.l2cache.overall_accesses::cpu1.data 230337 # number of overall (read+write) accesses
1951system.cpu1.l2cache.overall_accesses::total 737707 # number of overall (read+write) accesses
1952system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096017 # miss rate for ReadReq accesses
1953system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.141476 # miss rate for ReadReq accesses
1954system.cpu1.l2cache.ReadReq_miss_rate::total 0.112779 # miss rate for ReadReq accesses
1955system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950225 # miss rate for UpgradeReq accesses
1956system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950225 # miss rate for UpgradeReq accesses
1957system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962591 # miss rate for SCUpgradeReq accesses
1958system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962591 # miss rate for SCUpgradeReq accesses
1959system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1960system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1961system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.551836 # miss rate for ReadExReq accesses
1962system.cpu1.l2cache.ReadExReq_miss_rate::total 0.551836 # miss rate for ReadExReq accesses
1963system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026627 # miss rate for ReadCleanReq accesses
1964system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026627 # miss rate for ReadCleanReq accesses
1965system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.402728 # miss rate for ReadSharedReq accesses
1966system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.402728 # miss rate for ReadSharedReq accesses
1967system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096017 # miss rate for demand accesses
1968system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.141476 # miss rate for demand accesses
1969system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026627 # miss rate for demand accesses
1970system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443003 # miss rate for demand accesses
1971system.cpu1.l2cache.demand_miss_rate::total 0.157256 # miss rate for demand accesses
1972system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096017 # miss rate for overall accesses
1973system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.141476 # miss rate for overall accesses
1974system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026627 # miss rate for overall accesses
1975system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443003 # miss rate for overall accesses
1976system.cpu1.l2cache.overall_miss_rate::total 0.157256 # miss rate for overall accesses
1977system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20105.263158 # average ReadReq miss latency
1978system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20043.165468 # average ReadReq miss latency
1979system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20076.539101 # average ReadReq miss latency
1980system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19205.068459 # average UpgradeReq miss latency
1981system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19205.068459 # average UpgradeReq miss latency
1982system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19888.363377 # average SCUpgradeReq miss latency
1983system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19888.363377 # average SCUpgradeReq miss latency
1984system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1217750 # average SCUpgradeFailReq miss latency
1985system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1217750 # average SCUpgradeFailReq miss latency
1986system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38437.945999 # average ReadExReq miss latency
1987system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38437.945999 # average ReadExReq miss latency
1988system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32963.756732 # average ReadCleanReq miss latency
1989system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32963.756732 # average ReadCleanReq miss latency
1990system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 21739.450869 # average ReadSharedReq miss latency
1991system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 21739.450869 # average ReadSharedReq miss latency
1992system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20105.263158 # average overall miss latency
1993system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20043.165468 # average overall miss latency
1994system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32963.756732 # average overall miss latency
1995system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27357.928263 # average overall miss latency
1996system.cpu1.l2cache.demand_avg_miss_latency::total 27966.179348 # average overall miss latency
1997system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20105.263158 # average overall miss latency
1998system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20043.165468 # average overall miss latency
1999system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32963.756732 # average overall miss latency
2000system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27357.928263 # average overall miss latency
2001system.cpu1.l2cache.overall_avg_miss_latency::total 27966.179348 # average overall miss latency
2002system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2003system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2004system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
2005system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2006system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2007system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2008system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2009system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2010system.cpu1.l2cache.writebacks::writebacks 30382 # number of writebacks
2011system.cpu1.l2cache.writebacks::total 30382 # number of writebacks
2012system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 91 # number of ReadExReq MSHR hits
2013system.cpu1.l2cache.ReadExReq_mshr_hits::total 91 # number of ReadExReq MSHR hits
2014system.cpu1.l2cache.demand_mshr_hits::cpu1.data 91 # number of demand (read+write) MSHR hits
2015system.cpu1.l2cache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits
2016system.cpu1.l2cache.overall_mshr_hits::cpu1.data 91 # number of overall MSHR hits
2017system.cpu1.l2cache.overall_mshr_hits::total 91 # number of overall MSHR hits
2018system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 323 # number of ReadReq MSHR misses
2019system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 278 # number of ReadReq MSHR misses
2020system.cpu1.l2cache.ReadReq_mshr_misses::total 601 # number of ReadReq MSHR misses
2021system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2052 # number of CleanEvict MSHR misses
2022system.cpu1.l2cache.CleanEvict_mshr_misses::total 2052 # number of CleanEvict MSHR misses
2023system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24074 # number of HardPFReq MSHR misses
2024system.cpu1.l2cache.HardPFReq_mshr_misses::total 24074 # number of HardPFReq MSHR misses
2025system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27681 # number of UpgradeReq MSHR misses
2026system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27681 # number of UpgradeReq MSHR misses
2027system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22412 # number of SCUpgradeReq MSHR misses
2028system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22412 # number of SCUpgradeReq MSHR misses
2029system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
2030system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
2031system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34242 # number of ReadExReq MSHR misses
2032system.cpu1.l2cache.ReadExReq_mshr_misses::total 34242 # number of ReadExReq MSHR misses
2033system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 13368 # number of ReadCleanReq MSHR misses
2034system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 13368 # number of ReadCleanReq MSHR misses
2035system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 67707 # number of ReadSharedReq MSHR misses
2036system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 67707 # number of ReadSharedReq MSHR misses
2037system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 323 # number of demand (read+write) MSHR misses
2038system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 278 # number of demand (read+write) MSHR misses
2039system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13368 # number of demand (read+write) MSHR misses
2040system.cpu1.l2cache.demand_mshr_misses::cpu1.data 101949 # number of demand (read+write) MSHR misses
2041system.cpu1.l2cache.demand_mshr_misses::total 115918 # number of demand (read+write) MSHR misses
2042system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 323 # number of overall MSHR misses
2043system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 278 # number of overall MSHR misses
2044system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13368 # number of overall MSHR misses
2045system.cpu1.l2cache.overall_mshr_misses::cpu1.data 101949 # number of overall MSHR misses
2046system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24074 # number of overall MSHR misses
2047system.cpu1.l2cache.overall_mshr_misses::total 139992 # number of overall MSHR misses
2048system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2049system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 2508 # number of ReadReq MSHR uncacheable
2050system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 2685 # number of ReadReq MSHR uncacheable
2051system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2155 # number of WriteReq MSHR uncacheable
2052system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2155 # number of WriteReq MSHR uncacheable
2053system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2054system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 4663 # number of overall MSHR uncacheable misses
2055system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 4840 # number of overall MSHR uncacheable misses
2056system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4556000 # number of ReadReq MSHR miss cycles
2057system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3904000 # number of ReadReq MSHR miss cycles
2058system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 8460000 # number of ReadReq MSHR miss cycles
2059system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 852211217 # number of HardPFReq MSHR miss cycles
2060system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 852211217 # number of HardPFReq MSHR miss cycles
2061system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 446564500 # number of UpgradeReq MSHR miss cycles
2062system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 446564500 # number of UpgradeReq MSHR miss cycles
2063system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 346991500 # number of SCUpgradeReq MSHR miss cycles
2064system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 346991500 # number of SCUpgradeReq MSHR miss cycles
2065system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2165500 # number of SCUpgradeFailReq MSHR miss cycles
2066system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2165500 # number of SCUpgradeFailReq MSHR miss cycles
2067system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1103967000 # number of ReadExReq MSHR miss cycles
2068system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1103967000 # number of ReadExReq MSHR miss cycles
2069system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 360451500 # number of ReadCleanReq MSHR miss cycles
2070system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 360451500 # number of ReadCleanReq MSHR miss cycles
2071system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1065671000 # number of ReadSharedReq MSHR miss cycles
2072system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1065671000 # number of ReadSharedReq MSHR miss cycles
2073system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4556000 # number of demand (read+write) MSHR miss cycles
2074system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3904000 # number of demand (read+write) MSHR miss cycles
2075system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 360451500 # number of demand (read+write) MSHR miss cycles
2076system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2169638000 # number of demand (read+write) MSHR miss cycles
2077system.cpu1.l2cache.demand_mshr_miss_latency::total 2538549500 # number of demand (read+write) MSHR miss cycles
2078system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4556000 # number of overall MSHR miss cycles
2079system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3904000 # number of overall MSHR miss cycles
2080system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 360451500 # number of overall MSHR miss cycles
2081system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2169638000 # number of overall MSHR miss cycles
2082system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 852211217 # number of overall MSHR miss cycles
2083system.cpu1.l2cache.overall_mshr_miss_latency::total 3390760717 # number of overall MSHR miss cycles
2084system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13897500 # number of ReadReq MSHR uncacheable cycles
2085system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 282164000 # number of ReadReq MSHR uncacheable cycles
2086system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 296061500 # number of ReadReq MSHR uncacheable cycles
2087system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 208391000 # number of WriteReq MSHR uncacheable cycles
2088system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 208391000 # number of WriteReq MSHR uncacheable cycles
2089system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13897500 # number of overall MSHR uncacheable cycles
2090system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 490555000 # number of overall MSHR uncacheable cycles
2091system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 504452500 # number of overall MSHR uncacheable cycles
2092system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for ReadReq accesses
2093system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for ReadReq accesses
2094system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.112779 # mshr miss rate for ReadReq accesses
2095system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2096system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2097system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2098system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2099system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950225 # mshr miss rate for UpgradeReq accesses
2100system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950225 # mshr miss rate for UpgradeReq accesses
2101system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962591 # mshr miss rate for SCUpgradeReq accesses
2102system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962591 # mshr miss rate for SCUpgradeReq accesses
2103system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2104system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2105system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.550373 # mshr miss rate for ReadExReq accesses
2106system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.550373 # mshr miss rate for ReadExReq accesses
2107system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for ReadCleanReq accesses
2108system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadCleanReq accesses
2109system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.402728 # mshr miss rate for ReadSharedReq accesses
2110system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402728 # mshr miss rate for ReadSharedReq accesses
2111system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for demand accesses
2112system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for demand accesses
2113system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for demand accesses
2114system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442608 # mshr miss rate for demand accesses
2115system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157133 # mshr miss rate for demand accesses
2116system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.096017 # mshr miss rate for overall accesses
2117system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.141476 # mshr miss rate for overall accesses
2118system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026627 # mshr miss rate for overall accesses
2119system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442608 # mshr miss rate for overall accesses
2120system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2121system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189766 # mshr miss rate for overall accesses
2122system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average ReadReq mshr miss latency
2123system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average ReadReq mshr miss latency
2124system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14076.539101 # average ReadReq mshr miss latency
2125system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average HardPFReq mshr miss latency
2126system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35399.651782 # average HardPFReq mshr miss latency
2127system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16132.527727 # average UpgradeReq mshr miss latency
2128system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16132.527727 # average UpgradeReq mshr miss latency
2129system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15482.397823 # average SCUpgradeReq mshr miss latency
2130system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15482.397823 # average SCUpgradeReq mshr miss latency
2131system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1082750 # average SCUpgradeFailReq mshr miss latency
2132system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1082750 # average SCUpgradeFailReq mshr miss latency
2133system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32240.143683 # average ReadExReq mshr miss latency
2134system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32240.143683 # average ReadExReq mshr miss latency
2135system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average ReadCleanReq mshr miss latency
2136system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26963.756732 # average ReadCleanReq mshr miss latency
2137system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 15739.450869 # average ReadSharedReq mshr miss latency
2138system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 15739.450869 # average ReadSharedReq mshr miss latency
2139system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency
2140system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency
2141system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency
2142system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency
2143system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21899.528115 # average overall mshr miss latency
2144system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14105.263158 # average overall mshr miss latency
2145system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14043.165468 # average overall mshr miss latency
2146system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26963.756732 # average overall mshr miss latency
2147system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21281.601585 # average overall mshr miss latency
2148system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35399.651782 # average overall mshr miss latency
2149system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24221.103470 # average overall mshr miss latency
2150system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average ReadReq mshr uncacheable latency
2151system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112505.582137 # average ReadReq mshr uncacheable latency
2152system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 110264.990689 # average ReadReq mshr uncacheable latency
2153system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 96701.160093 # average WriteReq mshr uncacheable latency
2154system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 96701.160093 # average WriteReq mshr uncacheable latency
2155system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78516.949153 # average overall mshr uncacheable latency
2156system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 105201.586961 # average overall mshr uncacheable latency
2157system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 104225.723140 # average overall mshr uncacheable latency
2158system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2159system.cpu1.toL2Bus.trans_dist::ReadReq 53417 # Transaction distribution
2160system.cpu1.toL2Bus.trans_dist::ReadResp 719726 # Transaction distribution
2161system.cpu1.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution
2162system.cpu1.toL2Bus.trans_dist::WriteResp 2155 # Transaction distribution
2163system.cpu1.toL2Bus.trans_dist::Writeback 479672 # Transaction distribution
2164system.cpu1.toL2Bus.trans_dist::CleanEvict 677908 # Transaction distribution
2165system.cpu1.toL2Bus.trans_dist::HardPFReq 29213 # Transaction distribution
2166system.cpu1.toL2Bus.trans_dist::UpgradeReq 72925 # Transaction distribution
2167system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41207 # Transaction distribution
2168system.cpu1.toL2Bus.trans_dist::UpgradeResp 85236 # Transaction distribution
2169system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
2170system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution
2171system.cpu1.toL2Bus.trans_dist::ReadExReq 84437 # Transaction distribution
2172system.cpu1.toL2Bus.trans_dist::ReadExResp 66918 # Transaction distribution
2173system.cpu1.toL2Bus.trans_dist::ReadCleanReq 502041 # Transaction distribution
2174system.cpu1.toL2Bus.trans_dist::ReadSharedReq 506824 # Transaction distribution
2175system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
2176system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1497175 # Packet count per connected master and slave (bytes)
2177system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 834504 # Packet count per connected master and slave (bytes)
2178system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5289 # Packet count per connected master and slave (bytes)
2179system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9415 # Packet count per connected master and slave (bytes)
2180system.cpu1.toL2Bus.pkt_count::total 2346383 # Packet count per connected master and slave (bytes)
2181system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32131332 # Cumulative packet size per connected master and slave (bytes)
2182system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24936310 # Cumulative packet size per connected master and slave (bytes)
2183system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7860 # Cumulative packet size per connected master and slave (bytes)
2184system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13456 # Cumulative packet size per connected master and slave (bytes)
2185system.cpu1.toL2Bus.pkt_size::total 57088958 # Cumulative packet size per connected master and slave (bytes)
2186system.cpu1.toL2Bus.snoops 1117653 # Total snoops (count)
2187system.cpu1.toL2Bus.snoop_fanout::samples 2525896 # Request fanout histogram
2188system.cpu1.toL2Bus.snoop_fanout::mean 1.414848 # Request fanout histogram
2189system.cpu1.toL2Bus.snoop_fanout::stdev 0.492696 # Request fanout histogram
2190system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2191system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2192system.cpu1.toL2Bus.snoop_fanout::1 1478032 58.52% 58.52% # Request fanout histogram
2193system.cpu1.toL2Bus.snoop_fanout::2 1047864 41.48% 100.00% # Request fanout histogram
2194system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2195system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2196system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2197system.cpu1.toL2Bus.snoop_fanout::total 2525896 # Request fanout histogram
2198system.cpu1.toL2Bus.reqLayer0.occupancy 861521000 # Layer occupancy (ticks)
2199system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2200system.cpu1.toL2Bus.snoopLayer0.occupancy 79810000 # Layer occupancy (ticks)
2201system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2202system.cpu1.toL2Bus.respLayer0.occupancy 753238500 # Layer occupancy (ticks)
2203system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2204system.cpu1.toL2Bus.respLayer1.occupancy 375346000 # Layer occupancy (ticks)
2205system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2206system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks)
2207system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2208system.cpu1.toL2Bus.respLayer3.occupancy 6051499 # Layer occupancy (ticks)
2209system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2210system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
2211system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
2212system.iobus.trans_dist::WriteReq 59423 # Transaction distribution
2213system.iobus.trans_dist::WriteResp 59423 # Transaction distribution
2214system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes)
2215system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2216system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2217system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2218system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2219system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2220system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2221system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2222system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)

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2227system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2228system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2229system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2230system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2231system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2232system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2233system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2234system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2235system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
2236system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
2237system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
2238system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes)
2239system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes)
2240system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2241system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2242system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2243system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2244system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2245system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2246system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2247system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)

--- 4 unchanged lines hidden (view full) ---

2252system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2253system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2254system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2255system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2256system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
2257system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2258system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
2259system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2260system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes)
2261system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
2262system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
2263system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes)
2264system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks)
2265system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2266system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
2267system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2268system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
2269system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2270system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
2271system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2272system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)

--- 23 unchanged lines hidden (view full) ---

2296system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
2297system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2298system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
2299system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2300system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
2301system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2302system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
2303system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2304system.iobus.reqLayer27.occupancy 187554192 # Layer occupancy (ticks)
2305system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2306system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2307system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2308system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks)
2309system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2310system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
2311system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2312system.iocache.tags.replacements 36445 # number of replacements
2313system.iocache.tags.tagsinuse 14.390549 # Cycle average of tags in use
2314system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2315system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
2316system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2317system.iocache.tags.warmup_cycle 288373025000 # Cycle when the warmup percentage was hit.
2318system.iocache.tags.occ_blocks::realview.ide 14.390549 # Average occupied blocks per requestor
2319system.iocache.tags.occ_percent::realview.ide 0.899409 # Average percentage of cache occupancy
2320system.iocache.tags.occ_percent::total 0.899409 # Average percentage of cache occupancy
2321system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2322system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2323system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2324system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2325system.iocache.tags.data_accesses 328311 # Number of data accesses
2326system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2327system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2328system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2329system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2330system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
2331system.iocache.demand_misses::total 255 # number of demand (read+write) misses
2332system.iocache.overall_misses::realview.ide 255 # number of overall misses
2333system.iocache.overall_misses::total 255 # number of overall misses
2334system.iocache.ReadReq_miss_latency::realview.ide 32657877 # number of ReadReq miss cycles
2335system.iocache.ReadReq_miss_latency::total 32657877 # number of ReadReq miss cycles
2336system.iocache.WriteLineReq_miss_latency::realview.ide 4277536315 # number of WriteLineReq miss cycles
2337system.iocache.WriteLineReq_miss_latency::total 4277536315 # number of WriteLineReq miss cycles
2338system.iocache.demand_miss_latency::realview.ide 32657877 # number of demand (read+write) miss cycles
2339system.iocache.demand_miss_latency::total 32657877 # number of demand (read+write) miss cycles
2340system.iocache.overall_miss_latency::realview.ide 32657877 # number of overall miss cycles
2341system.iocache.overall_miss_latency::total 32657877 # number of overall miss cycles
2342system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2343system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2344system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2345system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2346system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
2347system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
2348system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
2349system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
2350system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2351system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2352system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2353system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2354system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2355system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2356system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2357system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2358system.iocache.ReadReq_avg_miss_latency::realview.ide 128070.105882 # average ReadReq miss latency
2359system.iocache.ReadReq_avg_miss_latency::total 128070.105882 # average ReadReq miss latency
2360system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118085.697742 # average WriteLineReq miss latency
2361system.iocache.WriteLineReq_avg_miss_latency::total 118085.697742 # average WriteLineReq miss latency
2362system.iocache.demand_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency
2363system.iocache.demand_avg_miss_latency::total 128070.105882 # average overall miss latency
2364system.iocache.overall_avg_miss_latency::realview.ide 128070.105882 # average overall miss latency
2365system.iocache.overall_avg_miss_latency::total 128070.105882 # average overall miss latency
2366system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
2367system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2368system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
2369system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2370system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked
2371system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2372system.iocache.fast_writes 0 # number of fast writes performed
2373system.iocache.cache_copies 0 # number of cache copies performed
2374system.iocache.writebacks::writebacks 36190 # number of writebacks
2375system.iocache.writebacks::total 36190 # number of writebacks
2376system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2377system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2378system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2379system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2380system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
2381system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
2382system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
2383system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
2384system.iocache.ReadReq_mshr_miss_latency::realview.ide 19907877 # number of ReadReq MSHR miss cycles
2385system.iocache.ReadReq_mshr_miss_latency::total 19907877 # number of ReadReq MSHR miss cycles
2386system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2466336315 # number of WriteLineReq MSHR miss cycles
2387system.iocache.WriteLineReq_mshr_miss_latency::total 2466336315 # number of WriteLineReq MSHR miss cycles
2388system.iocache.demand_mshr_miss_latency::realview.ide 19907877 # number of demand (read+write) MSHR miss cycles
2389system.iocache.demand_mshr_miss_latency::total 19907877 # number of demand (read+write) MSHR miss cycles
2390system.iocache.overall_mshr_miss_latency::realview.ide 19907877 # number of overall MSHR miss cycles
2391system.iocache.overall_mshr_miss_latency::total 19907877 # number of overall MSHR miss cycles
2392system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2393system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2394system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2395system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2396system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2397system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2398system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2399system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2400system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78070.105882 # average ReadReq mshr miss latency
2401system.iocache.ReadReq_avg_mshr_miss_latency::total 78070.105882 # average ReadReq mshr miss latency
2402system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68085.697742 # average WriteLineReq mshr miss latency
2403system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68085.697742 # average WriteLineReq mshr miss latency
2404system.iocache.demand_avg_mshr_miss_latency::realview.ide 78070.105882 # average overall mshr miss latency
2405system.iocache.demand_avg_mshr_miss_latency::total 78070.105882 # average overall mshr miss latency
2406system.iocache.overall_avg_mshr_miss_latency::realview.ide 78070.105882 # average overall mshr miss latency
2407system.iocache.overall_avg_mshr_miss_latency::total 78070.105882 # average overall mshr miss latency
2408system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2409system.l2c.tags.replacements 130014 # number of replacements
2410system.l2c.tags.tagsinuse 63961.093315 # Cycle average of tags in use
2411system.l2c.tags.total_refs 392369 # Total number of references to valid blocks.
2412system.l2c.tags.sampled_refs 194378 # Sample count of references to valid blocks.
2413system.l2c.tags.avg_refs 2.018587 # Average number of references to valid blocks.
2414system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2415system.l2c.tags.occ_blocks::writebacks 12058.686901 # Average occupied blocks per requestor
2416system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.020417 # Average occupied blocks per requestor
2417system.l2c.tags.occ_blocks::cpu0.itb.walker 0.045313 # Average occupied blocks per requestor
2418system.l2c.tags.occ_blocks::cpu0.inst 7839.345721 # Average occupied blocks per requestor
2419system.l2c.tags.occ_blocks::cpu0.data 2905.478880 # Average occupied blocks per requestor
2420system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37500.688357 # Average occupied blocks per requestor
2421system.l2c.tags.occ_blocks::cpu1.inst 950.717991 # Average occupied blocks per requestor
2422system.l2c.tags.occ_blocks::cpu1.data 465.629828 # Average occupied blocks per requestor
2423system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2237.479906 # Average occupied blocks per requestor
2424system.l2c.tags.occ_percent::writebacks 0.184001 # Average percentage of cache occupancy
2425system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000046 # Average percentage of cache occupancy
2426system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2427system.l2c.tags.occ_percent::cpu0.inst 0.119619 # Average percentage of cache occupancy
2428system.l2c.tags.occ_percent::cpu0.data 0.044334 # Average percentage of cache occupancy
2429system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.572215 # Average percentage of cache occupancy
2430system.l2c.tags.occ_percent::cpu1.inst 0.014507 # Average percentage of cache occupancy
2431system.l2c.tags.occ_percent::cpu1.data 0.007105 # Average percentage of cache occupancy
2432system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034141 # Average percentage of cache occupancy
2433system.l2c.tags.occ_percent::total 0.975969 # Average percentage of cache occupancy
2434system.l2c.tags.occ_task_id_blocks::1022 32308 # Occupied blocks per task id
2435system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
2436system.l2c.tags.occ_task_id_blocks::1024 32052 # Occupied blocks per task id
2437system.l2c.tags.age_task_id_blocks_1022::2 225 # Occupied blocks per task id
2438system.l2c.tags.age_task_id_blocks_1022::3 4677 # Occupied blocks per task id
2439system.l2c.tags.age_task_id_blocks_1022::4 27406 # Occupied blocks per task id
2440system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
2441system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
2442system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
2443system.l2c.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
2444system.l2c.tags.age_task_id_blocks_1024::3 1819 # Occupied blocks per task id
2445system.l2c.tags.age_task_id_blocks_1024::4 29951 # Occupied blocks per task id
2446system.l2c.tags.occ_task_id_percent::1022 0.492981 # Percentage of cache occupancy per task id
2447system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
2448system.l2c.tags.occ_task_id_percent::1024 0.489075 # Percentage of cache occupancy per task id
2449system.l2c.tags.tag_accesses 5325589 # Number of tag accesses
2450system.l2c.tags.data_accesses 5325589 # Number of data accesses
2451system.l2c.Writeback_hits::writebacks 226708 # number of Writeback hits
2452system.l2c.Writeback_hits::total 226708 # number of Writeback hits
2453system.l2c.UpgradeReq_hits::cpu0.data 2021 # number of UpgradeReq hits
2454system.l2c.UpgradeReq_hits::cpu1.data 691 # number of UpgradeReq hits
2455system.l2c.UpgradeReq_hits::total 2712 # number of UpgradeReq hits
2456system.l2c.SCUpgradeReq_hits::cpu0.data 141 # number of SCUpgradeReq hits
2457system.l2c.SCUpgradeReq_hits::cpu1.data 160 # number of SCUpgradeReq hits
2458system.l2c.SCUpgradeReq_hits::total 301 # number of SCUpgradeReq hits
2459system.l2c.ReadExReq_hits::cpu0.data 3915 # number of ReadExReq hits
2460system.l2c.ReadExReq_hits::cpu1.data 1420 # number of ReadExReq hits
2461system.l2c.ReadExReq_hits::total 5335 # number of ReadExReq hits
2462system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 81 # number of ReadSharedReq hits
2463system.l2c.ReadSharedReq_hits::cpu0.itb.walker 55 # number of ReadSharedReq hits
2464system.l2c.ReadSharedReq_hits::cpu0.inst 30090 # number of ReadSharedReq hits
2465system.l2c.ReadSharedReq_hits::cpu0.data 45920 # number of ReadSharedReq hits
2466system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45888 # number of ReadSharedReq hits
2467system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 41 # number of ReadSharedReq hits
2468system.l2c.ReadSharedReq_hits::cpu1.itb.walker 34 # number of ReadSharedReq hits
2469system.l2c.ReadSharedReq_hits::cpu1.inst 11628 # number of ReadSharedReq hits
2470system.l2c.ReadSharedReq_hits::cpu1.data 8389 # number of ReadSharedReq hits
2471system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5369 # number of ReadSharedReq hits
2472system.l2c.ReadSharedReq_hits::total 147495 # number of ReadSharedReq hits
2473system.l2c.demand_hits::cpu0.dtb.walker 81 # number of demand (read+write) hits
2474system.l2c.demand_hits::cpu0.itb.walker 55 # number of demand (read+write) hits
2475system.l2c.demand_hits::cpu0.inst 30090 # number of demand (read+write) hits
2476system.l2c.demand_hits::cpu0.data 49835 # number of demand (read+write) hits
2477system.l2c.demand_hits::cpu0.l2cache.prefetcher 45888 # number of demand (read+write) hits
2478system.l2c.demand_hits::cpu1.dtb.walker 41 # number of demand (read+write) hits
2479system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits
2480system.l2c.demand_hits::cpu1.inst 11628 # number of demand (read+write) hits
2481system.l2c.demand_hits::cpu1.data 9809 # number of demand (read+write) hits
2482system.l2c.demand_hits::cpu1.l2cache.prefetcher 5369 # number of demand (read+write) hits
2483system.l2c.demand_hits::total 152830 # number of demand (read+write) hits
2484system.l2c.overall_hits::cpu0.dtb.walker 81 # number of overall hits
2485system.l2c.overall_hits::cpu0.itb.walker 55 # number of overall hits
2486system.l2c.overall_hits::cpu0.inst 30090 # number of overall hits
2487system.l2c.overall_hits::cpu0.data 49835 # number of overall hits
2488system.l2c.overall_hits::cpu0.l2cache.prefetcher 45888 # number of overall hits
2489system.l2c.overall_hits::cpu1.dtb.walker 41 # number of overall hits
2490system.l2c.overall_hits::cpu1.itb.walker 34 # number of overall hits
2491system.l2c.overall_hits::cpu1.inst 11628 # number of overall hits
2492system.l2c.overall_hits::cpu1.data 9809 # number of overall hits
2493system.l2c.overall_hits::cpu1.l2cache.prefetcher 5369 # number of overall hits
2494system.l2c.overall_hits::total 152830 # number of overall hits
2495system.l2c.UpgradeReq_misses::cpu0.data 8373 # number of UpgradeReq misses
2496system.l2c.UpgradeReq_misses::cpu1.data 2542 # number of UpgradeReq misses
2497system.l2c.UpgradeReq_misses::total 10915 # number of UpgradeReq misses
2498system.l2c.SCUpgradeReq_misses::cpu0.data 478 # number of SCUpgradeReq misses
2499system.l2c.SCUpgradeReq_misses::cpu1.data 1195 # number of SCUpgradeReq misses
2500system.l2c.SCUpgradeReq_misses::total 1673 # number of SCUpgradeReq misses
2501system.l2c.ReadExReq_misses::cpu0.data 11367 # number of ReadExReq misses
2502system.l2c.ReadExReq_misses::cpu1.data 8062 # number of ReadExReq misses
2503system.l2c.ReadExReq_misses::total 19429 # number of ReadExReq misses
2504system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses
2505system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
2506system.l2c.ReadSharedReq_misses::cpu0.inst 17941 # number of ReadSharedReq misses
2507system.l2c.ReadSharedReq_misses::cpu0.data 8815 # number of ReadSharedReq misses
2508system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134305 # number of ReadSharedReq misses
2509system.l2c.ReadSharedReq_misses::cpu1.inst 1735 # number of ReadSharedReq misses
2510system.l2c.ReadSharedReq_misses::cpu1.data 851 # number of ReadSharedReq misses
2511system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6450 # number of ReadSharedReq misses
2512system.l2c.ReadSharedReq_misses::total 170106 # number of ReadSharedReq misses
2513system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses
2514system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
2515system.l2c.demand_misses::cpu0.inst 17941 # number of demand (read+write) misses
2516system.l2c.demand_misses::cpu0.data 20182 # number of demand (read+write) misses
2517system.l2c.demand_misses::cpu0.l2cache.prefetcher 134305 # number of demand (read+write) misses
2518system.l2c.demand_misses::cpu1.inst 1735 # number of demand (read+write) misses
2519system.l2c.demand_misses::cpu1.data 8913 # number of demand (read+write) misses
2520system.l2c.demand_misses::cpu1.l2cache.prefetcher 6450 # number of demand (read+write) misses
2521system.l2c.demand_misses::total 189535 # number of demand (read+write) misses
2522system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses
2523system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
2524system.l2c.overall_misses::cpu0.inst 17941 # number of overall misses
2525system.l2c.overall_misses::cpu0.data 20182 # number of overall misses
2526system.l2c.overall_misses::cpu0.l2cache.prefetcher 134305 # number of overall misses
2527system.l2c.overall_misses::cpu1.inst 1735 # number of overall misses
2528system.l2c.overall_misses::cpu1.data 8913 # number of overall misses
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2530system.l2c.overall_misses::total 189535 # number of overall misses
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2532system.l2c.UpgradeReq_miss_latency::cpu1.data 2669500 # number of UpgradeReq miss cycles
2533system.l2c.UpgradeReq_miss_latency::total 10457000 # number of UpgradeReq miss cycles
2534system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1236500 # number of SCUpgradeReq miss cycles
2535system.l2c.SCUpgradeReq_miss_latency::cpu1.data 708000 # number of SCUpgradeReq miss cycles
2536system.l2c.SCUpgradeReq_miss_latency::total 1944500 # number of SCUpgradeReq miss cycles
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2538system.l2c.ReadExReq_miss_latency::cpu1.data 658722000 # number of ReadExReq miss cycles
2539system.l2c.ReadExReq_miss_latency::total 1750787500 # number of ReadExReq miss cycles
2540system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 816000 # number of ReadSharedReq miss cycles
2541system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 166000 # number of ReadSharedReq miss cycles
2542system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1444848500 # number of ReadSharedReq miss cycles
2543system.l2c.ReadSharedReq_miss_latency::cpu0.data 766909500 # number of ReadSharedReq miss cycles
2544system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 12944226902 # number of ReadSharedReq miss cycles
2545system.l2c.ReadSharedReq_miss_latency::cpu1.inst 144716500 # number of ReadSharedReq miss cycles
2546system.l2c.ReadSharedReq_miss_latency::cpu1.data 75717500 # number of ReadSharedReq miss cycles
2547system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 743765397 # number of ReadSharedReq miss cycles
2548system.l2c.ReadSharedReq_miss_latency::total 16121166299 # number of ReadSharedReq miss cycles
2549system.l2c.demand_miss_latency::cpu0.dtb.walker 816000 # number of demand (read+write) miss cycles
2550system.l2c.demand_miss_latency::cpu0.itb.walker 166000 # number of demand (read+write) miss cycles
2551system.l2c.demand_miss_latency::cpu0.inst 1444848500 # number of demand (read+write) miss cycles
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2553system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12944226902 # number of demand (read+write) miss cycles
2554system.l2c.demand_miss_latency::cpu1.inst 144716500 # number of demand (read+write) miss cycles
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2556system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 743765397 # number of demand (read+write) miss cycles
2557system.l2c.demand_miss_latency::total 17871953799 # number of demand (read+write) miss cycles
2558system.l2c.overall_miss_latency::cpu0.dtb.walker 816000 # number of overall miss cycles
2559system.l2c.overall_miss_latency::cpu0.itb.walker 166000 # number of overall miss cycles
2560system.l2c.overall_miss_latency::cpu0.inst 1444848500 # number of overall miss cycles
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2563system.l2c.overall_miss_latency::cpu1.inst 144716500 # number of overall miss cycles
2564system.l2c.overall_miss_latency::cpu1.data 734439500 # number of overall miss cycles
2565system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 743765397 # number of overall miss cycles
2566system.l2c.overall_miss_latency::total 17871953799 # number of overall miss cycles
2567system.l2c.Writeback_accesses::writebacks 226708 # number of Writeback accesses(hits+misses)
2568system.l2c.Writeback_accesses::total 226708 # number of Writeback accesses(hits+misses)
2569system.l2c.UpgradeReq_accesses::cpu0.data 10394 # number of UpgradeReq accesses(hits+misses)
2570system.l2c.UpgradeReq_accesses::cpu1.data 3233 # number of UpgradeReq accesses(hits+misses)
2571system.l2c.UpgradeReq_accesses::total 13627 # number of UpgradeReq accesses(hits+misses)
2572system.l2c.SCUpgradeReq_accesses::cpu0.data 619 # number of SCUpgradeReq accesses(hits+misses)
2573system.l2c.SCUpgradeReq_accesses::cpu1.data 1355 # number of SCUpgradeReq accesses(hits+misses)
2574system.l2c.SCUpgradeReq_accesses::total 1974 # number of SCUpgradeReq accesses(hits+misses)
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2576system.l2c.ReadExReq_accesses::cpu1.data 9482 # number of ReadExReq accesses(hits+misses)
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2579system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 57 # number of ReadSharedReq accesses(hits+misses)
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2582system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 180193 # number of ReadSharedReq accesses(hits+misses)
2583system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 41 # number of ReadSharedReq accesses(hits+misses)
2584system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 34 # number of ReadSharedReq accesses(hits+misses)
2585system.l2c.ReadSharedReq_accesses::cpu1.inst 13363 # number of ReadSharedReq accesses(hits+misses)
2586system.l2c.ReadSharedReq_accesses::cpu1.data 9240 # number of ReadSharedReq accesses(hits+misses)
2587system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11819 # number of ReadSharedReq accesses(hits+misses)
2588system.l2c.ReadSharedReq_accesses::total 317601 # number of ReadSharedReq accesses(hits+misses)
2589system.l2c.demand_accesses::cpu0.dtb.walker 88 # number of demand (read+write) accesses
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2595system.l2c.demand_accesses::cpu1.itb.walker 34 # number of demand (read+write) accesses
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2600system.l2c.overall_accesses::cpu0.dtb.walker 88 # number of overall (read+write) accesses
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2607system.l2c.overall_accesses::cpu1.inst 13363 # number of overall (read+write) accesses
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2611system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805561 # miss rate for UpgradeReq accesses
2612system.l2c.UpgradeReq_miss_rate::cpu1.data 0.786267 # miss rate for UpgradeReq accesses
2613system.l2c.UpgradeReq_miss_rate::total 0.800983 # miss rate for UpgradeReq accesses
2614system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772213 # miss rate for SCUpgradeReq accesses
2615system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.881919 # miss rate for SCUpgradeReq accesses
2616system.l2c.SCUpgradeReq_miss_rate::total 0.847518 # miss rate for SCUpgradeReq accesses
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2618system.l2c.ReadExReq_miss_rate::cpu1.data 0.850243 # miss rate for ReadExReq accesses
2619system.l2c.ReadExReq_miss_rate::total 0.784566 # miss rate for ReadExReq accesses
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2621system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.035088 # miss rate for ReadSharedReq accesses
2622system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.373530 # miss rate for ReadSharedReq accesses
2623system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.161049 # miss rate for ReadSharedReq accesses
2624system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.745340 # miss rate for ReadSharedReq accesses
2625system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.129836 # miss rate for ReadSharedReq accesses
2626system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.092100 # miss rate for ReadSharedReq accesses
2627system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.545731 # miss rate for ReadSharedReq accesses
2628system.l2c.ReadSharedReq_miss_rate::total 0.535597 # miss rate for ReadSharedReq accesses
2629system.l2c.demand_miss_rate::cpu0.dtb.walker 0.079545 # miss rate for demand accesses
2630system.l2c.demand_miss_rate::cpu0.itb.walker 0.035088 # miss rate for demand accesses
2631system.l2c.demand_miss_rate::cpu0.inst 0.373530 # miss rate for demand accesses
2632system.l2c.demand_miss_rate::cpu0.data 0.288244 # miss rate for demand accesses
2633system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.745340 # miss rate for demand accesses
2634system.l2c.demand_miss_rate::cpu1.inst 0.129836 # miss rate for demand accesses
2635system.l2c.demand_miss_rate::cpu1.data 0.476071 # miss rate for demand accesses
2636system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.545731 # miss rate for demand accesses
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2638system.l2c.overall_miss_rate::cpu0.dtb.walker 0.079545 # miss rate for overall accesses
2639system.l2c.overall_miss_rate::cpu0.itb.walker 0.035088 # miss rate for overall accesses
2640system.l2c.overall_miss_rate::cpu0.inst 0.373530 # miss rate for overall accesses
2641system.l2c.overall_miss_rate::cpu0.data 0.288244 # miss rate for overall accesses
2642system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.745340 # miss rate for overall accesses
2643system.l2c.overall_miss_rate::cpu1.inst 0.129836 # miss rate for overall accesses
2644system.l2c.overall_miss_rate::cpu1.data 0.476071 # miss rate for overall accesses
2645system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.545731 # miss rate for overall accesses
2646system.l2c.overall_miss_rate::total 0.553605 # miss rate for overall accesses
2647system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 930.072853 # average UpgradeReq miss latency
2648system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1050.157356 # average UpgradeReq miss latency
2649system.l2c.UpgradeReq_avg_miss_latency::total 958.039395 # average UpgradeReq miss latency
2650system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2586.820084 # average SCUpgradeReq miss latency
2651system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 592.468619 # average SCUpgradeReq miss latency
2652system.l2c.SCUpgradeReq_avg_miss_latency::total 1162.283323 # average SCUpgradeReq miss latency
2653system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96073.326295 # average ReadExReq miss latency
2654system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81707.020590 # average ReadExReq miss latency
2655system.l2c.ReadExReq_avg_miss_latency::total 90112.074734 # average ReadExReq miss latency
2656system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 116571.428571 # average ReadSharedReq miss latency
2657system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadSharedReq miss latency
2658system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 80533.331475 # average ReadSharedReq miss latency
2659system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 87000.510493 # average ReadSharedReq miss latency
2660system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 96379.337344 # average ReadSharedReq miss latency
2661system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 83410.086455 # average ReadSharedReq miss latency
2662system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 88974.735605 # average ReadSharedReq miss latency
2663system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 115312.464651 # average ReadSharedReq miss latency
2664system.l2c.ReadSharedReq_avg_miss_latency::total 94771.297303 # average ReadSharedReq miss latency
2665system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 116571.428571 # average overall miss latency
2666system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency
2667system.l2c.demand_avg_miss_latency::cpu0.inst 80533.331475 # average overall miss latency
2668system.l2c.demand_avg_miss_latency::cpu0.data 92110.544049 # average overall miss latency
2669system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96379.337344 # average overall miss latency
2670system.l2c.demand_avg_miss_latency::cpu1.inst 83410.086455 # average overall miss latency
2671system.l2c.demand_avg_miss_latency::cpu1.data 82400.931224 # average overall miss latency
2672system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115312.464651 # average overall miss latency
2673system.l2c.demand_avg_miss_latency::total 94293.686121 # average overall miss latency
2674system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 116571.428571 # average overall miss latency
2675system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency
2676system.l2c.overall_avg_miss_latency::cpu0.inst 80533.331475 # average overall miss latency
2677system.l2c.overall_avg_miss_latency::cpu0.data 92110.544049 # average overall miss latency
2678system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96379.337344 # average overall miss latency
2679system.l2c.overall_avg_miss_latency::cpu1.inst 83410.086455 # average overall miss latency
2680system.l2c.overall_avg_miss_latency::cpu1.data 82400.931224 # average overall miss latency
2681system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115312.464651 # average overall miss latency
2682system.l2c.overall_avg_miss_latency::total 94293.686121 # average overall miss latency
2683system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2684system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2685system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2686system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2687system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2688system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2689system.l2c.fast_writes 0 # number of fast writes performed
2690system.l2c.cache_copies 0 # number of cache copies performed
2691system.l2c.writebacks::writebacks 99996 # number of writebacks
2692system.l2c.writebacks::total 99996 # number of writebacks
2693system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 2 # number of ReadSharedReq MSHR hits
2694system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits
2695system.l2c.ReadSharedReq_mshr_hits::total 12 # number of ReadSharedReq MSHR hits
2696system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
2697system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits
2698system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits
2699system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
2700system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits
2701system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits
2702system.l2c.CleanEvict_mshr_misses::writebacks 2923 # number of CleanEvict MSHR misses
2703system.l2c.CleanEvict_mshr_misses::total 2923 # number of CleanEvict MSHR misses
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2707system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 478 # number of SCUpgradeReq MSHR misses
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2726system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134305 # number of demand (read+write) MSHR misses
2727system.l2c.demand_mshr_misses::cpu1.inst 1725 # number of demand (read+write) MSHR misses
2728system.l2c.demand_mshr_misses::cpu1.data 8913 # number of demand (read+write) MSHR misses
2729system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6450 # number of demand (read+write) MSHR misses
2730system.l2c.demand_mshr_misses::total 189523 # number of demand (read+write) MSHR misses
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2734system.l2c.overall_mshr_misses::cpu0.data 20182 # number of overall MSHR misses
2735system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134305 # number of overall MSHR misses
2736system.l2c.overall_mshr_misses::cpu1.inst 1725 # number of overall MSHR misses
2737system.l2c.overall_mshr_misses::cpu1.data 8913 # number of overall MSHR misses
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2739system.l2c.overall_mshr_misses::total 189523 # number of overall MSHR misses
2740system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
2741system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32335 # number of ReadReq MSHR uncacheable
2742system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2743system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2504 # number of ReadReq MSHR uncacheable
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2746system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2155 # number of WriteReq MSHR uncacheable
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2748system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
2749system.l2c.overall_mshr_uncacheable_misses::cpu0.data 61054 # number of overall MSHR uncacheable misses
2750system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2751system.l2c.overall_mshr_uncacheable_misses::cpu1.data 4659 # number of overall MSHR uncacheable misses
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2753system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 174263500 # number of UpgradeReq MSHR miss cycles
2754system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 52800500 # number of UpgradeReq MSHR miss cycles
2755system.l2c.UpgradeReq_mshr_miss_latency::total 227064000 # number of UpgradeReq MSHR miss cycles
2756system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10023500 # number of SCUpgradeReq MSHR miss cycles
2757system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 24840000 # number of SCUpgradeReq MSHR miss cycles
2758system.l2c.SCUpgradeReq_mshr_miss_latency::total 34863500 # number of SCUpgradeReq MSHR miss cycles
2759system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 978395500 # number of ReadExReq MSHR miss cycles
2760system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 578102000 # number of ReadExReq MSHR miss cycles
2761system.l2c.ReadExReq_mshr_miss_latency::total 1556497500 # number of ReadExReq MSHR miss cycles
2762system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 746000 # number of ReadSharedReq MSHR miss cycles
2763system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 146000 # number of ReadSharedReq MSHR miss cycles
2764system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1265389000 # number of ReadSharedReq MSHR miss cycles
2765system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 678759500 # number of ReadSharedReq MSHR miss cycles
2766system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11601176902 # number of ReadSharedReq MSHR miss cycles
2767system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 126976000 # number of ReadSharedReq MSHR miss cycles
2768system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 67207500 # number of ReadSharedReq MSHR miss cycles
2769system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 679265397 # number of ReadSharedReq MSHR miss cycles
2770system.l2c.ReadSharedReq_mshr_miss_latency::total 14419666299 # number of ReadSharedReq MSHR miss cycles
2771system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 746000 # number of demand (read+write) MSHR miss cycles
2772system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 146000 # number of demand (read+write) MSHR miss cycles
2773system.l2c.demand_mshr_miss_latency::cpu0.inst 1265389000 # number of demand (read+write) MSHR miss cycles
2774system.l2c.demand_mshr_miss_latency::cpu0.data 1657155000 # number of demand (read+write) MSHR miss cycles
2775system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11601176902 # number of demand (read+write) MSHR miss cycles
2776system.l2c.demand_mshr_miss_latency::cpu1.inst 126976000 # number of demand (read+write) MSHR miss cycles
2777system.l2c.demand_mshr_miss_latency::cpu1.data 645309500 # number of demand (read+write) MSHR miss cycles
2778system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 679265397 # number of demand (read+write) MSHR miss cycles
2779system.l2c.demand_mshr_miss_latency::total 15976163799 # number of demand (read+write) MSHR miss cycles
2780system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 746000 # number of overall MSHR miss cycles
2781system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 146000 # number of overall MSHR miss cycles
2782system.l2c.overall_mshr_miss_latency::cpu0.inst 1265389000 # number of overall MSHR miss cycles
2783system.l2c.overall_mshr_miss_latency::cpu0.data 1657155000 # number of overall MSHR miss cycles
2784system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11601176902 # number of overall MSHR miss cycles
2785system.l2c.overall_mshr_miss_latency::cpu1.inst 126976000 # number of overall MSHR miss cycles
2786system.l2c.overall_mshr_miss_latency::cpu1.data 645309500 # number of overall MSHR miss cycles
2787system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 679265397 # number of overall MSHR miss cycles
2788system.l2c.overall_mshr_miss_latency::total 15976163799 # number of overall MSHR miss cycles
2789system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 570734000 # number of ReadReq MSHR uncacheable cycles
2790system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5521577000 # number of ReadReq MSHR uncacheable cycles
2791system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10711500 # number of ReadReq MSHR uncacheable cycles
2792system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 237033000 # number of ReadReq MSHR uncacheable cycles
2793system.l2c.ReadReq_mshr_uncacheable_latency::total 6340055500 # number of ReadReq MSHR uncacheable cycles
2794system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4233141500 # number of WriteReq MSHR uncacheable cycles
2795system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 171755500 # number of WriteReq MSHR uncacheable cycles
2796system.l2c.WriteReq_mshr_uncacheable_latency::total 4404897000 # number of WriteReq MSHR uncacheable cycles
2797system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 570734000 # number of overall MSHR uncacheable cycles
2798system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9754718500 # number of overall MSHR uncacheable cycles
2799system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10711500 # number of overall MSHR uncacheable cycles
2800system.l2c.overall_mshr_uncacheable_latency::cpu1.data 408788500 # number of overall MSHR uncacheable cycles
2801system.l2c.overall_mshr_uncacheable_latency::total 10744952500 # number of overall MSHR uncacheable cycles
2802system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2803system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2804system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805561 # mshr miss rate for UpgradeReq accesses
2805system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.786267 # mshr miss rate for UpgradeReq accesses
2806system.l2c.UpgradeReq_mshr_miss_rate::total 0.800983 # mshr miss rate for UpgradeReq accesses
2807system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772213 # mshr miss rate for SCUpgradeReq accesses
2808system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.881919 # mshr miss rate for SCUpgradeReq accesses
2809system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.847518 # mshr miss rate for SCUpgradeReq accesses
2810system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.743816 # mshr miss rate for ReadExReq accesses
2811system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850243 # mshr miss rate for ReadExReq accesses
2812system.l2c.ReadExReq_mshr_miss_rate::total 0.784566 # mshr miss rate for ReadExReq accesses
2813system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.079545 # mshr miss rate for ReadSharedReq accesses
2814system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.035088 # mshr miss rate for ReadSharedReq accesses
2815system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.373488 # mshr miss rate for ReadSharedReq accesses
2816system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161049 # mshr miss rate for ReadSharedReq accesses
2817system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745340 # mshr miss rate for ReadSharedReq accesses
2818system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.129088 # mshr miss rate for ReadSharedReq accesses
2819system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.092100 # mshr miss rate for ReadSharedReq accesses
2820system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545731 # mshr miss rate for ReadSharedReq accesses
2821system.l2c.ReadSharedReq_mshr_miss_rate::total 0.535559 # mshr miss rate for ReadSharedReq accesses
2822system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.079545 # mshr miss rate for demand accesses
2823system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.035088 # mshr miss rate for demand accesses
2824system.l2c.demand_mshr_miss_rate::cpu0.inst 0.373488 # mshr miss rate for demand accesses
2825system.l2c.demand_mshr_miss_rate::cpu0.data 0.288244 # mshr miss rate for demand accesses
2826system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745340 # mshr miss rate for demand accesses
2827system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129088 # mshr miss rate for demand accesses
2828system.l2c.demand_mshr_miss_rate::cpu1.data 0.476071 # mshr miss rate for demand accesses
2829system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545731 # mshr miss rate for demand accesses
2830system.l2c.demand_mshr_miss_rate::total 0.553570 # mshr miss rate for demand accesses
2831system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.079545 # mshr miss rate for overall accesses
2832system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.035088 # mshr miss rate for overall accesses
2833system.l2c.overall_mshr_miss_rate::cpu0.inst 0.373488 # mshr miss rate for overall accesses
2834system.l2c.overall_mshr_miss_rate::cpu0.data 0.288244 # mshr miss rate for overall accesses
2835system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.745340 # mshr miss rate for overall accesses
2836system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129088 # mshr miss rate for overall accesses
2837system.l2c.overall_mshr_miss_rate::cpu1.data 0.476071 # mshr miss rate for overall accesses
2838system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545731 # mshr miss rate for overall accesses
2839system.l2c.overall_mshr_miss_rate::total 0.553570 # mshr miss rate for overall accesses
2840system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20812.552251 # average UpgradeReq mshr miss latency
2841system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20771.243116 # average UpgradeReq mshr miss latency
2842system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20802.931745 # average UpgradeReq mshr miss latency
2843system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20969.665272 # average SCUpgradeReq mshr miss latency
2844system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20786.610879 # average SCUpgradeReq mshr miss latency
2845system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20838.912134 # average SCUpgradeReq mshr miss latency
2846system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86073.326295 # average ReadExReq mshr miss latency
2847system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71707.020590 # average ReadExReq mshr miss latency
2848system.l2c.ReadExReq_avg_mshr_miss_latency::total 80112.074734 # average ReadExReq mshr miss latency
2849system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average ReadSharedReq mshr miss latency
2850system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average ReadSharedReq mshr miss latency
2851system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average ReadSharedReq mshr miss latency
2852system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77000.510493 # average ReadSharedReq mshr miss latency
2853system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average ReadSharedReq mshr miss latency
2854system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average ReadSharedReq mshr miss latency
2855system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 78974.735605 # average ReadSharedReq mshr miss latency
2856system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average ReadSharedReq mshr miss latency
2857system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 84774.691047 # average ReadSharedReq mshr miss latency
2858system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average overall mshr miss latency
2859system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency
2860system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average overall mshr miss latency
2861system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82110.544049 # average overall mshr miss latency
2862system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average overall mshr miss latency
2863system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average overall mshr miss latency
2864system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency
2865system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency
2866system.l2c.demand_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency
2867system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 106571.428571 # average overall mshr miss latency
2868system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73000 # average overall mshr miss latency
2869system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70538.435810 # average overall mshr miss latency
2870system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82110.544049 # average overall mshr miss latency
2871system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86379.337344 # average overall mshr miss latency
2872system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73609.275362 # average overall mshr miss latency
2873system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72400.931224 # average overall mshr miss latency
2874system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 105312.464651 # average overall mshr miss latency
2875system.l2c.overall_avg_mshr_miss_latency::total 84296.701714 # average overall mshr miss latency
2876system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average ReadReq mshr uncacheable latency
2877system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170761.620535 # average ReadReq mshr uncacheable latency
2878system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average ReadReq mshr uncacheable latency
2879system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94661.741214 # average ReadReq mshr uncacheable latency
2880system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 143967.834597 # average ReadReq mshr uncacheable latency
2881system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147398.638532 # average WriteReq mshr uncacheable latency
2882system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 79700.928074 # average WriteReq mshr uncacheable latency
2883system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142673.349744 # average WriteReq mshr uncacheable latency
2884system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63260.252716 # average overall mshr uncacheable latency
2885system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 159771.980542 # average overall mshr uncacheable latency
2886system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60516.949153 # average overall mshr uncacheable latency
2887system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87741.682765 # average overall mshr uncacheable latency
2888system.l2c.overall_avg_mshr_uncacheable_latency::total 143434.329613 # average overall mshr uncacheable latency
2889system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2890system.membus.trans_dist::ReadReq 44038 # Transaction distribution
2891system.membus.trans_dist::ReadResp 214387 # Transaction distribution
2892system.membus.trans_dist::WriteReq 30874 # Transaction distribution
2893system.membus.trans_dist::WriteResp 30874 # Transaction distribution
2894system.membus.trans_dist::Writeback 136186 # Transaction distribution
2895system.membus.trans_dist::CleanEvict 15507 # Transaction distribution
2896system.membus.trans_dist::UpgradeReq 74602 # Transaction distribution
2897system.membus.trans_dist::SCUpgradeReq 39992 # Transaction distribution
2898system.membus.trans_dist::UpgradeResp 12685 # Transaction distribution
2899system.membus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution
2900system.membus.trans_dist::ReadExReq 39841 # Transaction distribution
2901system.membus.trans_dist::ReadExResp 19332 # Transaction distribution
2902system.membus.trans_dist::ReadSharedReq 170349 # Transaction distribution
2903system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2904system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
2905system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
2906system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
2907system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes)
2908system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 670072 # Packet count per connected master and slave (bytes)
2909system.membus.pkt_count_system.l2c.mem_side::total 791596 # Packet count per connected master and slave (bytes)
2910system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes)
2911system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes)
2912system.membus.pkt_count::total 900517 # Packet count per connected master and slave (bytes)
2913system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes)
2914system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
2915system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes)
2916system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18557448 # Cumulative packet size per connected master and slave (bytes)
2917system.membus.pkt_size_system.l2c.mem_side::total 18747458 # Cumulative packet size per connected master and slave (bytes)
2918system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes)
2919system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes)
2920system.membus.pkt_size::total 21064578 # Cumulative packet size per connected master and slave (bytes)
2921system.membus.snoops 123030 # Total snoops (count)
2922system.membus.snoop_fanout::samples 587901 # Request fanout histogram
2923system.membus.snoop_fanout::mean 1 # Request fanout histogram
2924system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2925system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2926system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2927system.membus.snoop_fanout::1 587901 100.00% 100.00% # Request fanout histogram
2928system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2929system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2930system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2931system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2932system.membus.snoop_fanout::total 587901 # Request fanout histogram
2933system.membus.reqLayer0.occupancy 88280499 # Layer occupancy (ticks)
2934system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2935system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks)
2936system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2937system.membus.reqLayer2.occupancy 11327500 # Layer occupancy (ticks)
2938system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2939system.membus.reqLayer5.occupancy 983138119 # Layer occupancy (ticks)
2940system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2941system.membus.respLayer2.occupancy 1138149025 # Layer occupancy (ticks)
2942system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2943system.membus.respLayer3.occupancy 64374606 # Layer occupancy (ticks)
2944system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2945system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2946system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2947system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2948system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2949system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2950system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2951system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

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2968system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
2969system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2970system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2971system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2972system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2973system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2974system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
2975system.realview.ethernet.droppedPackets 0 # number of packets dropped
2976system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks
2977system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
2978system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
2979system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
2980system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
2981system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
2982system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks
2983system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
2984system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
2985system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
2986system.toL2Bus.trans_dist::ReadReq 44042 # Transaction distribution
2987system.toL2Bus.trans_dist::ReadResp 480570 # Transaction distribution
2988system.toL2Bus.trans_dist::WriteReq 30874 # Transaction distribution
2989system.toL2Bus.trans_dist::WriteResp 30874 # Transaction distribution
2990system.toL2Bus.trans_dist::Writeback 362932 # Transaction distribution
2991system.toL2Bus.trans_dist::CleanEvict 82945 # Transaction distribution
2992system.toL2Bus.trans_dist::UpgradeReq 77217 # Transaction distribution
2993system.toL2Bus.trans_dist::SCUpgradeReq 40293 # Transaction distribution
2994system.toL2Bus.trans_dist::UpgradeResp 117510 # Transaction distribution
2995system.toL2Bus.trans_dist::SCUpgradeFailReq 92 # Transaction distribution
2996system.toL2Bus.trans_dist::UpgradeFailResp 92 # Transaction distribution
2997system.toL2Bus.trans_dist::ReadExReq 50721 # Transaction distribution
2998system.toL2Bus.trans_dist::ReadExResp 50721 # Transaction distribution
2999system.toL2Bus.trans_dist::ReadSharedReq 436543 # Transaction distribution
3000system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
3001system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1115711 # Packet count per connected master and slave (bytes)
3002system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 276298 # Packet count per connected master and slave (bytes)
3003system.toL2Bus.pkt_count::total 1392009 # Packet count per connected master and slave (bytes)
3004system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31905816 # Cumulative packet size per connected master and slave (bytes)
3005system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4776938 # Cumulative packet size per connected master and slave (bytes)
3006system.toL2Bus.pkt_size::total 36682754 # Cumulative packet size per connected master and slave (bytes)
3007system.toL2Bus.snoops 449881 # Total snoops (count)
3008system.toL2Bus.snoop_fanout::samples 1195846 # Request fanout histogram
3009system.toL2Bus.snoop_fanout::mean 1.169748 # Request fanout histogram
3010system.toL2Bus.snoop_fanout::stdev 0.375411 # Request fanout histogram
3011system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3012system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3013system.toL2Bus.snoop_fanout::1 992854 83.03% 83.03% # Request fanout histogram
3014system.toL2Bus.snoop_fanout::2 202992 16.97% 100.00% # Request fanout histogram
3015system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3016system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3017system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3018system.toL2Bus.snoop_fanout::total 1195846 # Request fanout histogram
3019system.toL2Bus.reqLayer0.occupancy 812251839 # Layer occupancy (ticks)
3020system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3021system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks)
3022system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3023system.toL2Bus.respLayer0.occupancy 627943021 # Layer occupancy (ticks)
3024system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3025system.toL2Bus.respLayer1.occupancy 221271516 # Layer occupancy (ticks)
3026system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3027
3028---------- End Simulation Statistics ----------