1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.675181 # Number of seconds simulated
4sim_ticks 2675180779000 # Number of ticks simulated
5final_tick 2675180779000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 349036 # Simulator instruction rate (inst/s)
8host_op_rate 416751 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 14917331050 # Simulator tick rate (ticks/s)
10host_mem_usage 433588 # Number of bytes of host memory used
11host_seconds 179.33 # Real time elapsed on the host
12sim_insts 62593972 # Number of instructions simulated
13sim_ops 74737529 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 120908 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 513788 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu0.l2cache.prefetcher 6659968 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 37828 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 531832 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 3262144 # Number of bytes read from this memory
26system.physmem.bytes_read::total 135383236 # Number of bytes read from this memory
27system.physmem.bytes_inst_read::cpu0.inst 120908 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu1.inst 37828 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 158736 # Number of instructions bytes read from this memory
30system.physmem.bytes_written::writebacks 4300032 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory
33system.physmem.bytes_written::total 7329168 # Number of bytes written to this memory
34system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 8117 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 8087 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 104062 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.inst 682 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.data 8328 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.l2cache.prefetcher 50971 # Number of read requests responded to by this memory
44system.physmem.num_reads::total 15712287 # Number of read requests responded to by this memory
45system.physmem.num_writes::writebacks 67188 # Number of write requests responded to by this memory
46system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
47system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory
48system.physmem.num_writes::total 824472 # Number of write requests responded to by this memory
49system.physmem.bw_read::realview.clcd 46447798 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.dtb.walker 48 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.itb.walker 96 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.inst 45196 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.data 192057 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.l2cache.prefetcher 2489539 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.dtb.walker 48 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.inst 14140 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.data 198802 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.l2cache.prefetcher 1219411 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::total 50607135 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_inst_read::cpu0.inst 45196 # Instruction read bandwidth from this memory (bytes/s)
61system.physmem.bw_inst_read::cpu1.inst 14140 # Instruction read bandwidth from this memory (bytes/s)
62system.physmem.bw_inst_read::total 59337 # Instruction read bandwidth from this memory (bytes/s)
63system.physmem.bw_write::writebacks 1607380 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_write::cpu0.data 6355 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_write::cpu1.data 1125956 # Write bandwidth from this memory (bytes/s)
66system.physmem.bw_write::total 2739691 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_total::writebacks 1607380 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::realview.clcd 46447798 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu0.itb.walker 96 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.inst 45196 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.data 198412 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.l2cache.prefetcher 2489539 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu1.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu1.inst 14140 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.data 1324758 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.l2cache.prefetcher 1219411 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::total 53346826 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.readReqs 15712287 # Number of read requests accepted
80system.physmem.writeReqs 824472 # Number of write requests accepted
81system.physmem.readBursts 15712287 # Number of DRAM read bursts, including those serviced by the write queue
82system.physmem.writeBursts 824472 # Number of DRAM write bursts, including those merged in the write queue
83system.physmem.bytesReadDRAM 1005465984 # Total number of bytes read from DRAM
84system.physmem.bytesReadWrQ 120384 # Total number of bytes read from write queue
85system.physmem.bytesWritten 7344256 # Total number of bytes written to DRAM
86system.physmem.bytesReadSys 135383236 # Total read bytes from the system interface side
87system.physmem.bytesWrittenSys 7329168 # Total written bytes from the system interface side
88system.physmem.servicedByWrQ 1881 # Number of DRAM read bursts serviced by the write queue
89system.physmem.mergedWrBursts 709695 # Number of DRAM write bursts merged with an existing one
90system.physmem.neitherReadNorWriteReqs 15472 # Number of requests that are neither read nor write
91system.physmem.perBankRdBursts::0 981539 # Per bank write bursts
92system.physmem.perBankRdBursts::1 981448 # Per bank write bursts
93system.physmem.perBankRdBursts::2 981211 # Per bank write bursts
94system.physmem.perBankRdBursts::3 981521 # Per bank write bursts
95system.physmem.perBankRdBursts::4 988300 # Per bank write bursts
96system.physmem.perBankRdBursts::5 981533 # Per bank write bursts
97system.physmem.perBankRdBursts::6 981210 # Per bank write bursts
98system.physmem.perBankRdBursts::7 981071 # Per bank write bursts
99system.physmem.perBankRdBursts::8 981831 # Per bank write bursts
100system.physmem.perBankRdBursts::9 982015 # Per bank write bursts
101system.physmem.perBankRdBursts::10 981421 # Per bank write bursts
102system.physmem.perBankRdBursts::11 980878 # Per bank write bursts
103system.physmem.perBankRdBursts::12 981926 # Per bank write bursts
104system.physmem.perBankRdBursts::13 981948 # Per bank write bursts
105system.physmem.perBankRdBursts::14 981516 # Per bank write bursts
106system.physmem.perBankRdBursts::15 981038 # Per bank write bursts
107system.physmem.perBankWrBursts::0 7155 # Per bank write bursts
108system.physmem.perBankWrBursts::1 7293 # Per bank write bursts
109system.physmem.perBankWrBursts::2 6957 # Per bank write bursts
110system.physmem.perBankWrBursts::3 6994 # Per bank write bursts
111system.physmem.perBankWrBursts::4 7537 # Per bank write bursts
112system.physmem.perBankWrBursts::5 7187 # Per bank write bursts
113system.physmem.perBankWrBursts::6 7207 # Per bank write bursts
114system.physmem.perBankWrBursts::7 7058 # Per bank write bursts
115system.physmem.perBankWrBursts::8 7329 # Per bank write bursts
116system.physmem.perBankWrBursts::9 7596 # Per bank write bursts
117system.physmem.perBankWrBursts::10 7177 # Per bank write bursts
118system.physmem.perBankWrBursts::11 6681 # Per bank write bursts
119system.physmem.perBankWrBursts::12 7505 # Per bank write bursts
120system.physmem.perBankWrBursts::13 7329 # Per bank write bursts
121system.physmem.perBankWrBursts::14 7034 # Per bank write bursts
122system.physmem.perBankWrBursts::15 6715 # Per bank write bursts
123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
124system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
125system.physmem.totGap 2675178052500 # Total gap between requests
126system.physmem.readPktSize::0 0 # Read request sizes (log2)
127system.physmem.readPktSize::1 0 # Read request sizes (log2)
128system.physmem.readPktSize::2 6799 # Read request sizes (log2)
129system.physmem.readPktSize::3 15532057 # Read request sizes (log2)
130system.physmem.readPktSize::4 0 # Read request sizes (log2)
131system.physmem.readPktSize::5 0 # Read request sizes (log2)
132system.physmem.readPktSize::6 173431 # Read request sizes (log2)
133system.physmem.writePktSize::0 0 # Write request sizes (log2)
134system.physmem.writePktSize::1 0 # Write request sizes (log2)
135system.physmem.writePktSize::2 757284 # Write request sizes (log2)
136system.physmem.writePktSize::3 0 # Write request sizes (log2)
137system.physmem.writePktSize::4 0 # Write request sizes (log2)
138system.physmem.writePktSize::5 0 # Write request sizes (log2)
139system.physmem.writePktSize::6 67188 # Write request sizes (log2)
140system.physmem.rdQLenPdf::0 1100287 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::1 996591 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::2 996926 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::3 1111424 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::4 1006011 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::5 1072049 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::6 2766642 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::7 2669294 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::8 3474563 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::9 133275 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::10 114946 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::11 106575 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::12 103058 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::13 20020 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::14 19187 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::15 18941 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::17 126 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::18 60 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::21 35 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::22 28 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::23 23 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::24 13 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::15 4098 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::16 4127 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::17 4820 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::18 5767 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::19 6235 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::20 6391 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::22 6628 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::23 6692 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::24 6804 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::25 6950 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::26 7066 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::27 7169 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::28 7372 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::29 7024 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::30 7083 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::31 7073 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::33 103 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::34 52 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::35 26 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
236system.physmem.bytesPerActivate::samples 1051606 # Bytes accessed per row activation
237system.physmem.bytesPerActivate::mean 963.108084 # Bytes accessed per row activation
238system.physmem.bytesPerActivate::gmean 883.927529 # Bytes accessed per row activation
239system.physmem.bytesPerActivate::stdev 220.726845 # Bytes accessed per row activation
240system.physmem.bytesPerActivate::0-127 33004 3.14% 3.14% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::128-255 22001 2.09% 5.23% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::256-383 9307 0.89% 6.12% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::384-511 2514 0.24% 6.35% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::512-639 3272 0.31% 6.67% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::640-767 2167 0.21% 6.87% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::768-895 8722 0.83% 7.70% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::896-1023 1051 0.10% 7.80% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::1024-1151 969568 92.20% 100.00% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::total 1051606 # Bytes accessed per row activation
250system.physmem.rdPerTurnAround::samples 6601 # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::mean 2380.003939 # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::stdev 98592.588392 # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::0-262143 6595 99.91% 99.91% # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::total 6601 # Reads before turning the bus around for writes
260system.physmem.wrPerTurnAround::samples 6601 # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::mean 17.384336 # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::gmean 17.341066 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::stdev 1.250693 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::16 2463 37.31% 37.31% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::17 32 0.48% 37.80% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::18 3686 55.84% 93.64% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::19 215 3.26% 96.89% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::20 85 1.29% 98.18% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::21 50 0.76% 98.94% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::22 28 0.42% 99.36% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::24 14 0.21% 99.85% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::25 7 0.11% 99.95% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::total 6601 # Writes before turning the bus around for reads
276system.physmem.totQLat 408788863752 # Total ticks spent queuing
277system.physmem.totMemAccLat 703358976252 # Total ticks spent from burst creation until serviced by the DRAM
278system.physmem.totBusLat 78552030000 # Total ticks spent in databus transfers
279system.physmem.avgQLat 26020.26 # Average queueing delay per DRAM burst
280system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
281system.physmem.avgMemAccLat 44770.26 # Average memory access latency per DRAM burst
282system.physmem.avgRdBW 375.85 # Average DRAM read bandwidth in MiByte/s
283system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s
284system.physmem.avgRdBWSys 50.61 # Average system read bandwidth in MiByte/s
285system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s
286system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
287system.physmem.busUtil 2.96 # Data bus utilization in percentage
288system.physmem.busUtilRead 2.94 # Data bus utilization in percentage for reads
289system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
290system.physmem.avgRdQLen 6.50 # Average read queue length when enqueuing
291system.physmem.avgWrQLen 26.70 # Average write queue length when enqueuing
292system.physmem.readRowHits 14689438 # Number of row buffer hits during reads
293system.physmem.writeRowHits 84116 # Number of row buffer hits during writes
294system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads
295system.physmem.writeRowHitRate 73.29 # Row buffer hit rate for writes
296system.physmem.avgGap 161771.61 # Average gap between requests
297system.physmem.pageHitRate 93.35 # Row buffer hit rate, read and write combined
298system.physmem.memoryStateTime::IDLE 2326940534750 # Time in different power states
299system.physmem.memoryStateTime::REF 89330020000 # Time in different power states
300system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
301system.physmem.memoryStateTime::ACT 258906121500 # Time in different power states
302system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
303system.physmem.actEnergy::0 3975289920 # Energy for activate commands per rank (pJ)
304system.physmem.actEnergy::1 3974851440 # Energy for activate commands per rank (pJ)
305system.physmem.preEnergy::0 2169057000 # Energy for precharge commands per rank (pJ)
306system.physmem.preEnergy::1 2168817750 # Energy for precharge commands per rank (pJ)
307system.physmem.readEnergy::0 61291097400 # Energy for read commands per rank (pJ)
308system.physmem.readEnergy::1 61250069400 # Energy for read commands per rank (pJ)
309system.physmem.writeEnergy::0 371874240 # Energy for write commands per rank (pJ)
310system.physmem.writeEnergy::1 371731680 # Energy for write commands per rank (pJ)
311system.physmem.refreshEnergy::0 174729519120 # Energy for refresh commands per rank (pJ)
312system.physmem.refreshEnergy::1 174729519120 # Energy for refresh commands per rank (pJ)
313system.physmem.actBackEnergy::0 149034867885 # Energy for active background per rank (pJ)
314system.physmem.actBackEnergy::1 147923300340 # Energy for active background per rank (pJ)
315system.physmem.preBackEnergy::0 1474373657250 # Energy for precharge background per rank (pJ)
316system.physmem.preBackEnergy::1 1475348716500 # Energy for precharge background per rank (pJ)
317system.physmem.totalEnergy::0 1865945362815 # Total energy per rank (pJ)
318system.physmem.totalEnergy::1 1865767006230 # Total energy per rank (pJ)
319system.physmem.averagePower::0 697.503604 # Core power per rank (mW)
320system.physmem.averagePower::1 697.436933 # Core power per rank (mW)
321system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
322system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
323system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
324system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
325system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
326system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
327system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
328system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
329system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
330system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
331system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s)
332system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
333system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
334system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s)
335system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
336system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
337system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s)
338system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
339system.membus.trans_dist::ReadReq 16891737 # Transaction distribution
340system.membus.trans_dist::ReadResp 16891737 # Transaction distribution
341system.membus.trans_dist::WriteReq 769090 # Transaction distribution
342system.membus.trans_dist::WriteResp 769090 # Transaction distribution
343system.membus.trans_dist::Writeback 67188 # Transaction distribution
344system.membus.trans_dist::UpgradeReq 56135 # Transaction distribution
345system.membus.trans_dist::SCUpgradeReq 22757 # Transaction distribution
346system.membus.trans_dist::UpgradeResp 15472 # Transaction distribution
347system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
348system.membus.trans_dist::ReadExReq 15580 # Transaction distribution
349system.membus.trans_dist::ReadExResp 8709 # Transaction distribution
350system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384390 # Packet count per connected master and slave (bytes)
351system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
352system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13404 # Packet count per connected master and slave (bytes)
353system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
354system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2098 # Packet count per connected master and slave (bytes)
355system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2043502 # Packet count per connected master and slave (bytes)
356system.membus.pkt_count_system.l2c.mem_side::total 4443432 # Packet count per connected master and slave (bytes)
357system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
358system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
359system.membus.pkt_count::total 35507496 # Packet count per connected master and slave (bytes)
360system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392696 # Cumulative packet size per connected master and slave (bytes)
361system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
362system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26808 # Cumulative packet size per connected master and slave (bytes)
363system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
364system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4196 # Cumulative packet size per connected master and slave (bytes)
365system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18456148 # Cumulative packet size per connected master and slave (bytes)
366system.membus.pkt_size_system.l2c.mem_side::total 20879924 # Cumulative packet size per connected master and slave (bytes)
367system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
368system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
369system.membus.pkt_size::total 145136180 # Cumulative packet size per connected master and slave (bytes)
370system.membus.snoops 70292 # Total snoops (count)
371system.membus.snoop_fanout::samples 326383 # Request fanout histogram
372system.membus.snoop_fanout::mean 1 # Request fanout histogram
373system.membus.snoop_fanout::stdev 0 # Request fanout histogram
374system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
375system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
376system.membus.snoop_fanout::1 326383 100.00% 100.00% # Request fanout histogram
377system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
378system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
379system.membus.snoop_fanout::min_value 1 # Request fanout histogram
380system.membus.snoop_fanout::max_value 1 # Request fanout histogram
381system.membus.snoop_fanout::total 326383 # Request fanout histogram
382system.membus.reqLayer0.occupancy 1567209495 # Layer occupancy (ticks)
383system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
384system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks)
385system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
386system.membus.reqLayer2.occupancy 11789999 # Layer occupancy (ticks)
387system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
388system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
389system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
390system.membus.reqLayer5.occupancy 2092500 # Layer occupancy (ticks)
391system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
392system.membus.reqLayer6.occupancy 18080219999 # Layer occupancy (ticks)
393system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
394system.membus.respLayer1.occupancy 4994463970 # Layer occupancy (ticks)
395system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
396system.membus.respLayer2.occupancy 38410223885 # Layer occupancy (ticks)
397system.membus.respLayer2.utilization 1.4 # Layer utilization (%)
398system.cpu_clk_domain.clock 500 # Clock period in ticks
399system.l2c.tags.replacements 91391 # number of replacements
400system.l2c.tags.tagsinuse 54779.294121 # Cycle average of tags in use
401system.l2c.tags.total_refs 364235 # Total number of references to valid blocks.
402system.l2c.tags.sampled_refs 156090 # Sample count of references to valid blocks.
403system.l2c.tags.avg_refs 2.333493 # Average number of references to valid blocks.
404system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
405system.l2c.tags.occ_blocks::writebacks 8096.170170 # Average occupied blocks per requestor
406system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.060665 # Average occupied blocks per requestor
407system.l2c.tags.occ_blocks::cpu0.itb.walker 1.035962 # Average occupied blocks per requestor
408system.l2c.tags.occ_blocks::cpu0.inst 869.411373 # Average occupied blocks per requestor
409system.l2c.tags.occ_blocks::cpu0.data 1869.125081 # Average occupied blocks per requestor
410system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29277.356218 # Average occupied blocks per requestor
411system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.888363 # Average occupied blocks per requestor
412system.l2c.tags.occ_blocks::cpu1.inst 410.348906 # Average occupied blocks per requestor
413system.l2c.tags.occ_blocks::cpu1.data 3214.362362 # Average occupied blocks per requestor
414system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11039.535021 # Average occupied blocks per requestor
415system.l2c.tags.occ_percent::writebacks 0.123538 # Average percentage of cache occupancy
416system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000001 # Average percentage of cache occupancy
417system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
418system.l2c.tags.occ_percent::cpu0.inst 0.013266 # Average percentage of cache occupancy
419system.l2c.tags.occ_percent::cpu0.data 0.028521 # Average percentage of cache occupancy
420system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.446737 # Average percentage of cache occupancy
421system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy
422system.l2c.tags.occ_percent::cpu1.inst 0.006261 # Average percentage of cache occupancy
423system.l2c.tags.occ_percent::cpu1.data 0.049047 # Average percentage of cache occupancy
424system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.168450 # Average percentage of cache occupancy
425system.l2c.tags.occ_percent::total 0.835866 # Average percentage of cache occupancy
426system.l2c.tags.occ_task_id_blocks::1022 51568 # Occupied blocks per task id
427system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
428system.l2c.tags.occ_task_id_blocks::1024 13123 # Occupied blocks per task id
429system.l2c.tags.age_task_id_blocks_1022::2 28 # Occupied blocks per task id
430system.l2c.tags.age_task_id_blocks_1022::3 4964 # Occupied blocks per task id
431system.l2c.tags.age_task_id_blocks_1022::4 46576 # Occupied blocks per task id
432system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
433system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
434system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
435system.l2c.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
436system.l2c.tags.age_task_id_blocks_1024::2 213 # Occupied blocks per task id
437system.l2c.tags.age_task_id_blocks_1024::3 1345 # Occupied blocks per task id
438system.l2c.tags.age_task_id_blocks_1024::4 11561 # Occupied blocks per task id
439system.l2c.tags.occ_task_id_percent::1022 0.786865 # Percentage of cache occupancy per task id
440system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id
441system.l2c.tags.occ_task_id_percent::1024 0.200241 # Percentage of cache occupancy per task id
442system.l2c.tags.tag_accesses 4855174 # Number of tag accesses
443system.l2c.tags.data_accesses 4855174 # Number of data accesses
444system.l2c.ReadReq_hits::cpu0.dtb.walker 111 # number of ReadReq hits
445system.l2c.ReadReq_hits::cpu0.itb.walker 56 # number of ReadReq hits
446system.l2c.ReadReq_hits::cpu0.inst 5971 # number of ReadReq hits
447system.l2c.ReadReq_hits::cpu0.data 15212 # number of ReadReq hits
448system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88244 # number of ReadReq hits
449system.l2c.ReadReq_hits::cpu1.dtb.walker 87 # number of ReadReq hits
450system.l2c.ReadReq_hits::cpu1.itb.walker 25 # number of ReadReq hits
451system.l2c.ReadReq_hits::cpu1.inst 4855 # number of ReadReq hits
452system.l2c.ReadReq_hits::cpu1.data 12536 # number of ReadReq hits
453system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47744 # number of ReadReq hits
454system.l2c.ReadReq_hits::total 174841 # number of ReadReq hits
455system.l2c.Writeback_hits::writebacks 208041 # number of Writeback hits
456system.l2c.Writeback_hits::total 208041 # number of Writeback hits
457system.l2c.UpgradeReq_hits::cpu0.data 3552 # number of UpgradeReq hits
458system.l2c.UpgradeReq_hits::cpu1.data 1697 # number of UpgradeReq hits
459system.l2c.UpgradeReq_hits::total 5249 # number of UpgradeReq hits
460system.l2c.SCUpgradeReq_hits::cpu0.data 114 # number of SCUpgradeReq hits
461system.l2c.SCUpgradeReq_hits::cpu1.data 201 # number of SCUpgradeReq hits
462system.l2c.SCUpgradeReq_hits::total 315 # number of SCUpgradeReq hits
463system.l2c.ReadExReq_hits::cpu0.data 2350 # number of ReadExReq hits
464system.l2c.ReadExReq_hits::cpu1.data 2153 # number of ReadExReq hits
465system.l2c.ReadExReq_hits::total 4503 # number of ReadExReq hits
466system.l2c.demand_hits::cpu0.dtb.walker 111 # number of demand (read+write) hits
467system.l2c.demand_hits::cpu0.itb.walker 56 # number of demand (read+write) hits
468system.l2c.demand_hits::cpu0.inst 5971 # number of demand (read+write) hits
469system.l2c.demand_hits::cpu0.data 17562 # number of demand (read+write) hits
470system.l2c.demand_hits::cpu0.l2cache.prefetcher 88244 # number of demand (read+write) hits
471system.l2c.demand_hits::cpu1.dtb.walker 87 # number of demand (read+write) hits
472system.l2c.demand_hits::cpu1.itb.walker 25 # number of demand (read+write) hits
473system.l2c.demand_hits::cpu1.inst 4855 # number of demand (read+write) hits
474system.l2c.demand_hits::cpu1.data 14689 # number of demand (read+write) hits
475system.l2c.demand_hits::cpu1.l2cache.prefetcher 47744 # number of demand (read+write) hits
476system.l2c.demand_hits::total 179344 # number of demand (read+write) hits
477system.l2c.overall_hits::cpu0.dtb.walker 111 # number of overall hits
478system.l2c.overall_hits::cpu0.itb.walker 56 # number of overall hits
479system.l2c.overall_hits::cpu0.inst 5971 # number of overall hits
480system.l2c.overall_hits::cpu0.data 17562 # number of overall hits
481system.l2c.overall_hits::cpu0.l2cache.prefetcher 88244 # number of overall hits
482system.l2c.overall_hits::cpu1.dtb.walker 87 # number of overall hits
483system.l2c.overall_hits::cpu1.itb.walker 25 # number of overall hits
484system.l2c.overall_hits::cpu1.inst 4855 # number of overall hits
485system.l2c.overall_hits::cpu1.data 14689 # number of overall hits
486system.l2c.overall_hits::cpu1.l2cache.prefetcher 47744 # number of overall hits
487system.l2c.overall_hits::total 179344 # number of overall hits
488system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses
489system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses
490system.l2c.ReadReq_misses::cpu0.inst 1474 # number of ReadReq misses
491system.l2c.ReadReq_misses::cpu0.data 3581 # number of ReadReq misses
492system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 104062 # number of ReadReq misses
493system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses
494system.l2c.ReadReq_misses::cpu1.inst 586 # number of ReadReq misses
495system.l2c.ReadReq_misses::cpu1.data 4041 # number of ReadReq misses
496system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 50971 # number of ReadReq misses
497system.l2c.ReadReq_misses::total 164723 # number of ReadReq misses
498system.l2c.UpgradeReq_misses::cpu0.data 7774 # number of UpgradeReq misses
499system.l2c.UpgradeReq_misses::cpu1.data 5401 # number of UpgradeReq misses
500system.l2c.UpgradeReq_misses::total 13175 # number of UpgradeReq misses
501system.l2c.SCUpgradeReq_misses::cpu0.data 1167 # number of SCUpgradeReq misses
502system.l2c.SCUpgradeReq_misses::cpu1.data 1038 # number of SCUpgradeReq misses
503system.l2c.SCUpgradeReq_misses::total 2205 # number of SCUpgradeReq misses
504system.l2c.ReadExReq_misses::cpu0.data 4506 # number of ReadExReq misses
505system.l2c.ReadExReq_misses::cpu1.data 4295 # number of ReadExReq misses
506system.l2c.ReadExReq_misses::total 8801 # number of ReadExReq misses
507system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses
508system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses
509system.l2c.demand_misses::cpu0.inst 1474 # number of demand (read+write) misses
510system.l2c.demand_misses::cpu0.data 8087 # number of demand (read+write) misses
511system.l2c.demand_misses::cpu0.l2cache.prefetcher 104062 # number of demand (read+write) misses
512system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses
513system.l2c.demand_misses::cpu1.inst 586 # number of demand (read+write) misses
514system.l2c.demand_misses::cpu1.data 8336 # number of demand (read+write) misses
515system.l2c.demand_misses::cpu1.l2cache.prefetcher 50971 # number of demand (read+write) misses
516system.l2c.demand_misses::total 173524 # number of demand (read+write) misses
517system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses
518system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses
519system.l2c.overall_misses::cpu0.inst 1474 # number of overall misses
520system.l2c.overall_misses::cpu0.data 8087 # number of overall misses
521system.l2c.overall_misses::cpu0.l2cache.prefetcher 104062 # number of overall misses
522system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses
523system.l2c.overall_misses::cpu1.inst 586 # number of overall misses
524system.l2c.overall_misses::cpu1.data 8336 # number of overall misses
525system.l2c.overall_misses::cpu1.l2cache.prefetcher 50971 # number of overall misses
526system.l2c.overall_misses::total 173524 # number of overall misses
527system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 107000 # number of ReadReq miss cycles
528system.l2c.ReadReq_miss_latency::cpu0.itb.walker 298500 # number of ReadReq miss cycles
529system.l2c.ReadReq_miss_latency::cpu0.inst 119004500 # number of ReadReq miss cycles
530system.l2c.ReadReq_miss_latency::cpu0.data 272579750 # number of ReadReq miss cycles
531system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 9018021941 # number of ReadReq miss cycles
532system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 164250 # number of ReadReq miss cycles
533system.l2c.ReadReq_miss_latency::cpu1.inst 50120250 # number of ReadReq miss cycles
534system.l2c.ReadReq_miss_latency::cpu1.data 314939500 # number of ReadReq miss cycles
535system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 6107091681 # number of ReadReq miss cycles
536system.l2c.ReadReq_miss_latency::total 15882327372 # number of ReadReq miss cycles
537system.l2c.UpgradeReq_miss_latency::cpu0.data 13917901 # number of UpgradeReq miss cycles
538system.l2c.UpgradeReq_miss_latency::cpu1.data 3379857 # number of UpgradeReq miss cycles
539system.l2c.UpgradeReq_miss_latency::total 17297758 # number of UpgradeReq miss cycles
540system.l2c.SCUpgradeReq_miss_latency::cpu0.data 704472 # number of SCUpgradeReq miss cycles
541system.l2c.SCUpgradeReq_miss_latency::cpu1.data 4360812 # number of SCUpgradeReq miss cycles
542system.l2c.SCUpgradeReq_miss_latency::total 5065284 # number of SCUpgradeReq miss cycles
543system.l2c.ReadExReq_miss_latency::cpu0.data 330076436 # number of ReadExReq miss cycles
544system.l2c.ReadExReq_miss_latency::cpu1.data 308773222 # number of ReadExReq miss cycles
545system.l2c.ReadExReq_miss_latency::total 638849658 # number of ReadExReq miss cycles
546system.l2c.demand_miss_latency::cpu0.dtb.walker 107000 # number of demand (read+write) miss cycles
547system.l2c.demand_miss_latency::cpu0.itb.walker 298500 # number of demand (read+write) miss cycles
548system.l2c.demand_miss_latency::cpu0.inst 119004500 # number of demand (read+write) miss cycles
549system.l2c.demand_miss_latency::cpu0.data 602656186 # number of demand (read+write) miss cycles
550system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 9018021941 # number of demand (read+write) miss cycles
551system.l2c.demand_miss_latency::cpu1.dtb.walker 164250 # number of demand (read+write) miss cycles
552system.l2c.demand_miss_latency::cpu1.inst 50120250 # number of demand (read+write) miss cycles
553system.l2c.demand_miss_latency::cpu1.data 623712722 # number of demand (read+write) miss cycles
554system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 6107091681 # number of demand (read+write) miss cycles
555system.l2c.demand_miss_latency::total 16521177030 # number of demand (read+write) miss cycles
556system.l2c.overall_miss_latency::cpu0.dtb.walker 107000 # number of overall miss cycles
557system.l2c.overall_miss_latency::cpu0.itb.walker 298500 # number of overall miss cycles
558system.l2c.overall_miss_latency::cpu0.inst 119004500 # number of overall miss cycles
559system.l2c.overall_miss_latency::cpu0.data 602656186 # number of overall miss cycles
560system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 9018021941 # number of overall miss cycles
561system.l2c.overall_miss_latency::cpu1.dtb.walker 164250 # number of overall miss cycles
562system.l2c.overall_miss_latency::cpu1.inst 50120250 # number of overall miss cycles
563system.l2c.overall_miss_latency::cpu1.data 623712722 # number of overall miss cycles
564system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 6107091681 # number of overall miss cycles
565system.l2c.overall_miss_latency::total 16521177030 # number of overall miss cycles
566system.l2c.ReadReq_accesses::cpu0.dtb.walker 113 # number of ReadReq accesses(hits+misses)
567system.l2c.ReadReq_accesses::cpu0.itb.walker 60 # number of ReadReq accesses(hits+misses)
568system.l2c.ReadReq_accesses::cpu0.inst 7445 # number of ReadReq accesses(hits+misses)
569system.l2c.ReadReq_accesses::cpu0.data 18793 # number of ReadReq accesses(hits+misses)
570system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 192306 # number of ReadReq accesses(hits+misses)
571system.l2c.ReadReq_accesses::cpu1.dtb.walker 89 # number of ReadReq accesses(hits+misses)
572system.l2c.ReadReq_accesses::cpu1.itb.walker 25 # number of ReadReq accesses(hits+misses)
573system.l2c.ReadReq_accesses::cpu1.inst 5441 # number of ReadReq accesses(hits+misses)
574system.l2c.ReadReq_accesses::cpu1.data 16577 # number of ReadReq accesses(hits+misses)
575system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 98715 # number of ReadReq accesses(hits+misses)
576system.l2c.ReadReq_accesses::total 339564 # number of ReadReq accesses(hits+misses)
577system.l2c.Writeback_accesses::writebacks 208041 # number of Writeback accesses(hits+misses)
578system.l2c.Writeback_accesses::total 208041 # number of Writeback accesses(hits+misses)
579system.l2c.UpgradeReq_accesses::cpu0.data 11326 # number of UpgradeReq accesses(hits+misses)
580system.l2c.UpgradeReq_accesses::cpu1.data 7098 # number of UpgradeReq accesses(hits+misses)
581system.l2c.UpgradeReq_accesses::total 18424 # number of UpgradeReq accesses(hits+misses)
582system.l2c.SCUpgradeReq_accesses::cpu0.data 1281 # number of SCUpgradeReq accesses(hits+misses)
583system.l2c.SCUpgradeReq_accesses::cpu1.data 1239 # number of SCUpgradeReq accesses(hits+misses)
584system.l2c.SCUpgradeReq_accesses::total 2520 # number of SCUpgradeReq accesses(hits+misses)
585system.l2c.ReadExReq_accesses::cpu0.data 6856 # number of ReadExReq accesses(hits+misses)
586system.l2c.ReadExReq_accesses::cpu1.data 6448 # number of ReadExReq accesses(hits+misses)
587system.l2c.ReadExReq_accesses::total 13304 # number of ReadExReq accesses(hits+misses)
588system.l2c.demand_accesses::cpu0.dtb.walker 113 # number of demand (read+write) accesses
589system.l2c.demand_accesses::cpu0.itb.walker 60 # number of demand (read+write) accesses
590system.l2c.demand_accesses::cpu0.inst 7445 # number of demand (read+write) accesses
591system.l2c.demand_accesses::cpu0.data 25649 # number of demand (read+write) accesses
592system.l2c.demand_accesses::cpu0.l2cache.prefetcher 192306 # number of demand (read+write) accesses
593system.l2c.demand_accesses::cpu1.dtb.walker 89 # number of demand (read+write) accesses
594system.l2c.demand_accesses::cpu1.itb.walker 25 # number of demand (read+write) accesses
595system.l2c.demand_accesses::cpu1.inst 5441 # number of demand (read+write) accesses
596system.l2c.demand_accesses::cpu1.data 23025 # number of demand (read+write) accesses
597system.l2c.demand_accesses::cpu1.l2cache.prefetcher 98715 # number of demand (read+write) accesses
598system.l2c.demand_accesses::total 352868 # number of demand (read+write) accesses
599system.l2c.overall_accesses::cpu0.dtb.walker 113 # number of overall (read+write) accesses
600system.l2c.overall_accesses::cpu0.itb.walker 60 # number of overall (read+write) accesses
601system.l2c.overall_accesses::cpu0.inst 7445 # number of overall (read+write) accesses
602system.l2c.overall_accesses::cpu0.data 25649 # number of overall (read+write) accesses
603system.l2c.overall_accesses::cpu0.l2cache.prefetcher 192306 # number of overall (read+write) accesses
604system.l2c.overall_accesses::cpu1.dtb.walker 89 # number of overall (read+write) accesses
605system.l2c.overall_accesses::cpu1.itb.walker 25 # number of overall (read+write) accesses
606system.l2c.overall_accesses::cpu1.inst 5441 # number of overall (read+write) accesses
607system.l2c.overall_accesses::cpu1.data 23025 # number of overall (read+write) accesses
608system.l2c.overall_accesses::cpu1.l2cache.prefetcher 98715 # number of overall (read+write) accesses
609system.l2c.overall_accesses::total 352868 # number of overall (read+write) accesses
610system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.017699 # miss rate for ReadReq accesses
611system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.066667 # miss rate for ReadReq accesses
612system.l2c.ReadReq_miss_rate::cpu0.inst 0.197985 # miss rate for ReadReq accesses
613system.l2c.ReadReq_miss_rate::cpu0.data 0.190550 # miss rate for ReadReq accesses
614system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.541127 # miss rate for ReadReq accesses
615system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.022472 # miss rate for ReadReq accesses
616system.l2c.ReadReq_miss_rate::cpu1.inst 0.107701 # miss rate for ReadReq accesses
617system.l2c.ReadReq_miss_rate::cpu1.data 0.243771 # miss rate for ReadReq accesses
618system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.516345 # miss rate for ReadReq accesses
619system.l2c.ReadReq_miss_rate::total 0.485101 # miss rate for ReadReq accesses
620system.l2c.UpgradeReq_miss_rate::cpu0.data 0.686385 # miss rate for UpgradeReq accesses
621system.l2c.UpgradeReq_miss_rate::cpu1.data 0.760919 # miss rate for UpgradeReq accesses
622system.l2c.UpgradeReq_miss_rate::total 0.715100 # miss rate for UpgradeReq accesses
623system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.911007 # miss rate for SCUpgradeReq accesses
624system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.837772 # miss rate for SCUpgradeReq accesses
625system.l2c.SCUpgradeReq_miss_rate::total 0.875000 # miss rate for SCUpgradeReq accesses
626system.l2c.ReadExReq_miss_rate::cpu0.data 0.657235 # miss rate for ReadExReq accesses
627system.l2c.ReadExReq_miss_rate::cpu1.data 0.666098 # miss rate for ReadExReq accesses
628system.l2c.ReadExReq_miss_rate::total 0.661530 # miss rate for ReadExReq accesses
629system.l2c.demand_miss_rate::cpu0.dtb.walker 0.017699 # miss rate for demand accesses
630system.l2c.demand_miss_rate::cpu0.itb.walker 0.066667 # miss rate for demand accesses
631system.l2c.demand_miss_rate::cpu0.inst 0.197985 # miss rate for demand accesses
632system.l2c.demand_miss_rate::cpu0.data 0.315295 # miss rate for demand accesses
633system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.541127 # miss rate for demand accesses
634system.l2c.demand_miss_rate::cpu1.dtb.walker 0.022472 # miss rate for demand accesses
635system.l2c.demand_miss_rate::cpu1.inst 0.107701 # miss rate for demand accesses
636system.l2c.demand_miss_rate::cpu1.data 0.362041 # miss rate for demand accesses
637system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.516345 # miss rate for demand accesses
638system.l2c.demand_miss_rate::total 0.491753 # miss rate for demand accesses
639system.l2c.overall_miss_rate::cpu0.dtb.walker 0.017699 # miss rate for overall accesses
640system.l2c.overall_miss_rate::cpu0.itb.walker 0.066667 # miss rate for overall accesses
641system.l2c.overall_miss_rate::cpu0.inst 0.197985 # miss rate for overall accesses
642system.l2c.overall_miss_rate::cpu0.data 0.315295 # miss rate for overall accesses
643system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.541127 # miss rate for overall accesses
644system.l2c.overall_miss_rate::cpu1.dtb.walker 0.022472 # miss rate for overall accesses
645system.l2c.overall_miss_rate::cpu1.inst 0.107701 # miss rate for overall accesses
646system.l2c.overall_miss_rate::cpu1.data 0.362041 # miss rate for overall accesses
647system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.516345 # miss rate for overall accesses
648system.l2c.overall_miss_rate::total 0.491753 # miss rate for overall accesses
649system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 53500 # average ReadReq miss latency
650system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74625 # average ReadReq miss latency
651system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80735.753053 # average ReadReq miss latency
652system.l2c.ReadReq_avg_miss_latency::cpu0.data 76118.332868 # average ReadReq miss latency
653system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689 # average ReadReq miss latency
654system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82125 # average ReadReq miss latency
655system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85529.436860 # average ReadReq miss latency
656system.l2c.ReadReq_avg_miss_latency::cpu1.data 77936.030685 # average ReadReq miss latency
657system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819 # average ReadReq miss latency
658system.l2c.ReadReq_avg_miss_latency::total 96418.395561 # average ReadReq miss latency
659system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1790.313995 # average UpgradeReq miss latency
660system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 625.783559 # average UpgradeReq miss latency
661system.l2c.UpgradeReq_avg_miss_latency::total 1312.922808 # average UpgradeReq miss latency
662system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 603.660668 # average SCUpgradeReq miss latency
663system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4201.167630 # average SCUpgradeReq miss latency
664system.l2c.SCUpgradeReq_avg_miss_latency::total 2297.180952 # average SCUpgradeReq miss latency
665system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73252.648913 # average ReadExReq miss latency
666system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71891.320605 # average ReadExReq miss latency
667system.l2c.ReadExReq_avg_miss_latency::total 72588.303375 # average ReadExReq miss latency
668system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 53500 # average overall miss latency
669system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74625 # average overall miss latency
670system.l2c.demand_avg_miss_latency::cpu0.inst 80735.753053 # average overall miss latency
671system.l2c.demand_avg_miss_latency::cpu0.data 74521.600841 # average overall miss latency
672system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689 # average overall miss latency
673system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82125 # average overall miss latency
674system.l2c.demand_avg_miss_latency::cpu1.inst 85529.436860 # average overall miss latency
675system.l2c.demand_avg_miss_latency::cpu1.data 74821.583733 # average overall miss latency
676system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819 # average overall miss latency
677system.l2c.demand_avg_miss_latency::total 95209.752138 # average overall miss latency
678system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 53500 # average overall miss latency
679system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74625 # average overall miss latency
680system.l2c.overall_avg_miss_latency::cpu0.inst 80735.753053 # average overall miss latency
681system.l2c.overall_avg_miss_latency::cpu0.data 74521.600841 # average overall miss latency
682system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 86660.086689 # average overall miss latency
683system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82125 # average overall miss latency
684system.l2c.overall_avg_miss_latency::cpu1.inst 85529.436860 # average overall miss latency
685system.l2c.overall_avg_miss_latency::cpu1.data 74821.583733 # average overall miss latency
686system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 119815.025819 # average overall miss latency
687system.l2c.overall_avg_miss_latency::total 95209.752138 # average overall miss latency
688system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
689system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
690system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
691system.l2c.blocked::no_targets 0 # number of cycles access was blocked
692system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
693system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
694system.l2c.fast_writes 0 # number of fast writes performed
695system.l2c.cache_copies 0 # number of cache copies performed
696system.l2c.writebacks::writebacks 67188 # number of writebacks
697system.l2c.writebacks::total 67188 # number of writebacks
698system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
699system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
700system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
701system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
702system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
703system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
704system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2 # number of ReadReq MSHR misses
705system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses
706system.l2c.ReadReq_mshr_misses::cpu0.inst 1474 # number of ReadReq MSHR misses
707system.l2c.ReadReq_mshr_misses::cpu0.data 3581 # number of ReadReq MSHR misses
708system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 104062 # number of ReadReq MSHR misses
709system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2 # number of ReadReq MSHR misses
710system.l2c.ReadReq_mshr_misses::cpu1.inst 585 # number of ReadReq MSHR misses
711system.l2c.ReadReq_mshr_misses::cpu1.data 4041 # number of ReadReq MSHR misses
712system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 50971 # number of ReadReq MSHR misses
713system.l2c.ReadReq_mshr_misses::total 164722 # number of ReadReq MSHR misses
714system.l2c.UpgradeReq_mshr_misses::cpu0.data 7774 # number of UpgradeReq MSHR misses
715system.l2c.UpgradeReq_mshr_misses::cpu1.data 5401 # number of UpgradeReq MSHR misses
716system.l2c.UpgradeReq_mshr_misses::total 13175 # number of UpgradeReq MSHR misses
717system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1167 # number of SCUpgradeReq MSHR misses
718system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1038 # number of SCUpgradeReq MSHR misses
719system.l2c.SCUpgradeReq_mshr_misses::total 2205 # number of SCUpgradeReq MSHR misses
720system.l2c.ReadExReq_mshr_misses::cpu0.data 4506 # number of ReadExReq MSHR misses
721system.l2c.ReadExReq_mshr_misses::cpu1.data 4295 # number of ReadExReq MSHR misses
722system.l2c.ReadExReq_mshr_misses::total 8801 # number of ReadExReq MSHR misses
723system.l2c.demand_mshr_misses::cpu0.dtb.walker 2 # number of demand (read+write) MSHR misses
724system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses
725system.l2c.demand_mshr_misses::cpu0.inst 1474 # number of demand (read+write) MSHR misses
726system.l2c.demand_mshr_misses::cpu0.data 8087 # number of demand (read+write) MSHR misses
727system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 104062 # number of demand (read+write) MSHR misses
728system.l2c.demand_mshr_misses::cpu1.dtb.walker 2 # number of demand (read+write) MSHR misses
729system.l2c.demand_mshr_misses::cpu1.inst 585 # number of demand (read+write) MSHR misses
730system.l2c.demand_mshr_misses::cpu1.data 8336 # number of demand (read+write) MSHR misses
731system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 50971 # number of demand (read+write) MSHR misses
732system.l2c.demand_mshr_misses::total 173523 # number of demand (read+write) MSHR misses
733system.l2c.overall_mshr_misses::cpu0.dtb.walker 2 # number of overall MSHR misses
734system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses
735system.l2c.overall_mshr_misses::cpu0.inst 1474 # number of overall MSHR misses
736system.l2c.overall_mshr_misses::cpu0.data 8087 # number of overall MSHR misses
737system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 104062 # number of overall MSHR misses
738system.l2c.overall_mshr_misses::cpu1.dtb.walker 2 # number of overall MSHR misses
739system.l2c.overall_mshr_misses::cpu1.inst 585 # number of overall MSHR misses
740system.l2c.overall_mshr_misses::cpu1.data 8336 # number of overall MSHR misses
741system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 50971 # number of overall MSHR misses
742system.l2c.overall_mshr_misses::total 173523 # number of overall MSHR misses
743system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 82500 # number of ReadReq MSHR miss cycles
744system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 250000 # number of ReadReq MSHR miss cycles
745system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 100663500 # number of ReadReq MSHR miss cycles
746system.l2c.ReadReq_mshr_miss_latency::cpu0.data 227794750 # number of ReadReq MSHR miss cycles
747system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 7718948941 # number of ReadReq MSHR miss cycles
748system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 138750 # number of ReadReq MSHR miss cycles
749system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 42844000 # number of ReadReq MSHR miss cycles
750system.l2c.ReadReq_mshr_miss_latency::cpu1.data 264712000 # number of ReadReq MSHR miss cycles
751system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 5479054183 # number of ReadReq MSHR miss cycles
752system.l2c.ReadReq_mshr_miss_latency::total 13834488624 # number of ReadReq MSHR miss cycles
753system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 78078748 # number of UpgradeReq MSHR miss cycles
754system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 54145386 # number of UpgradeReq MSHR miss cycles
755system.l2c.UpgradeReq_mshr_miss_latency::total 132224134 # number of UpgradeReq MSHR miss cycles
756system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 11801161 # number of SCUpgradeReq MSHR miss cycles
757system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 10401535 # number of SCUpgradeReq MSHR miss cycles
758system.l2c.SCUpgradeReq_mshr_miss_latency::total 22202696 # number of SCUpgradeReq MSHR miss cycles
759system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 273742064 # number of ReadExReq MSHR miss cycles
760system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 254569278 # number of ReadExReq MSHR miss cycles
761system.l2c.ReadExReq_mshr_miss_latency::total 528311342 # number of ReadExReq MSHR miss cycles
762system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 82500 # number of demand (read+write) MSHR miss cycles
763system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 250000 # number of demand (read+write) MSHR miss cycles
764system.l2c.demand_mshr_miss_latency::cpu0.inst 100663500 # number of demand (read+write) MSHR miss cycles
765system.l2c.demand_mshr_miss_latency::cpu0.data 501536814 # number of demand (read+write) MSHR miss cycles
766system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 7718948941 # number of demand (read+write) MSHR miss cycles
767system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 138750 # number of demand (read+write) MSHR miss cycles
768system.l2c.demand_mshr_miss_latency::cpu1.inst 42844000 # number of demand (read+write) MSHR miss cycles
769system.l2c.demand_mshr_miss_latency::cpu1.data 519281278 # number of demand (read+write) MSHR miss cycles
770system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 5479054183 # number of demand (read+write) MSHR miss cycles
771system.l2c.demand_mshr_miss_latency::total 14362799966 # number of demand (read+write) MSHR miss cycles
772system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 82500 # number of overall MSHR miss cycles
773system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 250000 # number of overall MSHR miss cycles
774system.l2c.overall_mshr_miss_latency::cpu0.inst 100663500 # number of overall MSHR miss cycles
775system.l2c.overall_mshr_miss_latency::cpu0.data 501536814 # number of overall MSHR miss cycles
776system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 7718948941 # number of overall MSHR miss cycles
777system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 138750 # number of overall MSHR miss cycles
778system.l2c.overall_mshr_miss_latency::cpu1.inst 42844000 # number of overall MSHR miss cycles
779system.l2c.overall_mshr_miss_latency::cpu1.data 519281278 # number of overall MSHR miss cycles
780system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 5479054183 # number of overall MSHR miss cycles
781system.l2c.overall_mshr_miss_latency::total 14362799966 # number of overall MSHR miss cycles
782system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 352521750 # number of ReadReq MSHR uncacheable cycles
783system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 156454617998 # number of ReadReq MSHR uncacheable cycles
784system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5602750 # number of ReadReq MSHR uncacheable cycles
785system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 10840620247 # number of ReadReq MSHR uncacheable cycles
786system.l2c.ReadReq_mshr_uncacheable_latency::total 167653362745 # number of ReadReq MSHR uncacheable cycles
787system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1361015000 # number of WriteReq MSHR uncacheable cycles
788system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 15491155851 # number of WriteReq MSHR uncacheable cycles
789system.l2c.WriteReq_mshr_uncacheable_latency::total 16852170851 # number of WriteReq MSHR uncacheable cycles
790system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 352521750 # number of overall MSHR uncacheable cycles
791system.l2c.overall_mshr_uncacheable_latency::cpu0.data 157815632998 # number of overall MSHR uncacheable cycles
792system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5602750 # number of overall MSHR uncacheable cycles
793system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26331776098 # number of overall MSHR uncacheable cycles
794system.l2c.overall_mshr_uncacheable_latency::total 184505533596 # number of overall MSHR uncacheable cycles
795system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017699 # mshr miss rate for ReadReq accesses
796system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066667 # mshr miss rate for ReadReq accesses
797system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for ReadReq accesses
798system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.190550 # mshr miss rate for ReadReq accesses
799system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for ReadReq accesses
800system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for ReadReq accesses
801system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for ReadReq accesses
802system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.243771 # mshr miss rate for ReadReq accesses
803system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for ReadReq accesses
804system.l2c.ReadReq_mshr_miss_rate::total 0.485099 # mshr miss rate for ReadReq accesses
805system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.686385 # mshr miss rate for UpgradeReq accesses
806system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760919 # mshr miss rate for UpgradeReq accesses
807system.l2c.UpgradeReq_mshr_miss_rate::total 0.715100 # mshr miss rate for UpgradeReq accesses
808system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911007 # mshr miss rate for SCUpgradeReq accesses
809system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.837772 # mshr miss rate for SCUpgradeReq accesses
810system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.875000 # mshr miss rate for SCUpgradeReq accesses
811system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.657235 # mshr miss rate for ReadExReq accesses
812system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.666098 # mshr miss rate for ReadExReq accesses
813system.l2c.ReadExReq_mshr_miss_rate::total 0.661530 # mshr miss rate for ReadExReq accesses
814system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.017699 # mshr miss rate for demand accesses
815system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.066667 # mshr miss rate for demand accesses
816system.l2c.demand_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for demand accesses
817system.l2c.demand_mshr_miss_rate::cpu0.data 0.315295 # mshr miss rate for demand accesses
818system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for demand accesses
819system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for demand accesses
820system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for demand accesses
821system.l2c.demand_mshr_miss_rate::cpu1.data 0.362041 # mshr miss rate for demand accesses
822system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for demand accesses
823system.l2c.demand_mshr_miss_rate::total 0.491750 # mshr miss rate for demand accesses
824system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.017699 # mshr miss rate for overall accesses
825system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.066667 # mshr miss rate for overall accesses
826system.l2c.overall_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for overall accesses
827system.l2c.overall_mshr_miss_rate::cpu0.data 0.315295 # mshr miss rate for overall accesses
828system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for overall accesses
829system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for overall accesses
830system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for overall accesses
831system.l2c.overall_mshr_miss_rate::cpu1.data 0.362041 # mshr miss rate for overall accesses
832system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for overall accesses
833system.l2c.overall_mshr_miss_rate::total 0.491750 # mshr miss rate for overall accesses
834system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average ReadReq mshr miss latency
835system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
836system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average ReadReq mshr miss latency
837system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63612.049707 # average ReadReq mshr miss latency
838system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average ReadReq mshr miss latency
839system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average ReadReq mshr miss latency
840system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average ReadReq mshr miss latency
841system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65506.557783 # average ReadReq mshr miss latency
842system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average ReadReq mshr miss latency
843system.l2c.ReadReq_avg_mshr_miss_latency::total 83986.890786 # average ReadReq mshr miss latency
844system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10043.574479 # average UpgradeReq mshr miss latency
845system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.066839 # average UpgradeReq mshr miss latency
846system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.987400 # average UpgradeReq mshr miss latency
847system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10112.391602 # average SCUpgradeReq mshr miss latency
848system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.746628 # average SCUpgradeReq mshr miss latency
849system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.249887 # average SCUpgradeReq mshr miss latency
850system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60750.569019 # average ReadExReq mshr miss latency
851system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59271.077532 # average ReadExReq mshr miss latency
852system.l2c.ReadExReq_avg_mshr_miss_latency::total 60028.558346 # average ReadExReq mshr miss latency
853system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency
854system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
855system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency
856system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency
857system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency
858system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency
859system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency
860system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency
861system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency
862system.l2c.demand_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency
863system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency
864system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
865system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency
866system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency
867system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency
868system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency
869system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency
870system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency
871system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency
872system.l2c.overall_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency
873system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
874system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
875system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
876system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
877system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
878system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
879system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
880system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
881system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
882system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
883system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
884system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
885system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
886system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
887system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
888system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
889system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
890system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
891system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
892system.cf0.dma_write_txs 0 # Number of DMA write transactions.
893system.toL2Bus.trans_dist::ReadReq 1633013 # Transaction distribution
894system.toL2Bus.trans_dist::ReadResp 1633009 # Transaction distribution
895system.toL2Bus.trans_dist::WriteReq 769090 # Transaction distribution
896system.toL2Bus.trans_dist::WriteResp 769090 # Transaction distribution
897system.toL2Bus.trans_dist::Writeback 208041 # Transaction distribution
898system.toL2Bus.trans_dist::UpgradeReq 61292 # Transaction distribution
899system.toL2Bus.trans_dist::SCUpgradeReq 23072 # Transaction distribution
900system.toL2Bus.trans_dist::UpgradeResp 84364 # Transaction distribution
901system.toL2Bus.trans_dist::SCUpgradeFailReq 39 # Transaction distribution
902system.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution
903system.toL2Bus.trans_dist::ReadExReq 23321 # Transaction distribution
904system.toL2Bus.trans_dist::ReadExResp 23321 # Transaction distribution
905system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2956029 # Packet count per connected master and slave (bytes)
906system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2099720 # Packet count per connected master and slave (bytes)
907system.toL2Bus.pkt_count::total 5055749 # Packet count per connected master and slave (bytes)
908system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 25795270 # Cumulative packet size per connected master and slave (bytes)
909system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15582958 # Cumulative packet size per connected master and slave (bytes)
910system.toL2Bus.pkt_size::total 41378228 # Cumulative packet size per connected master and slave (bytes)
911system.toL2Bus.snoops 171942 # Total snoops (count)
912system.toL2Bus.snoop_fanout::samples 753795 # Request fanout histogram
913system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
914system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
915system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
916system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
917system.toL2Bus.snoop_fanout::1 753795 100.00% 100.00% # Request fanout histogram
918system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
919system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
920system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
921system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
922system.toL2Bus.snoop_fanout::total 753795 # Request fanout histogram
923system.toL2Bus.reqLayer0.occupancy 2576673570 # Layer occupancy (ticks)
924system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
925system.toL2Bus.respLayer0.occupancy 2390227339 # Layer occupancy (ticks)
926system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
927system.toL2Bus.respLayer1.occupancy 1329617427 # Layer occupancy (ticks)
928system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
929system.iobus.trans_dist::ReadReq 16716140 # Transaction distribution
930system.iobus.trans_dist::ReadResp 16716140 # Transaction distribution
931system.iobus.trans_dist::WriteReq 8087 # Transaction distribution
932system.iobus.trans_dist::WriteResp 8087 # Transaction distribution
933system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30962 # Packet count per connected master and slave (bytes)
934system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8820 # Packet count per connected master and slave (bytes)
935system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
936system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes)
937system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
938system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
939system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
940system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
941system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
942system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
943system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
944system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
945system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
946system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
947system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
948system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
949system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
950system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
951system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
952system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
953system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
954system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
955system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
956system.iobus.pkt_count_system.bridge.master::total 2384390 # Packet count per connected master and slave (bytes)
957system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
958system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
959system.iobus.pkt_count::total 33448454 # Packet count per connected master and slave (bytes)
960system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40731 # Cumulative packet size per connected master and slave (bytes)
961system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17640 # Cumulative packet size per connected master and slave (bytes)
962system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
963system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes)
964system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
965system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
966system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
967system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
968system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
969system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
970system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
971system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
972system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
973system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
974system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
975system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
976system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
977system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
978system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
979system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
980system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
981system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
982system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
983system.iobus.pkt_size_system.bridge.master::total 2392696 # Cumulative packet size per connected master and slave (bytes)
984system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
985system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
986system.iobus.pkt_size::total 126648952 # Cumulative packet size per connected master and slave (bytes)
987system.iobus.reqLayer0.occupancy 21726000 # Layer occupancy (ticks)
988system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
989system.iobus.reqLayer1.occupancy 4416000 # Layer occupancy (ticks)
990system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
991system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
992system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
993system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks)
994system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
995system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
996system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
997system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
998system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
999system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
1000system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
1001system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
1002system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
1003system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
1004system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
1005system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
1006system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
1007system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
1008system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
1009system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
1010system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
1011system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
1012system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
1013system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
1014system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
1015system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
1016system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
1017system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
1018system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
1019system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
1020system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
1021system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
1022system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
1023system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
1024system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
1025system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
1026system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
1027system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
1028system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
1029system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
1030system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
1031system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
1032system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
1033system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks)
1034system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%)
1035system.iobus.respLayer0.occupancy 2376303000 # Layer occupancy (ticks)
1036system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
1037system.iobus.respLayer1.occupancy 39178496115 # Layer occupancy (ticks)
1038system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
1039system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1040system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1041system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1042system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1043system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1044system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1045system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1046system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

1054system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1055system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1056system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1057system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1058system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1059system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1060system.cpu0.dtb.inst_hits 0 # ITB inst hits
1061system.cpu0.dtb.inst_misses 0 # ITB inst misses
1062system.cpu0.dtb.read_hits 7131006 # DTB read hits
1063system.cpu0.dtb.read_misses 3644 # DTB read misses
1064system.cpu0.dtb.write_hits 6127729 # DTB write hits
1065system.cpu0.dtb.write_misses 663 # DTB write misses
1066system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1067system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1068system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1069system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1070system.cpu0.dtb.flush_entries 1893 # Number of entries that have been flushed from TLB
1071system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1072system.cpu0.dtb.prefetch_faults 116 # Number of TLB faults due to prefetch
1073system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1074system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
1075system.cpu0.dtb.read_accesses 7134650 # DTB read accesses
1076system.cpu0.dtb.write_accesses 6128392 # DTB write accesses
1077system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
1078system.cpu0.dtb.hits 13258735 # DTB hits
1079system.cpu0.dtb.misses 4307 # DTB misses
1080system.cpu0.dtb.accesses 13263042 # DTB accesses
1081system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1082system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1083system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1084system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1085system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1086system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1087system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1088system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1094system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1095system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1096system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1097system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1098system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1099system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1100system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1101system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1102system.cpu0.itb.inst_hits 31182741 # ITB inst hits
1103system.cpu0.itb.inst_misses 2176 # ITB inst misses
1104system.cpu0.itb.read_hits 0 # DTB read hits
1105system.cpu0.itb.read_misses 0 # DTB read misses
1106system.cpu0.itb.write_hits 0 # DTB write hits
1107system.cpu0.itb.write_misses 0 # DTB write misses
1108system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
1109system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1110system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1111system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1112system.cpu0.itb.flush_entries 1281 # Number of entries that have been flushed from TLB
1113system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1114system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1115system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1116system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1117system.cpu0.itb.read_accesses 0 # DTB read accesses
1118system.cpu0.itb.write_accesses 0 # DTB write accesses
1119system.cpu0.itb.inst_accesses 31184917 # ITB inst accesses
1120system.cpu0.itb.hits 31182741 # DTB hits
1121system.cpu0.itb.misses 2176 # DTB misses
1122system.cpu0.itb.accesses 31184917 # DTB accesses
1123system.cpu0.numCycles 5349463018 # number of cpu cycles simulated
1124system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1125system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1126system.cpu0.committedInsts 30507218 # Number of instructions committed
1127system.cpu0.committedOps 36803230 # Number of ops (including micro ops) committed
1128system.cpu0.num_int_alu_accesses 32859018 # Number of integer alu accesses
1129system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses
1130system.cpu0.num_func_calls 1290775 # number of times a function call or return occured
1131system.cpu0.num_conditional_control_insts 3957686 # number of instructions that are conditional controls
1132system.cpu0.num_int_insts 32859018 # number of integer instructions
1133system.cpu0.num_fp_insts 5449 # number of float instructions
1134system.cpu0.num_int_register_reads 60131579 # number of times the integer registers were read
1135system.cpu0.num_int_register_writes 21902535 # number of times the integer registers were written
1136system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read
1137system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written
1138system.cpu0.num_cc_register_reads 133610661 # number of times the CC registers were read
1139system.cpu0.num_cc_register_writes 14490121 # number of times the CC registers were written
1140system.cpu0.num_mem_refs 13795466 # number of memory refs
1141system.cpu0.num_load_insts 7343231 # Number of load instructions
1142system.cpu0.num_store_insts 6452235 # Number of store instructions
1143system.cpu0.num_idle_cycles 4898257252.279955 # Number of idle cycles
1144system.cpu0.num_busy_cycles 451205765.720045 # Number of busy cycles
1145system.cpu0.not_idle_fraction 0.084346 # Percentage of non-idle cycles
1146system.cpu0.idle_fraction 0.915654 # Percentage of idle cycles
1147system.cpu0.Branches 5660514 # Number of branches fetched
1148system.cpu0.op_class::No_OpClass 16321 0.04% 0.04% # Class of executed instruction
1149system.cpu0.op_class::IntAlu 23591543 62.99% 63.03% # Class of executed instruction
1150system.cpu0.op_class::IntMult 47189 0.13% 63.16% # Class of executed instruction
1151system.cpu0.op_class::IntDiv 0 0.00% 63.16% # Class of executed instruction
1152system.cpu0.op_class::FloatAdd 0 0.00% 63.16% # Class of executed instruction
1153system.cpu0.op_class::FloatCmp 0 0.00% 63.16% # Class of executed instruction
1154system.cpu0.op_class::FloatCvt 0 0.00% 63.16% # Class of executed instruction
1155system.cpu0.op_class::FloatMult 0 0.00% 63.16% # Class of executed instruction
1156system.cpu0.op_class::FloatDiv 0 0.00% 63.16% # Class of executed instruction
1157system.cpu0.op_class::FloatSqrt 0 0.00% 63.16% # Class of executed instruction
1158system.cpu0.op_class::SimdAdd 0 0.00% 63.16% # Class of executed instruction
1159system.cpu0.op_class::SimdAddAcc 0 0.00% 63.16% # Class of executed instruction
1160system.cpu0.op_class::SimdAlu 0 0.00% 63.16% # Class of executed instruction
1161system.cpu0.op_class::SimdCmp 0 0.00% 63.16% # Class of executed instruction
1162system.cpu0.op_class::SimdCvt 0 0.00% 63.16% # Class of executed instruction
1163system.cpu0.op_class::SimdMisc 0 0.00% 63.16% # Class of executed instruction
1164system.cpu0.op_class::SimdMult 0 0.00% 63.16% # Class of executed instruction
1165system.cpu0.op_class::SimdMultAcc 0 0.00% 63.16% # Class of executed instruction
1166system.cpu0.op_class::SimdShift 0 0.00% 63.16% # Class of executed instruction
1167system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.16% # Class of executed instruction
1168system.cpu0.op_class::SimdSqrt 0 0.00% 63.16% # Class of executed instruction
1169system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.16% # Class of executed instruction
1170system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.16% # Class of executed instruction
1171system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.16% # Class of executed instruction
1172system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.16% # Class of executed instruction
1173system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.16% # Class of executed instruction
1174system.cpu0.op_class::SimdFloatMisc 1591 0.00% 63.17% # Class of executed instruction
1175system.cpu0.op_class::SimdFloatMult 0 0.00% 63.17% # Class of executed instruction
1176system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.17% # Class of executed instruction
1177system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.17% # Class of executed instruction
1178system.cpu0.op_class::MemRead 7343231 19.61% 82.77% # Class of executed instruction
1179system.cpu0.op_class::MemWrite 6452235 17.23% 100.00% # Class of executed instruction
1180system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1181system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1182system.cpu0.op_class::total 37452110 # Class of executed instruction
1183system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1184system.cpu0.kern.inst.quiesce 51950 # number of quiesce instructions executed
1185system.cpu0.icache.tags.replacements 369506 # number of replacements
1186system.cpu0.icache.tags.tagsinuse 511.465010 # Cycle average of tags in use
1187system.cpu0.icache.tags.total_refs 30812705 # Total number of references to valid blocks.
1188system.cpu0.icache.tags.sampled_refs 370018 # Sample count of references to valid blocks.
1189system.cpu0.icache.tags.avg_refs 83.273530 # Average number of references to valid blocks.
1190system.cpu0.icache.tags.warmup_cycle 10201796750 # Cycle when the warmup percentage was hit.
1191system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.465010 # Average occupied blocks per requestor
1192system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998955 # Average percentage of cache occupancy
1193system.cpu0.icache.tags.occ_percent::total 0.998955 # Average percentage of cache occupancy
1194system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1195system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id
1196system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
1197system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1198system.cpu0.icache.tags.tag_accesses 62735467 # Number of tag accesses
1199system.cpu0.icache.tags.data_accesses 62735467 # Number of data accesses
1200system.cpu0.icache.ReadReq_hits::cpu0.inst 30812705 # number of ReadReq hits
1201system.cpu0.icache.ReadReq_hits::total 30812705 # number of ReadReq hits
1202system.cpu0.icache.demand_hits::cpu0.inst 30812705 # number of demand (read+write) hits
1203system.cpu0.icache.demand_hits::total 30812705 # number of demand (read+write) hits
1204system.cpu0.icache.overall_hits::cpu0.inst 30812705 # number of overall hits
1205system.cpu0.icache.overall_hits::total 30812705 # number of overall hits
1206system.cpu0.icache.ReadReq_misses::cpu0.inst 370019 # number of ReadReq misses
1207system.cpu0.icache.ReadReq_misses::total 370019 # number of ReadReq misses
1208system.cpu0.icache.demand_misses::cpu0.inst 370019 # number of demand (read+write) misses
1209system.cpu0.icache.demand_misses::total 370019 # number of demand (read+write) misses
1210system.cpu0.icache.overall_misses::cpu0.inst 370019 # number of overall misses
1211system.cpu0.icache.overall_misses::total 370019 # number of overall misses
1212system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 3209345752 # number of ReadReq miss cycles
1213system.cpu0.icache.ReadReq_miss_latency::total 3209345752 # number of ReadReq miss cycles
1214system.cpu0.icache.demand_miss_latency::cpu0.inst 3209345752 # number of demand (read+write) miss cycles
1215system.cpu0.icache.demand_miss_latency::total 3209345752 # number of demand (read+write) miss cycles
1216system.cpu0.icache.overall_miss_latency::cpu0.inst 3209345752 # number of overall miss cycles
1217system.cpu0.icache.overall_miss_latency::total 3209345752 # number of overall miss cycles
1218system.cpu0.icache.ReadReq_accesses::cpu0.inst 31182724 # number of ReadReq accesses(hits+misses)
1219system.cpu0.icache.ReadReq_accesses::total 31182724 # number of ReadReq accesses(hits+misses)
1220system.cpu0.icache.demand_accesses::cpu0.inst 31182724 # number of demand (read+write) accesses
1221system.cpu0.icache.demand_accesses::total 31182724 # number of demand (read+write) accesses
1222system.cpu0.icache.overall_accesses::cpu0.inst 31182724 # number of overall (read+write) accesses
1223system.cpu0.icache.overall_accesses::total 31182724 # number of overall (read+write) accesses
1224system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011866 # miss rate for ReadReq accesses
1225system.cpu0.icache.ReadReq_miss_rate::total 0.011866 # miss rate for ReadReq accesses
1226system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011866 # miss rate for demand accesses
1227system.cpu0.icache.demand_miss_rate::total 0.011866 # miss rate for demand accesses
1228system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011866 # miss rate for overall accesses
1229system.cpu0.icache.overall_miss_rate::total 0.011866 # miss rate for overall accesses
1230system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8673.462044 # average ReadReq miss latency
1231system.cpu0.icache.ReadReq_avg_miss_latency::total 8673.462044 # average ReadReq miss latency
1232system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8673.462044 # average overall miss latency
1233system.cpu0.icache.demand_avg_miss_latency::total 8673.462044 # average overall miss latency
1234system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8673.462044 # average overall miss latency
1235system.cpu0.icache.overall_avg_miss_latency::total 8673.462044 # average overall miss latency
1236system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1237system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1238system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1239system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1240system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1241system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1242system.cpu0.icache.fast_writes 0 # number of fast writes performed
1243system.cpu0.icache.cache_copies 0 # number of cache copies performed
1244system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 370019 # number of ReadReq MSHR misses
1245system.cpu0.icache.ReadReq_mshr_misses::total 370019 # number of ReadReq MSHR misses
1246system.cpu0.icache.demand_mshr_misses::cpu0.inst 370019 # number of demand (read+write) MSHR misses
1247system.cpu0.icache.demand_mshr_misses::total 370019 # number of demand (read+write) MSHR misses
1248system.cpu0.icache.overall_mshr_misses::cpu0.inst 370019 # number of overall MSHR misses
1249system.cpu0.icache.overall_mshr_misses::total 370019 # number of overall MSHR misses
1250system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2653955748 # number of ReadReq MSHR miss cycles
1251system.cpu0.icache.ReadReq_mshr_miss_latency::total 2653955748 # number of ReadReq MSHR miss cycles
1252system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2653955748 # number of demand (read+write) MSHR miss cycles
1253system.cpu0.icache.demand_mshr_miss_latency::total 2653955748 # number of demand (read+write) MSHR miss cycles
1254system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2653955748 # number of overall MSHR miss cycles
1255system.cpu0.icache.overall_mshr_miss_latency::total 2653955748 # number of overall MSHR miss cycles
1256system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 531257750 # number of ReadReq MSHR uncacheable cycles
1257system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 531257750 # number of ReadReq MSHR uncacheable cycles
1258system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 531257750 # number of overall MSHR uncacheable cycles
1259system.cpu0.icache.overall_mshr_uncacheable_latency::total 531257750 # number of overall MSHR uncacheable cycles
1260system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for ReadReq accesses
1261system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011866 # mshr miss rate for ReadReq accesses
1262system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for demand accesses
1263system.cpu0.icache.demand_mshr_miss_rate::total 0.011866 # mshr miss rate for demand accesses
1264system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for overall accesses
1265system.cpu0.icache.overall_mshr_miss_rate::total 0.011866 # mshr miss rate for overall accesses
1266system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average ReadReq mshr miss latency
1267system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7172.485056 # average ReadReq mshr miss latency
1268system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency
1269system.cpu0.icache.demand_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency
1270system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency
1271system.cpu0.icache.overall_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency
1272system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1273system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1274system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1275system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1276system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1277system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 4129417 # number of hwpf identified
1278system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 113341 # number of hwpf that were already in mshr
1279system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 3763718 # number of hwpf that were already in the cache
1280system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 300 # number of hwpf that were already in the prefetch queue
1281system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
1282system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 22 # number of hwpf removed because MSHR allocated
1283system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 252036 # number of hwpf issued
1284system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 312183 # number of hwpf spanning a virtual page
1285system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
1286system.cpu0.l2cache.tags.replacements 213190 # number of replacements
1287system.cpu0.l2cache.tags.tagsinuse 16168.240053 # Cycle average of tags in use
1288system.cpu0.l2cache.tags.total_refs 848978 # Total number of references to valid blocks.
1289system.cpu0.l2cache.tags.sampled_refs 228702 # Sample count of references to valid blocks.
1290system.cpu0.l2cache.tags.avg_refs 3.712158 # Average number of references to valid blocks.
1291system.cpu0.l2cache.tags.warmup_cycle 7921739000 # Cycle when the warmup percentage was hit.
1292system.cpu0.l2cache.tags.occ_blocks::writebacks 4749.054127 # Average occupied blocks per requestor
1293system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.517230 # Average occupied blocks per requestor
1294system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.260718 # Average occupied blocks per requestor
1295system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 821.211493 # Average occupied blocks per requestor
1296system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1542.145038 # Average occupied blocks per requestor
1297system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9052.051448 # Average occupied blocks per requestor
1298system.cpu0.l2cache.tags.occ_percent::writebacks 0.289859 # Average percentage of cache occupancy
1299system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000215 # Average percentage of cache occupancy
1300system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy
1301system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.050123 # Average percentage of cache occupancy
1302system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.094125 # Average percentage of cache occupancy
1303system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.552493 # Average percentage of cache occupancy
1304system.cpu0.l2cache.tags.occ_percent::total 0.986831 # Average percentage of cache occupancy
1305system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8284 # Occupied blocks per task id
1306system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
1307system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7219 # Occupied blocks per task id
1308system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1260 # Occupied blocks per task id
1309system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1944 # Occupied blocks per task id
1310system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 5080 # Occupied blocks per task id
1311system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
1312system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
1313system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1775 # Occupied blocks per task id
1314system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1943 # Occupied blocks per task id
1315system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3501 # Occupied blocks per task id
1316system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.505615 # Percentage of cache occupancy per task id
1317system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
1318system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.440613 # Percentage of cache occupancy per task id
1319system.cpu0.l2cache.tags.tag_accesses 17864213 # Number of tag accesses
1320system.cpu0.l2cache.tags.data_accesses 17864213 # Number of data accesses
1321system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4737 # number of ReadReq hits
1322system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 2374 # number of ReadReq hits
1323system.cpu0.l2cache.ReadReq_hits::cpu0.inst 361048 # number of ReadReq hits
1324system.cpu0.l2cache.ReadReq_hits::cpu0.data 184302 # number of ReadReq hits
1325system.cpu0.l2cache.ReadReq_hits::total 552461 # number of ReadReq hits
1326system.cpu0.l2cache.Writeback_hits::writebacks 286361 # number of Writeback hits
1327system.cpu0.l2cache.Writeback_hits::total 286361 # number of Writeback hits
1328system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 5612 # number of UpgradeReq hits
1329system.cpu0.l2cache.UpgradeReq_hits::total 5612 # number of UpgradeReq hits
1330system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 831 # number of SCUpgradeReq hits
1331system.cpu0.l2cache.SCUpgradeReq_hits::total 831 # number of SCUpgradeReq hits
1332system.cpu0.l2cache.ReadExReq_hits::cpu0.data 133749 # number of ReadExReq hits
1333system.cpu0.l2cache.ReadExReq_hits::total 133749 # number of ReadExReq hits
1334system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4737 # number of demand (read+write) hits
1335system.cpu0.l2cache.demand_hits::cpu0.itb.walker 2374 # number of demand (read+write) hits
1336system.cpu0.l2cache.demand_hits::cpu0.inst 361048 # number of demand (read+write) hits
1337system.cpu0.l2cache.demand_hits::cpu0.data 318051 # number of demand (read+write) hits
1338system.cpu0.l2cache.demand_hits::total 686210 # number of demand (read+write) hits
1339system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4737 # number of overall hits
1340system.cpu0.l2cache.overall_hits::cpu0.itb.walker 2374 # number of overall hits
1341system.cpu0.l2cache.overall_hits::cpu0.inst 361048 # number of overall hits
1342system.cpu0.l2cache.overall_hits::cpu0.data 318051 # number of overall hits
1343system.cpu0.l2cache.overall_hits::total 686210 # number of overall hits
1344system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses
1345system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 146 # number of ReadReq misses
1346system.cpu0.l2cache.ReadReq_misses::cpu0.inst 8693 # number of ReadReq misses
1347system.cpu0.l2cache.ReadReq_misses::cpu0.data 48360 # number of ReadReq misses
1348system.cpu0.l2cache.ReadReq_misses::total 57424 # number of ReadReq misses
1349system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses
1350system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses
1351system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 18405 # number of UpgradeReq misses
1352system.cpu0.l2cache.UpgradeReq_misses::total 18405 # number of UpgradeReq misses
1353system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 10323 # number of SCUpgradeReq misses
1354system.cpu0.l2cache.SCUpgradeReq_misses::total 10323 # number of SCUpgradeReq misses
1355system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses
1356system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
1357system.cpu0.l2cache.ReadExReq_misses::cpu0.data 24100 # number of ReadExReq misses
1358system.cpu0.l2cache.ReadExReq_misses::total 24100 # number of ReadExReq misses
1359system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses
1360system.cpu0.l2cache.demand_misses::cpu0.itb.walker 146 # number of demand (read+write) misses
1361system.cpu0.l2cache.demand_misses::cpu0.inst 8693 # number of demand (read+write) misses
1362system.cpu0.l2cache.demand_misses::cpu0.data 72460 # number of demand (read+write) misses
1363system.cpu0.l2cache.demand_misses::total 81524 # number of demand (read+write) misses
1364system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses
1365system.cpu0.l2cache.overall_misses::cpu0.itb.walker 146 # number of overall misses
1366system.cpu0.l2cache.overall_misses::cpu0.inst 8693 # number of overall misses
1367system.cpu0.l2cache.overall_misses::cpu0.data 72460 # number of overall misses
1368system.cpu0.l2cache.overall_misses::total 81524 # number of overall misses
1369system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4897000 # number of ReadReq miss cycles
1370system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3307000 # number of ReadReq miss cycles
1371system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 300815745 # number of ReadReq miss cycles
1372system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 1253383203 # number of ReadReq miss cycles
1373system.cpu0.l2cache.ReadReq_miss_latency::total 1562402948 # number of ReadReq miss cycles
1374system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 288253128 # number of UpgradeReq miss cycles
1375system.cpu0.l2cache.UpgradeReq_miss_latency::total 288253128 # number of UpgradeReq miss cycles
1376system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 204026156 # number of SCUpgradeReq miss cycles
1377system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 204026156 # number of SCUpgradeReq miss cycles
1378system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1056000 # number of SCUpgradeFailReq miss cycles
1379system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1056000 # number of SCUpgradeFailReq miss cycles
1380system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 855610215 # number of ReadExReq miss cycles
1381system.cpu0.l2cache.ReadExReq_miss_latency::total 855610215 # number of ReadExReq miss cycles
1382system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4897000 # number of demand (read+write) miss cycles
1383system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3307000 # number of demand (read+write) miss cycles
1384system.cpu0.l2cache.demand_miss_latency::cpu0.inst 300815745 # number of demand (read+write) miss cycles
1385system.cpu0.l2cache.demand_miss_latency::cpu0.data 2108993418 # number of demand (read+write) miss cycles
1386system.cpu0.l2cache.demand_miss_latency::total 2418013163 # number of demand (read+write) miss cycles
1387system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4897000 # number of overall miss cycles
1388system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3307000 # number of overall miss cycles
1389system.cpu0.l2cache.overall_miss_latency::cpu0.inst 300815745 # number of overall miss cycles
1390system.cpu0.l2cache.overall_miss_latency::cpu0.data 2108993418 # number of overall miss cycles
1391system.cpu0.l2cache.overall_miss_latency::total 2418013163 # number of overall miss cycles
1392system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 4962 # number of ReadReq accesses(hits+misses)
1393system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2520 # number of ReadReq accesses(hits+misses)
1394system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 369741 # number of ReadReq accesses(hits+misses)
1395system.cpu0.l2cache.ReadReq_accesses::cpu0.data 232662 # number of ReadReq accesses(hits+misses)
1396system.cpu0.l2cache.ReadReq_accesses::total 609885 # number of ReadReq accesses(hits+misses)
1397system.cpu0.l2cache.Writeback_accesses::writebacks 286363 # number of Writeback accesses(hits+misses)
1398system.cpu0.l2cache.Writeback_accesses::total 286363 # number of Writeback accesses(hits+misses)
1399system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 24017 # number of UpgradeReq accesses(hits+misses)
1400system.cpu0.l2cache.UpgradeReq_accesses::total 24017 # number of UpgradeReq accesses(hits+misses)
1401system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11154 # number of SCUpgradeReq accesses(hits+misses)
1402system.cpu0.l2cache.SCUpgradeReq_accesses::total 11154 # number of SCUpgradeReq accesses(hits+misses)
1403system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
1404system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
1405system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 157849 # number of ReadExReq accesses(hits+misses)
1406system.cpu0.l2cache.ReadExReq_accesses::total 157849 # number of ReadExReq accesses(hits+misses)
1407system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 4962 # number of demand (read+write) accesses
1408system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 2520 # number of demand (read+write) accesses
1409system.cpu0.l2cache.demand_accesses::cpu0.inst 369741 # number of demand (read+write) accesses
1410system.cpu0.l2cache.demand_accesses::cpu0.data 390511 # number of demand (read+write) accesses
1411system.cpu0.l2cache.demand_accesses::total 767734 # number of demand (read+write) accesses
1412system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 4962 # number of overall (read+write) accesses
1413system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2520 # number of overall (read+write) accesses
1414system.cpu0.l2cache.overall_accesses::cpu0.inst 369741 # number of overall (read+write) accesses
1415system.cpu0.l2cache.overall_accesses::cpu0.data 390511 # number of overall (read+write) accesses
1416system.cpu0.l2cache.overall_accesses::total 767734 # number of overall (read+write) accesses
1417system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for ReadReq accesses
1418system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057937 # miss rate for ReadReq accesses
1419system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.023511 # miss rate for ReadReq accesses
1420system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.207855 # miss rate for ReadReq accesses
1421system.cpu0.l2cache.ReadReq_miss_rate::total 0.094155 # miss rate for ReadReq accesses
1422system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses
1423system.cpu0.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses
1424system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.766332 # miss rate for UpgradeReq accesses
1425system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.766332 # miss rate for UpgradeReq accesses
1426system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.925498 # miss rate for SCUpgradeReq accesses
1427system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.925498 # miss rate for SCUpgradeReq accesses
1428system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1429system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1430system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.152678 # miss rate for ReadExReq accesses
1431system.cpu0.l2cache.ReadExReq_miss_rate::total 0.152678 # miss rate for ReadExReq accesses
1432system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for demand accesses
1433system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057937 # miss rate for demand accesses
1434system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.023511 # miss rate for demand accesses
1435system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.185552 # miss rate for demand accesses
1436system.cpu0.l2cache.demand_miss_rate::total 0.106188 # miss rate for demand accesses
1437system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for overall accesses
1438system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057937 # miss rate for overall accesses
1439system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.023511 # miss rate for overall accesses
1440system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.185552 # miss rate for overall accesses
1441system.cpu0.l2cache.overall_miss_rate::total 0.106188 # miss rate for overall accesses
1442system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21764.444444 # average ReadReq miss latency
1443system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22650.684932 # average ReadReq miss latency
1444system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 34604.365006 # average ReadReq miss latency
1445system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 25917.766811 # average ReadReq miss latency
1446system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27208.187308 # average ReadReq miss latency
1447system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 15661.674980 # average UpgradeReq miss latency
1448system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 15661.674980 # average UpgradeReq miss latency
1449system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19764.230941 # average SCUpgradeReq miss latency
1450system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19764.230941 # average SCUpgradeReq miss latency
1451system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 528000 # average SCUpgradeFailReq miss latency
1452system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528000 # average SCUpgradeFailReq miss latency
1453system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 35502.498548 # average ReadExReq miss latency
1454system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 35502.498548 # average ReadExReq miss latency
1455system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21764.444444 # average overall miss latency
1456system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22650.684932 # average overall miss latency
1457system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34604.365006 # average overall miss latency
1458system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 29105.622661 # average overall miss latency
1459system.cpu0.l2cache.demand_avg_miss_latency::total 29660.138892 # average overall miss latency
1460system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21764.444444 # average overall miss latency
1461system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22650.684932 # average overall miss latency
1462system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34604.365006 # average overall miss latency
1463system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 29105.622661 # average overall miss latency
1464system.cpu0.l2cache.overall_avg_miss_latency::total 29660.138892 # average overall miss latency
1465system.cpu0.l2cache.blocked_cycles::no_mshrs 1020 # number of cycles access was blocked
1466system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1467system.cpu0.l2cache.blocked::no_mshrs 31 # number of cycles access was blocked
1468system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1469system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.903226 # average number of cycles each access was blocked
1470system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1471system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1472system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1473system.cpu0.l2cache.writebacks::writebacks 141584 # number of writebacks
1474system.cpu0.l2cache.writebacks::total 141584 # number of writebacks
1475system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1192 # number of ReadReq MSHR hits
1476system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 751 # number of ReadReq MSHR hits
1477system.cpu0.l2cache.ReadReq_mshr_hits::total 1943 # number of ReadReq MSHR hits
1478system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 493 # number of ReadExReq MSHR hits
1479system.cpu0.l2cache.ReadExReq_mshr_hits::total 493 # number of ReadExReq MSHR hits
1480system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1192 # number of demand (read+write) MSHR hits
1481system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1244 # number of demand (read+write) MSHR hits
1482system.cpu0.l2cache.demand_mshr_hits::total 2436 # number of demand (read+write) MSHR hits
1483system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1192 # number of overall MSHR hits
1484system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1244 # number of overall MSHR hits
1485system.cpu0.l2cache.overall_mshr_hits::total 2436 # number of overall MSHR hits
1486system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 225 # number of ReadReq MSHR misses
1487system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 146 # number of ReadReq MSHR misses
1488system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 7501 # number of ReadReq MSHR misses
1489system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 47609 # number of ReadReq MSHR misses
1490system.cpu0.l2cache.ReadReq_mshr_misses::total 55481 # number of ReadReq MSHR misses
1491system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses
1492system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses
1493system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 252027 # number of HardPFReq MSHR misses
1494system.cpu0.l2cache.HardPFReq_mshr_misses::total 252027 # number of HardPFReq MSHR misses
1495system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 18405 # number of UpgradeReq MSHR misses
1496system.cpu0.l2cache.UpgradeReq_mshr_misses::total 18405 # number of UpgradeReq MSHR misses
1497system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 10323 # number of SCUpgradeReq MSHR misses
1498system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 10323 # number of SCUpgradeReq MSHR misses
1499system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses
1500system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
1501system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 23607 # number of ReadExReq MSHR misses
1502system.cpu0.l2cache.ReadExReq_mshr_misses::total 23607 # number of ReadExReq MSHR misses
1503system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 225 # number of demand (read+write) MSHR misses
1504system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 146 # number of demand (read+write) MSHR misses
1505system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 7501 # number of demand (read+write) MSHR misses
1506system.cpu0.l2cache.demand_mshr_misses::cpu0.data 71216 # number of demand (read+write) MSHR misses
1507system.cpu0.l2cache.demand_mshr_misses::total 79088 # number of demand (read+write) MSHR misses
1508system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 225 # number of overall MSHR misses
1509system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 146 # number of overall MSHR misses
1510system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 7501 # number of overall MSHR misses
1511system.cpu0.l2cache.overall_mshr_misses::cpu0.data 71216 # number of overall MSHR misses
1512system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 252027 # number of overall MSHR misses
1513system.cpu0.l2cache.overall_mshr_misses::total 331115 # number of overall MSHR misses
1514system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of ReadReq MSHR miss cycles
1515system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2285000 # number of ReadReq MSHR miss cycles
1516system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 227161754 # number of ReadReq MSHR miss cycles
1517system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 910924475 # number of ReadReq MSHR miss cycles
1518system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1143693229 # number of ReadReq MSHR miss cycles
1519system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 10450561115 # number of HardPFReq MSHR miss cycles
1520system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 10450561115 # number of HardPFReq MSHR miss cycles
1521system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 330354697 # number of UpgradeReq MSHR miss cycles
1522system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 330354697 # number of UpgradeReq MSHR miss cycles
1523system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 150011322 # number of SCUpgradeReq MSHR miss cycles
1524system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 150011322 # number of SCUpgradeReq MSHR miss cycles
1525system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 888000 # number of SCUpgradeFailReq MSHR miss cycles
1526system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 888000 # number of SCUpgradeFailReq MSHR miss cycles
1527system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 642746273 # number of ReadExReq MSHR miss cycles
1528system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 642746273 # number of ReadExReq MSHR miss cycles
1529system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of demand (read+write) MSHR miss cycles
1530system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2285000 # number of demand (read+write) MSHR miss cycles
1531system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 227161754 # number of demand (read+write) MSHR miss cycles
1532system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1553670748 # number of demand (read+write) MSHR miss cycles
1533system.cpu0.l2cache.demand_mshr_miss_latency::total 1786439502 # number of demand (read+write) MSHR miss cycles
1534system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of overall MSHR miss cycles
1535system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2285000 # number of overall MSHR miss cycles
1536system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 227161754 # number of overall MSHR miss cycles
1537system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1553670748 # number of overall MSHR miss cycles
1538system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 10450561115 # number of overall MSHR miss cycles
1539system.cpu0.l2cache.overall_mshr_miss_latency::total 12237000617 # number of overall MSHR miss cycles
1540system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 478295250 # number of ReadReq MSHR uncacheable cycles
1541system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 176453658508 # number of ReadReq MSHR uncacheable cycles
1542system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 176931953758 # number of ReadReq MSHR uncacheable cycles
1543system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1575154999 # number of WriteReq MSHR uncacheable cycles
1544system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1575154999 # number of WriteReq MSHR uncacheable cycles
1545system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 478295250 # number of overall MSHR uncacheable cycles
1546system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 178028813507 # number of overall MSHR uncacheable cycles
1547system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 178507108757 # number of overall MSHR uncacheable cycles
1548system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for ReadReq accesses
1549system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for ReadReq accesses
1550system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for ReadReq accesses
1551system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.204627 # mshr miss rate for ReadReq accesses
1552system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.090970 # mshr miss rate for ReadReq accesses
1553system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses
1554system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses
1555system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1556system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1557system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.766332 # mshr miss rate for UpgradeReq accesses
1558system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.766332 # mshr miss rate for UpgradeReq accesses
1559system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.925498 # mshr miss rate for SCUpgradeReq accesses
1560system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.925498 # mshr miss rate for SCUpgradeReq accesses
1561system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1562system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1563system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.149554 # mshr miss rate for ReadExReq accesses
1564system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149554 # mshr miss rate for ReadExReq accesses
1565system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for demand accesses
1566system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for demand accesses
1567system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for demand accesses
1568system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.182366 # mshr miss rate for demand accesses
1569system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103015 # mshr miss rate for demand accesses
1570system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for overall accesses
1571system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for overall accesses
1572system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for overall accesses
1573system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.182366 # mshr miss rate for overall accesses
1574system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1575system.cpu0.l2cache.overall_mshr_miss_rate::total 0.431289 # mshr miss rate for overall accesses
1576system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average ReadReq mshr miss latency
1577system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average ReadReq mshr miss latency
1578system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average ReadReq mshr miss latency
1579system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 19133.451133 # average ReadReq mshr miss latency
1580system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20614.142301 # average ReadReq mshr miss latency
1581system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825 # average HardPFReq mshr miss latency
1582system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41466.037825 # average HardPFReq mshr miss latency
1583system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17949.182124 # average UpgradeReq mshr miss latency
1584system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17949.182124 # average UpgradeReq mshr miss latency
1585system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14531.756466 # average SCUpgradeReq mshr miss latency
1586system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14531.756466 # average SCUpgradeReq mshr miss latency
1587system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 444000 # average SCUpgradeFailReq mshr miss latency
1588system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 444000 # average SCUpgradeFailReq mshr miss latency
1589system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 27226.935782 # average ReadExReq mshr miss latency
1590system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27226.935782 # average ReadExReq mshr miss latency
1591system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average overall mshr miss latency
1592system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average overall mshr miss latency
1593system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average overall mshr miss latency
1594system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21816.315828 # average overall mshr miss latency
1595system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22587.996940 # average overall mshr miss latency
1596system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average overall mshr miss latency
1597system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average overall mshr miss latency
1598system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average overall mshr miss latency
1599system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21816.315828 # average overall mshr miss latency
1600system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825 # average overall mshr miss latency
1601system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36956.950356 # average overall mshr miss latency
1602system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1603system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1604system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1605system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1606system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1607system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1608system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1609system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1610system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1611system.cpu0.dcache.tags.replacements 355829 # number of replacements
1612system.cpu0.dcache.tags.tagsinuse 496.967445 # Cycle average of tags in use
1613system.cpu0.dcache.tags.total_refs 11721464 # Total number of references to valid blocks.
1614system.cpu0.dcache.tags.sampled_refs 356159 # Sample count of references to valid blocks.
1615system.cpu0.dcache.tags.avg_refs 32.910762 # Average number of references to valid blocks.
1616system.cpu0.dcache.tags.warmup_cycle 767187000 # Cycle when the warmup percentage was hit.
1617system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.967445 # Average occupied blocks per requestor
1618system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970640 # Average percentage of cache occupancy
1619system.cpu0.dcache.tags.occ_percent::total 0.970640 # Average percentage of cache occupancy
1620system.cpu0.dcache.tags.occ_task_id_blocks::1024 330 # Occupied blocks per task id
1621system.cpu0.dcache.tags.age_task_id_blocks_1024::2 330 # Occupied blocks per task id
1622system.cpu0.dcache.tags.occ_task_id_percent::1024 0.644531 # Percentage of cache occupancy per task id
1623system.cpu0.dcache.tags.tag_accesses 24668842 # Number of tag accesses
1624system.cpu0.dcache.tags.data_accesses 24668842 # Number of data accesses
1625system.cpu0.dcache.ReadReq_hits::cpu0.data 5548461 # number of ReadReq hits
1626system.cpu0.dcache.ReadReq_hits::total 5548461 # number of ReadReq hits
1627system.cpu0.dcache.WriteReq_hits::cpu0.data 5771889 # number of WriteReq hits
1628system.cpu0.dcache.WriteReq_hits::total 5771889 # number of WriteReq hits
1629system.cpu0.dcache.SoftPFReq_hits::cpu0.data 62661 # number of SoftPFReq hits
1630system.cpu0.dcache.SoftPFReq_hits::total 62661 # number of SoftPFReq hits
1631system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 153118 # number of LoadLockedReq hits
1632system.cpu0.dcache.LoadLockedReq_hits::total 153118 # number of LoadLockedReq hits
1633system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152372 # number of StoreCondReq hits
1634system.cpu0.dcache.StoreCondReq_hits::total 152372 # number of StoreCondReq hits
1635system.cpu0.dcache.demand_hits::cpu0.data 11320350 # number of demand (read+write) hits
1636system.cpu0.dcache.demand_hits::total 11320350 # number of demand (read+write) hits
1637system.cpu0.dcache.overall_hits::cpu0.data 11383011 # number of overall hits
1638system.cpu0.dcache.overall_hits::total 11383011 # number of overall hits
1639system.cpu0.dcache.ReadReq_misses::cpu0.data 178532 # number of ReadReq misses
1640system.cpu0.dcache.ReadReq_misses::total 178532 # number of ReadReq misses
1641system.cpu0.dcache.WriteReq_misses::cpu0.data 183693 # number of WriteReq misses
1642system.cpu0.dcache.WriteReq_misses::total 183693 # number of WriteReq misses
1643system.cpu0.dcache.SoftPFReq_misses::cpu0.data 66756 # number of SoftPFReq misses
1644system.cpu0.dcache.SoftPFReq_misses::total 66756 # number of SoftPFReq misses
1645system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10498 # number of LoadLockedReq misses
1646system.cpu0.dcache.LoadLockedReq_misses::total 10498 # number of LoadLockedReq misses
1647system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11173 # number of StoreCondReq misses
1648system.cpu0.dcache.StoreCondReq_misses::total 11173 # number of StoreCondReq misses
1649system.cpu0.dcache.demand_misses::cpu0.data 362225 # number of demand (read+write) misses
1650system.cpu0.dcache.demand_misses::total 362225 # number of demand (read+write) misses
1651system.cpu0.dcache.overall_misses::cpu0.data 428981 # number of overall misses
1652system.cpu0.dcache.overall_misses::total 428981 # number of overall misses
1653system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2139066005 # number of ReadReq miss cycles
1654system.cpu0.dcache.ReadReq_miss_latency::total 2139066005 # number of ReadReq miss cycles
1655system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 2832298001 # number of WriteReq miss cycles
1656system.cpu0.dcache.WriteReq_miss_latency::total 2832298001 # number of WriteReq miss cycles
1657system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 176126000 # number of LoadLockedReq miss cycles
1658system.cpu0.dcache.LoadLockedReq_miss_latency::total 176126000 # number of LoadLockedReq miss cycles
1659system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 261398841 # number of StoreCondReq miss cycles
1660system.cpu0.dcache.StoreCondReq_miss_latency::total 261398841 # number of StoreCondReq miss cycles
1661system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1128000 # number of StoreCondFailReq miss cycles
1662system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1128000 # number of StoreCondFailReq miss cycles
1663system.cpu0.dcache.demand_miss_latency::cpu0.data 4971364006 # number of demand (read+write) miss cycles
1664system.cpu0.dcache.demand_miss_latency::total 4971364006 # number of demand (read+write) miss cycles
1665system.cpu0.dcache.overall_miss_latency::cpu0.data 4971364006 # number of overall miss cycles
1666system.cpu0.dcache.overall_miss_latency::total 4971364006 # number of overall miss cycles
1667system.cpu0.dcache.ReadReq_accesses::cpu0.data 5726993 # number of ReadReq accesses(hits+misses)
1668system.cpu0.dcache.ReadReq_accesses::total 5726993 # number of ReadReq accesses(hits+misses)
1669system.cpu0.dcache.WriteReq_accesses::cpu0.data 5955582 # number of WriteReq accesses(hits+misses)
1670system.cpu0.dcache.WriteReq_accesses::total 5955582 # number of WriteReq accesses(hits+misses)
1671system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129417 # number of SoftPFReq accesses(hits+misses)
1672system.cpu0.dcache.SoftPFReq_accesses::total 129417 # number of SoftPFReq accesses(hits+misses)
1673system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163616 # number of LoadLockedReq accesses(hits+misses)
1674system.cpu0.dcache.LoadLockedReq_accesses::total 163616 # number of LoadLockedReq accesses(hits+misses)
1675system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 163545 # number of StoreCondReq accesses(hits+misses)
1676system.cpu0.dcache.StoreCondReq_accesses::total 163545 # number of StoreCondReq accesses(hits+misses)
1677system.cpu0.dcache.demand_accesses::cpu0.data 11682575 # number of demand (read+write) accesses
1678system.cpu0.dcache.demand_accesses::total 11682575 # number of demand (read+write) accesses
1679system.cpu0.dcache.overall_accesses::cpu0.data 11811992 # number of overall (read+write) accesses
1680system.cpu0.dcache.overall_accesses::total 11811992 # number of overall (read+write) accesses
1681system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031174 # miss rate for ReadReq accesses
1682system.cpu0.dcache.ReadReq_miss_rate::total 0.031174 # miss rate for ReadReq accesses
1683system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030844 # miss rate for WriteReq accesses
1684system.cpu0.dcache.WriteReq_miss_rate::total 0.030844 # miss rate for WriteReq accesses
1685system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.515821 # miss rate for SoftPFReq accesses
1686system.cpu0.dcache.SoftPFReq_miss_rate::total 0.515821 # miss rate for SoftPFReq accesses
1687system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064162 # miss rate for LoadLockedReq accesses
1688system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064162 # miss rate for LoadLockedReq accesses
1689system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.068318 # miss rate for StoreCondReq accesses
1690system.cpu0.dcache.StoreCondReq_miss_rate::total 0.068318 # miss rate for StoreCondReq accesses
1691system.cpu0.dcache.demand_miss_rate::cpu0.data 0.031006 # miss rate for demand accesses
1692system.cpu0.dcache.demand_miss_rate::total 0.031006 # miss rate for demand accesses
1693system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036317 # miss rate for overall accesses
1694system.cpu0.dcache.overall_miss_rate::total 0.036317 # miss rate for overall accesses
1695system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 11981.415124 # average ReadReq miss latency
1696system.cpu0.dcache.ReadReq_avg_miss_latency::total 11981.415124 # average ReadReq miss latency
1697system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15418.649600 # average WriteReq miss latency
1698system.cpu0.dcache.WriteReq_avg_miss_latency::total 15418.649600 # average WriteReq miss latency
1699system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16777.100400 # average LoadLockedReq miss latency
1700system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16777.100400 # average LoadLockedReq miss latency
1701system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23395.582297 # average StoreCondReq miss latency
1702system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23395.582297 # average StoreCondReq miss latency
1703system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
1704system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1705system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13724.519307 # average overall miss latency
1706system.cpu0.dcache.demand_avg_miss_latency::total 13724.519307 # average overall miss latency
1707system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11588.774342 # average overall miss latency
1708system.cpu0.dcache.overall_avg_miss_latency::total 11588.774342 # average overall miss latency
1709system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1710system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1711system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1712system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1713system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1714system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1715system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1716system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1717system.cpu0.dcache.writebacks::writebacks 286365 # number of writebacks
1718system.cpu0.dcache.writebacks::total 286365 # number of writebacks
1719system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3418 # number of ReadReq MSHR hits
1720system.cpu0.dcache.ReadReq_mshr_hits::total 3418 # number of ReadReq MSHR hits
1721system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2438 # number of WriteReq MSHR hits
1722system.cpu0.dcache.WriteReq_mshr_hits::total 2438 # number of WriteReq MSHR hits
1723system.cpu0.dcache.demand_mshr_hits::cpu0.data 5856 # number of demand (read+write) MSHR hits
1724system.cpu0.dcache.demand_mshr_hits::total 5856 # number of demand (read+write) MSHR hits
1725system.cpu0.dcache.overall_mshr_hits::cpu0.data 5856 # number of overall MSHR hits
1726system.cpu0.dcache.overall_mshr_hits::total 5856 # number of overall MSHR hits
1727system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 175114 # number of ReadReq MSHR misses
1728system.cpu0.dcache.ReadReq_mshr_misses::total 175114 # number of ReadReq MSHR misses
1729system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 181255 # number of WriteReq MSHR misses
1730system.cpu0.dcache.WriteReq_mshr_misses::total 181255 # number of WriteReq MSHR misses
1731system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 47050 # number of SoftPFReq MSHR misses
1732system.cpu0.dcache.SoftPFReq_mshr_misses::total 47050 # number of SoftPFReq MSHR misses
1733system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 10498 # number of LoadLockedReq MSHR misses
1734system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10498 # number of LoadLockedReq MSHR misses
1735system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 11156 # number of StoreCondReq MSHR misses
1736system.cpu0.dcache.StoreCondReq_mshr_misses::total 11156 # number of StoreCondReq MSHR misses
1737system.cpu0.dcache.demand_mshr_misses::cpu0.data 356369 # number of demand (read+write) MSHR misses
1738system.cpu0.dcache.demand_mshr_misses::total 356369 # number of demand (read+write) MSHR misses
1739system.cpu0.dcache.overall_mshr_misses::cpu0.data 403419 # number of overall MSHR misses
1740system.cpu0.dcache.overall_mshr_misses::total 403419 # number of overall MSHR misses
1741system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1737360745 # number of ReadReq MSHR miss cycles
1742system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1737360745 # number of ReadReq MSHR miss cycles
1743system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 2335118999 # number of WriteReq MSHR miss cycles
1744system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2335118999 # number of WriteReq MSHR miss cycles
1745system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 699675494 # number of SoftPFReq MSHR miss cycles
1746system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 699675494 # number of SoftPFReq MSHR miss cycles
1747system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 155125000 # number of LoadLockedReq MSHR miss cycles
1748system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 155125000 # number of LoadLockedReq MSHR miss cycles
1749system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 237977159 # number of StoreCondReq MSHR miss cycles
1750system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 237977159 # number of StoreCondReq MSHR miss cycles
1751system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1080000 # number of StoreCondFailReq MSHR miss cycles
1752system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1080000 # number of StoreCondFailReq MSHR miss cycles
1753system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 4072479744 # number of demand (read+write) MSHR miss cycles
1754system.cpu0.dcache.demand_mshr_miss_latency::total 4072479744 # number of demand (read+write) MSHR miss cycles
1755system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4772155238 # number of overall MSHR miss cycles
1756system.cpu0.dcache.overall_mshr_miss_latency::total 4772155238 # number of overall MSHR miss cycles
1757system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 185341734990 # number of ReadReq MSHR uncacheable cycles
1758system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 185341734990 # number of ReadReq MSHR uncacheable cycles
1759system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1669232496 # number of WriteReq MSHR uncacheable cycles
1760system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1669232496 # number of WriteReq MSHR uncacheable cycles
1761system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 187010967486 # number of overall MSHR uncacheable cycles
1762system.cpu0.dcache.overall_mshr_uncacheable_latency::total 187010967486 # number of overall MSHR uncacheable cycles
1763system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030577 # mshr miss rate for ReadReq accesses
1764system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030577 # mshr miss rate for ReadReq accesses
1765system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030434 # mshr miss rate for WriteReq accesses
1766system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030434 # mshr miss rate for WriteReq accesses
1767system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.363553 # mshr miss rate for SoftPFReq accesses
1768system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.363553 # mshr miss rate for SoftPFReq accesses
1769system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064162 # mshr miss rate for LoadLockedReq accesses
1770system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064162 # mshr miss rate for LoadLockedReq accesses
1771system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.068214 # mshr miss rate for StoreCondReq accesses
1772system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.068214 # mshr miss rate for StoreCondReq accesses
1773system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030504 # mshr miss rate for demand accesses
1774system.cpu0.dcache.demand_mshr_miss_rate::total 0.030504 # mshr miss rate for demand accesses
1775system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034153 # mshr miss rate for overall accesses
1776system.cpu0.dcache.overall_mshr_miss_rate::total 0.034153 # mshr miss rate for overall accesses
1777system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 9921.312659 # average ReadReq mshr miss latency
1778system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9921.312659 # average ReadReq mshr miss latency
1779system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12883.059772 # average WriteReq mshr miss latency
1780system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12883.059772 # average WriteReq mshr miss latency
1781system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14870.892540 # average SoftPFReq mshr miss latency
1782system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14870.892540 # average SoftPFReq mshr miss latency
1783system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14776.624119 # average LoadLockedReq mshr miss latency
1784system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14776.624119 # average LoadLockedReq mshr miss latency
1785system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21331.763984 # average StoreCondReq mshr miss latency
1786system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21331.763984 # average StoreCondReq mshr miss latency
1787system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1788system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1789system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11427.704834 # average overall mshr miss latency
1790system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11427.704834 # average overall mshr miss latency
1791system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11829.277347 # average overall mshr miss latency
1792system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11829.277347 # average overall mshr miss latency
1793system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1794system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1795system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1796system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1797system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1798system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1799system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1800system.cpu0.toL2Bus.trans_dist::ReadReq 1907557 # Transaction distribution
1801system.cpu0.toL2Bus.trans_dist::ReadResp 1767698 # Transaction distribution
1802system.cpu0.toL2Bus.trans_dist::WriteReq 12543 # Transaction distribution
1803system.cpu0.toL2Bus.trans_dist::WriteResp 12543 # Transaction distribution
1804system.cpu0.toL2Bus.trans_dist::Writeback 286363 # Transaction distribution
1805system.cpu0.toL2Bus.trans_dist::HardPFReq 331583 # Transaction distribution
1806system.cpu0.toL2Bus.trans_dist::UpgradeReq 53089 # Transaction distribution
1807system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23925 # Transaction distribution
1808system.cpu0.toL2Bus.trans_dist::UpgradeResp 60027 # Transaction distribution
1809system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution
1810system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution
1811system.cpu0.toL2Bus.trans_dist::ReadExReq 171374 # Transaction distribution
1812system.cpu0.toL2Bus.trans_dist::ReadExResp 163301 # Transaction distribution
1813system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 753056 # Packet count per connected master and slave (bytes)
1814system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 3449820 # Packet count per connected master and slave (bytes)
1815system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6852 # Packet count per connected master and slave (bytes)
1816system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 13348 # Packet count per connected master and slave (bytes)
1817system.cpu0.toL2Bus.pkt_count::total 4223076 # Packet count per connected master and slave (bytes)
1818system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 23690016 # Cumulative packet size per connected master and slave (bytes)
1819system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 48159078 # Cumulative packet size per connected master and slave (bytes)
1820system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10080 # Cumulative packet size per connected master and slave (bytes)
1821system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 19848 # Cumulative packet size per connected master and slave (bytes)
1822system.cpu0.toL2Bus.pkt_size::total 71879022 # Cumulative packet size per connected master and slave (bytes)
1823system.cpu0.toL2Bus.snoops 631972 # Total snoops (count)
1824system.cpu0.toL2Bus.snoop_fanout::samples 1656253 # Request fanout histogram
1825system.cpu0.toL2Bus.snoop_fanout::mean 5.339000 # Request fanout histogram
1826system.cpu0.toL2Bus.snoop_fanout::stdev 0.473370 # Request fanout histogram
1827system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1828system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1829system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1830system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1831system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1832system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1833system.cpu0.toL2Bus.snoop_fanout::5 1094784 66.10% 66.10% # Request fanout histogram
1834system.cpu0.toL2Bus.snoop_fanout::6 561469 33.90% 100.00% # Request fanout histogram
1835system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1836system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1837system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1838system.cpu0.toL2Bus.snoop_fanout::total 1656253 # Request fanout histogram
1839system.cpu0.toL2Bus.reqLayer0.occupancy 1405252745 # Layer occupancy (ticks)
1840system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1841system.cpu0.toL2Bus.snoopLayer0.occupancy 72604500 # Layer occupancy (ticks)
1842system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1843system.cpu0.toL2Bus.respLayer0.occupancy 563408502 # Layer occupancy (ticks)
1844system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1845system.cpu0.toL2Bus.respLayer1.occupancy 1726182117 # Layer occupancy (ticks)
1846system.cpu0.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1847system.cpu0.toL2Bus.respLayer2.occupancy 4332000 # Layer occupancy (ticks)
1848system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1849system.cpu0.toL2Bus.respLayer3.occupancy 8386000 # Layer occupancy (ticks)
1850system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1851system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1852system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1853system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1854system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1855system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1856system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1857system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed

--- 8 unchanged lines hidden (view full) ---

1866system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1867system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1868system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1869system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1870system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1871system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1872system.cpu1.dtb.inst_hits 0 # ITB inst hits
1873system.cpu1.dtb.inst_misses 0 # ITB inst misses
1874system.cpu1.dtb.read_hits 6599972 # DTB read hits
1875system.cpu1.dtb.read_misses 3720 # DTB read misses
1876system.cpu1.dtb.write_hits 5539858 # DTB write hits
1877system.cpu1.dtb.write_misses 1581 # DTB write misses
1878system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1879system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1880system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1881system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1882system.cpu1.dtb.flush_entries 1672 # Number of entries that have been flushed from TLB
1883system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1884system.cpu1.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch
1885system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1886system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
1887system.cpu1.dtb.read_accesses 6603692 # DTB read accesses
1888system.cpu1.dtb.write_accesses 5541439 # DTB write accesses
1889system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1890system.cpu1.dtb.hits 12139830 # DTB hits
1891system.cpu1.dtb.misses 5301 # DTB misses
1892system.cpu1.dtb.accesses 12145131 # DTB accesses
1893system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1894system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1895system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1896system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1897system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1898system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1899system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1900system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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1906system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1907system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1908system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1909system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1910system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1911system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1912system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1913system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1914system.cpu1.itb.inst_hits 32728613 # ITB inst hits
1915system.cpu1.itb.inst_misses 2200 # ITB inst misses
1916system.cpu1.itb.read_hits 0 # DTB read hits
1917system.cpu1.itb.read_misses 0 # DTB read misses
1918system.cpu1.itb.write_hits 0 # DTB write hits
1919system.cpu1.itb.write_misses 0 # DTB write misses
1920system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1921system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1922system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1923system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1924system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB
1925system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1926system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1927system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1928system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1929system.cpu1.itb.read_accesses 0 # DTB read accesses
1930system.cpu1.itb.write_accesses 0 # DTB write accesses
1931system.cpu1.itb.inst_accesses 32730813 # ITB inst accesses
1932system.cpu1.itb.hits 32728613 # DTB hits
1933system.cpu1.itb.misses 2200 # DTB misses
1934system.cpu1.itb.accesses 32730813 # DTB accesses
1935system.cpu1.numCycles 5350361558 # number of cpu cycles simulated
1936system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1937system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1938system.cpu1.committedInsts 32086754 # Number of instructions committed
1939system.cpu1.committedOps 37934299 # Number of ops (including micro ops) committed
1940system.cpu1.num_int_alu_accesses 33961237 # Number of integer alu accesses
1941system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses
1942system.cpu1.num_func_calls 973285 # number of times a function call or return occured
1943system.cpu1.num_conditional_control_insts 3888456 # number of instructions that are conditional controls
1944system.cpu1.num_int_insts 33961237 # number of integer instructions
1945system.cpu1.num_fp_insts 4436 # number of float instructions
1946system.cpu1.num_int_register_reads 60527961 # number of times the integer registers were read
1947system.cpu1.num_int_register_writes 22681940 # number of times the integer registers were written
1948system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read
1949system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written
1950system.cpu1.num_cc_register_reads 134686779 # number of times the CC registers were read
1951system.cpu1.num_cc_register_writes 15567897 # number of times the CC registers were written
1952system.cpu1.num_mem_refs 12531559 # number of memory refs
1953system.cpu1.num_load_insts 6744563 # Number of load instructions
1954system.cpu1.num_store_insts 5786996 # Number of store instructions
1955system.cpu1.num_idle_cycles 5182201093.372063 # Number of idle cycles
1956system.cpu1.num_busy_cycles 168160464.627937 # Number of busy cycles
1957system.cpu1.not_idle_fraction 0.031430 # Percentage of non-idle cycles
1958system.cpu1.idle_fraction 0.968570 # Percentage of idle cycles
1959system.cpu1.Branches 5094014 # Number of branches fetched
1960system.cpu1.op_class::No_OpClass 12501 0.03% 0.03% # Class of executed instruction
1961system.cpu1.op_class::IntAlu 25826807 67.22% 67.25% # Class of executed instruction
1962system.cpu1.op_class::IntMult 50699 0.13% 67.38% # Class of executed instruction
1963system.cpu1.op_class::IntDiv 0 0.00% 67.38% # Class of executed instruction
1964system.cpu1.op_class::FloatAdd 0 0.00% 67.38% # Class of executed instruction
1965system.cpu1.op_class::FloatCmp 0 0.00% 67.38% # Class of executed instruction
1966system.cpu1.op_class::FloatCvt 0 0.00% 67.38% # Class of executed instruction
1967system.cpu1.op_class::FloatMult 0 0.00% 67.38% # Class of executed instruction
1968system.cpu1.op_class::FloatDiv 0 0.00% 67.38% # Class of executed instruction
1969system.cpu1.op_class::FloatSqrt 0 0.00% 67.38% # Class of executed instruction
1970system.cpu1.op_class::SimdAdd 0 0.00% 67.38% # Class of executed instruction
1971system.cpu1.op_class::SimdAddAcc 0 0.00% 67.38% # Class of executed instruction
1972system.cpu1.op_class::SimdAlu 0 0.00% 67.38% # Class of executed instruction
1973system.cpu1.op_class::SimdCmp 0 0.00% 67.38% # Class of executed instruction
1974system.cpu1.op_class::SimdCvt 0 0.00% 67.38% # Class of executed instruction
1975system.cpu1.op_class::SimdMisc 0 0.00% 67.38% # Class of executed instruction
1976system.cpu1.op_class::SimdMult 0 0.00% 67.38% # Class of executed instruction
1977system.cpu1.op_class::SimdMultAcc 0 0.00% 67.38% # Class of executed instruction
1978system.cpu1.op_class::SimdShift 0 0.00% 67.38% # Class of executed instruction
1979system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.38% # Class of executed instruction
1980system.cpu1.op_class::SimdSqrt 0 0.00% 67.38% # Class of executed instruction
1981system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.38% # Class of executed instruction
1982system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.38% # Class of executed instruction
1983system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.38% # Class of executed instruction
1984system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.38% # Class of executed instruction
1985system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.38% # Class of executed instruction
1986system.cpu1.op_class::SimdFloatMisc 745 0.00% 67.38% # Class of executed instruction
1987system.cpu1.op_class::SimdFloatMult 0 0.00% 67.38% # Class of executed instruction
1988system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.38% # Class of executed instruction
1989system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.38% # Class of executed instruction
1990system.cpu1.op_class::MemRead 6744563 17.55% 84.94% # Class of executed instruction
1991system.cpu1.op_class::MemWrite 5786996 15.06% 100.00% # Class of executed instruction
1992system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1993system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1994system.cpu1.op_class::total 38422311 # Class of executed instruction
1995system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1996system.cpu1.kern.inst.quiesce 40934 # number of quiesce instructions executed
1997system.cpu1.icache.tags.replacements 375227 # number of replacements
1998system.cpu1.icache.tags.tagsinuse 498.528279 # Cycle average of tags in use
1999system.cpu1.icache.tags.total_refs 32352870 # Total number of references to valid blocks.
2000system.cpu1.icache.tags.sampled_refs 375739 # Sample count of references to valid blocks.
2001system.cpu1.icache.tags.avg_refs 86.104636 # Average number of references to valid blocks.
2002system.cpu1.icache.tags.warmup_cycle 79843888000 # Cycle when the warmup percentage was hit.
2003system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.528279 # Average occupied blocks per requestor
2004system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973688 # Average percentage of cache occupancy
2005system.cpu1.icache.tags.occ_percent::total 0.973688 # Average percentage of cache occupancy
2006system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2007system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
2008system.cpu1.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
2009system.cpu1.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
2010system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
2011system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2012system.cpu1.icache.tags.tag_accesses 65832957 # Number of tag accesses
2013system.cpu1.icache.tags.data_accesses 65832957 # Number of data accesses
2014system.cpu1.icache.ReadReq_hits::cpu1.inst 32352870 # number of ReadReq hits
2015system.cpu1.icache.ReadReq_hits::total 32352870 # number of ReadReq hits
2016system.cpu1.icache.demand_hits::cpu1.inst 32352870 # number of demand (read+write) hits
2017system.cpu1.icache.demand_hits::total 32352870 # number of demand (read+write) hits
2018system.cpu1.icache.overall_hits::cpu1.inst 32352870 # number of overall hits
2019system.cpu1.icache.overall_hits::total 32352870 # number of overall hits
2020system.cpu1.icache.ReadReq_misses::cpu1.inst 375739 # number of ReadReq misses
2021system.cpu1.icache.ReadReq_misses::total 375739 # number of ReadReq misses
2022system.cpu1.icache.demand_misses::cpu1.inst 375739 # number of demand (read+write) misses
2023system.cpu1.icache.demand_misses::total 375739 # number of demand (read+write) misses
2024system.cpu1.icache.overall_misses::cpu1.inst 375739 # number of overall misses
2025system.cpu1.icache.overall_misses::total 375739 # number of overall misses
2026system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3159151510 # number of ReadReq miss cycles
2027system.cpu1.icache.ReadReq_miss_latency::total 3159151510 # number of ReadReq miss cycles
2028system.cpu1.icache.demand_miss_latency::cpu1.inst 3159151510 # number of demand (read+write) miss cycles
2029system.cpu1.icache.demand_miss_latency::total 3159151510 # number of demand (read+write) miss cycles
2030system.cpu1.icache.overall_miss_latency::cpu1.inst 3159151510 # number of overall miss cycles
2031system.cpu1.icache.overall_miss_latency::total 3159151510 # number of overall miss cycles
2032system.cpu1.icache.ReadReq_accesses::cpu1.inst 32728609 # number of ReadReq accesses(hits+misses)
2033system.cpu1.icache.ReadReq_accesses::total 32728609 # number of ReadReq accesses(hits+misses)
2034system.cpu1.icache.demand_accesses::cpu1.inst 32728609 # number of demand (read+write) accesses
2035system.cpu1.icache.demand_accesses::total 32728609 # number of demand (read+write) accesses
2036system.cpu1.icache.overall_accesses::cpu1.inst 32728609 # number of overall (read+write) accesses
2037system.cpu1.icache.overall_accesses::total 32728609 # number of overall (read+write) accesses
2038system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011480 # miss rate for ReadReq accesses
2039system.cpu1.icache.ReadReq_miss_rate::total 0.011480 # miss rate for ReadReq accesses
2040system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011480 # miss rate for demand accesses
2041system.cpu1.icache.demand_miss_rate::total 0.011480 # miss rate for demand accesses
2042system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011480 # miss rate for overall accesses
2043system.cpu1.icache.overall_miss_rate::total 0.011480 # miss rate for overall accesses
2044system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8407.834987 # average ReadReq miss latency
2045system.cpu1.icache.ReadReq_avg_miss_latency::total 8407.834987 # average ReadReq miss latency
2046system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency
2047system.cpu1.icache.demand_avg_miss_latency::total 8407.834987 # average overall miss latency
2048system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency
2049system.cpu1.icache.overall_avg_miss_latency::total 8407.834987 # average overall miss latency
2050system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2051system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2052system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
2053system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
2054system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2055system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2056system.cpu1.icache.fast_writes 0 # number of fast writes performed
2057system.cpu1.icache.cache_copies 0 # number of cache copies performed
2058system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 375739 # number of ReadReq MSHR misses
2059system.cpu1.icache.ReadReq_mshr_misses::total 375739 # number of ReadReq MSHR misses
2060system.cpu1.icache.demand_mshr_misses::cpu1.inst 375739 # number of demand (read+write) MSHR misses
2061system.cpu1.icache.demand_mshr_misses::total 375739 # number of demand (read+write) MSHR misses
2062system.cpu1.icache.overall_mshr_misses::cpu1.inst 375739 # number of overall MSHR misses
2063system.cpu1.icache.overall_mshr_misses::total 375739 # number of overall MSHR misses
2064system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2595414990 # number of ReadReq MSHR miss cycles
2065system.cpu1.icache.ReadReq_mshr_miss_latency::total 2595414990 # number of ReadReq MSHR miss cycles
2066system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2595414990 # number of demand (read+write) MSHR miss cycles
2067system.cpu1.icache.demand_mshr_miss_latency::total 2595414990 # number of demand (read+write) MSHR miss cycles
2068system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2595414990 # number of overall MSHR miss cycles
2069system.cpu1.icache.overall_mshr_miss_latency::total 2595414990 # number of overall MSHR miss cycles
2070system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8511750 # number of ReadReq MSHR uncacheable cycles
2071system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8511750 # number of ReadReq MSHR uncacheable cycles
2072system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8511750 # number of overall MSHR uncacheable cycles
2073system.cpu1.icache.overall_mshr_uncacheable_latency::total 8511750 # number of overall MSHR uncacheable cycles
2074system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for ReadReq accesses
2075system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011480 # mshr miss rate for ReadReq accesses
2076system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for demand accesses
2077system.cpu1.icache.demand_mshr_miss_rate::total 0.011480 # mshr miss rate for demand accesses
2078system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for overall accesses
2079system.cpu1.icache.overall_mshr_miss_rate::total 0.011480 # mshr miss rate for overall accesses
2080system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average ReadReq mshr miss latency
2081system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6907.494271 # average ReadReq mshr miss latency
2082system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency
2083system.cpu1.icache.demand_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency
2084system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency
2085system.cpu1.icache.overall_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency
2086system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2087system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2088system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2089system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2090system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2091system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 3539349 # number of hwpf identified
2092system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 109722 # number of hwpf that were already in mshr
2093system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 3291325 # number of hwpf that were already in the cache
2094system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 217 # number of hwpf that were already in the prefetch queue
2095system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
2096system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 15 # number of hwpf removed because MSHR allocated
2097system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 138070 # number of hwpf issued
2098system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 329563 # number of hwpf spanning a virtual page
2099system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
2100system.cpu1.l2cache.tags.replacements 122650 # number of replacements
2101system.cpu1.l2cache.tags.tagsinuse 15477.303394 # Cycle average of tags in use
2102system.cpu1.l2cache.tags.total_refs 769651 # Total number of references to valid blocks.
2103system.cpu1.l2cache.tags.sampled_refs 138796 # Sample count of references to valid blocks.
2104system.cpu1.l2cache.tags.avg_refs 5.545196 # Average number of references to valid blocks.
2105system.cpu1.l2cache.tags.warmup_cycle 2606454315500 # Cycle when the warmup percentage was hit.
2106system.cpu1.l2cache.tags.occ_blocks::writebacks 5482.269126 # Average occupied blocks per requestor
2107system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.040765 # Average occupied blocks per requestor
2108system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.187836 # Average occupied blocks per requestor
2109system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 603.787912 # Average occupied blocks per requestor
2110system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2723.851785 # Average occupied blocks per requestor
2111system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6655.165971 # Average occupied blocks per requestor
2112system.cpu1.l2cache.tags.occ_percent::writebacks 0.334611 # Average percentage of cache occupancy
2113system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000735 # Average percentage of cache occupancy
2114system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000011 # Average percentage of cache occupancy
2115system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036852 # Average percentage of cache occupancy
2116system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.166251 # Average percentage of cache occupancy
2117system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.406199 # Average percentage of cache occupancy
2118system.cpu1.l2cache.tags.occ_percent::total 0.944660 # Average percentage of cache occupancy
2119system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7087 # Occupied blocks per task id
2120system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
2121system.cpu1.l2cache.tags.occ_task_id_blocks::1024 9051 # Occupied blocks per task id
2122system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id
2123system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id
2124system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 481 # Occupied blocks per task id
2125system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4215 # Occupied blocks per task id
2126system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 2330 # Occupied blocks per task id
2127system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
2128system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
2129system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
2130system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
2131system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id
2132system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1744 # Occupied blocks per task id
2133system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5747 # Occupied blocks per task id
2134system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1414 # Occupied blocks per task id
2135system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.432556 # Percentage of cache occupancy per task id
2136system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
2137system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.552429 # Percentage of cache occupancy per task id
2138system.cpu1.l2cache.tags.tag_accesses 16022455 # Number of tag accesses
2139system.cpu1.l2cache.tags.data_accesses 16022455 # Number of data accesses
2140system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 6174 # number of ReadReq hits
2141system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2268 # number of ReadReq hits
2142system.cpu1.l2cache.ReadReq_hits::cpu1.inst 369218 # number of ReadReq hits
2143system.cpu1.l2cache.ReadReq_hits::cpu1.data 169436 # number of ReadReq hits
2144system.cpu1.l2cache.ReadReq_hits::total 547096 # number of ReadReq hits
2145system.cpu1.l2cache.Writeback_hits::writebacks 225255 # number of Writeback hits
2146system.cpu1.l2cache.Writeback_hits::total 225255 # number of Writeback hits
2147system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1340 # number of UpgradeReq hits
2148system.cpu1.l2cache.UpgradeReq_hits::total 1340 # number of UpgradeReq hits
2149system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 885 # number of SCUpgradeReq hits
2150system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits
2151system.cpu1.l2cache.ReadExReq_hits::cpu1.data 86607 # number of ReadExReq hits
2152system.cpu1.l2cache.ReadExReq_hits::total 86607 # number of ReadExReq hits
2153system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 6174 # number of demand (read+write) hits
2154system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2268 # number of demand (read+write) hits
2155system.cpu1.l2cache.demand_hits::cpu1.inst 369218 # number of demand (read+write) hits
2156system.cpu1.l2cache.demand_hits::cpu1.data 256043 # number of demand (read+write) hits
2157system.cpu1.l2cache.demand_hits::total 633703 # number of demand (read+write) hits
2158system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 6174 # number of overall hits
2159system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2268 # number of overall hits
2160system.cpu1.l2cache.overall_hits::cpu1.inst 369218 # number of overall hits
2161system.cpu1.l2cache.overall_hits::cpu1.data 256043 # number of overall hits
2162system.cpu1.l2cache.overall_hits::total 633703 # number of overall hits
2163system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 268 # number of ReadReq misses
2164system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 169 # number of ReadReq misses
2165system.cpu1.l2cache.ReadReq_misses::cpu1.inst 6377 # number of ReadReq misses
2166system.cpu1.l2cache.ReadReq_misses::cpu1.data 56923 # number of ReadReq misses
2167system.cpu1.l2cache.ReadReq_misses::total 63737 # number of ReadReq misses
2168system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 20417 # number of UpgradeReq misses
2169system.cpu1.l2cache.UpgradeReq_misses::total 20417 # number of UpgradeReq misses
2170system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 12784 # number of SCUpgradeReq misses
2171system.cpu1.l2cache.SCUpgradeReq_misses::total 12784 # number of SCUpgradeReq misses
2172system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses
2173system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses
2174system.cpu1.l2cache.ReadExReq_misses::cpu1.data 23524 # number of ReadExReq misses
2175system.cpu1.l2cache.ReadExReq_misses::total 23524 # number of ReadExReq misses
2176system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 268 # number of demand (read+write) misses
2177system.cpu1.l2cache.demand_misses::cpu1.itb.walker 169 # number of demand (read+write) misses
2178system.cpu1.l2cache.demand_misses::cpu1.inst 6377 # number of demand (read+write) misses
2179system.cpu1.l2cache.demand_misses::cpu1.data 80447 # number of demand (read+write) misses
2180system.cpu1.l2cache.demand_misses::total 87261 # number of demand (read+write) misses
2181system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 268 # number of overall misses
2182system.cpu1.l2cache.overall_misses::cpu1.itb.walker 169 # number of overall misses
2183system.cpu1.l2cache.overall_misses::cpu1.inst 6377 # number of overall misses
2184system.cpu1.l2cache.overall_misses::cpu1.data 80447 # number of overall misses
2185system.cpu1.l2cache.overall_misses::total 87261 # number of overall misses
2186system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 5694000 # number of ReadReq miss cycles
2187system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3369000 # number of ReadReq miss cycles
2188system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 191106990 # number of ReadReq miss cycles
2189system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1462989443 # number of ReadReq miss cycles
2190system.cpu1.l2cache.ReadReq_miss_latency::total 1663159433 # number of ReadReq miss cycles
2191system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 341145571 # number of UpgradeReq miss cycles
2192system.cpu1.l2cache.UpgradeReq_miss_latency::total 341145571 # number of UpgradeReq miss cycles
2193system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 259918262 # number of SCUpgradeReq miss cycles
2194system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 259918262 # number of SCUpgradeReq miss cycles
2195system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 478999 # number of SCUpgradeFailReq miss cycles
2196system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 478999 # number of SCUpgradeFailReq miss cycles
2197system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 892976093 # number of ReadExReq miss cycles
2198system.cpu1.l2cache.ReadExReq_miss_latency::total 892976093 # number of ReadExReq miss cycles
2199system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 5694000 # number of demand (read+write) miss cycles
2200system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3369000 # number of demand (read+write) miss cycles
2201system.cpu1.l2cache.demand_miss_latency::cpu1.inst 191106990 # number of demand (read+write) miss cycles
2202system.cpu1.l2cache.demand_miss_latency::cpu1.data 2355965536 # number of demand (read+write) miss cycles
2203system.cpu1.l2cache.demand_miss_latency::total 2556135526 # number of demand (read+write) miss cycles
2204system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 5694000 # number of overall miss cycles
2205system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3369000 # number of overall miss cycles
2206system.cpu1.l2cache.overall_miss_latency::cpu1.inst 191106990 # number of overall miss cycles
2207system.cpu1.l2cache.overall_miss_latency::cpu1.data 2355965536 # number of overall miss cycles
2208system.cpu1.l2cache.overall_miss_latency::total 2556135526 # number of overall miss cycles
2209system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6442 # number of ReadReq accesses(hits+misses)
2210system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2437 # number of ReadReq accesses(hits+misses)
2211system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 375595 # number of ReadReq accesses(hits+misses)
2212system.cpu1.l2cache.ReadReq_accesses::cpu1.data 226359 # number of ReadReq accesses(hits+misses)
2213system.cpu1.l2cache.ReadReq_accesses::total 610833 # number of ReadReq accesses(hits+misses)
2214system.cpu1.l2cache.Writeback_accesses::writebacks 225255 # number of Writeback accesses(hits+misses)
2215system.cpu1.l2cache.Writeback_accesses::total 225255 # number of Writeback accesses(hits+misses)
2216system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 21757 # number of UpgradeReq accesses(hits+misses)
2217system.cpu1.l2cache.UpgradeReq_accesses::total 21757 # number of UpgradeReq accesses(hits+misses)
2218system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 13669 # number of SCUpgradeReq accesses(hits+misses)
2219system.cpu1.l2cache.SCUpgradeReq_accesses::total 13669 # number of SCUpgradeReq accesses(hits+misses)
2220system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses)
2221system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses)
2222system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 110131 # number of ReadExReq accesses(hits+misses)
2223system.cpu1.l2cache.ReadExReq_accesses::total 110131 # number of ReadExReq accesses(hits+misses)
2224system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6442 # number of demand (read+write) accesses
2225system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2437 # number of demand (read+write) accesses
2226system.cpu1.l2cache.demand_accesses::cpu1.inst 375595 # number of demand (read+write) accesses
2227system.cpu1.l2cache.demand_accesses::cpu1.data 336490 # number of demand (read+write) accesses
2228system.cpu1.l2cache.demand_accesses::total 720964 # number of demand (read+write) accesses
2229system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6442 # number of overall (read+write) accesses
2230system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2437 # number of overall (read+write) accesses
2231system.cpu1.l2cache.overall_accesses::cpu1.inst 375595 # number of overall (read+write) accesses
2232system.cpu1.l2cache.overall_accesses::cpu1.data 336490 # number of overall (read+write) accesses
2233system.cpu1.l2cache.overall_accesses::total 720964 # number of overall (read+write) accesses
2234system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041602 # miss rate for ReadReq accesses
2235system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.069348 # miss rate for ReadReq accesses
2236system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.016978 # miss rate for ReadReq accesses
2237system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.251472 # miss rate for ReadReq accesses
2238system.cpu1.l2cache.ReadReq_miss_rate::total 0.104344 # miss rate for ReadReq accesses
2239system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.938411 # miss rate for UpgradeReq accesses
2240system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.938411 # miss rate for UpgradeReq accesses
2241system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.935255 # miss rate for SCUpgradeReq accesses
2242system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.935255 # miss rate for SCUpgradeReq accesses
2243system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2244system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2245system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.213600 # miss rate for ReadExReq accesses
2246system.cpu1.l2cache.ReadExReq_miss_rate::total 0.213600 # miss rate for ReadExReq accesses
2247system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.041602 # miss rate for demand accesses
2248system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.069348 # miss rate for demand accesses
2249system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.016978 # miss rate for demand accesses
2250system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.239077 # miss rate for demand accesses
2251system.cpu1.l2cache.demand_miss_rate::total 0.121034 # miss rate for demand accesses
2252system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.041602 # miss rate for overall accesses
2253system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.069348 # miss rate for overall accesses
2254system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.016978 # miss rate for overall accesses
2255system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.239077 # miss rate for overall accesses
2256system.cpu1.l2cache.overall_miss_rate::total 0.121034 # miss rate for overall accesses
2257system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21246.268657 # average ReadReq miss latency
2258system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19934.911243 # average ReadReq miss latency
2259system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29968.165281 # average ReadReq miss latency
2260system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 25701.200622 # average ReadReq miss latency
2261system.cpu1.l2cache.ReadReq_avg_miss_latency::total 26094.096569 # average ReadReq miss latency
2262system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 16708.898026 # average UpgradeReq miss latency
2263system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 16708.898026 # average UpgradeReq miss latency
2264system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20331.528630 # average SCUpgradeReq miss latency
2265system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20331.528630 # average SCUpgradeReq miss latency
2266system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 239499.500000 # average SCUpgradeFailReq miss latency
2267system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 239499.500000 # average SCUpgradeFailReq miss latency
2268system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37960.214802 # average ReadExReq miss latency
2269system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37960.214802 # average ReadExReq miss latency
2270system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21246.268657 # average overall miss latency
2271system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19934.911243 # average overall miss latency
2272system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29968.165281 # average overall miss latency
2273system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29285.934044 # average overall miss latency
2274system.cpu1.l2cache.demand_avg_miss_latency::total 29292.989148 # average overall miss latency
2275system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21246.268657 # average overall miss latency
2276system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19934.911243 # average overall miss latency
2277system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29968.165281 # average overall miss latency
2278system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29285.934044 # average overall miss latency
2279system.cpu1.l2cache.overall_avg_miss_latency::total 29292.989148 # average overall miss latency
2280system.cpu1.l2cache.blocked_cycles::no_mshrs 579 # number of cycles access was blocked
2281system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2282system.cpu1.l2cache.blocked::no_mshrs 19 # number of cycles access was blocked
2283system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2284system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.473684 # average number of cycles each access was blocked
2285system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2286system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2287system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2288system.cpu1.l2cache.writebacks::writebacks 66455 # number of writebacks
2289system.cpu1.l2cache.writebacks::total 66455 # number of writebacks
2290system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 767 # number of ReadReq MSHR hits
2291system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 80 # number of ReadReq MSHR hits
2292system.cpu1.l2cache.ReadReq_mshr_hits::total 847 # number of ReadReq MSHR hits
2293system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 1344 # number of ReadExReq MSHR hits
2294system.cpu1.l2cache.ReadExReq_mshr_hits::total 1344 # number of ReadExReq MSHR hits
2295system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 767 # number of demand (read+write) MSHR hits
2296system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1424 # number of demand (read+write) MSHR hits
2297system.cpu1.l2cache.demand_mshr_hits::total 2191 # number of demand (read+write) MSHR hits
2298system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 767 # number of overall MSHR hits
2299system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1424 # number of overall MSHR hits
2300system.cpu1.l2cache.overall_mshr_hits::total 2191 # number of overall MSHR hits
2301system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 268 # number of ReadReq MSHR misses
2302system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 169 # number of ReadReq MSHR misses
2303system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 5610 # number of ReadReq MSHR misses
2304system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 56843 # number of ReadReq MSHR misses
2305system.cpu1.l2cache.ReadReq_mshr_misses::total 62890 # number of ReadReq MSHR misses
2306system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 138069 # number of HardPFReq MSHR misses
2307system.cpu1.l2cache.HardPFReq_mshr_misses::total 138069 # number of HardPFReq MSHR misses
2308system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 20417 # number of UpgradeReq MSHR misses
2309system.cpu1.l2cache.UpgradeReq_mshr_misses::total 20417 # number of UpgradeReq MSHR misses
2310system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 12784 # number of SCUpgradeReq MSHR misses
2311system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 12784 # number of SCUpgradeReq MSHR misses
2312system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 2 # number of SCUpgradeFailReq MSHR misses
2313system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses
2314system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 22180 # number of ReadExReq MSHR misses
2315system.cpu1.l2cache.ReadExReq_mshr_misses::total 22180 # number of ReadExReq MSHR misses
2316system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 268 # number of demand (read+write) MSHR misses
2317system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 169 # number of demand (read+write) MSHR misses
2318system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 5610 # number of demand (read+write) MSHR misses
2319system.cpu1.l2cache.demand_mshr_misses::cpu1.data 79023 # number of demand (read+write) MSHR misses
2320system.cpu1.l2cache.demand_mshr_misses::total 85070 # number of demand (read+write) MSHR misses
2321system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 268 # number of overall MSHR misses
2322system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 169 # number of overall MSHR misses
2323system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 5610 # number of overall MSHR misses
2324system.cpu1.l2cache.overall_mshr_misses::cpu1.data 79023 # number of overall MSHR misses
2325system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 138069 # number of overall MSHR misses
2326system.cpu1.l2cache.overall_mshr_misses::total 223139 # number of overall MSHR misses
2327system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 3817500 # number of ReadReq MSHR miss cycles
2328system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2186000 # number of ReadReq MSHR miss cycles
2329system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 137414260 # number of ReadReq MSHR miss cycles
2330system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1062900207 # number of ReadReq MSHR miss cycles
2331system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1206317967 # number of ReadReq MSHR miss cycles
2332system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 7048181570 # number of HardPFReq MSHR miss cycles
2333system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 7048181570 # number of HardPFReq MSHR miss cycles
2334system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 332046976 # number of UpgradeReq MSHR miss cycles
2335system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 332046976 # number of UpgradeReq MSHR miss cycles
2336system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 180785968 # number of SCUpgradeReq MSHR miss cycles
2337system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 180785968 # number of SCUpgradeReq MSHR miss cycles
2338system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 373999 # number of SCUpgradeFailReq MSHR miss cycles
2339system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 373999 # number of SCUpgradeFailReq MSHR miss cycles
2340system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 591403879 # number of ReadExReq MSHR miss cycles
2341system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 591403879 # number of ReadExReq MSHR miss cycles
2342system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 3817500 # number of demand (read+write) MSHR miss cycles
2343system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2186000 # number of demand (read+write) MSHR miss cycles
2344system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 137414260 # number of demand (read+write) MSHR miss cycles
2345system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1654304086 # number of demand (read+write) MSHR miss cycles
2346system.cpu1.l2cache.demand_mshr_miss_latency::total 1797721846 # number of demand (read+write) MSHR miss cycles
2347system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 3817500 # number of overall MSHR miss cycles
2348system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2186000 # number of overall MSHR miss cycles
2349system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 137414260 # number of overall MSHR miss cycles
2350system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1654304086 # number of overall MSHR miss cycles
2351system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7048181570 # number of overall MSHR miss cycles
2352system.cpu1.l2cache.overall_mshr_miss_latency::total 8845903416 # number of overall MSHR miss cycles
2353system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7648750 # number of ReadReq MSHR uncacheable cycles
2354system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 12231230753 # number of ReadReq MSHR uncacheable cycles
2355system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 12238879503 # number of ReadReq MSHR uncacheable cycles
2356system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 28539732155 # number of WriteReq MSHR uncacheable cycles
2357system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28539732155 # number of WriteReq MSHR uncacheable cycles
2358system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7648750 # number of overall MSHR uncacheable cycles
2359system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 40770962908 # number of overall MSHR uncacheable cycles
2360system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 40778611658 # number of overall MSHR uncacheable cycles
2361system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for ReadReq accesses
2362system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for ReadReq accesses
2363system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for ReadReq accesses
2364system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.251119 # mshr miss rate for ReadReq accesses
2365system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.102958 # mshr miss rate for ReadReq accesses
2366system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2367system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2368system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.938411 # mshr miss rate for UpgradeReq accesses
2369system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938411 # mshr miss rate for UpgradeReq accesses
2370system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935255 # mshr miss rate for SCUpgradeReq accesses
2371system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.935255 # mshr miss rate for SCUpgradeReq accesses
2372system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2373system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2374system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.201397 # mshr miss rate for ReadExReq accesses
2375system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.201397 # mshr miss rate for ReadExReq accesses
2376system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for demand accesses
2377system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for demand accesses
2378system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for demand accesses
2379system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for demand accesses
2380system.cpu1.l2cache.demand_mshr_miss_rate::total 0.117995 # mshr miss rate for demand accesses
2381system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041602 # mshr miss rate for overall accesses
2382system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.069348 # mshr miss rate for overall accesses
2383system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for overall accesses
2384system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234845 # mshr miss rate for overall accesses
2385system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2386system.cpu1.l2cache.overall_mshr_miss_rate::total 0.309501 # mshr miss rate for overall accesses
2387system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average ReadReq mshr miss latency
2388system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average ReadReq mshr miss latency
2389system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average ReadReq mshr miss latency
2390system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 18698.875974 # average ReadReq mshr miss latency
2391system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 19181.395564 # average ReadReq mshr miss latency
2392system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365 # average HardPFReq mshr miss latency
2393system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51048.255365 # average HardPFReq mshr miss latency
2394system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16263.259832 # average UpgradeReq mshr miss latency
2395system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16263.259832 # average UpgradeReq mshr miss latency
2396system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14141.580726 # average SCUpgradeReq mshr miss latency
2397system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14141.580726 # average SCUpgradeReq mshr miss latency
2398system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186999.500000 # average SCUpgradeFailReq mshr miss latency
2399system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186999.500000 # average SCUpgradeFailReq mshr miss latency
2400system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 26663.835843 # average ReadExReq mshr miss latency
2401system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26663.835843 # average ReadExReq mshr miss latency
2402system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average overall mshr miss latency
2403system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average overall mshr miss latency
2404system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency
2405system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20934.463207 # average overall mshr miss latency
2406system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21132.265734 # average overall mshr miss latency
2407system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14244.402985 # average overall mshr miss latency
2408system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12934.911243 # average overall mshr miss latency
2409system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24494.520499 # average overall mshr miss latency
2410system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20934.463207 # average overall mshr miss latency
2411system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365 # average overall mshr miss latency
2412system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39643.018101 # average overall mshr miss latency
2413system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2414system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2415system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2416system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2417system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2418system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2419system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2420system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2421system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2422system.cpu1.dcache.tags.replacements 313601 # number of replacements
2423system.cpu1.dcache.tags.tagsinuse 474.302028 # Cycle average of tags in use
2424system.cpu1.dcache.tags.total_refs 10949850 # Total number of references to valid blocks.
2425system.cpu1.dcache.tags.sampled_refs 314113 # Sample count of references to valid blocks.
2426system.cpu1.dcache.tags.avg_refs 34.859589 # Average number of references to valid blocks.
2427system.cpu1.dcache.tags.warmup_cycle 76456711000 # Cycle when the warmup percentage was hit.
2428system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.302028 # Average occupied blocks per requestor
2429system.cpu1.dcache.tags.occ_percent::cpu1.data 0.926371 # Average percentage of cache occupancy
2430system.cpu1.dcache.tags.occ_percent::total 0.926371 # Average percentage of cache occupancy
2431system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2432system.cpu1.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
2433system.cpu1.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id
2434system.cpu1.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
2435system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2436system.cpu1.dcache.tags.tag_accesses 22948274 # Number of tag accesses
2437system.cpu1.dcache.tags.data_accesses 22948274 # Number of data accesses
2438system.cpu1.dcache.ReadReq_hits::cpu1.data 6183420 # number of ReadReq hits
2439system.cpu1.dcache.ReadReq_hits::total 6183420 # number of ReadReq hits
2440system.cpu1.dcache.WriteReq_hits::cpu1.data 4558750 # number of WriteReq hits
2441system.cpu1.dcache.WriteReq_hits::total 4558750 # number of WriteReq hits
2442system.cpu1.dcache.SoftPFReq_hits::cpu1.data 19290 # number of SoftPFReq hits
2443system.cpu1.dcache.SoftPFReq_hits::total 19290 # number of SoftPFReq hits
2444system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77402 # number of LoadLockedReq hits
2445system.cpu1.dcache.LoadLockedReq_hits::total 77402 # number of LoadLockedReq hits
2446system.cpu1.dcache.StoreCondReq_hits::cpu1.data 75753 # number of StoreCondReq hits
2447system.cpu1.dcache.StoreCondReq_hits::total 75753 # number of StoreCondReq hits
2448system.cpu1.dcache.demand_hits::cpu1.data 10742170 # number of demand (read+write) hits
2449system.cpu1.dcache.demand_hits::total 10742170 # number of demand (read+write) hits
2450system.cpu1.dcache.overall_hits::cpu1.data 10761460 # number of overall hits
2451system.cpu1.dcache.overall_hits::total 10761460 # number of overall hits
2452system.cpu1.dcache.ReadReq_misses::cpu1.data 187243 # number of ReadReq misses
2453system.cpu1.dcache.ReadReq_misses::total 187243 # number of ReadReq misses
2454system.cpu1.dcache.WriteReq_misses::cpu1.data 134937 # number of WriteReq misses
2455system.cpu1.dcache.WriteReq_misses::total 134937 # number of WriteReq misses
2456system.cpu1.dcache.SoftPFReq_misses::cpu1.data 43327 # number of SoftPFReq misses
2457system.cpu1.dcache.SoftPFReq_misses::total 43327 # number of SoftPFReq misses
2458system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12089 # number of LoadLockedReq misses
2459system.cpu1.dcache.LoadLockedReq_misses::total 12089 # number of LoadLockedReq misses
2460system.cpu1.dcache.StoreCondReq_misses::cpu1.data 13673 # number of StoreCondReq misses
2461system.cpu1.dcache.StoreCondReq_misses::total 13673 # number of StoreCondReq misses
2462system.cpu1.dcache.demand_misses::cpu1.data 322180 # number of demand (read+write) misses
2463system.cpu1.dcache.demand_misses::total 322180 # number of demand (read+write) misses
2464system.cpu1.dcache.overall_misses::cpu1.data 365507 # number of overall misses
2465system.cpu1.dcache.overall_misses::total 365507 # number of overall misses
2466system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2299329756 # number of ReadReq miss cycles
2467system.cpu1.dcache.ReadReq_miss_latency::total 2299329756 # number of ReadReq miss cycles
2468system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2509975628 # number of WriteReq miss cycles
2469system.cpu1.dcache.WriteReq_miss_latency::total 2509975628 # number of WriteReq miss cycles
2470system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 218034000 # number of LoadLockedReq miss cycles
2471system.cpu1.dcache.LoadLockedReq_miss_latency::total 218034000 # number of LoadLockedReq miss cycles
2472system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 317344970 # number of StoreCondReq miss cycles
2473system.cpu1.dcache.StoreCondReq_miss_latency::total 317344970 # number of StoreCondReq miss cycles
2474system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 524000 # number of StoreCondFailReq miss cycles
2475system.cpu1.dcache.StoreCondFailReq_miss_latency::total 524000 # number of StoreCondFailReq miss cycles
2476system.cpu1.dcache.demand_miss_latency::cpu1.data 4809305384 # number of demand (read+write) miss cycles
2477system.cpu1.dcache.demand_miss_latency::total 4809305384 # number of demand (read+write) miss cycles
2478system.cpu1.dcache.overall_miss_latency::cpu1.data 4809305384 # number of overall miss cycles
2479system.cpu1.dcache.overall_miss_latency::total 4809305384 # number of overall miss cycles
2480system.cpu1.dcache.ReadReq_accesses::cpu1.data 6370663 # number of ReadReq accesses(hits+misses)
2481system.cpu1.dcache.ReadReq_accesses::total 6370663 # number of ReadReq accesses(hits+misses)
2482system.cpu1.dcache.WriteReq_accesses::cpu1.data 4693687 # number of WriteReq accesses(hits+misses)
2483system.cpu1.dcache.WriteReq_accesses::total 4693687 # number of WriteReq accesses(hits+misses)
2484system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 62617 # number of SoftPFReq accesses(hits+misses)
2485system.cpu1.dcache.SoftPFReq_accesses::total 62617 # number of SoftPFReq accesses(hits+misses)
2486system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89491 # number of LoadLockedReq accesses(hits+misses)
2487system.cpu1.dcache.LoadLockedReq_accesses::total 89491 # number of LoadLockedReq accesses(hits+misses)
2488system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89426 # number of StoreCondReq accesses(hits+misses)
2489system.cpu1.dcache.StoreCondReq_accesses::total 89426 # number of StoreCondReq accesses(hits+misses)
2490system.cpu1.dcache.demand_accesses::cpu1.data 11064350 # number of demand (read+write) accesses
2491system.cpu1.dcache.demand_accesses::total 11064350 # number of demand (read+write) accesses
2492system.cpu1.dcache.overall_accesses::cpu1.data 11126967 # number of overall (read+write) accesses
2493system.cpu1.dcache.overall_accesses::total 11126967 # number of overall (read+write) accesses
2494system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029391 # miss rate for ReadReq accesses
2495system.cpu1.dcache.ReadReq_miss_rate::total 0.029391 # miss rate for ReadReq accesses
2496system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028749 # miss rate for WriteReq accesses
2497system.cpu1.dcache.WriteReq_miss_rate::total 0.028749 # miss rate for WriteReq accesses
2498system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.691937 # miss rate for SoftPFReq accesses
2499system.cpu1.dcache.SoftPFReq_miss_rate::total 0.691937 # miss rate for SoftPFReq accesses
2500system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135086 # miss rate for LoadLockedReq accesses
2501system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135086 # miss rate for LoadLockedReq accesses
2502system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.152897 # miss rate for StoreCondReq accesses
2503system.cpu1.dcache.StoreCondReq_miss_rate::total 0.152897 # miss rate for StoreCondReq accesses
2504system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029119 # miss rate for demand accesses
2505system.cpu1.dcache.demand_miss_rate::total 0.029119 # miss rate for demand accesses
2506system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032849 # miss rate for overall accesses
2507system.cpu1.dcache.overall_miss_rate::total 0.032849 # miss rate for overall accesses
2508system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12279.923714 # average ReadReq miss latency
2509system.cpu1.dcache.ReadReq_avg_miss_latency::total 12279.923714 # average ReadReq miss latency
2510system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18601.092569 # average WriteReq miss latency
2511system.cpu1.dcache.WriteReq_avg_miss_latency::total 18601.092569 # average WriteReq miss latency
2512system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18035.734966 # average LoadLockedReq miss latency
2513system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18035.734966 # average LoadLockedReq miss latency
2514system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23209.607987 # average StoreCondReq miss latency
2515system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23209.607987 # average StoreCondReq miss latency
2516system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2517system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2518system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14927.386504 # average overall miss latency
2519system.cpu1.dcache.demand_avg_miss_latency::total 14927.386504 # average overall miss latency
2520system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13157.902267 # average overall miss latency
2521system.cpu1.dcache.overall_avg_miss_latency::total 13157.902267 # average overall miss latency
2522system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2523system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2524system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
2525system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
2526system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2527system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2528system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2529system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2530system.cpu1.dcache.writebacks::writebacks 225255 # number of writebacks
2531system.cpu1.dcache.writebacks::total 225255 # number of writebacks
2532system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 794 # number of ReadReq MSHR hits
2533system.cpu1.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits
2534system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 3242 # number of WriteReq MSHR hits
2535system.cpu1.dcache.WriteReq_mshr_hits::total 3242 # number of WriteReq MSHR hits
2536system.cpu1.dcache.demand_mshr_hits::cpu1.data 4036 # number of demand (read+write) MSHR hits
2537system.cpu1.dcache.demand_mshr_hits::total 4036 # number of demand (read+write) MSHR hits
2538system.cpu1.dcache.overall_mshr_hits::cpu1.data 4036 # number of overall MSHR hits
2539system.cpu1.dcache.overall_mshr_hits::total 4036 # number of overall MSHR hits
2540system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 186449 # number of ReadReq MSHR misses
2541system.cpu1.dcache.ReadReq_mshr_misses::total 186449 # number of ReadReq MSHR misses
2542system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 131695 # number of WriteReq MSHR misses
2543system.cpu1.dcache.WriteReq_mshr_misses::total 131695 # number of WriteReq MSHR misses
2544system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 27821 # number of SoftPFReq MSHR misses
2545system.cpu1.dcache.SoftPFReq_mshr_misses::total 27821 # number of SoftPFReq MSHR misses
2546system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12089 # number of LoadLockedReq MSHR misses
2547system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12089 # number of LoadLockedReq MSHR misses
2548system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 13671 # number of StoreCondReq MSHR misses
2549system.cpu1.dcache.StoreCondReq_mshr_misses::total 13671 # number of StoreCondReq MSHR misses
2550system.cpu1.dcache.demand_mshr_misses::cpu1.data 318144 # number of demand (read+write) MSHR misses
2551system.cpu1.dcache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses
2552system.cpu1.dcache.overall_mshr_misses::cpu1.data 345965 # number of overall MSHR misses
2553system.cpu1.dcache.overall_mshr_misses::total 345965 # number of overall MSHR misses
2554system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1916001744 # number of ReadReq MSHR miss cycles
2555system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1916001744 # number of ReadReq MSHR miss cycles
2556system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2027549872 # number of WriteReq MSHR miss cycles
2557system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2027549872 # number of WriteReq MSHR miss cycles
2558system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 596503999 # number of SoftPFReq MSHR miss cycles
2559system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 596503999 # number of SoftPFReq MSHR miss cycles
2560system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 193851000 # number of LoadLockedReq MSHR miss cycles
2561system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 193851000 # number of LoadLockedReq MSHR miss cycles
2562system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 289002030 # number of StoreCondReq MSHR miss cycles
2563system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 289002030 # number of StoreCondReq MSHR miss cycles
2564system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 494000 # number of StoreCondFailReq MSHR miss cycles
2565system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 494000 # number of StoreCondFailReq MSHR miss cycles
2566system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3943551616 # number of demand (read+write) MSHR miss cycles
2567system.cpu1.dcache.demand_mshr_miss_latency::total 3943551616 # number of demand (read+write) MSHR miss cycles
2568system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4540055615 # number of overall MSHR miss cycles
2569system.cpu1.dcache.overall_mshr_miss_latency::total 4540055615 # number of overall MSHR miss cycles
2570system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 12848996742 # number of ReadReq MSHR uncacheable cycles
2571system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 12848996742 # number of ReadReq MSHR uncacheable cycles
2572system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34213847345 # number of WriteReq MSHR uncacheable cycles
2573system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34213847345 # number of WriteReq MSHR uncacheable cycles
2574system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 47062844087 # number of overall MSHR uncacheable cycles
2575system.cpu1.dcache.overall_mshr_uncacheable_latency::total 47062844087 # number of overall MSHR uncacheable cycles
2576system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029267 # mshr miss rate for ReadReq accesses
2577system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029267 # mshr miss rate for ReadReq accesses
2578system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028058 # mshr miss rate for WriteReq accesses
2579system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028058 # mshr miss rate for WriteReq accesses
2580system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.444304 # mshr miss rate for SoftPFReq accesses
2581system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.444304 # mshr miss rate for SoftPFReq accesses
2582system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.135086 # mshr miss rate for LoadLockedReq accesses
2583system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.135086 # mshr miss rate for LoadLockedReq accesses
2584system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.152875 # mshr miss rate for StoreCondReq accesses
2585system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.152875 # mshr miss rate for StoreCondReq accesses
2586system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028754 # mshr miss rate for demand accesses
2587system.cpu1.dcache.demand_mshr_miss_rate::total 0.028754 # mshr miss rate for demand accesses
2588system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031092 # mshr miss rate for overall accesses
2589system.cpu1.dcache.overall_mshr_miss_rate::total 0.031092 # mshr miss rate for overall accesses
2590system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10276.277931 # average ReadReq mshr miss latency
2591system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10276.277931 # average ReadReq mshr miss latency
2592system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15395.799932 # average WriteReq mshr miss latency
2593system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15395.799932 # average WriteReq mshr miss latency
2594system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21440.782107 # average SoftPFReq mshr miss latency
2595system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21440.782107 # average SoftPFReq mshr miss latency
2596system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16035.321367 # average LoadLockedReq mshr miss latency
2597system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16035.321367 # average LoadLockedReq mshr miss latency
2598system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21139.787141 # average StoreCondReq mshr miss latency
2599system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21139.787141 # average StoreCondReq mshr miss latency
2600system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2601system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2602system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12395.492657 # average overall mshr miss latency
2603system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12395.492657 # average overall mshr miss latency
2604system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13122.875479 # average overall mshr miss latency
2605system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13122.875479 # average overall mshr miss latency
2606system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2607system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2608system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2609system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2610system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2611system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2612system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2613system.cpu1.toL2Bus.trans_dist::ReadReq 957719 # Transaction distribution
2614system.cpu1.toL2Bus.trans_dist::ReadResp 715905 # Transaction distribution
2615system.cpu1.toL2Bus.trans_dist::WriteReq 756547 # Transaction distribution
2616system.cpu1.toL2Bus.trans_dist::WriteResp 756547 # Transaction distribution
2617system.cpu1.toL2Bus.trans_dist::Writeback 225255 # Transaction distribution
2618system.cpu1.toL2Bus.trans_dist::HardPFReq 189199 # Transaction distribution
2619system.cpu1.toL2Bus.trans_dist::UpgradeReq 53977 # Transaction distribution
2620system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23970 # Transaction distribution
2621system.cpu1.toL2Bus.trans_dist::UpgradeResp 50977 # Transaction distribution
2622system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution
2623system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution
2624system.cpu1.toL2Bus.trans_dist::ReadExReq 119927 # Transaction distribution
2625system.cpu1.toL2Bus.trans_dist::ReadExResp 111476 # Transaction distribution
2626system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 751552 # Packet count per connected master and slave (bytes)
2627system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 2675268 # Packet count per connected master and slave (bytes)
2628system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6827 # Packet count per connected master and slave (bytes)
2629system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16819 # Packet count per connected master and slave (bytes)
2630system.cpu1.toL2Bus.pkt_count::total 3450466 # Packet count per connected master and slave (bytes)
2631system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24038516 # Cumulative packet size per connected master and slave (bytes)
2632system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 40612602 # Cumulative packet size per connected master and slave (bytes)
2633system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9748 # Cumulative packet size per connected master and slave (bytes)
2634system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25768 # Cumulative packet size per connected master and slave (bytes)
2635system.cpu1.toL2Bus.pkt_size::total 64686634 # Cumulative packet size per connected master and slave (bytes)
2636system.cpu1.toL2Bus.snoops 549743 # Total snoops (count)
2637system.cpu1.toL2Bus.snoop_fanout::samples 1492746 # Request fanout histogram
2638system.cpu1.toL2Bus.snoop_fanout::mean 5.338347 # Request fanout histogram
2639system.cpu1.toL2Bus.snoop_fanout::stdev 0.473147 # Request fanout histogram
2640system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2641system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2642system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2643system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2644system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
2645system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
2646system.cpu1.toL2Bus.snoop_fanout::5 987680 66.17% 66.17% # Request fanout histogram
2647system.cpu1.toL2Bus.snoop_fanout::6 505066 33.83% 100.00% # Request fanout histogram
2648system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2649system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
2650system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
2651system.cpu1.toL2Bus.snoop_fanout::total 1492746 # Request fanout histogram
2652system.cpu1.toL2Bus.reqLayer0.occupancy 1514414783 # Layer occupancy (ticks)
2653system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2654system.cpu1.toL2Bus.snoopLayer0.occupancy 42402999 # Layer occupancy (ticks)
2655system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2656system.cpu1.toL2Bus.respLayer0.occupancy 563804260 # Layer occupancy (ticks)
2657system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2658system.cpu1.toL2Bus.respLayer1.occupancy 984220768 # Layer occupancy (ticks)
2659system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2660system.cpu1.toL2Bus.respLayer2.occupancy 4390000 # Layer occupancy (ticks)
2661system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2662system.cpu1.toL2Bus.respLayer3.occupancy 10377250 # Layer occupancy (ticks)
2663system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2664system.iocache.tags.replacements 0 # number of replacements
2665system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
2666system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2667system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
2668system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
2669system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2670system.iocache.tags.tag_accesses 0 # Number of tag accesses
2671system.iocache.tags.data_accesses 0 # Number of data accesses
2672system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2673system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2674system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2675system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2676system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2677system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2678system.iocache.fast_writes 0 # number of fast writes performed
2679system.iocache.cache_copies 0 # number of cache copies performed
2680system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of ReadReq MSHR uncacheable cycles
2681system.iocache.ReadReq_mshr_uncacheable_latency::total 1782387791115 # number of ReadReq MSHR uncacheable cycles
2682system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of overall MSHR uncacheable cycles
2683system.iocache.overall_mshr_uncacheable_latency::total 1782387791115 # number of overall MSHR uncacheable cycles
2684system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
2685system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2686system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
2687system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2688system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2689
2690---------- End Simulation Statistics ----------