1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.194312 # Number of seconds simulated
4sim_ticks 1194312178000 # Number of ticks simulated
5final_tick 1194312178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 475403 # Simulator instruction rate (inst/s)
8host_op_rate 567868 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9241250441 # Simulator tick rate (ticks/s)
10host_mem_usage 438040 # Number of bytes of host memory used
11host_seconds 129.24 # Real time elapsed on the host
12sim_insts 61439698 # Number of instructions simulated
13sim_ops 73389630 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 393932 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 4710012 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 323460 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 4796088 # Number of bytes read from this memory
25system.physmem.bytes_read::total 62128516 # Number of bytes read from this memory
26system.physmem.bytes_inst_read::cpu0.inst 393932 # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::cpu1.inst 323460 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::total 717392 # Number of instructions bytes read from this memory
29system.physmem.bytes_written::writebacks 4097216 # Number of bytes written to this memory
30system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
32system.physmem.bytes_written::total 7124560 # Number of bytes written to this memory
33system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.inst 12383 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.data 73653 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.inst 5145 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.data 74957 # Number of read requests responded to by this memory
42system.physmem.num_reads::total 6654210 # Number of read requests responded to by this memory
43system.physmem.num_writes::writebacks 64019 # Number of write requests responded to by this memory
44system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
45system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
46system.physmem.num_writes::total 820855 # Number of write requests responded to by this memory
47system.physmem.bw_read::realview.clcd 43459753 # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.inst 329840 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.data 3943703 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.inst 270834 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.data 4015774 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::total 52020332 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_inst_read::cpu0.inst 329840 # Instruction read bandwidth from this memory (bytes/s)
58system.physmem.bw_inst_read::cpu1.inst 270834 # Instruction read bandwidth from this memory (bytes/s)
59system.physmem.bw_inst_read::total 600674 # Instruction read bandwidth from this memory (bytes/s)
60system.physmem.bw_write::writebacks 3430607 # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_write::cpu0.data 14234 # Write bandwidth from this memory (bytes/s)
62system.physmem.bw_write::cpu1.data 2520567 # Write bandwidth from this memory (bytes/s)
63system.physmem.bw_write::total 5965408 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_total::writebacks 3430607 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::realview.clcd 43459753 # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.inst 329840 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.data 3957937 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu1.inst 270834 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu1.data 6536341 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::total 57985740 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.readReqs 6654210 # Number of read requests accepted
76system.physmem.writeReqs 820855 # Number of write requests accepted
77system.physmem.readBursts 6654210 # Number of DRAM read bursts, including those serviced by the write queue
78system.physmem.writeBursts 820855 # Number of DRAM write bursts, including those merged in the write queue
79system.physmem.bytesReadDRAM 425838464 # Total number of bytes read from DRAM
80system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue
81system.physmem.bytesWritten 7136448 # Total number of bytes written to DRAM
82system.physmem.bytesReadSys 62128516 # Total read bytes from the system interface side
83system.physmem.bytesWrittenSys 7124560 # Total written bytes from the system interface side
84system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue
85system.physmem.mergedWrBursts 709321 # Number of DRAM write bursts merged with an existing one
86system.physmem.neitherReadNorWriteReqs 12079 # Number of requests that are neither read nor write
87system.physmem.perBankRdBursts::0 415236 # Per bank write bursts
88system.physmem.perBankRdBursts::1 415218 # Per bank write bursts
89system.physmem.perBankRdBursts::2 415240 # Per bank write bursts
90system.physmem.perBankRdBursts::3 415658 # Per bank write bursts
91system.physmem.perBankRdBursts::4 422402 # Per bank write bursts
92system.physmem.perBankRdBursts::5 415506 # Per bank write bursts
93system.physmem.perBankRdBursts::6 415779 # Per bank write bursts
94system.physmem.perBankRdBursts::7 415682 # Per bank write bursts
95system.physmem.perBankRdBursts::8 416047 # Per bank write bursts
96system.physmem.perBankRdBursts::9 415577 # Per bank write bursts
97system.physmem.perBankRdBursts::10 415398 # Per bank write bursts
98system.physmem.perBankRdBursts::11 414862 # Per bank write bursts
99system.physmem.perBankRdBursts::12 415007 # Per bank write bursts
100system.physmem.perBankRdBursts::13 415552 # Per bank write bursts
101system.physmem.perBankRdBursts::14 415496 # Per bank write bursts
102system.physmem.perBankRdBursts::15 415066 # Per bank write bursts
103system.physmem.perBankWrBursts::0 6763 # Per bank write bursts
104system.physmem.perBankWrBursts::1 6728 # Per bank write bursts
105system.physmem.perBankWrBursts::2 6819 # Per bank write bursts
106system.physmem.perBankWrBursts::3 7055 # Per bank write bursts
107system.physmem.perBankWrBursts::4 7301 # Per bank write bursts
108system.physmem.perBankWrBursts::5 7028 # Per bank write bursts
109system.physmem.perBankWrBursts::6 7316 # Per bank write bursts
110system.physmem.perBankWrBursts::7 7231 # Per bank write bursts
111system.physmem.perBankWrBursts::8 7485 # Per bank write bursts
112system.physmem.perBankWrBursts::9 7107 # Per bank write bursts
113system.physmem.perBankWrBursts::10 7000 # Per bank write bursts
114system.physmem.perBankWrBursts::11 6549 # Per bank write bursts
115system.physmem.perBankWrBursts::12 6696 # Per bank write bursts
116system.physmem.perBankWrBursts::13 6902 # Per bank write bursts
117system.physmem.perBankWrBursts::14 6960 # Per bank write bursts
118system.physmem.perBankWrBursts::15 6567 # Per bank write bursts
119system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
120system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
121system.physmem.totGap 1194307723500 # Total gap between requests
122system.physmem.readPktSize::0 0 # Read request sizes (log2)
123system.physmem.readPktSize::1 0 # Read request sizes (log2)
124system.physmem.readPktSize::2 6799 # Read request sizes (log2)
125system.physmem.readPktSize::3 6488089 # Read request sizes (log2)
126system.physmem.readPktSize::4 0 # Read request sizes (log2)
127system.physmem.readPktSize::5 0 # Read request sizes (log2)
128system.physmem.readPktSize::6 159322 # Read request sizes (log2)
129system.physmem.writePktSize::0 0 # Write request sizes (log2)
130system.physmem.writePktSize::1 0 # Write request sizes (log2)
131system.physmem.writePktSize::2 756836 # Write request sizes (log2)
132system.physmem.writePktSize::3 0 # Write request sizes (log2)
133system.physmem.writePktSize::4 0 # Write request sizes (log2)
134system.physmem.writePktSize::5 0 # Write request sizes (log2)
135system.physmem.writePktSize::6 64019 # Write request sizes (log2)
136system.physmem.rdQLenPdf::0 572550 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::1 410650 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::2 412558 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::3 460055 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::4 417389 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::5 445707 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::6 1151151 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::7 1116358 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::8 1442650 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::9 62467 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::10 48974 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::11 44870 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::12 43130 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::13 8689 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::14 8270 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::15 8147 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
168system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::15 3883 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::16 3903 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::17 6452 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::18 6480 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::19 6485 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::20 6485 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::21 6491 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::22 6485 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::23 6483 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::24 6485 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::25 6483 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::26 6486 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::27 6495 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::28 6488 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::29 6484 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::30 6486 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::31 6484 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::32 6481 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
232system.physmem.bytesPerActivate::samples 473292 # Bytes accessed per row activation
233system.physmem.bytesPerActivate::mean 914.815615 # Bytes accessed per row activation
234system.physmem.bytesPerActivate::gmean 785.169464 # Bytes accessed per row activation
235system.physmem.bytesPerActivate::stdev 288.643252 # Bytes accessed per row activation
236system.physmem.bytesPerActivate::0-127 25022 5.29% 5.29% # Bytes accessed per row activation
237system.physmem.bytesPerActivate::128-255 21566 4.56% 9.84% # Bytes accessed per row activation
238system.physmem.bytesPerActivate::256-383 5869 1.24% 11.08% # Bytes accessed per row activation
239system.physmem.bytesPerActivate::384-511 2391 0.51% 11.59% # Bytes accessed per row activation
240system.physmem.bytesPerActivate::512-639 2344 0.50% 12.08% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::640-767 1629 0.34% 12.43% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::768-895 4093 0.86% 13.29% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::896-1023 899 0.19% 13.48% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::1024-1151 409479 86.52% 100.00% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::total 473292 # Bytes accessed per row activation
246system.physmem.rdPerTurnAround::samples 6481 # Reads before turning the bus around for writes
247system.physmem.rdPerTurnAround::mean 1026.648974 # Reads before turning the bus around for writes
248system.physmem.rdPerTurnAround::stdev 26505.494009 # Reads before turning the bus around for writes
249system.physmem.rdPerTurnAround::0-65535 6473 99.88% 99.88% # Reads before turning the bus around for writes
250system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.89% # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::total 6481 # Reads before turning the bus around for writes
257system.physmem.wrPerTurnAround::samples 6481 # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::mean 17.205215 # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::gmean 17.176618 # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::stdev 0.984217 # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::16 2581 39.82% 39.82% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::17 15 0.23% 40.06% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::18 3862 59.59% 99.65% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::19 20 0.31% 99.95% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::total 6481 # Writes before turning the bus around for reads
267system.physmem.totQLat 170730095750 # Total ticks spent queuing
268system.physmem.totMemAccLat 295487458250 # Total ticks spent from burst creation until serviced by the DRAM
269system.physmem.totBusLat 33268630000 # Total ticks spent in databus transfers
270system.physmem.avgQLat 25659.32 # Average queueing delay per DRAM burst
271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
272system.physmem.avgMemAccLat 44409.32 # Average memory access latency per DRAM burst
273system.physmem.avgRdBW 356.56 # Average DRAM read bandwidth in MiByte/s
274system.physmem.avgWrBW 5.98 # Average achieved write bandwidth in MiByte/s
275system.physmem.avgRdBWSys 52.02 # Average system read bandwidth in MiByte/s
276system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s
277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
278system.physmem.busUtil 2.83 # Data bus utilization in percentage
279system.physmem.busUtilRead 2.79 # Data bus utilization in percentage for reads
280system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes
281system.physmem.avgRdQLen 4.36 # Average read queue length when enqueuing
282system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing
283system.physmem.readRowHits 6199598 # Number of row buffer hits during reads
284system.physmem.writeRowHits 92343 # Number of row buffer hits during writes
285system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads
286system.physmem.writeRowHitRate 82.79 # Row buffer hit rate for writes
287system.physmem.avgGap 159772.22 # Average gap between requests
288system.physmem.pageHitRate 93.00 # Row buffer hit rate, read and write combined
289system.physmem.memoryStateTime::IDLE 945808643750 # Time in different power states
290system.physmem.memoryStateTime::REF 39880620000 # Time in different power states
291system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
292system.physmem.memoryStateTime::ACT 208620525000 # Time in different power states
293system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
294system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
295system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
296system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
297system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
298system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
299system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
300system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
301system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
302system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
303system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
304system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s)
305system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
306system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
307system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s)
308system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
309system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
310system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
311system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
312system.membus.throughput 60005732 # Throughput (bytes/s)
313system.membus.trans_dist::ReadReq 7703348 # Transaction distribution
314system.membus.trans_dist::ReadResp 7703348 # Transaction distribution
315system.membus.trans_dist::WriteReq 767581 # Transaction distribution
316system.membus.trans_dist::WriteResp 767581 # Transaction distribution
317system.membus.trans_dist::Writeback 64019 # Transaction distribution
318system.membus.trans_dist::UpgradeReq 31325 # Transaction distribution
319system.membus.trans_dist::SCUpgradeReq 17234 # Transaction distribution
320system.membus.trans_dist::UpgradeResp 12079 # Transaction distribution
321system.membus.trans_dist::ReadExReq 137481 # Transaction distribution
322system.membus.trans_dist::ReadExResp 137066 # Transaction distribution
323system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382642 # Packet count per connected master and slave (bytes)
324system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
325system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10312 # Packet count per connected master and slave (bytes)
326system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
327system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes)
328system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971036 # Packet count per connected master and slave (bytes)
329system.membus.pkt_count_system.l2c.mem_side::total 4364934 # Packet count per connected master and slave (bytes)
330system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes)
331system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes)
332system.membus.pkt_count::total 17341062 # Packet count per connected master and slave (bytes)
333system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389989 # Cumulative packet size per connected master and slave (bytes)
334system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
335system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20624 # Cumulative packet size per connected master and slave (bytes)
336system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
337system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes)
338system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17348564 # Cumulative packet size per connected master and slave (bytes)
339system.membus.tot_pkt_size_system.l2c.mem_side::total 19761065 # Cumulative packet size per connected master and slave (bytes)
340system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes)
341system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes)
342system.membus.tot_pkt_size::total 71665577 # Cumulative packet size per connected master and slave (bytes)
343system.membus.data_through_bus 71665577 # Total data (bytes)
344system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
345system.membus.reqLayer0.occupancy 1224785500 # Layer occupancy (ticks)
346system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
347system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks)
348system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
349system.membus.reqLayer2.occupancy 9231500 # Layer occupancy (ticks)
350system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
351system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks)
352system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
353system.membus.reqLayer5.occupancy 778500 # Layer occupancy (ticks)
354system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
355system.membus.reqLayer6.occupancy 9212282000 # Layer occupancy (ticks)
356system.membus.reqLayer6.utilization 0.8 # Layer utilization (%)
357system.membus.respLayer1.occupancy 5079172023 # Layer occupancy (ticks)
358system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
359system.membus.respLayer2.occupancy 16050388750 # Layer occupancy (ticks)
360system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
361system.cpu_clk_domain.clock 500 # Clock period in ticks
362system.l2c.tags.replacements 69203 # number of replacements
363system.l2c.tags.tagsinuse 52959.316379 # Cycle average of tags in use
364system.l2c.tags.total_refs 1672724 # Total number of references to valid blocks.
365system.l2c.tags.sampled_refs 134375 # Sample count of references to valid blocks.
366system.l2c.tags.avg_refs 12.448179 # Average number of references to valid blocks.
367system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
368system.l2c.tags.occ_blocks::writebacks 40136.915421 # Average occupied blocks per requestor
369system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor
370system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor
371system.l2c.tags.occ_blocks::cpu0.inst 3716.167205 # Average occupied blocks per requestor
372system.l2c.tags.occ_blocks::cpu0.data 4233.542603 # Average occupied blocks per requestor
373system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.741623 # Average occupied blocks per requestor
374system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001622 # Average occupied blocks per requestor
375system.l2c.tags.occ_blocks::cpu1.inst 2809.362324 # Average occupied blocks per requestor
376system.l2c.tags.occ_blocks::cpu1.data 2060.583626 # Average occupied blocks per requestor
377system.l2c.tags.occ_percent::writebacks 0.612441 # Average percentage of cache occupancy
378system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
379system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
380system.l2c.tags.occ_percent::cpu0.inst 0.056704 # Average percentage of cache occupancy
381system.l2c.tags.occ_percent::cpu0.data 0.064599 # Average percentage of cache occupancy
382system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
383system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
384system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy
385system.l2c.tags.occ_percent::cpu1.data 0.031442 # Average percentage of cache occupancy
386system.l2c.tags.occ_percent::total 0.808095 # Average percentage of cache occupancy
387system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
388system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id
389system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
390system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
391system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id
392system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
393system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id
394system.l2c.tags.age_task_id_blocks_1024::3 8176 # Occupied blocks per task id
395system.l2c.tags.age_task_id_blocks_1024::4 55031 # Occupied blocks per task id
396system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
397system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id
398system.l2c.tags.tag_accesses 17204185 # Number of tag accesses
399system.l2c.tags.data_accesses 17204185 # Number of data accesses
400system.l2c.ReadReq_hits::cpu0.dtb.walker 3944 # number of ReadReq hits
401system.l2c.ReadReq_hits::cpu0.itb.walker 1786 # number of ReadReq hits
402system.l2c.ReadReq_hits::cpu0.inst 419390 # number of ReadReq hits
403system.l2c.ReadReq_hits::cpu0.data 205855 # number of ReadReq hits
404system.l2c.ReadReq_hits::cpu1.dtb.walker 5333 # number of ReadReq hits
405system.l2c.ReadReq_hits::cpu1.itb.walker 1846 # number of ReadReq hits
406system.l2c.ReadReq_hits::cpu1.inst 464270 # number of ReadReq hits
407system.l2c.ReadReq_hits::cpu1.data 143434 # number of ReadReq hits
408system.l2c.ReadReq_hits::total 1245858 # number of ReadReq hits
409system.l2c.Writeback_hits::writebacks 570720 # number of Writeback hits
410system.l2c.Writeback_hits::total 570720 # number of Writeback hits
411system.l2c.UpgradeReq_hits::cpu0.data 1291 # number of UpgradeReq hits
412system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits
413system.l2c.UpgradeReq_hits::total 1814 # number of UpgradeReq hits
414system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits
415system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits
416system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits
417system.l2c.ReadExReq_hits::cpu0.data 56339 # number of ReadExReq hits
418system.l2c.ReadExReq_hits::cpu1.data 52717 # number of ReadExReq hits
419system.l2c.ReadExReq_hits::total 109056 # number of ReadExReq hits
420system.l2c.demand_hits::cpu0.dtb.walker 3944 # number of demand (read+write) hits
421system.l2c.demand_hits::cpu0.itb.walker 1786 # number of demand (read+write) hits
422system.l2c.demand_hits::cpu0.inst 419390 # number of demand (read+write) hits
423system.l2c.demand_hits::cpu0.data 262194 # number of demand (read+write) hits
424system.l2c.demand_hits::cpu1.dtb.walker 5333 # number of demand (read+write) hits
425system.l2c.demand_hits::cpu1.itb.walker 1846 # number of demand (read+write) hits
426system.l2c.demand_hits::cpu1.inst 464270 # number of demand (read+write) hits
427system.l2c.demand_hits::cpu1.data 196151 # number of demand (read+write) hits
428system.l2c.demand_hits::total 1354914 # number of demand (read+write) hits
429system.l2c.overall_hits::cpu0.dtb.walker 3944 # number of overall hits
430system.l2c.overall_hits::cpu0.itb.walker 1786 # number of overall hits
431system.l2c.overall_hits::cpu0.inst 419390 # number of overall hits
432system.l2c.overall_hits::cpu0.data 262194 # number of overall hits
433system.l2c.overall_hits::cpu1.dtb.walker 5333 # number of overall hits
434system.l2c.overall_hits::cpu1.itb.walker 1846 # number of overall hits
435system.l2c.overall_hits::cpu1.inst 464270 # number of overall hits
436system.l2c.overall_hits::cpu1.data 196151 # number of overall hits
437system.l2c.overall_hits::total 1354914 # number of overall hits
438system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
439system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
440system.l2c.ReadReq_misses::cpu0.inst 5741 # number of ReadReq misses
441system.l2c.ReadReq_misses::cpu0.data 7844 # number of ReadReq misses
442system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
443system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
444system.l2c.ReadReq_misses::cpu1.inst 5048 # number of ReadReq misses
445system.l2c.ReadReq_misses::cpu1.data 3616 # number of ReadReq misses
446system.l2c.ReadReq_misses::total 22257 # number of ReadReq misses
447system.l2c.UpgradeReq_misses::cpu0.data 4858 # number of UpgradeReq misses
448system.l2c.UpgradeReq_misses::cpu1.data 3744 # number of UpgradeReq misses
449system.l2c.UpgradeReq_misses::total 8602 # number of UpgradeReq misses
450system.l2c.SCUpgradeReq_misses::cpu0.data 567 # number of SCUpgradeReq misses
451system.l2c.SCUpgradeReq_misses::cpu1.data 472 # number of SCUpgradeReq misses
452system.l2c.SCUpgradeReq_misses::total 1039 # number of SCUpgradeReq misses
453system.l2c.ReadExReq_misses::cpu0.data 67076 # number of ReadExReq misses
454system.l2c.ReadExReq_misses::cpu1.data 72428 # number of ReadExReq misses
455system.l2c.ReadExReq_misses::total 139504 # number of ReadExReq misses
456system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
457system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
458system.l2c.demand_misses::cpu0.inst 5741 # number of demand (read+write) misses
459system.l2c.demand_misses::cpu0.data 74920 # number of demand (read+write) misses
460system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
461system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
462system.l2c.demand_misses::cpu1.inst 5048 # number of demand (read+write) misses
463system.l2c.demand_misses::cpu1.data 76044 # number of demand (read+write) misses
464system.l2c.demand_misses::total 161761 # number of demand (read+write) misses
465system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
466system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
467system.l2c.overall_misses::cpu0.inst 5741 # number of overall misses
468system.l2c.overall_misses::cpu0.data 74920 # number of overall misses
469system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
470system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
471system.l2c.overall_misses::cpu1.inst 5048 # number of overall misses
472system.l2c.overall_misses::cpu1.data 76044 # number of overall misses
473system.l2c.overall_misses::total 161761 # number of overall misses
474system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 32000 # number of ReadReq miss cycles
475system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles
476system.l2c.ReadReq_miss_latency::cpu0.inst 405931250 # number of ReadReq miss cycles
477system.l2c.ReadReq_miss_latency::cpu0.data 580562999 # number of ReadReq miss cycles
478system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 320500 # number of ReadReq miss cycles
479system.l2c.ReadReq_miss_latency::cpu1.itb.walker 75000 # number of ReadReq miss cycles
480system.l2c.ReadReq_miss_latency::cpu1.inst 360408000 # number of ReadReq miss cycles
481system.l2c.ReadReq_miss_latency::cpu1.data 277006500 # number of ReadReq miss cycles
482system.l2c.ReadReq_miss_latency::total 1624485749 # number of ReadReq miss cycles
483system.l2c.UpgradeReq_miss_latency::cpu0.data 12826446 # number of UpgradeReq miss cycles
484system.l2c.UpgradeReq_miss_latency::cpu1.data 12064984 # number of UpgradeReq miss cycles
485system.l2c.UpgradeReq_miss_latency::total 24891430 # number of UpgradeReq miss cycles
486system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1764424 # number of SCUpgradeReq miss cycles
487system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2465394 # number of SCUpgradeReq miss cycles
488system.l2c.SCUpgradeReq_miss_latency::total 4229818 # number of SCUpgradeReq miss cycles
489system.l2c.ReadExReq_miss_latency::cpu0.data 4470263914 # number of ReadExReq miss cycles
490system.l2c.ReadExReq_miss_latency::cpu1.data 5223424391 # number of ReadExReq miss cycles
491system.l2c.ReadExReq_miss_latency::total 9693688305 # number of ReadExReq miss cycles
492system.l2c.demand_miss_latency::cpu0.dtb.walker 32000 # number of demand (read+write) miss cycles
493system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles
494system.l2c.demand_miss_latency::cpu0.inst 405931250 # number of demand (read+write) miss cycles
495system.l2c.demand_miss_latency::cpu0.data 5050826913 # number of demand (read+write) miss cycles
496system.l2c.demand_miss_latency::cpu1.dtb.walker 320500 # number of demand (read+write) miss cycles
497system.l2c.demand_miss_latency::cpu1.itb.walker 75000 # number of demand (read+write) miss cycles
498system.l2c.demand_miss_latency::cpu1.inst 360408000 # number of demand (read+write) miss cycles
499system.l2c.demand_miss_latency::cpu1.data 5500430891 # number of demand (read+write) miss cycles
500system.l2c.demand_miss_latency::total 11318174054 # number of demand (read+write) miss cycles
501system.l2c.overall_miss_latency::cpu0.dtb.walker 32000 # number of overall miss cycles
502system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles
503system.l2c.overall_miss_latency::cpu0.inst 405931250 # number of overall miss cycles
504system.l2c.overall_miss_latency::cpu0.data 5050826913 # number of overall miss cycles
505system.l2c.overall_miss_latency::cpu1.dtb.walker 320500 # number of overall miss cycles
506system.l2c.overall_miss_latency::cpu1.itb.walker 75000 # number of overall miss cycles
507system.l2c.overall_miss_latency::cpu1.inst 360408000 # number of overall miss cycles
508system.l2c.overall_miss_latency::cpu1.data 5500430891 # number of overall miss cycles
509system.l2c.overall_miss_latency::total 11318174054 # number of overall miss cycles
510system.l2c.ReadReq_accesses::cpu0.dtb.walker 3945 # number of ReadReq accesses(hits+misses)
511system.l2c.ReadReq_accesses::cpu0.itb.walker 1788 # number of ReadReq accesses(hits+misses)
512system.l2c.ReadReq_accesses::cpu0.inst 425131 # number of ReadReq accesses(hits+misses)
513system.l2c.ReadReq_accesses::cpu0.data 213699 # number of ReadReq accesses(hits+misses)
514system.l2c.ReadReq_accesses::cpu1.dtb.walker 5337 # number of ReadReq accesses(hits+misses)
515system.l2c.ReadReq_accesses::cpu1.itb.walker 1847 # number of ReadReq accesses(hits+misses)
516system.l2c.ReadReq_accesses::cpu1.inst 469318 # number of ReadReq accesses(hits+misses)
517system.l2c.ReadReq_accesses::cpu1.data 147050 # number of ReadReq accesses(hits+misses)
518system.l2c.ReadReq_accesses::total 1268115 # number of ReadReq accesses(hits+misses)
519system.l2c.Writeback_accesses::writebacks 570720 # number of Writeback accesses(hits+misses)
520system.l2c.Writeback_accesses::total 570720 # number of Writeback accesses(hits+misses)
521system.l2c.UpgradeReq_accesses::cpu0.data 6149 # number of UpgradeReq accesses(hits+misses)
522system.l2c.UpgradeReq_accesses::cpu1.data 4267 # number of UpgradeReq accesses(hits+misses)
523system.l2c.UpgradeReq_accesses::total 10416 # number of UpgradeReq accesses(hits+misses)
524system.l2c.SCUpgradeReq_accesses::cpu0.data 781 # number of SCUpgradeReq accesses(hits+misses)
525system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses)
526system.l2c.SCUpgradeReq_accesses::total 1350 # number of SCUpgradeReq accesses(hits+misses)
527system.l2c.ReadExReq_accesses::cpu0.data 123415 # number of ReadExReq accesses(hits+misses)
528system.l2c.ReadExReq_accesses::cpu1.data 125145 # number of ReadExReq accesses(hits+misses)
529system.l2c.ReadExReq_accesses::total 248560 # number of ReadExReq accesses(hits+misses)
530system.l2c.demand_accesses::cpu0.dtb.walker 3945 # number of demand (read+write) accesses
531system.l2c.demand_accesses::cpu0.itb.walker 1788 # number of demand (read+write) accesses
532system.l2c.demand_accesses::cpu0.inst 425131 # number of demand (read+write) accesses
533system.l2c.demand_accesses::cpu0.data 337114 # number of demand (read+write) accesses
534system.l2c.demand_accesses::cpu1.dtb.walker 5337 # number of demand (read+write) accesses
535system.l2c.demand_accesses::cpu1.itb.walker 1847 # number of demand (read+write) accesses
536system.l2c.demand_accesses::cpu1.inst 469318 # number of demand (read+write) accesses
537system.l2c.demand_accesses::cpu1.data 272195 # number of demand (read+write) accesses
538system.l2c.demand_accesses::total 1516675 # number of demand (read+write) accesses
539system.l2c.overall_accesses::cpu0.dtb.walker 3945 # number of overall (read+write) accesses
540system.l2c.overall_accesses::cpu0.itb.walker 1788 # number of overall (read+write) accesses
541system.l2c.overall_accesses::cpu0.inst 425131 # number of overall (read+write) accesses
542system.l2c.overall_accesses::cpu0.data 337114 # number of overall (read+write) accesses
543system.l2c.overall_accesses::cpu1.dtb.walker 5337 # number of overall (read+write) accesses
544system.l2c.overall_accesses::cpu1.itb.walker 1847 # number of overall (read+write) accesses
545system.l2c.overall_accesses::cpu1.inst 469318 # number of overall (read+write) accesses
546system.l2c.overall_accesses::cpu1.data 272195 # number of overall (read+write) accesses
547system.l2c.overall_accesses::total 1516675 # number of overall (read+write) accesses
548system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000253 # miss rate for ReadReq accesses
549system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001119 # miss rate for ReadReq accesses
550system.l2c.ReadReq_miss_rate::cpu0.inst 0.013504 # miss rate for ReadReq accesses
551system.l2c.ReadReq_miss_rate::cpu0.data 0.036706 # miss rate for ReadReq accesses
552system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000749 # miss rate for ReadReq accesses
553system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000541 # miss rate for ReadReq accesses
554system.l2c.ReadReq_miss_rate::cpu1.inst 0.010756 # miss rate for ReadReq accesses
555system.l2c.ReadReq_miss_rate::cpu1.data 0.024590 # miss rate for ReadReq accesses
556system.l2c.ReadReq_miss_rate::total 0.017551 # miss rate for ReadReq accesses
557system.l2c.UpgradeReq_miss_rate::cpu0.data 0.790047 # miss rate for UpgradeReq accesses
558system.l2c.UpgradeReq_miss_rate::cpu1.data 0.877431 # miss rate for UpgradeReq accesses
559system.l2c.UpgradeReq_miss_rate::total 0.825845 # miss rate for UpgradeReq accesses
560system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.725992 # miss rate for SCUpgradeReq accesses
561system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.829525 # miss rate for SCUpgradeReq accesses
562system.l2c.SCUpgradeReq_miss_rate::total 0.769630 # miss rate for SCUpgradeReq accesses
563system.l2c.ReadExReq_miss_rate::cpu0.data 0.543500 # miss rate for ReadExReq accesses
564system.l2c.ReadExReq_miss_rate::cpu1.data 0.578753 # miss rate for ReadExReq accesses
565system.l2c.ReadExReq_miss_rate::total 0.561249 # miss rate for ReadExReq accesses
566system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000253 # miss rate for demand accesses
567system.l2c.demand_miss_rate::cpu0.itb.walker 0.001119 # miss rate for demand accesses
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569system.l2c.demand_miss_rate::cpu0.data 0.222239 # miss rate for demand accesses
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767system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.762019 # average UpgradeReq mshr miss latency
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770system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.472458 # average SCUpgradeReq mshr miss latency
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792system.l2c.overall_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency
793system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
794system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
795system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
796system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
797system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
798system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
799system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
800system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency

--- 4 unchanged lines hidden (view full) ---

805system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
806system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
807system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
808system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
809system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
810system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
811system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
812system.cf0.dma_write_txs 0 # Number of DMA write transactions.
813system.toL2Bus.throughput 119643708 # Throughput (bytes/s)
814system.toL2Bus.trans_dist::ReadReq 2534658 # Transaction distribution
815system.toL2Bus.trans_dist::ReadResp 2534658 # Transaction distribution
816system.toL2Bus.trans_dist::WriteReq 767581 # Transaction distribution
817system.toL2Bus.trans_dist::WriteResp 767581 # Transaction distribution
818system.toL2Bus.trans_dist::Writeback 570720 # Transaction distribution
819system.toL2Bus.trans_dist::UpgradeReq 30701 # Transaction distribution
820system.toL2Bus.trans_dist::SCUpgradeReq 17545 # Transaction distribution
821system.toL2Bus.trans_dist::UpgradeResp 48246 # Transaction distribution
822system.toL2Bus.trans_dist::ReadExReq 260694 # Transaction distribution
823system.toL2Bus.trans_dist::ReadExResp 260694 # Transaction distribution
824system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864108 # Packet count per connected master and slave (bytes)
825system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226294 # Packet count per connected master and slave (bytes)
826system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6184 # Packet count per connected master and slave (bytes)
827system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12819 # Packet count per connected master and slave (bytes)
828system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939372 # Packet count per connected master and slave (bytes)
829system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600756 # Packet count per connected master and slave (bytes)
830system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6173 # Packet count per connected master and slave (bytes)
831system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15243 # Packet count per connected master and slave (bytes)
832system.toL2Bus.pkt_count::total 7670949 # Packet count per connected master and slave (bytes)
833system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27234976 # Cumulative packet size per connected master and slave (bytes)
834system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41362613 # Cumulative packet size per connected master and slave (bytes)
835system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7152 # Cumulative packet size per connected master and slave (bytes)
836system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15780 # Cumulative packet size per connected master and slave (bytes)
837system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30036788 # Cumulative packet size per connected master and slave (bytes)
838system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39599456 # Cumulative packet size per connected master and slave (bytes)
839system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7388 # Cumulative packet size per connected master and slave (bytes)
840system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21348 # Cumulative packet size per connected master and slave (bytes)
841system.toL2Bus.tot_pkt_size::total 138285501 # Cumulative packet size per connected master and slave (bytes)
842system.toL2Bus.data_through_bus 138285501 # Total data (bytes)
843system.toL2Bus.snoop_data_through_bus 4606436 # Total snoop data (bytes)
844system.toL2Bus.reqLayer0.occupancy 4757764712 # Layer occupancy (ticks)
845system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
846system.toL2Bus.respLayer0.occupancy 1924888432 # Layer occupancy (ticks)
847system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
848system.toL2Bus.respLayer1.occupancy 1752701680 # Layer occupancy (ticks)
849system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
850system.toL2Bus.respLayer2.occupancy 4396499 # Layer occupancy (ticks)
851system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
852system.toL2Bus.respLayer3.occupancy 8876994 # Layer occupancy (ticks)
853system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
854system.toL2Bus.respLayer6.occupancy 2115350205 # Layer occupancy (ticks)
855system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
856system.toL2Bus.respLayer7.occupancy 2925844707 # Layer occupancy (ticks)
857system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
858system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks)
859system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%)
860system.toL2Bus.respLayer9.occupancy 9906999 # Layer occupancy (ticks)
861system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%)
862system.iobus.throughput 45460895 # Throughput (bytes/s)
863system.iobus.trans_dist::ReadReq 7671423 # Transaction distribution
864system.iobus.trans_dist::ReadResp 7671423 # Transaction distribution
865system.iobus.trans_dist::WriteReq 7962 # Transaction distribution
866system.iobus.trans_dist::WriteResp 7962 # Transaction distribution
867system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30548 # Packet count per connected master and slave (bytes)
868system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8040 # Packet count per connected master and slave (bytes)
869system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
870system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
871system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
872system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
873system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
874system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
875system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
876system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
877system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
878system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
879system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
880system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
881system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
882system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
883system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
884system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
885system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
886system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
887system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
888system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
889system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
890system.iobus.pkt_count_system.bridge.master::total 2382642 # Packet count per connected master and slave (bytes)
891system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
892system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
893system.iobus.pkt_count::total 15358770 # Packet count per connected master and slave (bytes)
894system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40317 # Cumulative packet size per connected master and slave (bytes)
895system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16080 # Cumulative packet size per connected master and slave (bytes)
896system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
897system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
898system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
899system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
900system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
901system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
902system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
903system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
904system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
905system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
906system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
907system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
908system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
909system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
910system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
911system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
912system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
913system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
914system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
915system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
916system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
917system.iobus.tot_pkt_size_system.bridge.master::total 2389989 # Cumulative packet size per connected master and slave (bytes)
918system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
919system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
920system.iobus.tot_pkt_size::total 54294501 # Cumulative packet size per connected master and slave (bytes)
921system.iobus.data_through_bus 54294501 # Total data (bytes)
922system.iobus.reqLayer0.occupancy 21416000 # Layer occupancy (ticks)
923system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
924system.iobus.reqLayer1.occupancy 4026000 # Layer occupancy (ticks)
925system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
926system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
927system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
928system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks)
929system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
930system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
931system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
932system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
933system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
934system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks)
935system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
936system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
937system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
938system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
939system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
940system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
941system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
942system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
943system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
944system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
945system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)

--- 14 unchanged lines hidden (view full) ---

960system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
961system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
962system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
963system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
964system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
965system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
966system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
967system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
968system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks)
969system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%)
970system.iobus.respLayer0.occupancy 2374680000 # Layer occupancy (ticks)
971system.iobus.respLayer0.utilization 0.2 # Layer utilization (%)
972system.iobus.respLayer1.occupancy 16364250250 # Layer occupancy (ticks)
973system.iobus.respLayer1.utilization 1.4 # Layer utilization (%)
974system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
975system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
976system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
977system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
978system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
979system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
980system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
981system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

989system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
990system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
991system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
992system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
993system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
994system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
995system.cpu0.dtb.inst_hits 0 # ITB inst hits
996system.cpu0.dtb.inst_misses 0 # ITB inst misses
997system.cpu0.dtb.read_hits 6063582 # DTB read hits
998system.cpu0.dtb.read_misses 3748 # DTB read misses
999system.cpu0.dtb.write_hits 5648980 # DTB write hits
1000system.cpu0.dtb.write_misses 807 # DTB write misses
1001system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1002system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1003system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1004system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1005system.cpu0.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB
1006system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1007system.cpu0.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
1008system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1009system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
1010system.cpu0.dtb.read_accesses 6067330 # DTB read accesses
1011system.cpu0.dtb.write_accesses 5649787 # DTB write accesses
1012system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
1013system.cpu0.dtb.hits 11712562 # DTB hits
1014system.cpu0.dtb.misses 4555 # DTB misses
1015system.cpu0.dtb.accesses 11717117 # DTB accesses
1016system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1017system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1018system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1019system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1020system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1021system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1022system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1023system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1029system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1030system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1031system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1032system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1033system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1034system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1035system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1036system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1037system.cpu0.itb.inst_hits 29557926 # ITB inst hits
1038system.cpu0.itb.inst_misses 2205 # ITB inst misses
1039system.cpu0.itb.read_hits 0 # DTB read hits
1040system.cpu0.itb.read_misses 0 # DTB read misses
1041system.cpu0.itb.write_hits 0 # DTB write hits
1042system.cpu0.itb.write_misses 0 # DTB write misses
1043system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
1044system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1045system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1046system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1047system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB
1048system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1049system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1050system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1051system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1052system.cpu0.itb.read_accesses 0 # DTB read accesses
1053system.cpu0.itb.write_accesses 0 # DTB write accesses
1054system.cpu0.itb.inst_accesses 29560131 # ITB inst accesses
1055system.cpu0.itb.hits 29557926 # DTB hits
1056system.cpu0.itb.misses 2205 # DTB misses
1057system.cpu0.itb.accesses 29560131 # DTB accesses
1058system.cpu0.numCycles 2388624356 # number of cpu cycles simulated
1059system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
1060system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
1061system.cpu0.committedInsts 28859743 # Number of instructions committed
1062system.cpu0.committedOps 34624628 # Number of ops (including micro ops) committed
1063system.cpu0.num_int_alu_accesses 30439288 # Number of integer alu accesses
1064system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
1065system.cpu0.num_func_calls 1241573 # number of times a function call or return occured
1066system.cpu0.num_conditional_control_insts 4174263 # number of instructions that are conditional controls
1067system.cpu0.num_int_insts 30439288 # number of integer instructions
1068system.cpu0.num_fp_insts 3860 # number of float instructions
1069system.cpu0.num_int_register_reads 53589242 # number of times the integer registers were read
1070system.cpu0.num_int_register_writes 19764786 # number of times the integer registers were written
1071system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
1072system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
1073system.cpu0.num_cc_register_reads 123695766 # number of times the CC registers were read
1074system.cpu0.num_cc_register_writes 15045730 # number of times the CC registers were written
1075system.cpu0.num_mem_refs 12225186 # number of memory refs
1076system.cpu0.num_load_insts 6245915 # Number of load instructions
1077system.cpu0.num_store_insts 5979271 # Number of store instructions
1078system.cpu0.num_idle_cycles 2246427873.598119 # Number of idle cycles
1079system.cpu0.num_busy_cycles 142196482.401881 # Number of busy cycles
1080system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles
1081system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles
1082system.cpu0.Branches 5599312 # Number of branches fetched
1083system.cpu0.op_class::No_OpClass 14563 0.04% 0.04% # Class of executed instruction
1084system.cpu0.op_class::IntAlu 22957352 65.14% 65.18% # Class of executed instruction
1085system.cpu0.op_class::IntMult 43755 0.12% 65.31% # Class of executed instruction
1086system.cpu0.op_class::IntDiv 0 0.00% 65.31% # Class of executed instruction
1087system.cpu0.op_class::FloatAdd 0 0.00% 65.31% # Class of executed instruction
1088system.cpu0.op_class::FloatCmp 0 0.00% 65.31% # Class of executed instruction
1089system.cpu0.op_class::FloatCvt 0 0.00% 65.31% # Class of executed instruction
1090system.cpu0.op_class::FloatMult 0 0.00% 65.31% # Class of executed instruction
1091system.cpu0.op_class::FloatDiv 0 0.00% 65.31% # Class of executed instruction
1092system.cpu0.op_class::FloatSqrt 0 0.00% 65.31% # Class of executed instruction
1093system.cpu0.op_class::SimdAdd 0 0.00% 65.31% # Class of executed instruction
1094system.cpu0.op_class::SimdAddAcc 0 0.00% 65.31% # Class of executed instruction
1095system.cpu0.op_class::SimdAlu 0 0.00% 65.31% # Class of executed instruction
1096system.cpu0.op_class::SimdCmp 0 0.00% 65.31% # Class of executed instruction
1097system.cpu0.op_class::SimdCvt 0 0.00% 65.31% # Class of executed instruction
1098system.cpu0.op_class::SimdMisc 0 0.00% 65.31% # Class of executed instruction
1099system.cpu0.op_class::SimdMult 0 0.00% 65.31% # Class of executed instruction
1100system.cpu0.op_class::SimdMultAcc 0 0.00% 65.31% # Class of executed instruction
1101system.cpu0.op_class::SimdShift 0 0.00% 65.31% # Class of executed instruction
1102system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.31% # Class of executed instruction
1103system.cpu0.op_class::SimdSqrt 0 0.00% 65.31% # Class of executed instruction
1104system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.31% # Class of executed instruction
1105system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.31% # Class of executed instruction
1106system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.31% # Class of executed instruction
1107system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.31% # Class of executed instruction
1108system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.31% # Class of executed instruction
1109system.cpu0.op_class::SimdFloatMisc 692 0.00% 65.31% # Class of executed instruction
1110system.cpu0.op_class::SimdFloatMult 0 0.00% 65.31% # Class of executed instruction
1111system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.31% # Class of executed instruction
1112system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.31% # Class of executed instruction
1113system.cpu0.op_class::MemRead 6245915 17.72% 83.03% # Class of executed instruction
1114system.cpu0.op_class::MemWrite 5979271 16.97% 100.00% # Class of executed instruction
1115system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1116system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1117system.cpu0.op_class::total 35241548 # Class of executed instruction
1118system.cpu0.kern.inst.arm 0 # number of arm instructions executed
1119system.cpu0.kern.inst.quiesce 47055 # number of quiesce instructions executed
1120system.cpu0.icache.tags.replacements 425168 # number of replacements
1121system.cpu0.icache.tags.tagsinuse 509.375466 # Cycle average of tags in use
1122system.cpu0.icache.tags.total_refs 29132228 # Total number of references to valid blocks.
1123system.cpu0.icache.tags.sampled_refs 425680 # Sample count of references to valid blocks.
1124system.cpu0.icache.tags.avg_refs 68.436920 # Average number of references to valid blocks.
1125system.cpu0.icache.tags.warmup_cycle 75988011000 # Cycle when the warmup percentage was hit.
1126system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.375466 # Average occupied blocks per requestor
1127system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994874 # Average percentage of cache occupancy
1128system.cpu0.icache.tags.occ_percent::total 0.994874 # Average percentage of cache occupancy
1129system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1130system.cpu0.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
1131system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
1132system.cpu0.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id
1133system.cpu0.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
1134system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1135system.cpu0.icache.tags.tag_accesses 29983590 # Number of tag accesses
1136system.cpu0.icache.tags.data_accesses 29983590 # Number of data accesses
1137system.cpu0.icache.ReadReq_hits::cpu0.inst 29132228 # number of ReadReq hits
1138system.cpu0.icache.ReadReq_hits::total 29132228 # number of ReadReq hits
1139system.cpu0.icache.demand_hits::cpu0.inst 29132228 # number of demand (read+write) hits
1140system.cpu0.icache.demand_hits::total 29132228 # number of demand (read+write) hits
1141system.cpu0.icache.overall_hits::cpu0.inst 29132228 # number of overall hits
1142system.cpu0.icache.overall_hits::total 29132228 # number of overall hits
1143system.cpu0.icache.ReadReq_misses::cpu0.inst 425681 # number of ReadReq misses
1144system.cpu0.icache.ReadReq_misses::total 425681 # number of ReadReq misses
1145system.cpu0.icache.demand_misses::cpu0.inst 425681 # number of demand (read+write) misses
1146system.cpu0.icache.demand_misses::total 425681 # number of demand (read+write) misses
1147system.cpu0.icache.overall_misses::cpu0.inst 425681 # number of overall misses
1148system.cpu0.icache.overall_misses::total 425681 # number of overall misses
1149system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899766682 # number of ReadReq miss cycles
1150system.cpu0.icache.ReadReq_miss_latency::total 5899766682 # number of ReadReq miss cycles
1151system.cpu0.icache.demand_miss_latency::cpu0.inst 5899766682 # number of demand (read+write) miss cycles
1152system.cpu0.icache.demand_miss_latency::total 5899766682 # number of demand (read+write) miss cycles
1153system.cpu0.icache.overall_miss_latency::cpu0.inst 5899766682 # number of overall miss cycles
1154system.cpu0.icache.overall_miss_latency::total 5899766682 # number of overall miss cycles
1155system.cpu0.icache.ReadReq_accesses::cpu0.inst 29557909 # number of ReadReq accesses(hits+misses)
1156system.cpu0.icache.ReadReq_accesses::total 29557909 # number of ReadReq accesses(hits+misses)
1157system.cpu0.icache.demand_accesses::cpu0.inst 29557909 # number of demand (read+write) accesses
1158system.cpu0.icache.demand_accesses::total 29557909 # number of demand (read+write) accesses
1159system.cpu0.icache.overall_accesses::cpu0.inst 29557909 # number of overall (read+write) accesses
1160system.cpu0.icache.overall_accesses::total 29557909 # number of overall (read+write) accesses
1161system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014402 # miss rate for ReadReq accesses
1162system.cpu0.icache.ReadReq_miss_rate::total 0.014402 # miss rate for ReadReq accesses
1163system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014402 # miss rate for demand accesses
1164system.cpu0.icache.demand_miss_rate::total 0.014402 # miss rate for demand accesses
1165system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014402 # miss rate for overall accesses
1166system.cpu0.icache.overall_miss_rate::total 0.014402 # miss rate for overall accesses
1167system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13859.595993 # average ReadReq miss latency
1168system.cpu0.icache.ReadReq_avg_miss_latency::total 13859.595993 # average ReadReq miss latency
1169system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency
1170system.cpu0.icache.demand_avg_miss_latency::total 13859.595993 # average overall miss latency
1171system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency
1172system.cpu0.icache.overall_avg_miss_latency::total 13859.595993 # average overall miss latency
1173system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1174system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1175system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1176system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
1177system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1178system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1179system.cpu0.icache.fast_writes 0 # number of fast writes performed
1180system.cpu0.icache.cache_copies 0 # number of cache copies performed
1181system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425681 # number of ReadReq MSHR misses
1182system.cpu0.icache.ReadReq_mshr_misses::total 425681 # number of ReadReq MSHR misses
1183system.cpu0.icache.demand_mshr_misses::cpu0.inst 425681 # number of demand (read+write) MSHR misses
1184system.cpu0.icache.demand_mshr_misses::total 425681 # number of demand (read+write) MSHR misses
1185system.cpu0.icache.overall_mshr_misses::cpu0.inst 425681 # number of overall MSHR misses
1186system.cpu0.icache.overall_mshr_misses::total 425681 # number of overall MSHR misses
1187system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5046160318 # number of ReadReq MSHR miss cycles
1188system.cpu0.icache.ReadReq_mshr_miss_latency::total 5046160318 # number of ReadReq MSHR miss cycles
1189system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5046160318 # number of demand (read+write) MSHR miss cycles
1190system.cpu0.icache.demand_mshr_miss_latency::total 5046160318 # number of demand (read+write) MSHR miss cycles
1191system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5046160318 # number of overall MSHR miss cycles
1192system.cpu0.icache.overall_mshr_miss_latency::total 5046160318 # number of overall MSHR miss cycles
1193system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 442165750 # number of ReadReq MSHR uncacheable cycles
1194system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 442165750 # number of ReadReq MSHR uncacheable cycles
1195system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 442165750 # number of overall MSHR uncacheable cycles
1196system.cpu0.icache.overall_mshr_uncacheable_latency::total 442165750 # number of overall MSHR uncacheable cycles
1197system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for ReadReq accesses
1198system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014402 # mshr miss rate for ReadReq accesses
1199system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for demand accesses
1200system.cpu0.icache.demand_mshr_miss_rate::total 0.014402 # mshr miss rate for demand accesses
1201system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014402 # mshr miss rate for overall accesses
1202system.cpu0.icache.overall_mshr_miss_rate::total 0.014402 # mshr miss rate for overall accesses
1203system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average ReadReq mshr miss latency
1204system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11854.323585 # average ReadReq mshr miss latency
1205system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average overall mshr miss latency
1206system.cpu0.icache.demand_avg_mshr_miss_latency::total 11854.323585 # average overall mshr miss latency
1207system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11854.323585 # average overall mshr miss latency
1208system.cpu0.icache.overall_avg_mshr_miss_latency::total 11854.323585 # average overall mshr miss latency
1209system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1210system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1211system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1212system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1213system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1214system.cpu0.dcache.tags.replacements 329792 # number of replacements
1215system.cpu0.dcache.tags.tagsinuse 452.041842 # Cycle average of tags in use
1216system.cpu0.dcache.tags.total_refs 11239100 # Total number of references to valid blocks.
1217system.cpu0.dcache.tags.sampled_refs 330304 # Sample count of references to valid blocks.
1218system.cpu0.dcache.tags.avg_refs 34.026533 # Average number of references to valid blocks.
1219system.cpu0.dcache.tags.warmup_cycle 671364250 # Cycle when the warmup percentage was hit.
1220system.cpu0.dcache.tags.occ_blocks::cpu0.data 452.041842 # Average occupied blocks per requestor
1221system.cpu0.dcache.tags.occ_percent::cpu0.data 0.882894 # Average percentage of cache occupancy
1222system.cpu0.dcache.tags.occ_percent::total 0.882894 # Average percentage of cache occupancy
1223system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1224system.cpu0.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
1225system.cpu0.dcache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
1226system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id
1227system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
1228system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1229system.cpu0.dcache.tags.tag_accesses 46848154 # Number of tag accesses
1230system.cpu0.dcache.tags.data_accesses 46848154 # Number of data accesses
1231system.cpu0.dcache.ReadReq_hits::cpu0.data 5514035 # number of ReadReq hits
1232system.cpu0.dcache.ReadReq_hits::total 5514035 # number of ReadReq hits
1233system.cpu0.dcache.WriteReq_hits::cpu0.data 5340154 # number of WriteReq hits
1234system.cpu0.dcache.WriteReq_hits::total 5340154 # number of WriteReq hits
1235system.cpu0.dcache.SoftPFReq_hits::cpu0.data 64966 # number of SoftPFReq hits
1236system.cpu0.dcache.SoftPFReq_hits::total 64966 # number of SoftPFReq hits
1237system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148024 # number of LoadLockedReq hits
1238system.cpu0.dcache.LoadLockedReq_hits::total 148024 # number of LoadLockedReq hits
1239system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149636 # number of StoreCondReq hits
1240system.cpu0.dcache.StoreCondReq_hits::total 149636 # number of StoreCondReq hits
1241system.cpu0.dcache.demand_hits::cpu0.data 10854189 # number of demand (read+write) hits
1242system.cpu0.dcache.demand_hits::total 10854189 # number of demand (read+write) hits
1243system.cpu0.dcache.overall_hits::cpu0.data 10919155 # number of overall hits
1244system.cpu0.dcache.overall_hits::total 10919155 # number of overall hits
1245system.cpu0.dcache.ReadReq_misses::cpu0.data 179189 # number of ReadReq misses
1246system.cpu0.dcache.ReadReq_misses::total 179189 # number of ReadReq misses
1247system.cpu0.dcache.WriteReq_misses::cpu0.data 145422 # number of WriteReq misses
1248system.cpu0.dcache.WriteReq_misses::total 145422 # number of WriteReq misses
1249system.cpu0.dcache.SoftPFReq_misses::cpu0.data 62829 # number of SoftPFReq misses
1250system.cpu0.dcache.SoftPFReq_misses::total 62829 # number of SoftPFReq misses
1251system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9439 # number of LoadLockedReq misses
1252system.cpu0.dcache.LoadLockedReq_misses::total 9439 # number of LoadLockedReq misses
1253system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7485 # number of StoreCondReq misses
1254system.cpu0.dcache.StoreCondReq_misses::total 7485 # number of StoreCondReq misses
1255system.cpu0.dcache.demand_misses::cpu0.data 324611 # number of demand (read+write) misses
1256system.cpu0.dcache.demand_misses::total 324611 # number of demand (read+write) misses
1257system.cpu0.dcache.overall_misses::cpu0.data 387440 # number of overall misses
1258system.cpu0.dcache.overall_misses::total 387440 # number of overall misses
1259system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2350643732 # number of ReadReq miss cycles
1260system.cpu0.dcache.ReadReq_miss_latency::total 2350643732 # number of ReadReq miss cycles
1261system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5817567140 # number of WriteReq miss cycles
1262system.cpu0.dcache.WriteReq_miss_latency::total 5817567140 # number of WriteReq miss cycles
1263system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94706749 # number of LoadLockedReq miss cycles
1264system.cpu0.dcache.LoadLockedReq_miss_latency::total 94706749 # number of LoadLockedReq miss cycles
1265system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44450567 # number of StoreCondReq miss cycles
1266system.cpu0.dcache.StoreCondReq_miss_latency::total 44450567 # number of StoreCondReq miss cycles
1267system.cpu0.dcache.demand_miss_latency::cpu0.data 8168210872 # number of demand (read+write) miss cycles
1268system.cpu0.dcache.demand_miss_latency::total 8168210872 # number of demand (read+write) miss cycles
1269system.cpu0.dcache.overall_miss_latency::cpu0.data 8168210872 # number of overall miss cycles
1270system.cpu0.dcache.overall_miss_latency::total 8168210872 # number of overall miss cycles
1271system.cpu0.dcache.ReadReq_accesses::cpu0.data 5693224 # number of ReadReq accesses(hits+misses)
1272system.cpu0.dcache.ReadReq_accesses::total 5693224 # number of ReadReq accesses(hits+misses)
1273system.cpu0.dcache.WriteReq_accesses::cpu0.data 5485576 # number of WriteReq accesses(hits+misses)
1274system.cpu0.dcache.WriteReq_accesses::total 5485576 # number of WriteReq accesses(hits+misses)
1275system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 127795 # number of SoftPFReq accesses(hits+misses)
1276system.cpu0.dcache.SoftPFReq_accesses::total 127795 # number of SoftPFReq accesses(hits+misses)
1277system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157463 # number of LoadLockedReq accesses(hits+misses)
1278system.cpu0.dcache.LoadLockedReq_accesses::total 157463 # number of LoadLockedReq accesses(hits+misses)
1279system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157121 # number of StoreCondReq accesses(hits+misses)
1280system.cpu0.dcache.StoreCondReq_accesses::total 157121 # number of StoreCondReq accesses(hits+misses)
1281system.cpu0.dcache.demand_accesses::cpu0.data 11178800 # number of demand (read+write) accesses
1282system.cpu0.dcache.demand_accesses::total 11178800 # number of demand (read+write) accesses
1283system.cpu0.dcache.overall_accesses::cpu0.data 11306595 # number of overall (read+write) accesses
1284system.cpu0.dcache.overall_accesses::total 11306595 # number of overall (read+write) accesses
1285system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031474 # miss rate for ReadReq accesses
1286system.cpu0.dcache.ReadReq_miss_rate::total 0.031474 # miss rate for ReadReq accesses
1287system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026510 # miss rate for WriteReq accesses
1288system.cpu0.dcache.WriteReq_miss_rate::total 0.026510 # miss rate for WriteReq accesses
1289system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.491639 # miss rate for SoftPFReq accesses
1290system.cpu0.dcache.SoftPFReq_miss_rate::total 0.491639 # miss rate for SoftPFReq accesses
1291system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059944 # miss rate for LoadLockedReq accesses
1292system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059944 # miss rate for LoadLockedReq accesses
1293system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047638 # miss rate for StoreCondReq accesses
1294system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047638 # miss rate for StoreCondReq accesses
1295system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029038 # miss rate for demand accesses
1296system.cpu0.dcache.demand_miss_rate::total 0.029038 # miss rate for demand accesses
1297system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034267 # miss rate for overall accesses
1298system.cpu0.dcache.overall_miss_rate::total 0.034267 # miss rate for overall accesses
1299system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13118.236789 # average ReadReq miss latency
1300system.cpu0.dcache.ReadReq_avg_miss_latency::total 13118.236789 # average ReadReq miss latency
1301system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40004.725145 # average WriteReq miss latency
1302system.cpu0.dcache.WriteReq_avg_miss_latency::total 40004.725145 # average WriteReq miss latency
1303system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.557474 # average LoadLockedReq miss latency
1304system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.557474 # average LoadLockedReq miss latency
1305system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5938.619506 # average StoreCondReq miss latency
1306system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5938.619506 # average StoreCondReq miss latency
1307system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25163.074794 # average overall miss latency
1308system.cpu0.dcache.demand_avg_miss_latency::total 25163.074794 # average overall miss latency
1309system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21082.518253 # average overall miss latency
1310system.cpu0.dcache.overall_avg_miss_latency::total 21082.518253 # average overall miss latency
1311system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1312system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1313system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1314system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
1315system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1316system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1317system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1318system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1319system.cpu0.dcache.writebacks::writebacks 305747 # number of writebacks
1320system.cpu0.dcache.writebacks::total 305747 # number of writebacks
1321system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits
1322system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits
1323system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 4042 # number of WriteReq MSHR hits
1324system.cpu0.dcache.WriteReq_mshr_hits::total 4042 # number of WriteReq MSHR hits
1325system.cpu0.dcache.demand_mshr_hits::cpu0.data 4318 # number of demand (read+write) MSHR hits
1326system.cpu0.dcache.demand_mshr_hits::total 4318 # number of demand (read+write) MSHR hits
1327system.cpu0.dcache.overall_mshr_hits::cpu0.data 4318 # number of overall MSHR hits
1328system.cpu0.dcache.overall_mshr_hits::total 4318 # number of overall MSHR hits
1329system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 178913 # number of ReadReq MSHR misses
1330system.cpu0.dcache.ReadReq_mshr_misses::total 178913 # number of ReadReq MSHR misses
1331system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141380 # number of WriteReq MSHR misses
1332system.cpu0.dcache.WriteReq_mshr_misses::total 141380 # number of WriteReq MSHR misses
1333system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 48508 # number of SoftPFReq MSHR misses
1334system.cpu0.dcache.SoftPFReq_mshr_misses::total 48508 # number of SoftPFReq MSHR misses
1335system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9439 # number of LoadLockedReq MSHR misses
1336system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9439 # number of LoadLockedReq MSHR misses
1337system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses
1338system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses
1339system.cpu0.dcache.demand_mshr_misses::cpu0.data 320293 # number of demand (read+write) MSHR misses
1340system.cpu0.dcache.demand_mshr_misses::total 320293 # number of demand (read+write) MSHR misses
1341system.cpu0.dcache.overall_mshr_misses::cpu0.data 368801 # number of overall MSHR misses
1342system.cpu0.dcache.overall_mshr_misses::total 368801 # number of overall MSHR misses
1343system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1988652518 # number of ReadReq MSHR miss cycles
1344system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1988652518 # number of ReadReq MSHR miss cycles
1345system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5320324110 # number of WriteReq MSHR miss cycles
1346system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5320324110 # number of WriteReq MSHR miss cycles
1347system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 853626758 # number of SoftPFReq MSHR miss cycles
1348system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 853626758 # number of SoftPFReq MSHR miss cycles
1349system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 75777251 # number of LoadLockedReq MSHR miss cycles
1350system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 75777251 # number of LoadLockedReq MSHR miss cycles
1351system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29483433 # number of StoreCondReq MSHR miss cycles
1352system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29483433 # number of StoreCondReq MSHR miss cycles
1353system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7308976628 # number of demand (read+write) MSHR miss cycles
1354system.cpu0.dcache.demand_mshr_miss_latency::total 7308976628 # number of demand (read+write) MSHR miss cycles
1355system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8162603386 # number of overall MSHR miss cycles
1356system.cpu0.dcache.overall_mshr_miss_latency::total 8162603386 # number of overall MSHR miss cycles
1357system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13564535750 # number of ReadReq MSHR uncacheable cycles
1358system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13564535750 # number of ReadReq MSHR uncacheable cycles
1359system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170801000 # number of WriteReq MSHR uncacheable cycles
1360system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170801000 # number of WriteReq MSHR uncacheable cycles
1361system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14735336750 # number of overall MSHR uncacheable cycles
1362system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14735336750 # number of overall MSHR uncacheable cycles
1363system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031426 # mshr miss rate for ReadReq accesses
1364system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031426 # mshr miss rate for ReadReq accesses
1365system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025773 # mshr miss rate for WriteReq accesses
1366system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025773 # mshr miss rate for WriteReq accesses
1367system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.379577 # mshr miss rate for SoftPFReq accesses
1368system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.379577 # mshr miss rate for SoftPFReq accesses
1369system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059944 # mshr miss rate for LoadLockedReq accesses
1370system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059944 # mshr miss rate for LoadLockedReq accesses
1371system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047626 # mshr miss rate for StoreCondReq accesses
1372system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047626 # mshr miss rate for StoreCondReq accesses
1373system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028652 # mshr miss rate for demand accesses
1374system.cpu0.dcache.demand_mshr_miss_rate::total 0.028652 # mshr miss rate for demand accesses
1375system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032618 # mshr miss rate for overall accesses
1376system.cpu0.dcache.overall_mshr_miss_rate::total 0.032618 # mshr miss rate for overall accesses
1377system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11115.192960 # average ReadReq mshr miss latency
1378system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11115.192960 # average ReadReq mshr miss latency
1379system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37631.377210 # average WriteReq mshr miss latency
1380system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37631.377210 # average WriteReq mshr miss latency
1381system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17597.649006 # average SoftPFReq mshr miss latency
1382system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17597.649006 # average SoftPFReq mshr miss latency
1383system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8028.101600 # average LoadLockedReq mshr miss latency
1384system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8028.101600 # average LoadLockedReq mshr miss latency
1385system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3940.055192 # average StoreCondReq mshr miss latency
1386system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3940.055192 # average StoreCondReq mshr miss latency
1387system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22819.657713 # average overall mshr miss latency
1388system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22819.657713 # average overall mshr miss latency
1389system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22132.812509 # average overall mshr miss latency
1390system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22132.812509 # average overall mshr miss latency
1391system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1392system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1393system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1394system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1395system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1396system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1397system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1398system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1399system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1400system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1401system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1402system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1403system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1404system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1405system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

1413system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1414system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1415system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1416system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1417system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1418system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1419system.cpu1.dtb.inst_hits 0 # ITB inst hits
1420system.cpu1.dtb.inst_misses 0 # ITB inst misses
1421system.cpu1.dtb.read_hits 7408792 # DTB read hits
1422system.cpu1.dtb.read_misses 3640 # DTB read misses
1423system.cpu1.dtb.write_hits 5825509 # DTB write hits
1424system.cpu1.dtb.write_misses 1435 # DTB write misses
1425system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
1426system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1427system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1428system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1429system.cpu1.dtb.flush_entries 1866 # Number of entries that have been flushed from TLB
1430system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1431system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
1432system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1433system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
1434system.cpu1.dtb.read_accesses 7412432 # DTB read accesses
1435system.cpu1.dtb.write_accesses 5826944 # DTB write accesses
1436system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1437system.cpu1.dtb.hits 13234301 # DTB hits
1438system.cpu1.dtb.misses 5075 # DTB misses
1439system.cpu1.dtb.accesses 13239376 # DTB accesses
1440system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1441system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1442system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1443system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1444system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1445system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1446system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1447system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1453system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1454system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1455system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1456system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1457system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1458system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1459system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1460system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1461system.cpu1.itb.inst_hits 33190882 # ITB inst hits
1462system.cpu1.itb.inst_misses 2171 # ITB inst misses
1463system.cpu1.itb.read_hits 0 # DTB read hits
1464system.cpu1.itb.read_misses 0 # DTB read misses
1465system.cpu1.itb.write_hits 0 # DTB write hits
1466system.cpu1.itb.write_misses 0 # DTB write misses
1467system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
1468system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1469system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
1470system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
1471system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB
1472system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1473system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1474system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1475system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1476system.cpu1.itb.read_accesses 0 # DTB read accesses
1477system.cpu1.itb.write_accesses 0 # DTB write accesses
1478system.cpu1.itb.inst_accesses 33193053 # ITB inst accesses
1479system.cpu1.itb.hits 33190882 # DTB hits
1480system.cpu1.itb.misses 2171 # DTB misses
1481system.cpu1.itb.accesses 33193053 # DTB accesses
1482system.cpu1.numCycles 2387219429 # number of cpu cycles simulated
1483system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1484system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1485system.cpu1.committedInsts 32579955 # Number of instructions committed
1486system.cpu1.committedOps 38765002 # Number of ops (including micro ops) committed
1487system.cpu1.num_int_alu_accesses 35167643 # Number of integer alu accesses
1488system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
1489system.cpu1.num_func_calls 962341 # number of times a function call or return occured
1490system.cpu1.num_conditional_control_insts 3529676 # number of instructions that are conditional controls
1491system.cpu1.num_int_insts 35167643 # number of integer instructions
1492system.cpu1.num_fp_insts 6793 # number of float instructions
1493system.cpu1.num_int_register_reads 64976079 # number of times the integer registers were read
1494system.cpu1.num_int_register_writes 23977665 # number of times the integer registers were written
1495system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
1496system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
1497system.cpu1.num_cc_register_reads 139669414 # number of times the CC registers were read
1498system.cpu1.num_cc_register_writes 14465628 # number of times the CC registers were written
1499system.cpu1.num_mem_refs 13620676 # number of memory refs
1500system.cpu1.num_load_insts 7578910 # Number of load instructions
1501system.cpu1.num_store_insts 6041766 # Number of store instructions
1502system.cpu1.num_idle_cycles 1873842319.884373 # Number of idle cycles
1503system.cpu1.num_busy_cycles 513377109.115627 # Number of busy cycles
1504system.cpu1.not_idle_fraction 0.215052 # Percentage of non-idle cycles
1505system.cpu1.idle_fraction 0.784948 # Percentage of idle cycles
1506system.cpu1.Branches 4944984 # Number of branches fetched
1507system.cpu1.op_class::No_OpClass 14265 0.04% 0.04% # Class of executed instruction
1508system.cpu1.op_class::IntAlu 25564023 65.13% 65.17% # Class of executed instruction
1509system.cpu1.op_class::IntMult 50133 0.13% 65.29% # Class of executed instruction
1510system.cpu1.op_class::IntDiv 0 0.00% 65.29% # Class of executed instruction
1511system.cpu1.op_class::FloatAdd 0 0.00% 65.29% # Class of executed instruction
1512system.cpu1.op_class::FloatCmp 0 0.00% 65.29% # Class of executed instruction
1513system.cpu1.op_class::FloatCvt 0 0.00% 65.29% # Class of executed instruction
1514system.cpu1.op_class::FloatMult 0 0.00% 65.29% # Class of executed instruction
1515system.cpu1.op_class::FloatDiv 0 0.00% 65.29% # Class of executed instruction
1516system.cpu1.op_class::FloatSqrt 0 0.00% 65.29% # Class of executed instruction
1517system.cpu1.op_class::SimdAdd 0 0.00% 65.29% # Class of executed instruction
1518system.cpu1.op_class::SimdAddAcc 0 0.00% 65.29% # Class of executed instruction
1519system.cpu1.op_class::SimdAlu 0 0.00% 65.29% # Class of executed instruction
1520system.cpu1.op_class::SimdCmp 0 0.00% 65.29% # Class of executed instruction
1521system.cpu1.op_class::SimdCvt 0 0.00% 65.29% # Class of executed instruction
1522system.cpu1.op_class::SimdMisc 0 0.00% 65.29% # Class of executed instruction
1523system.cpu1.op_class::SimdMult 0 0.00% 65.29% # Class of executed instruction
1524system.cpu1.op_class::SimdMultAcc 0 0.00% 65.29% # Class of executed instruction
1525system.cpu1.op_class::SimdShift 0 0.00% 65.29% # Class of executed instruction
1526system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.29% # Class of executed instruction
1527system.cpu1.op_class::SimdSqrt 0 0.00% 65.29% # Class of executed instruction
1528system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.29% # Class of executed instruction
1529system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.29% # Class of executed instruction
1530system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.29% # Class of executed instruction
1531system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.29% # Class of executed instruction
1532system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.29% # Class of executed instruction
1533system.cpu1.op_class::SimdFloatMisc 1482 0.00% 65.30% # Class of executed instruction
1534system.cpu1.op_class::SimdFloatMult 0 0.00% 65.30% # Class of executed instruction
1535system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.30% # Class of executed instruction
1536system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.30% # Class of executed instruction
1537system.cpu1.op_class::MemRead 7578910 19.31% 84.61% # Class of executed instruction
1538system.cpu1.op_class::MemWrite 6041766 15.39% 100.00% # Class of executed instruction
1539system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1540system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1541system.cpu1.op_class::total 39250579 # Class of executed instruction
1542system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1543system.cpu1.kern.inst.quiesce 44258 # number of quiesce instructions executed
1544system.cpu1.icache.tags.replacements 469324 # number of replacements
1545system.cpu1.icache.tags.tagsinuse 478.642267 # Cycle average of tags in use
1546system.cpu1.icache.tags.total_refs 32721042 # Total number of references to valid blocks.
1547system.cpu1.icache.tags.sampled_refs 469836 # Sample count of references to valid blocks.
1548system.cpu1.icache.tags.avg_refs 69.643539 # Average number of references to valid blocks.
1549system.cpu1.icache.tags.warmup_cycle 93149552500 # Cycle when the warmup percentage was hit.
1550system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.642267 # Average occupied blocks per requestor
1551system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934848 # Average percentage of cache occupancy
1552system.cpu1.icache.tags.occ_percent::total 0.934848 # Average percentage of cache occupancy
1553system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1554system.cpu1.icache.tags.age_task_id_blocks_1024::2 456 # Occupied blocks per task id
1555system.cpu1.icache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
1556system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1557system.cpu1.icache.tags.tag_accesses 33660714 # Number of tag accesses
1558system.cpu1.icache.tags.data_accesses 33660714 # Number of data accesses
1559system.cpu1.icache.ReadReq_hits::cpu1.inst 32721042 # number of ReadReq hits
1560system.cpu1.icache.ReadReq_hits::total 32721042 # number of ReadReq hits
1561system.cpu1.icache.demand_hits::cpu1.inst 32721042 # number of demand (read+write) hits
1562system.cpu1.icache.demand_hits::total 32721042 # number of demand (read+write) hits
1563system.cpu1.icache.overall_hits::cpu1.inst 32721042 # number of overall hits
1564system.cpu1.icache.overall_hits::total 32721042 # number of overall hits
1565system.cpu1.icache.ReadReq_misses::cpu1.inst 469836 # number of ReadReq misses
1566system.cpu1.icache.ReadReq_misses::total 469836 # number of ReadReq misses
1567system.cpu1.icache.demand_misses::cpu1.inst 469836 # number of demand (read+write) misses
1568system.cpu1.icache.demand_misses::total 469836 # number of demand (read+write) misses
1569system.cpu1.icache.overall_misses::cpu1.inst 469836 # number of overall misses
1570system.cpu1.icache.overall_misses::total 469836 # number of overall misses
1571system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6435695955 # number of ReadReq miss cycles
1572system.cpu1.icache.ReadReq_miss_latency::total 6435695955 # number of ReadReq miss cycles
1573system.cpu1.icache.demand_miss_latency::cpu1.inst 6435695955 # number of demand (read+write) miss cycles
1574system.cpu1.icache.demand_miss_latency::total 6435695955 # number of demand (read+write) miss cycles
1575system.cpu1.icache.overall_miss_latency::cpu1.inst 6435695955 # number of overall miss cycles
1576system.cpu1.icache.overall_miss_latency::total 6435695955 # number of overall miss cycles
1577system.cpu1.icache.ReadReq_accesses::cpu1.inst 33190878 # number of ReadReq accesses(hits+misses)
1578system.cpu1.icache.ReadReq_accesses::total 33190878 # number of ReadReq accesses(hits+misses)
1579system.cpu1.icache.demand_accesses::cpu1.inst 33190878 # number of demand (read+write) accesses
1580system.cpu1.icache.demand_accesses::total 33190878 # number of demand (read+write) accesses
1581system.cpu1.icache.overall_accesses::cpu1.inst 33190878 # number of overall (read+write) accesses
1582system.cpu1.icache.overall_accesses::total 33190878 # number of overall (read+write) accesses
1583system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014156 # miss rate for ReadReq accesses
1584system.cpu1.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses
1585system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014156 # miss rate for demand accesses
1586system.cpu1.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses
1587system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014156 # miss rate for overall accesses
1588system.cpu1.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses
1589system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13697.749757 # average ReadReq miss latency
1590system.cpu1.icache.ReadReq_avg_miss_latency::total 13697.749757 # average ReadReq miss latency
1591system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency
1592system.cpu1.icache.demand_avg_miss_latency::total 13697.749757 # average overall miss latency
1593system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency
1594system.cpu1.icache.overall_avg_miss_latency::total 13697.749757 # average overall miss latency
1595system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1596system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1597system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1598system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1599system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1600system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1601system.cpu1.icache.fast_writes 0 # number of fast writes performed
1602system.cpu1.icache.cache_copies 0 # number of cache copies performed
1603system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469836 # number of ReadReq MSHR misses
1604system.cpu1.icache.ReadReq_mshr_misses::total 469836 # number of ReadReq MSHR misses
1605system.cpu1.icache.demand_mshr_misses::cpu1.inst 469836 # number of demand (read+write) MSHR misses
1606system.cpu1.icache.demand_mshr_misses::total 469836 # number of demand (read+write) MSHR misses
1607system.cpu1.icache.overall_mshr_misses::cpu1.inst 469836 # number of overall MSHR misses
1608system.cpu1.icache.overall_mshr_misses::total 469836 # number of overall MSHR misses
1609system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5494111045 # number of ReadReq MSHR miss cycles
1610system.cpu1.icache.ReadReq_mshr_miss_latency::total 5494111045 # number of ReadReq MSHR miss cycles
1611system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5494111045 # number of demand (read+write) MSHR miss cycles
1612system.cpu1.icache.demand_mshr_miss_latency::total 5494111045 # number of demand (read+write) MSHR miss cycles
1613system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5494111045 # number of overall MSHR miss cycles
1614system.cpu1.icache.overall_mshr_miss_latency::total 5494111045 # number of overall MSHR miss cycles
1615system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6835750 # number of ReadReq MSHR uncacheable cycles
1616system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6835750 # number of ReadReq MSHR uncacheable cycles
1617system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6835750 # number of overall MSHR uncacheable cycles
1618system.cpu1.icache.overall_mshr_uncacheable_latency::total 6835750 # number of overall MSHR uncacheable cycles
1619system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for ReadReq accesses
1620system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses
1621system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for demand accesses
1622system.cpu1.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses
1623system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for overall accesses
1624system.cpu1.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses
1625system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average ReadReq mshr miss latency
1626system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11693.678315 # average ReadReq mshr miss latency
1627system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average overall mshr miss latency
1628system.cpu1.icache.demand_avg_mshr_miss_latency::total 11693.678315 # average overall mshr miss latency
1629system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average overall mshr miss latency
1630system.cpu1.icache.overall_avg_mshr_miss_latency::total 11693.678315 # average overall mshr miss latency
1631system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1632system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1633system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1634system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1635system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1636system.cpu1.dcache.tags.replacements 292234 # number of replacements
1637system.cpu1.dcache.tags.tagsinuse 471.923930 # Cycle average of tags in use
1638system.cpu1.dcache.tags.total_refs 11040887 # Total number of references to valid blocks.
1639system.cpu1.dcache.tags.sampled_refs 292603 # Sample count of references to valid blocks.
1640system.cpu1.dcache.tags.avg_refs 37.733335 # Average number of references to valid blocks.
1641system.cpu1.dcache.tags.warmup_cycle 84705826250 # Cycle when the warmup percentage was hit.
1642system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.923930 # Average occupied blocks per requestor
1643system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921726 # Average percentage of cache occupancy
1644system.cpu1.dcache.tags.occ_percent::total 0.921726 # Average percentage of cache occupancy
1645system.cpu1.dcache.tags.occ_task_id_blocks::1024 369 # Occupied blocks per task id
1646system.cpu1.dcache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id
1647system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
1648system.cpu1.dcache.tags.occ_task_id_percent::1024 0.720703 # Percentage of cache occupancy per task id
1649system.cpu1.dcache.tags.tag_accesses 45818347 # Number of tag accesses
1650system.cpu1.dcache.tags.data_accesses 45818347 # Number of data accesses
1651system.cpu1.dcache.ReadReq_hits::cpu1.data 6006097 # number of ReadReq hits
1652system.cpu1.dcache.ReadReq_hits::total 6006097 # number of ReadReq hits
1653system.cpu1.dcache.WriteReq_hits::cpu1.data 4823101 # number of WriteReq hits
1654system.cpu1.dcache.WriteReq_hits::total 4823101 # number of WriteReq hits
1655system.cpu1.dcache.SoftPFReq_hits::cpu1.data 22483 # number of SoftPFReq hits
1656system.cpu1.dcache.SoftPFReq_hits::total 22483 # number of SoftPFReq hits
1657system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81936 # number of LoadLockedReq hits
1658system.cpu1.dcache.LoadLockedReq_hits::total 81936 # number of LoadLockedReq hits
1659system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82707 # number of StoreCondReq hits
1660system.cpu1.dcache.StoreCondReq_hits::total 82707 # number of StoreCondReq hits
1661system.cpu1.dcache.demand_hits::cpu1.data 10829198 # number of demand (read+write) hits
1662system.cpu1.dcache.demand_hits::total 10829198 # number of demand (read+write) hits
1663system.cpu1.dcache.overall_hits::cpu1.data 10851681 # number of overall hits
1664system.cpu1.dcache.overall_hits::total 10851681 # number of overall hits
1665system.cpu1.dcache.ReadReq_misses::cpu1.data 144053 # number of ReadReq misses
1666system.cpu1.dcache.ReadReq_misses::total 144053 # number of ReadReq misses
1667system.cpu1.dcache.WriteReq_misses::cpu1.data 152082 # number of WriteReq misses
1668system.cpu1.dcache.WriteReq_misses::total 152082 # number of WriteReq misses
1669system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41875 # number of SoftPFReq misses
1670system.cpu1.dcache.SoftPFReq_misses::total 41875 # number of SoftPFReq misses
1671system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11222 # number of LoadLockedReq misses
1672system.cpu1.dcache.LoadLockedReq_misses::total 11222 # number of LoadLockedReq misses
1673system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10064 # number of StoreCondReq misses
1674system.cpu1.dcache.StoreCondReq_misses::total 10064 # number of StoreCondReq misses
1675system.cpu1.dcache.demand_misses::cpu1.data 296135 # number of demand (read+write) misses
1676system.cpu1.dcache.demand_misses::total 296135 # number of demand (read+write) misses
1677system.cpu1.dcache.overall_misses::cpu1.data 338010 # number of overall misses
1678system.cpu1.dcache.overall_misses::total 338010 # number of overall misses
1679system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1718496498 # number of ReadReq miss cycles
1680system.cpu1.dcache.ReadReq_miss_latency::total 1718496498 # number of ReadReq miss cycles
1681system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6437170330 # number of WriteReq miss cycles
1682system.cpu1.dcache.WriteReq_miss_latency::total 6437170330 # number of WriteReq miss cycles
1683system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 96291249 # number of LoadLockedReq miss cycles
1684system.cpu1.dcache.LoadLockedReq_miss_latency::total 96291249 # number of LoadLockedReq miss cycles
1685system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52005971 # number of StoreCondReq miss cycles
1686system.cpu1.dcache.StoreCondReq_miss_latency::total 52005971 # number of StoreCondReq miss cycles
1687system.cpu1.dcache.demand_miss_latency::cpu1.data 8155666828 # number of demand (read+write) miss cycles
1688system.cpu1.dcache.demand_miss_latency::total 8155666828 # number of demand (read+write) miss cycles
1689system.cpu1.dcache.overall_miss_latency::cpu1.data 8155666828 # number of overall miss cycles
1690system.cpu1.dcache.overall_miss_latency::total 8155666828 # number of overall miss cycles
1691system.cpu1.dcache.ReadReq_accesses::cpu1.data 6150150 # number of ReadReq accesses(hits+misses)
1692system.cpu1.dcache.ReadReq_accesses::total 6150150 # number of ReadReq accesses(hits+misses)
1693system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975183 # number of WriteReq accesses(hits+misses)
1694system.cpu1.dcache.WriteReq_accesses::total 4975183 # number of WriteReq accesses(hits+misses)
1695system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 64358 # number of SoftPFReq accesses(hits+misses)
1696system.cpu1.dcache.SoftPFReq_accesses::total 64358 # number of SoftPFReq accesses(hits+misses)
1697system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93158 # number of LoadLockedReq accesses(hits+misses)
1698system.cpu1.dcache.LoadLockedReq_accesses::total 93158 # number of LoadLockedReq accesses(hits+misses)
1699system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92771 # number of StoreCondReq accesses(hits+misses)
1700system.cpu1.dcache.StoreCondReq_accesses::total 92771 # number of StoreCondReq accesses(hits+misses)
1701system.cpu1.dcache.demand_accesses::cpu1.data 11125333 # number of demand (read+write) accesses
1702system.cpu1.dcache.demand_accesses::total 11125333 # number of demand (read+write) accesses
1703system.cpu1.dcache.overall_accesses::cpu1.data 11189691 # number of overall (read+write) accesses
1704system.cpu1.dcache.overall_accesses::total 11189691 # number of overall (read+write) accesses
1705system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023423 # miss rate for ReadReq accesses
1706system.cpu1.dcache.ReadReq_miss_rate::total 0.023423 # miss rate for ReadReq accesses
1707system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030568 # miss rate for WriteReq accesses
1708system.cpu1.dcache.WriteReq_miss_rate::total 0.030568 # miss rate for WriteReq accesses
1709system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.650657 # miss rate for SoftPFReq accesses
1710system.cpu1.dcache.SoftPFReq_miss_rate::total 0.650657 # miss rate for SoftPFReq accesses
1711system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120462 # miss rate for LoadLockedReq accesses
1712system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120462 # miss rate for LoadLockedReq accesses
1713system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108482 # miss rate for StoreCondReq accesses
1714system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108482 # miss rate for StoreCondReq accesses
1715system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026618 # miss rate for demand accesses
1716system.cpu1.dcache.demand_miss_rate::total 0.026618 # miss rate for demand accesses
1717system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030207 # miss rate for overall accesses
1718system.cpu1.dcache.overall_miss_rate::total 0.030207 # miss rate for overall accesses
1719system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11929.612698 # average ReadReq miss latency
1720system.cpu1.dcache.ReadReq_avg_miss_latency::total 11929.612698 # average ReadReq miss latency
1721system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42326.970516 # average WriteReq miss latency
1722system.cpu1.dcache.WriteReq_avg_miss_latency::total 42326.970516 # average WriteReq miss latency
1723system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8580.578239 # average LoadLockedReq miss latency
1724system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8580.578239 # average LoadLockedReq miss latency
1725system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5167.524940 # average StoreCondReq miss latency
1726system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5167.524940 # average StoreCondReq miss latency
1727system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27540.367832 # average overall miss latency
1728system.cpu1.dcache.demand_avg_miss_latency::total 27540.367832 # average overall miss latency
1729system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24128.477939 # average overall miss latency
1730system.cpu1.dcache.overall_avg_miss_latency::total 24128.477939 # average overall miss latency
1731system.cpu1.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked
1732system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1733system.cpu1.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
1734system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1735system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked
1736system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1737system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1738system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1739system.cpu1.dcache.writebacks::writebacks 264973 # number of writebacks
1740system.cpu1.dcache.writebacks::total 264973 # number of writebacks
1741system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379 # number of ReadReq MSHR hits
1742system.cpu1.dcache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits
1743system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 2067 # number of WriteReq MSHR hits
1744system.cpu1.dcache.WriteReq_mshr_hits::total 2067 # number of WriteReq MSHR hits
1745system.cpu1.dcache.demand_mshr_hits::cpu1.data 2446 # number of demand (read+write) MSHR hits
1746system.cpu1.dcache.demand_mshr_hits::total 2446 # number of demand (read+write) MSHR hits
1747system.cpu1.dcache.overall_mshr_hits::cpu1.data 2446 # number of overall MSHR hits
1748system.cpu1.dcache.overall_mshr_hits::total 2446 # number of overall MSHR hits
1749system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143674 # number of ReadReq MSHR misses
1750system.cpu1.dcache.ReadReq_mshr_misses::total 143674 # number of ReadReq MSHR misses
1751system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150015 # number of WriteReq MSHR misses
1752system.cpu1.dcache.WriteReq_mshr_misses::total 150015 # number of WriteReq MSHR misses
1753system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 26855 # number of SoftPFReq MSHR misses
1754system.cpu1.dcache.SoftPFReq_mshr_misses::total 26855 # number of SoftPFReq MSHR misses
1755system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11222 # number of LoadLockedReq MSHR misses
1756system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11222 # number of LoadLockedReq MSHR misses
1757system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses
1758system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses
1759system.cpu1.dcache.demand_mshr_misses::cpu1.data 293689 # number of demand (read+write) MSHR misses
1760system.cpu1.dcache.demand_mshr_misses::total 293689 # number of demand (read+write) MSHR misses
1761system.cpu1.dcache.overall_mshr_misses::cpu1.data 320544 # number of overall MSHR misses
1762system.cpu1.dcache.overall_mshr_misses::total 320544 # number of overall MSHR misses
1763system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1427169251 # number of ReadReq MSHR miss cycles
1764system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1427169251 # number of ReadReq MSHR miss cycles
1765system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6022199670 # number of WriteReq MSHR miss cycles
1766system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6022199670 # number of WriteReq MSHR miss cycles
1767system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 445093004 # number of SoftPFReq MSHR miss cycles
1768system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 445093004 # number of SoftPFReq MSHR miss cycles
1769system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73834751 # number of LoadLockedReq MSHR miss cycles
1770system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73834751 # number of LoadLockedReq MSHR miss cycles
1771system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31881029 # number of StoreCondReq MSHR miss cycles
1772system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31881029 # number of StoreCondReq MSHR miss cycles
1773system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7449368921 # number of demand (read+write) MSHR miss cycles
1774system.cpu1.dcache.demand_mshr_miss_latency::total 7449368921 # number of demand (read+write) MSHR miss cycles
1775system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7894461925 # number of overall MSHR miss cycles
1776system.cpu1.dcache.overall_mshr_miss_latency::total 7894461925 # number of overall MSHR miss cycles
1777system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168604609000 # number of ReadReq MSHR uncacheable cycles
1778system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168604609000 # number of ReadReq MSHR uncacheable cycles
1779system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187299088 # number of WriteReq MSHR uncacheable cycles
1780system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187299088 # number of WriteReq MSHR uncacheable cycles
1781system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791908088 # number of overall MSHR uncacheable cycles
1782system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791908088 # number of overall MSHR uncacheable cycles
1783system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023361 # mshr miss rate for ReadReq accesses
1784system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023361 # mshr miss rate for ReadReq accesses
1785system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030153 # mshr miss rate for WriteReq accesses
1786system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030153 # mshr miss rate for WriteReq accesses
1787system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.417275 # mshr miss rate for SoftPFReq accesses
1788system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.417275 # mshr miss rate for SoftPFReq accesses
1789system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120462 # mshr miss rate for LoadLockedReq accesses
1790system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120462 # mshr miss rate for LoadLockedReq accesses
1791system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108461 # mshr miss rate for StoreCondReq accesses
1792system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108461 # mshr miss rate for StoreCondReq accesses
1793system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026398 # mshr miss rate for demand accesses
1794system.cpu1.dcache.demand_mshr_miss_rate::total 0.026398 # mshr miss rate for demand accesses
1795system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for overall accesses
1796system.cpu1.dcache.overall_mshr_miss_rate::total 0.028646 # mshr miss rate for overall accesses
1797system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9933.385658 # average ReadReq mshr miss latency
1798system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9933.385658 # average ReadReq mshr miss latency
1799system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40143.983402 # average WriteReq mshr miss latency
1800system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40143.983402 # average WriteReq mshr miss latency
1801system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16573.934239 # average SoftPFReq mshr miss latency
1802system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16573.934239 # average SoftPFReq mshr miss latency
1803system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6579.464534 # average LoadLockedReq mshr miss latency
1804system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6579.464534 # average LoadLockedReq mshr miss latency
1805system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3168.458458 # average StoreCondReq mshr miss latency
1806system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3168.458458 # average StoreCondReq mshr miss latency
1807system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25364.821022 # average overall mshr miss latency
1808system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25364.821022 # average overall mshr miss latency
1809system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24628.325363 # average overall mshr miss latency
1810system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24628.325363 # average overall mshr miss latency
1811system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1812system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1813system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1814system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1815system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1816system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1817system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1818system.iocache.tags.replacements 0 # number of replacements
1819system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
1820system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
1821system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
1822system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
1823system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1824system.iocache.tags.tag_accesses 0 # Number of tag accesses
1825system.iocache.tags.data_accesses 0 # Number of data accesses
1826system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1827system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1828system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
1829system.iocache.blocked::no_targets 0 # number of cycles access was blocked
1830system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1831system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1832system.iocache.fast_writes 0 # number of fast writes performed
1833system.iocache.cache_copies 0 # number of cache copies performed
1834system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745112259250 # number of ReadReq MSHR uncacheable cycles
1835system.iocache.ReadReq_mshr_uncacheable_latency::total 745112259250 # number of ReadReq MSHR uncacheable cycles
1836system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745112259250 # number of overall MSHR uncacheable cycles
1837system.iocache.overall_mshr_uncacheable_latency::total 745112259250 # number of overall MSHR uncacheable cycles
1838system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
1839system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1840system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
1841system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1842system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
1843
1844---------- End Simulation Statistics ----------