1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.871806 # Number of seconds simulated
4sim_ticks 2871806231000 # Number of ticks simulated
5final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 717242 # Simulator instruction rate (inst/s)
8host_op_rate 867543 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 15665668571 # Simulator tick rate (ticks/s)
10host_mem_usage 616200 # Number of bytes of host memory used
11host_seconds 183.32 # Real time elapsed on the host
12sim_insts 131483712 # Number of instructions simulated
13sim_ops 159036662 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1158756 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1268260 # Number of bytes read from this memory

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682system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14153.803140 # average overall miss latency
683system.cpu0.dcache.overall_avg_miss_latency::total 14153.803140 # average overall miss latency
684system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
685system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
686system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
687system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
688system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
689system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
690system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks
691system.cpu0.dcache.writebacks::total 733230 # number of writebacks
692system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25285 # number of ReadReq MSHR hits
693system.cpu0.dcache.ReadReq_mshr_hits::total 25285 # number of ReadReq MSHR hits
694system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits
695system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
696system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15695 # number of LoadLockedReq MSHR hits
697system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15695 # number of LoadLockedReq MSHR hits

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732system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1800000 # number of StoreCondFailReq MSHR miss cycles
733system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1800000 # number of StoreCondFailReq MSHR miss cycles
734system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432714000 # number of demand (read+write) MSHR miss cycles
735system.cpu0.dcache.demand_mshr_miss_latency::total 11432714000 # number of demand (read+write) MSHR miss cycles
736system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000 # number of overall MSHR miss cycles
737system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles
738system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles
739system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles
740system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628843000 # number of overall MSHR uncacheable cycles
741system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628843000 # number of overall MSHR uncacheable cycles
742system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses
743system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses
744system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses
745system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017926 # mshr miss rate for WriteReq accesses
746system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231342 # mshr miss rate for SoftPFReq accesses
747system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231342 # mshr miss rate for SoftPFReq accesses
748system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016916 # mshr miss rate for LoadLockedReq accesses
749system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016916 # mshr miss rate for LoadLockedReq accesses

--- 16 unchanged lines hidden (view full) ---

766system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
767system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
768system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15641.111446 # average overall mshr miss latency
769system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15641.111446 # average overall mshr miss latency
770system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260 # average overall mshr miss latency
771system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # average overall mshr miss latency
772system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208342.804161 # average ReadReq mshr uncacheable latency
773system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208342.804161 # average ReadReq mshr uncacheable latency
774system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109901.899993 # average overall mshr uncacheable latency
775system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109901.899993 # average overall mshr uncacheable latency
776system.cpu0.icache.tags.replacements 1147026 # number of replacements
777system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use
778system.cpu0.icache.tags.total_refs 120430031 # Total number of references to valid blocks.
779system.cpu0.icache.tags.sampled_refs 1147538 # Sample count of references to valid blocks.
780system.cpu0.icache.tags.avg_refs 104.946443 # Average number of references to valid blocks.
781system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit.
782system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor
783system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy

--- 42 unchanged lines hidden (view full) ---

826system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10667.958262 # average overall miss latency
827system.cpu0.icache.overall_avg_miss_latency::total 10667.958262 # average overall miss latency
828system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
829system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
830system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
831system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
832system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
833system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
834system.cpu0.icache.writebacks::writebacks 1147026 # number of writebacks
835system.cpu0.icache.writebacks::total 1147026 # number of writebacks
836system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147547 # number of ReadReq MSHR misses
837system.cpu0.icache.ReadReq_mshr_misses::total 1147547 # number of ReadReq MSHR misses
838system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147547 # number of demand (read+write) MSHR misses
839system.cpu0.icache.demand_mshr_misses::total 1147547 # number of demand (read+write) MSHR misses
840system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147547 # number of overall MSHR misses
841system.cpu0.icache.overall_mshr_misses::total 1147547 # number of overall MSHR misses

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864system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency
865system.cpu0.icache.demand_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency
866system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10167.958262 # average overall mshr miss latency
867system.cpu0.icache.overall_avg_mshr_miss_latency::total 10167.958262 # average overall mshr miss latency
868system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency
869system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency
870system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency
871system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency
872system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935584 # number of hwpf issued
873system.cpu0.l2cache.prefetcher.pfIdentified 1935659 # number of prefetch candidates identified
874system.cpu0.l2cache.prefetcher.pfBufferHit 66 # number of redundant prefetches already in prefetch queue
875system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
876system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
877system.cpu0.l2cache.prefetcher.pfSpanPage 246453 # number of prefetches not generated due to page crossing
878system.cpu0.l2cache.tags.replacements 273594 # number of replacements
879system.cpu0.l2cache.tags.tagsinuse 16077.204583 # Cycle average of tags in use

--- 185 unchanged lines hidden (view full) ---

1065system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43698.326879 # average overall miss latency
1066system.cpu0.l2cache.overall_avg_miss_latency::total 50634.109884 # average overall miss latency
1067system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1068system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1069system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1070system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1071system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1072system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1073system.cpu0.l2cache.unused_prefetches 10692 # number of HardPF blocks evicted w/o reference
1074system.cpu0.l2cache.writebacks::writebacks 231848 # number of writebacks
1075system.cpu0.l2cache.writebacks::total 231848 # number of writebacks
1076system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1793 # number of ReadExReq MSHR hits
1077system.cpu0.l2cache.ReadExReq_mshr_hits::total 1793 # number of ReadExReq MSHR hits
1078system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 59 # number of ReadSharedReq MSHR hits
1079system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 59 # number of ReadSharedReq MSHR hits
1080system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1852 # number of demand (read+write) MSHR hits

--- 62 unchanged lines hidden (view full) ---

1143system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1575500 # number of overall MSHR miss cycles
1144system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3008596500 # number of overall MSHR miss cycles
1145system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5022496500 # number of overall MSHR miss cycles
1146system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20425308140 # number of overall MSHR miss cycles
1147system.cpu0.l2cache.overall_mshr_miss_latency::total 28461338140 # number of overall MSHR miss cycles
1148system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles
1149system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6373893500 # number of ReadReq MSHR uncacheable cycles
1150system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560105000 # number of ReadReq MSHR uncacheable cycles
1151system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles
1152system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6373893500 # number of overall MSHR uncacheable cycles
1153system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7560105000 # number of overall MSHR uncacheable cycles
1154system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013766 # mshr miss rate for ReadReq accesses
1155system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.014908 # mshr miss rate for ReadReq accesses
1156system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.014117 # mshr miss rate for ReadReq accesses
1157system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1158system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1159system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses
1160system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses
1161system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses

--- 43 unchanged lines hidden (view full) ---

1205system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency
1206system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency
1207system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency
1208system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average overall mshr miss latency
1209system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 # average overall mshr miss latency
1210system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency
1211system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency
1212system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency
1213system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency
1214system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316 # average overall mshr uncacheable latency
1215system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226 # average overall mshr uncacheable latency
1216system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter.
1217system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1218system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1219system.cpu0.toL2Bus.snoop_filter.tot_snoops 319838 # Total number of snoops made to the snoop filter.
1220system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316964 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1221system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2874 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1222system.cpu0.toL2Bus.trans_dist::ReadReq 63699 # Transaction distribution
1223system.cpu0.toL2Bus.trans_dist::ReadResp 1766064 # Transaction distribution

--- 383 unchanged lines hidden (view full) ---

1607system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20616.095936 # average overall miss latency
1608system.cpu1.dcache.overall_avg_miss_latency::total 20616.095936 # average overall miss latency
1609system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1610system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1611system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1612system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1613system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1614system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1615system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks
1616system.cpu1.dcache.writebacks::total 148452 # number of writebacks
1617system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits
1618system.cpu1.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
1619system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11671 # number of LoadLockedReq MSHR hits
1620system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11671 # number of LoadLockedReq MSHR hits
1621system.cpu1.dcache.demand_mshr_hits::cpu1.data 223 # number of demand (read+write) MSHR hits
1622system.cpu1.dcache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits

--- 32 unchanged lines hidden (view full) ---

1655system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4985000 # number of StoreCondFailReq MSHR miss cycles
1656system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4985000 # number of StoreCondFailReq MSHR miss cycles
1657system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4262527500 # number of demand (read+write) MSHR miss cycles
1658system.cpu1.dcache.demand_mshr_miss_latency::total 4262527500 # number of demand (read+write) MSHR miss cycles
1659system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000 # number of overall MSHR miss cycles
1660system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles
1661system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles
1662system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles
1663system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 439527500 # number of overall MSHR uncacheable cycles
1664system.cpu1.dcache.overall_mshr_uncacheable_latency::total 439527500 # number of overall MSHR uncacheable cycles
1665system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses
1666system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses
1667system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses
1668system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028102 # mshr miss rate for WriteReq accesses
1669system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360930 # mshr miss rate for SoftPFReq accesses
1670system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360930 # mshr miss rate for SoftPFReq accesses
1671system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056993 # mshr miss rate for LoadLockedReq accesses
1672system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056993 # mshr miss rate for LoadLockedReq accesses

--- 16 unchanged lines hidden (view full) ---

1689system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1690system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1691system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22182.525227 # average overall mshr miss latency
1692system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22182.525227 # average overall mshr miss latency
1693system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355 # average overall mshr miss latency
1694system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency
1695system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency
1696system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency
1697system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720 # average overall mshr uncacheable latency
1698system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720 # average overall mshr uncacheable latency
1699system.cpu1.icache.tags.replacements 463484 # number of replacements
1700system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use
1701system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks.
1702system.cpu1.icache.tags.sampled_refs 463996 # Sample count of references to valid blocks.
1703system.cpu1.icache.tags.avg_refs 29.004039 # Average number of references to valid blocks.
1704system.cpu1.icache.tags.warmup_cycle 106358922000 # Cycle when the warmup percentage was hit.
1705system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310914 # Average occupied blocks per requestor
1706system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy

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1749system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency
1750system.cpu1.icache.overall_avg_miss_latency::total 9082.120320 # average overall miss latency
1751system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1752system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1753system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1754system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1755system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1756system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1757system.cpu1.icache.writebacks::writebacks 463484 # number of writebacks
1758system.cpu1.icache.writebacks::total 463484 # number of writebacks
1759system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463996 # number of ReadReq MSHR misses
1760system.cpu1.icache.ReadReq_mshr_misses::total 463996 # number of ReadReq MSHR misses
1761system.cpu1.icache.demand_mshr_misses::cpu1.inst 463996 # number of demand (read+write) MSHR misses
1762system.cpu1.icache.demand_mshr_misses::total 463996 # number of demand (read+write) MSHR misses
1763system.cpu1.icache.overall_mshr_misses::cpu1.inst 463996 # number of overall MSHR misses
1764system.cpu1.icache.overall_mshr_misses::total 463996 # number of overall MSHR misses

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1787system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency
1788system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency
1789system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency
1790system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency
1791system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency
1792system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency
1793system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency
1794system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency
1795system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued
1796system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified
1797system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue
1798system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1799system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1800system.cpu1.l2cache.prefetcher.pfSpanPage 50208 # number of prefetches not generated due to page crossing
1801system.cpu1.l2cache.tags.replacements 31332 # number of replacements
1802system.cpu1.l2cache.tags.tagsinuse 14956.481117 # Cycle average of tags in use

--- 180 unchanged lines hidden (view full) ---

1983system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32054.155988 # average overall miss latency
1984system.cpu1.l2cache.overall_avg_miss_latency::total 34329.100414 # average overall miss latency
1985system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1986system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1987system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1988system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1989system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1990system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1991system.cpu1.l2cache.unused_prefetches 502 # number of HardPF blocks evicted w/o reference
1992system.cpu1.l2cache.writebacks::writebacks 26072 # number of writebacks
1993system.cpu1.l2cache.writebacks::total 26072 # number of writebacks
1994system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 73 # number of ReadExReq MSHR hits
1995system.cpu1.l2cache.ReadExReq_mshr_hits::total 73 # number of ReadExReq MSHR hits
1996system.cpu1.l2cache.demand_mshr_hits::cpu1.data 73 # number of demand (read+write) MSHR hits
1997system.cpu1.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
1998system.cpu1.l2cache.overall_mshr_hits::cpu1.data 73 # number of overall MSHR hits

--- 60 unchanged lines hidden (view full) ---

2059system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4155500 # number of overall MSHR miss cycles
2060system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 476217500 # number of overall MSHR miss cycles
2061system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2493275000 # number of overall MSHR miss cycles
2062system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 927478543 # number of overall MSHR miss cycles
2063system.cpu1.l2cache.overall_mshr_miss_latency::total 3906024043 # number of overall MSHR miss cycles
2064system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles
2065system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414523000 # number of ReadReq MSHR uncacheable cycles
2066system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436742000 # number of ReadReq MSHR uncacheable cycles
2067system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles
2068system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 414523000 # number of overall MSHR uncacheable cycles
2069system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 436742000 # number of overall MSHR uncacheable cycles
2070system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for ReadReq accesses
2071system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for ReadReq accesses
2072system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140986 # mshr miss rate for ReadReq accesses
2073system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2074system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2075system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2076system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2077system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses

--- 43 unchanged lines hidden (view full) ---

2121system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency
2122system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency
2123system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency
2124system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average overall mshr miss latency
2125system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 # average overall mshr miss latency
2126system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency
2127system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency
2128system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency
2129system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency
2130system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214 # average overall mshr uncacheable latency
2131system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348 # average overall mshr uncacheable latency
2132system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter.
2133system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2134system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2135system.cpu1.toL2Bus.snoop_filter.tot_snoops 168501 # Total number of snoops made to the snoop filter.
2136system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166697 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2137system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1804 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2138system.cpu1.toL2Bus.trans_dist::ReadReq 10096 # Transaction distribution
2139system.cpu1.toL2Bus.trans_dist::ReadResp 652859 # Transaction distribution

--- 154 unchanged lines hidden (view full) ---

2294system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2295system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2296system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2297system.iocache.tags.data_accesses 328311 # Number of data accesses
2298system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2299system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2300system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2301system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2302system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses
2303system.iocache.demand_misses::total 36479 # number of demand (read+write) misses
2304system.iocache.overall_misses::realview.ide 36479 # number of overall misses
2305system.iocache.overall_misses::total 36479 # number of overall misses
2306system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles
2307system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles
2308system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles
2309system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles
2310system.iocache.demand_miss_latency::realview.ide 4609993722 # number of demand (read+write) miss cycles
2311system.iocache.demand_miss_latency::total 4609993722 # number of demand (read+write) miss cycles
2312system.iocache.overall_miss_latency::realview.ide 4609993722 # number of overall miss cycles
2313system.iocache.overall_miss_latency::total 4609993722 # number of overall miss cycles
2314system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2315system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2316system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2317system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2318system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses
2319system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses
2320system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses
2321system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses
2322system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2323system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2324system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2325system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2326system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2327system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2328system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2329system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2330system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608 # average ReadReq miss latency
2331system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency
2332system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency
2333system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency
2334system.iocache.demand_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency
2335system.iocache.demand_avg_miss_latency::total 126373.906138 # average overall miss latency
2336system.iocache.overall_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency
2337system.iocache.overall_avg_miss_latency::total 126373.906138 # average overall miss latency
2338system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked
2339system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2340system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
2341system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2342system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked
2343system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2344system.iocache.writebacks::writebacks 36206 # number of writebacks
2345system.iocache.writebacks::total 36206 # number of writebacks
2346system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2347system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2348system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2349system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2350system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses
2351system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses
2352system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses
2353system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses
2354system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles
2355system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles
2356system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles
2357system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles
2358system.iocache.demand_mshr_miss_latency::realview.ide 2784349209 # number of demand (read+write) MSHR miss cycles
2359system.iocache.demand_mshr_miss_latency::total 2784349209 # number of demand (read+write) MSHR miss cycles
2360system.iocache.overall_mshr_miss_latency::realview.ide 2784349209 # number of overall MSHR miss cycles
2361system.iocache.overall_mshr_miss_latency::total 2784349209 # number of overall MSHR miss cycles
2362system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2363system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2364system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2365system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2366system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2367system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2368system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2369system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2370system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608 # average ReadReq mshr miss latency
2371system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency
2372system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency
2373system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency
2374system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency
2375system.iocache.demand_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency
2376system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency
2377system.iocache.overall_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency
2378system.l2c.tags.replacements 124374 # number of replacements
2379system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use
2380system.l2c.tags.total_refs 421293 # Total number of references to valid blocks.
2381system.l2c.tags.sampled_refs 188431 # Sample count of references to valid blocks.
2382system.l2c.tags.avg_refs 2.235795 # Average number of references to valid blocks.
2383system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2384system.l2c.tags.occ_blocks::writebacks 13456.936548 # Average occupied blocks per requestor
2385system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.884029 # Average occupied blocks per requestor

--- 265 unchanged lines hidden (view full) ---

2651system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155144.114957 # average overall miss latency
2652system.l2c.overall_avg_miss_latency::total 143055.948758 # average overall miss latency
2653system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2654system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2655system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2656system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2657system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2658system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2659system.l2c.writebacks::writebacks 97172 # number of writebacks
2660system.l2c.writebacks::total 97172 # number of writebacks
2661system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 4 # number of ReadSharedReq MSHR hits
2662system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 9 # number of ReadSharedReq MSHR hits
2663system.l2c.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits
2664system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
2665system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
2666system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits

--- 87 unchanged lines hidden (view full) ---

2754system.l2c.overall_mshr_miss_latency::cpu1.data 1047597021 # number of overall MSHR miss cycles
2755system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 796678627 # number of overall MSHR miss cycles
2756system.l2c.overall_mshr_miss_latency::total 25144697820 # number of overall MSHR miss cycles
2757system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles
2758system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801182501 # number of ReadReq MSHR uncacheable cycles
2759system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles
2760system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359054501 # number of ReadReq MSHR uncacheable cycles
2761system.l2c.ReadReq_mshr_uncacheable_latency::total 7203084502 # number of ReadReq MSHR uncacheable cycles
2762system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles
2763system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5801182501 # number of overall MSHR uncacheable cycles
2764system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles
2765system.l2c.overall_mshr_uncacheable_latency::cpu1.data 359054501 # number of overall MSHR uncacheable cycles
2766system.l2c.overall_mshr_uncacheable_latency::total 7203084502 # number of overall MSHR uncacheable cycles
2767system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2768system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2769system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.224375 # mshr miss rate for UpgradeReq accesses
2770system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.533969 # mshr miss rate for UpgradeReq accesses
2771system.l2c.UpgradeReq_mshr_miss_rate::total 0.252741 # mshr miss rate for UpgradeReq accesses
2772system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.224278 # mshr miss rate for SCUpgradeReq accesses
2773system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.576698 # mshr miss rate for SCUpgradeReq accesses
2774system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.383350 # mshr miss rate for SCUpgradeReq accesses

--- 63 unchanged lines hidden (view full) ---

2838system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123232.210446 # average overall mshr miss latency
2839system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145140.941337 # average overall mshr miss latency
2840system.l2c.overall_avg_mshr_miss_latency::total 133059.737740 # average overall mshr miss latency
2841system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency
2842system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182329.650847 # average ReadReq mshr uncacheable latency
2843system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency
2844system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116613.998376 # average ReadReq mshr uncacheable latency
2845system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163353.770314 # average ReadReq mshr uncacheable latency
2846system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency
2847system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96179.827923 # average overall mshr uncacheable latency
2848system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency
2849system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65258.906034 # average overall mshr uncacheable latency
2850system.l2c.overall_avg_mshr_uncacheable_latency::total 96019.362305 # average overall mshr uncacheable latency
2851system.membus.trans_dist::ReadReq 44095 # Transaction distribution
2852system.membus.trans_dist::ReadResp 214453 # Transaction distribution
2853system.membus.trans_dist::WriteReq 30922 # Transaction distribution
2854system.membus.trans_dist::WriteResp 30922 # Transaction distribution
2855system.membus.trans_dist::WritebackDirty 133378 # Transaction distribution
2856system.membus.trans_dist::CleanEvict 14958 # Transaction distribution
2857system.membus.trans_dist::UpgradeReq 73332 # Transaction distribution
2858system.membus.trans_dist::SCUpgradeReq 39852 # Transaction distribution

--- 136 unchanged lines hidden ---