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1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.871782 # Number of seconds simulated
4sim_ticks 2871782342000 # Number of ticks simulated
5final_tick 2871782342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 937604 # Simulator instruction rate (inst/s)
8host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 20478123685 # Simulator tick rate (ticks/s)
10host_mem_usage 614632 # Number of bytes of host memory used
11host_seconds 140.24 # Real time elapsed on the host
12sim_insts 131486349 # Number of instructions simulated
13sim_ops 159039994 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1156004 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1264932 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602496 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 151508 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 548500 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.l2cache.prefetcher 349120 # Number of bytes read from this memory
25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
26system.physmem.bytes_read::total 12074032 # Number of bytes read from this memory
27system.physmem.bytes_inst_read::cpu0.inst 1156004 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu1.inst 151508 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 1307512 # Number of instructions bytes read from this memory
30system.physmem.bytes_written::writebacks 8524352 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
33system.physmem.bytes_written::total 8541916 # Number of bytes written to this memory
34system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.inst 26516 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.data 20284 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.l2cache.prefetcher 134414 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.inst 2522 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.data 8591 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.l2cache.prefetcher 5455 # Number of read requests responded to by this memory
43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
44system.physmem.num_reads::total 197805 # Number of read requests responded to by this memory
45system.physmem.num_writes::writebacks 133193 # Number of write requests responded to by this memory
46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
48system.physmem.num_writes::total 137584 # Number of write requests responded to by this memory
49system.physmem.bw_read::cpu0.dtb.walker 111 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.inst 402539 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.data 440469 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.l2cache.prefetcher 2995525 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.inst 52757 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.data 190996 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.l2cache.prefetcher 121569 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::total 4204369 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_inst_read::cpu0.inst 402539 # Instruction read bandwidth from this memory (bytes/s)
61system.physmem.bw_inst_read::cpu1.inst 52757 # Instruction read bandwidth from this memory (bytes/s)
62system.physmem.bw_inst_read::total 455296 # Instruction read bandwidth from this memory (bytes/s)
63system.physmem.bw_write::writebacks 2968314 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
66system.physmem.bw_write::total 2974430 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_total::writebacks 2968314 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.dtb.walker 111 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu0.inst 402539 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.data 446571 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.l2cache.prefetcher 2995525 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu1.inst 52757 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu1.data 191010 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.l2cache.prefetcher 121569 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::total 7178799 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.readReqs 197805 # Number of read requests accepted
80system.physmem.writeReqs 137584 # Number of write requests accepted
81system.physmem.readBursts 197805 # Number of DRAM read bursts, including those serviced by the write queue
82system.physmem.writeBursts 137584 # Number of DRAM write bursts, including those merged in the write queue
83system.physmem.bytesReadDRAM 12650304 # Total number of bytes read from DRAM
84system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue
85system.physmem.bytesWritten 8554240 # Total number of bytes written to DRAM
86system.physmem.bytesReadSys 12074032 # Total read bytes from the system interface side
87system.physmem.bytesWrittenSys 8541916 # Total written bytes from the system interface side
88system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue
89system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one
90system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
91system.physmem.perBankRdBursts::0 11699 # Per bank write bursts
92system.physmem.perBankRdBursts::1 11843 # Per bank write bursts
93system.physmem.perBankRdBursts::2 11790 # Per bank write bursts
94system.physmem.perBankRdBursts::3 11735 # Per bank write bursts
95system.physmem.perBankRdBursts::4 20524 # Per bank write bursts
96system.physmem.perBankRdBursts::5 11797 # Per bank write bursts
97system.physmem.perBankRdBursts::6 12442 # Per bank write bursts
98system.physmem.perBankRdBursts::7 12572 # Per bank write bursts
99system.physmem.perBankRdBursts::8 12187 # Per bank write bursts
100system.physmem.perBankRdBursts::9 12631 # Per bank write bursts
101system.physmem.perBankRdBursts::10 11774 # Per bank write bursts
102system.physmem.perBankRdBursts::11 11306 # Per bank write bursts
103system.physmem.perBankRdBursts::12 11587 # Per bank write bursts
104system.physmem.perBankRdBursts::13 11723 # Per bank write bursts
105system.physmem.perBankRdBursts::14 11020 # Per bank write bursts
106system.physmem.perBankRdBursts::15 11031 # Per bank write bursts
107system.physmem.perBankWrBursts::0 8350 # Per bank write bursts
108system.physmem.perBankWrBursts::1 8610 # Per bank write bursts
109system.physmem.perBankWrBursts::2 8670 # Per bank write bursts
110system.physmem.perBankWrBursts::3 8312 # Per bank write bursts
111system.physmem.perBankWrBursts::4 8160 # Per bank write bursts
112system.physmem.perBankWrBursts::5 8304 # Per bank write bursts
113system.physmem.perBankWrBursts::6 8940 # Per bank write bursts
114system.physmem.perBankWrBursts::7 8786 # Per bank write bursts
115system.physmem.perBankWrBursts::8 8636 # Per bank write bursts
116system.physmem.perBankWrBursts::9 9040 # Per bank write bursts
117system.physmem.perBankWrBursts::10 8341 # Per bank write bursts
118system.physmem.perBankWrBursts::11 8261 # Per bank write bursts
119system.physmem.perBankWrBursts::12 8330 # Per bank write bursts
120system.physmem.perBankWrBursts::13 7860 # Per bank write bursts
121system.physmem.perBankWrBursts::14 7712 # Per bank write bursts
122system.physmem.perBankWrBursts::15 7348 # Per bank write bursts
123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
124system.physmem.numWrRetry 27 # Number of times write queue was full causing retry
125system.physmem.totGap 2871781902000 # Total gap between requests
126system.physmem.readPktSize::0 0 # Read request sizes (log2)
127system.physmem.readPktSize::1 0 # Read request sizes (log2)
128system.physmem.readPktSize::2 9732 # Read request sizes (log2)
129system.physmem.readPktSize::3 28 # Read request sizes (log2)
130system.physmem.readPktSize::4 0 # Read request sizes (log2)
131system.physmem.readPktSize::5 0 # Read request sizes (log2)
132system.physmem.readPktSize::6 188045 # Read request sizes (log2)
133system.physmem.writePktSize::0 0 # Write request sizes (log2)
134system.physmem.writePktSize::1 0 # Write request sizes (log2)
135system.physmem.writePktSize::2 4391 # Write request sizes (log2)
136system.physmem.writePktSize::3 0 # Write request sizes (log2)
137system.physmem.writePktSize::4 0 # Write request sizes (log2)
138system.physmem.writePktSize::5 0 # Write request sizes (log2)
139system.physmem.writePktSize::6 133193 # Write request sizes (log2)
140system.physmem.rdQLenPdf::0 138723 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::1 15603 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::2 10240 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::3 8695 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::4 6977 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::5 5455 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::6 4557 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::7 3833 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::8 3359 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::9 91 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::11 38 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::12 14 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
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179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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187system.physmem.wrQLenPdf::15 2692 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see
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190system.physmem.wrQLenPdf::18 5083 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::19 6476 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::20 6358 # What write queue length does an incoming req see
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200system.physmem.wrQLenPdf::28 8780 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::29 10954 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::30 8505 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::31 7731 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::32 7612 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::33 1066 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::34 335 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::35 261 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::39 173 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::43 126 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::48 94 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::50 136 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::52 128 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::54 118 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::56 92 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::58 60 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::59 92 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see
236system.physmem.bytesPerActivate::samples 87582 # Bytes accessed per row activation
237system.physmem.bytesPerActivate::mean 242.110023 # Bytes accessed per row activation
238system.physmem.bytesPerActivate::gmean 136.595388 # Bytes accessed per row activation
239system.physmem.bytesPerActivate::stdev 304.444001 # Bytes accessed per row activation
240system.physmem.bytesPerActivate::0-127 46635 53.25% 53.25% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::128-255 17297 19.75% 73.00% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::256-383 6011 6.86% 79.86% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::384-511 3421 3.91% 83.77% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::512-639 2493 2.85% 86.61% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::640-767 1531 1.75% 88.36% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::768-895 857 0.98% 89.34% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::896-1023 971 1.11% 90.45% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::1024-1151 8366 9.55% 100.00% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::total 87582 # Bytes accessed per row activation
250system.physmem.rdPerTurnAround::samples 6415 # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::mean 30.812159 # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::stdev 590.882305 # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::0-2047 6413 99.97% 99.97% # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::total 6415 # Reads before turning the bus around for writes
257system.physmem.wrPerTurnAround::samples 6415 # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::mean 20.835542 # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::gmean 18.951972 # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::stdev 14.109397 # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::16-19 5337 83.20% 83.20% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::20-23 463 7.22% 90.41% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::24-27 65 1.01% 91.43% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::28-31 41 0.64% 92.07% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::32-35 43 0.67% 92.74% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::36-39 15 0.23% 92.97% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::40-43 61 0.95% 93.92% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::44-47 12 0.19% 94.11% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::48-51 120 1.87% 95.98% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::52-55 12 0.19% 96.17% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::56-59 8 0.12% 96.29% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::60-63 12 0.19% 96.48% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::64-67 75 1.17% 97.65% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::68-71 9 0.14% 97.79% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::72-75 4 0.06% 97.85% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::76-79 25 0.39% 98.24% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::80-83 75 1.17% 99.41% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::116-119 1 0.02% 99.59% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::128-131 11 0.17% 99.77% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::132-135 3 0.05% 99.81% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::136-139 1 0.02% 99.83% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::144-147 5 0.08% 99.91% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::160-163 2 0.03% 99.95% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::total 6415 # Writes before turning the bus around for reads
295system.physmem.totQLat 4510532456 # Total ticks spent queuing
296system.physmem.totMemAccLat 8216676206 # Total ticks spent from burst creation until serviced by the DRAM
297system.physmem.totBusLat 988305000 # Total ticks spent in databus transfers
298system.physmem.avgQLat 22819.54 # Average queueing delay per DRAM burst
299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
300system.physmem.avgMemAccLat 41569.54 # Average memory access latency per DRAM burst
301system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s
302system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s
303system.physmem.avgRdBWSys 4.20 # Average system read bandwidth in MiByte/s
304system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s
305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
306system.physmem.busUtil 0.06 # Data bus utilization in percentage
307system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
308system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
309system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing
310system.physmem.avgWrQLen 25.88 # Average write queue length when enqueuing
311system.physmem.readRowHits 165067 # Number of row buffer hits during reads
312system.physmem.writeRowHits 78671 # Number of row buffer hits during writes
313system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads
314system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes
315system.physmem.avgGap 8562540.52 # Average gap between requests
316system.physmem.pageHitRate 73.56 # Row buffer hit rate, read and write combined
317system.physmem_0.actEnergy 341273520 # Energy for activate commands per rank (pJ)
318system.physmem_0.preEnergy 186210750 # Energy for precharge commands per rank (pJ)
319system.physmem_0.readEnergy 814335600 # Energy for read commands per rank (pJ)
320system.physmem_0.writeEnergy 441495360 # Energy for write commands per rank (pJ)
321system.physmem_0.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ)
322system.physmem_0.actBackEnergy 86023351485 # Energy for active background per rank (pJ)
323system.physmem_0.preBackEnergy 1647608604750 # Energy for precharge background per rank (pJ)
324system.physmem_0.totalEnergy 1922985930585 # Total energy per rank (pJ)
325system.physmem_0.averagePower 669.614762 # Core power per rank (mW)
326system.physmem_0.memoryStateTime::IDLE 2740794855198 # Time in different power states
327system.physmem_0.memoryStateTime::REF 95895020000 # Time in different power states
328system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
329system.physmem_0.memoryStateTime::ACT 35089613552 # Time in different power states
330system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
331system.physmem_1.actEnergy 320846400 # Energy for activate commands per rank (pJ)
332system.physmem_1.preEnergy 175065000 # Energy for precharge commands per rank (pJ)
333system.physmem_1.readEnergy 727412400 # Energy for read commands per rank (pJ)
334system.physmem_1.writeEnergy 424621440 # Energy for write commands per rank (pJ)
335system.physmem_1.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ)
336system.physmem_1.actBackEnergy 84787415640 # Energy for active background per rank (pJ)
337system.physmem_1.preBackEnergy 1648692759000 # Energy for precharge background per rank (pJ)
338system.physmem_1.totalEnergy 1922698779000 # Total energy per rank (pJ)
339system.physmem_1.averagePower 669.514771 # Core power per rank (mW)
340system.physmem_1.memoryStateTime::IDLE 2742610583350 # Time in different power states
341system.physmem_1.memoryStateTime::REF 95895020000 # Time in different power states
342system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
343system.physmem_1.memoryStateTime::ACT 33276576650 # Time in different power states
344system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
345system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
346system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
347system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
348system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
349system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
350system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
351system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory

--- 39 unchanged lines hidden (view full) ---

391system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
392system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
393system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
394system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
395system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
396system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
397system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
398system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
399system.cpu0.dtb.walker.walks 8793 # Table walker walks requested
400system.cpu0.dtb.walker.walksShort 8793 # Table walker walks initiated with short descriptors
401system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1631 # Level at which table walker walks with short descriptors terminate
402system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7162 # Level at which table walker walks with short descriptors terminate
403system.cpu0.dtb.walker.walkWaitTime::samples 8793 # Table walker wait (enqueue to first request) latency
404system.cpu0.dtb.walker.walkWaitTime::0 8793 100.00% 100.00% # Table walker wait (enqueue to first request) latency
405system.cpu0.dtb.walker.walkWaitTime::total 8793 # Table walker wait (enqueue to first request) latency
406system.cpu0.dtb.walker.walkCompletionTime::samples 7275 # Table walker service (enqueue to completion) latency
407system.cpu0.dtb.walker.walkCompletionTime::mean 12044.604811 # Table walker service (enqueue to completion) latency
408system.cpu0.dtb.walker.walkCompletionTime::gmean 11100.960867 # Table walker service (enqueue to completion) latency
409system.cpu0.dtb.walker.walkCompletionTime::stdev 5725.376750 # Table walker service (enqueue to completion) latency
410system.cpu0.dtb.walker.walkCompletionTime::0-16383 6764 92.98% 92.98% # Table walker service (enqueue to completion) latency
411system.cpu0.dtb.walker.walkCompletionTime::16384-32767 475 6.53% 99.51% # Table walker service (enqueue to completion) latency
412system.cpu0.dtb.walker.walkCompletionTime::32768-49151 28 0.38% 99.89% # Table walker service (enqueue to completion) latency
413system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.05% 99.95% # Table walker service (enqueue to completion) latency
414system.cpu0.dtb.walker.walkCompletionTime::131072-147455 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
415system.cpu0.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
416system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
417system.cpu0.dtb.walker.walkCompletionTime::total 7275 # Table walker service (enqueue to completion) latency
418system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution
419system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution
420system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution
421system.cpu0.dtb.walker.walkPageSizes::4K 5691 78.23% 78.23% # Table walker page sizes translated
422system.cpu0.dtb.walker.walkPageSizes::1M 1584 21.77% 100.00% # Table walker page sizes translated
423system.cpu0.dtb.walker.walkPageSizes::total 7275 # Table walker page sizes translated
424system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8793 # Table walker requests started/completed, data/inst
425system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
426system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8793 # Table walker requests started/completed, data/inst
427system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7275 # Table walker requests started/completed, data/inst
428system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
429system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7275 # Table walker requests started/completed, data/inst
430system.cpu0.dtb.walker.walkRequestOrigin::total 16068 # Table walker requests started/completed, data/inst
431system.cpu0.dtb.inst_hits 0 # ITB inst hits
432system.cpu0.dtb.inst_misses 0 # ITB inst misses
433system.cpu0.dtb.read_hits 25747110 # DTB read hits
434system.cpu0.dtb.read_misses 7587 # DTB read misses
435system.cpu0.dtb.write_hits 19248161 # DTB write hits
436system.cpu0.dtb.write_misses 1206 # DTB write misses
437system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
438system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
439system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
440system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
441system.cpu0.dtb.flush_entries 3752 # Number of entries that have been flushed from TLB
442system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
443system.cpu0.dtb.prefetch_faults 1822 # Number of TLB faults due to prefetch
444system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
445system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions
446system.cpu0.dtb.read_accesses 25754697 # DTB read accesses
447system.cpu0.dtb.write_accesses 19249367 # DTB write accesses
448system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
449system.cpu0.dtb.hits 44995271 # DTB hits
450system.cpu0.dtb.misses 8793 # DTB misses
451system.cpu0.dtb.accesses 45004064 # DTB accesses
452system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
455system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
456system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
459system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 21 unchanged lines hidden (view full) ---

481system.cpu0.itb.walker.walks 3674 # Table walker walks requested
482system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors
483system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate
484system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate
485system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency
486system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency
487system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency
488system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency
489system.cpu0.itb.walker.walkCompletionTime::mean 12540.566770 # Table walker service (enqueue to completion) latency
490system.cpu0.itb.walker.walkCompletionTime::gmean 11604.890292 # Table walker service (enqueue to completion) latency
491system.cpu0.itb.walker.walkCompletionTime::stdev 7309.377161 # Table walker service (enqueue to completion) latency
492system.cpu0.itb.walker.walkCompletionTime::0-32767 2541 98.64% 98.64% # Table walker service (enqueue to completion) latency
493system.cpu0.itb.walker.walkCompletionTime::32768-65535 33 1.28% 99.92% # Table walker service (enqueue to completion) latency
494system.cpu0.itb.walker.walkCompletionTime::131072-163839 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
495system.cpu0.itb.walker.walkCompletionTime::262144-294911 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
496system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency
497system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution
498system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution
499system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution
500system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated
501system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated
502system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated
503system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
504system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst
505system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst
506system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
507system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst
508system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst
509system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst
510system.cpu0.itb.inst_hits 121581439 # ITB inst hits
511system.cpu0.itb.inst_misses 3674 # ITB inst misses
512system.cpu0.itb.read_hits 0 # DTB read hits
513system.cpu0.itb.read_misses 0 # DTB read misses
514system.cpu0.itb.write_hits 0 # DTB write hits
515system.cpu0.itb.write_misses 0 # DTB write misses
516system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
517system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
518system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
519system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
520system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB
521system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
522system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
523system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
524system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
525system.cpu0.itb.read_accesses 0 # DTB read accesses
526system.cpu0.itb.write_accesses 0 # DTB write accesses
527system.cpu0.itb.inst_accesses 121585113 # ITB inst accesses
528system.cpu0.itb.hits 121581439 # DTB hits
529system.cpu0.itb.misses 3674 # DTB misses
530system.cpu0.itb.accesses 121585113 # DTB accesses
531system.cpu0.numCycles 5743564684 # number of cpu cycles simulated
532system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
533system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
534system.cpu0.kern.inst.arm 0 # number of arm instructions executed
535system.cpu0.kern.inst.quiesce 1899 # number of quiesce instructions executed
536system.cpu0.committedInsts 117764996 # Number of instructions committed
537system.cpu0.committedOps 142323546 # Number of ops (including micro ops) committed
538system.cpu0.num_int_alu_accesses 125936873 # Number of integer alu accesses
539system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses
540system.cpu0.num_func_calls 12772448 # number of times a function call or return occured
541system.cpu0.num_conditional_control_insts 16008688 # number of instructions that are conditional controls
542system.cpu0.num_int_insts 125936873 # number of integer instructions
543system.cpu0.num_fp_insts 11483 # number of float instructions
544system.cpu0.num_int_register_reads 231719006 # number of times the integer registers were read
545system.cpu0.num_int_register_writes 87450436 # number of times the integer registers were written
546system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read
547system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written
548system.cpu0.num_cc_register_reads 515468589 # number of times the CC registers were read
549system.cpu0.num_cc_register_writes 53496392 # number of times the CC registers were written
550system.cpu0.num_mem_refs 46152180 # number of memory refs
551system.cpu0.num_load_insts 26006060 # Number of load instructions
552system.cpu0.num_store_insts 20146120 # Number of store instructions
553system.cpu0.num_idle_cycles 5455990176.452100 # Number of idle cycles
554system.cpu0.num_busy_cycles 287574507.547900 # Number of busy cycles
555system.cpu0.not_idle_fraction 0.050069 # Percentage of non-idle cycles
556system.cpu0.idle_fraction 0.949931 # Percentage of idle cycles
557system.cpu0.Branches 29546529 # Number of branches fetched
558system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction
559system.cpu0.op_class::IntAlu 99842345 68.33% 68.33% # Class of executed instruction
560system.cpu0.op_class::IntMult 112141 0.08% 68.41% # Class of executed instruction
561system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction
562system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction
563system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction
564system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction
565system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction
566system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction
567system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction
568system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction
569system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction
570system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction
571system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction
572system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction
573system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction
574system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction
575system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction
576system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction
577system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction
578system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction
579system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction
580system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction
581system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction
582system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction
583system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction
584system.cpu0.op_class::SimdFloatMisc 8311 0.01% 68.41% # Class of executed instruction
585system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction
586system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction
587system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction
588system.cpu0.op_class::MemRead 26006060 17.80% 86.21% # Class of executed instruction
589system.cpu0.op_class::MemWrite 20146120 13.79% 100.00% # Class of executed instruction
590system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
591system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
592system.cpu0.op_class::total 146117292 # Class of executed instruction
593system.cpu0.dcache.tags.replacements 732778 # number of replacements
594system.cpu0.dcache.tags.tagsinuse 487.345221 # Cycle average of tags in use
595system.cpu0.dcache.tags.total_refs 44083181 # Total number of references to valid blocks.
596system.cpu0.dcache.tags.sampled_refs 733290 # Sample count of references to valid blocks.
597system.cpu0.dcache.tags.avg_refs 60.116981 # Average number of references to valid blocks.
598system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit.
599system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.345221 # Average occupied blocks per requestor
600system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951846 # Average percentage of cache occupancy
601system.cpu0.dcache.tags.occ_percent::total 0.951846 # Average percentage of cache occupancy
602system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
603system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
604system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id
605system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
606system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
607system.cpu0.dcache.tags.tag_accesses 90667478 # Number of tag accesses
608system.cpu0.dcache.tags.data_accesses 90667478 # Number of data accesses
609system.cpu0.dcache.ReadReq_hits::cpu0.data 24441740 # number of ReadReq hits
610system.cpu0.dcache.ReadReq_hits::total 24441740 # number of ReadReq hits
611system.cpu0.dcache.WriteReq_hits::cpu0.data 18494582 # number of WriteReq hits
612system.cpu0.dcache.WriteReq_hits::total 18494582 # number of WriteReq hits
613system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326232 # number of SoftPFReq hits
614system.cpu0.dcache.SoftPFReq_hits::total 326232 # number of SoftPFReq hits
615system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374079 # number of LoadLockedReq hits
616system.cpu0.dcache.LoadLockedReq_hits::total 374079 # number of LoadLockedReq hits
617system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371656 # number of StoreCondReq hits
618system.cpu0.dcache.StoreCondReq_hits::total 371656 # number of StoreCondReq hits
619system.cpu0.dcache.demand_hits::cpu0.data 42936322 # number of demand (read+write) hits
620system.cpu0.dcache.demand_hits::total 42936322 # number of demand (read+write) hits
621system.cpu0.dcache.overall_hits::cpu0.data 43262554 # number of overall hits
622system.cpu0.dcache.overall_hits::total 43262554 # number of overall hits
623system.cpu0.dcache.ReadReq_misses::cpu0.data 418013 # number of ReadReq misses
624system.cpu0.dcache.ReadReq_misses::total 418013 # number of ReadReq misses
625system.cpu0.dcache.WriteReq_misses::cpu0.data 337667 # number of WriteReq misses
626system.cpu0.dcache.WriteReq_misses::total 337667 # number of WriteReq misses
627system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133440 # number of SoftPFReq misses
628system.cpu0.dcache.SoftPFReq_misses::total 133440 # number of SoftPFReq misses
629system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22337 # number of LoadLockedReq misses
630system.cpu0.dcache.LoadLockedReq_misses::total 22337 # number of LoadLockedReq misses
631system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19808 # number of StoreCondReq misses
632system.cpu0.dcache.StoreCondReq_misses::total 19808 # number of StoreCondReq misses
633system.cpu0.dcache.demand_misses::cpu0.data 755680 # number of demand (read+write) misses
634system.cpu0.dcache.demand_misses::total 755680 # number of demand (read+write) misses
635system.cpu0.dcache.overall_misses::cpu0.data 889120 # number of overall misses
636system.cpu0.dcache.overall_misses::total 889120 # number of overall misses
637system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5665137000 # number of ReadReq miss cycles
638system.cpu0.dcache.ReadReq_miss_latency::total 5665137000 # number of ReadReq miss cycles
639system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6926542000 # number of WriteReq miss cycles
640system.cpu0.dcache.WriteReq_miss_latency::total 6926542000 # number of WriteReq miss cycles
641system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 343483500 # number of LoadLockedReq miss cycles
642system.cpu0.dcache.LoadLockedReq_miss_latency::total 343483500 # number of LoadLockedReq miss cycles
643system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 502731000 # number of StoreCondReq miss cycles
644system.cpu0.dcache.StoreCondReq_miss_latency::total 502731000 # number of StoreCondReq miss cycles
645system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1840500 # number of StoreCondFailReq miss cycles
646system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1840500 # number of StoreCondFailReq miss cycles
647system.cpu0.dcache.demand_miss_latency::cpu0.data 12591679000 # number of demand (read+write) miss cycles
648system.cpu0.dcache.demand_miss_latency::total 12591679000 # number of demand (read+write) miss cycles
649system.cpu0.dcache.overall_miss_latency::cpu0.data 12591679000 # number of overall miss cycles
650system.cpu0.dcache.overall_miss_latency::total 12591679000 # number of overall miss cycles
651system.cpu0.dcache.ReadReq_accesses::cpu0.data 24859753 # number of ReadReq accesses(hits+misses)
652system.cpu0.dcache.ReadReq_accesses::total 24859753 # number of ReadReq accesses(hits+misses)
653system.cpu0.dcache.WriteReq_accesses::cpu0.data 18832249 # number of WriteReq accesses(hits+misses)
654system.cpu0.dcache.WriteReq_accesses::total 18832249 # number of WriteReq accesses(hits+misses)
655system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459672 # number of SoftPFReq accesses(hits+misses)
656system.cpu0.dcache.SoftPFReq_accesses::total 459672 # number of SoftPFReq accesses(hits+misses)
657system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396416 # number of LoadLockedReq accesses(hits+misses)
658system.cpu0.dcache.LoadLockedReq_accesses::total 396416 # number of LoadLockedReq accesses(hits+misses)
659system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391464 # number of StoreCondReq accesses(hits+misses)
660system.cpu0.dcache.StoreCondReq_accesses::total 391464 # number of StoreCondReq accesses(hits+misses)
661system.cpu0.dcache.demand_accesses::cpu0.data 43692002 # number of demand (read+write) accesses
662system.cpu0.dcache.demand_accesses::total 43692002 # number of demand (read+write) accesses
663system.cpu0.dcache.overall_accesses::cpu0.data 44151674 # number of overall (read+write) accesses
664system.cpu0.dcache.overall_accesses::total 44151674 # number of overall (read+write) accesses
665system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016815 # miss rate for ReadReq accesses
666system.cpu0.dcache.ReadReq_miss_rate::total 0.016815 # miss rate for ReadReq accesses
667system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017930 # miss rate for WriteReq accesses
668system.cpu0.dcache.WriteReq_miss_rate::total 0.017930 # miss rate for WriteReq accesses
669system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290294 # miss rate for SoftPFReq accesses
670system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290294 # miss rate for SoftPFReq accesses
671system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056347 # miss rate for LoadLockedReq accesses
672system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056347 # miss rate for LoadLockedReq accesses
673system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050600 # miss rate for StoreCondReq accesses
674system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050600 # miss rate for StoreCondReq accesses
675system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017296 # miss rate for demand accesses
676system.cpu0.dcache.demand_miss_rate::total 0.017296 # miss rate for demand accesses
677system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020138 # miss rate for overall accesses
678system.cpu0.dcache.overall_miss_rate::total 0.020138 # miss rate for overall accesses
679system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13552.537840 # average ReadReq miss latency
680system.cpu0.dcache.ReadReq_avg_miss_latency::total 13552.537840 # average ReadReq miss latency
681system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20512.937302 # average WriteReq miss latency
682system.cpu0.dcache.WriteReq_avg_miss_latency::total 20512.937302 # average WriteReq miss latency
683system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15377.333572 # average LoadLockedReq miss latency
684system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15377.333572 # average LoadLockedReq miss latency
685system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25380.199919 # average StoreCondReq miss latency
686system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25380.199919 # average StoreCondReq miss latency
687system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
688system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
689system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16662.713053 # average overall miss latency
690system.cpu0.dcache.demand_avg_miss_latency::total 16662.713053 # average overall miss latency
691system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14161.956766 # average overall miss latency
692system.cpu0.dcache.overall_avg_miss_latency::total 14161.956766 # average overall miss latency
693system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
694system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
695system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
696system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
697system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
698system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
699system.cpu0.dcache.fast_writes 0 # number of fast writes performed
700system.cpu0.dcache.cache_copies 0 # number of cache copies performed
701system.cpu0.dcache.writebacks::writebacks 732778 # number of writebacks
702system.cpu0.dcache.writebacks::total 732778 # number of writebacks
703system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25286 # number of ReadReq MSHR hits
704system.cpu0.dcache.ReadReq_mshr_hits::total 25286 # number of ReadReq MSHR hits
705system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2 # number of WriteReq MSHR hits
706system.cpu0.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
707system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15664 # number of LoadLockedReq MSHR hits
708system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15664 # number of LoadLockedReq MSHR hits
709system.cpu0.dcache.demand_mshr_hits::cpu0.data 25288 # number of demand (read+write) MSHR hits
710system.cpu0.dcache.demand_mshr_hits::total 25288 # number of demand (read+write) MSHR hits
711system.cpu0.dcache.overall_mshr_hits::cpu0.data 25288 # number of overall MSHR hits
712system.cpu0.dcache.overall_mshr_hits::total 25288 # number of overall MSHR hits
713system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 392727 # number of ReadReq MSHR misses
714system.cpu0.dcache.ReadReq_mshr_misses::total 392727 # number of ReadReq MSHR misses
715system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337665 # number of WriteReq MSHR misses
716system.cpu0.dcache.WriteReq_mshr_misses::total 337665 # number of WriteReq MSHR misses
717system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106338 # number of SoftPFReq MSHR misses
718system.cpu0.dcache.SoftPFReq_mshr_misses::total 106338 # number of SoftPFReq MSHR misses
719system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6673 # number of LoadLockedReq MSHR misses
720system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6673 # number of LoadLockedReq MSHR misses
721system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19808 # number of StoreCondReq MSHR misses
722system.cpu0.dcache.StoreCondReq_mshr_misses::total 19808 # number of StoreCondReq MSHR misses
723system.cpu0.dcache.demand_mshr_misses::cpu0.data 730392 # number of demand (read+write) MSHR misses
724system.cpu0.dcache.demand_mshr_misses::total 730392 # number of demand (read+write) MSHR misses
725system.cpu0.dcache.overall_mshr_misses::cpu0.data 836730 # number of overall MSHR misses
726system.cpu0.dcache.overall_mshr_misses::total 836730 # number of overall MSHR misses
727system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable
728system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31820 # number of ReadReq MSHR uncacheable
729system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
730system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
731system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses
732system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60319 # number of overall MSHR uncacheable misses
733system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4843447000 # number of ReadReq MSHR miss cycles
734system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4843447000 # number of ReadReq MSHR miss cycles
735system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6588824500 # number of WriteReq MSHR miss cycles
736system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6588824500 # number of WriteReq MSHR miss cycles
737system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1737105000 # number of SoftPFReq MSHR miss cycles
738system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737105000 # number of SoftPFReq MSHR miss cycles
739system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102846500 # number of LoadLockedReq MSHR miss cycles
740system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102846500 # number of LoadLockedReq MSHR miss cycles
741system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 482970000 # number of StoreCondReq MSHR miss cycles
742system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 482970000 # number of StoreCondReq MSHR miss cycles
743system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1793500 # number of StoreCondFailReq MSHR miss cycles
744system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles
745system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432271500 # number of demand (read+write) MSHR miss cycles
746system.cpu0.dcache.demand_mshr_miss_latency::total 11432271500 # number of demand (read+write) MSHR miss cycles
747system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13169376500 # number of overall MSHR miss cycles
748system.cpu0.dcache.overall_mshr_miss_latency::total 13169376500 # number of overall MSHR miss cycles
749system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629050000 # number of ReadReq MSHR uncacheable cycles
750system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629050000 # number of ReadReq MSHR uncacheable cycles
751system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400878000 # number of WriteReq MSHR uncacheable cycles
752system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400878000 # number of WriteReq MSHR uncacheable cycles
753system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029928000 # number of overall MSHR uncacheable cycles
754system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029928000 # number of overall MSHR uncacheable cycles
755system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015798 # mshr miss rate for ReadReq accesses
756system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015798 # mshr miss rate for ReadReq accesses
757system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017930 # mshr miss rate for WriteReq accesses
758system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017930 # mshr miss rate for WriteReq accesses
759system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231335 # mshr miss rate for SoftPFReq accesses
760system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231335 # mshr miss rate for SoftPFReq accesses
761system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016833 # mshr miss rate for LoadLockedReq accesses
762system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016833 # mshr miss rate for LoadLockedReq accesses
763system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050600 # mshr miss rate for StoreCondReq accesses
764system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050600 # mshr miss rate for StoreCondReq accesses
765system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016717 # mshr miss rate for demand accesses
766system.cpu0.dcache.demand_mshr_miss_rate::total 0.016717 # mshr miss rate for demand accesses
767system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018951 # mshr miss rate for overall accesses
768system.cpu0.dcache.overall_mshr_miss_rate::total 0.018951 # mshr miss rate for overall accesses
769system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12332.859722 # average ReadReq mshr miss latency
770system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12332.859722 # average ReadReq mshr miss latency
771system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19512.903321 # average WriteReq mshr miss latency
772system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19512.903321 # average WriteReq mshr miss latency
773system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16335.693731 # average SoftPFReq mshr miss latency
774system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16335.693731 # average SoftPFReq mshr miss latency
775system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15412.333283 # average LoadLockedReq mshr miss latency
776system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15412.333283 # average LoadLockedReq mshr miss latency
777system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24382.572698 # average StoreCondReq mshr miss latency
778system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24382.572698 # average StoreCondReq mshr miss latency
779system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
780system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
781system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15652.240851 # average overall mshr miss latency
782system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15652.240851 # average overall mshr miss latency
783system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15739.099232 # average overall mshr miss latency
784system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15739.099232 # average overall mshr miss latency
785system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208329.666876 # average ReadReq mshr uncacheable latency
786system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208329.666876 # average ReadReq mshr uncacheable latency
787system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189511.140742 # average WriteReq mshr uncacheable latency
788system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189511.140742 # average WriteReq mshr uncacheable latency
789system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199438.452229 # average overall mshr uncacheable latency
790system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199438.452229 # average overall mshr uncacheable latency
791system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
792system.cpu0.icache.tags.replacements 1147265 # number of replacements
793system.cpu0.icache.tags.tagsinuse 511.321425 # Cycle average of tags in use
794system.cpu0.icache.tags.total_refs 120433653 # Total number of references to valid blocks.
795system.cpu0.icache.tags.sampled_refs 1147777 # Sample count of references to valid blocks.
796system.cpu0.icache.tags.avg_refs 104.927746 # Average number of references to valid blocks.
797system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit.
798system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321425 # Average occupied blocks per requestor
799system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy
800system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy
801system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
802system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
803system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id
804system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
805system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
806system.cpu0.icache.tags.tag_accesses 244310664 # Number of tag accesses
807system.cpu0.icache.tags.data_accesses 244310664 # Number of data accesses
808system.cpu0.icache.ReadReq_hits::cpu0.inst 120433653 # number of ReadReq hits
809system.cpu0.icache.ReadReq_hits::total 120433653 # number of ReadReq hits
810system.cpu0.icache.demand_hits::cpu0.inst 120433653 # number of demand (read+write) hits
811system.cpu0.icache.demand_hits::total 120433653 # number of demand (read+write) hits
812system.cpu0.icache.overall_hits::cpu0.inst 120433653 # number of overall hits
813system.cpu0.icache.overall_hits::total 120433653 # number of overall hits
814system.cpu0.icache.ReadReq_misses::cpu0.inst 1147786 # number of ReadReq misses
815system.cpu0.icache.ReadReq_misses::total 1147786 # number of ReadReq misses
816system.cpu0.icache.demand_misses::cpu0.inst 1147786 # number of demand (read+write) misses
817system.cpu0.icache.demand_misses::total 1147786 # number of demand (read+write) misses
818system.cpu0.icache.overall_misses::cpu0.inst 1147786 # number of overall misses
819system.cpu0.icache.overall_misses::total 1147786 # number of overall misses
820system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12247651500 # number of ReadReq miss cycles
821system.cpu0.icache.ReadReq_miss_latency::total 12247651500 # number of ReadReq miss cycles
822system.cpu0.icache.demand_miss_latency::cpu0.inst 12247651500 # number of demand (read+write) miss cycles
823system.cpu0.icache.demand_miss_latency::total 12247651500 # number of demand (read+write) miss cycles
824system.cpu0.icache.overall_miss_latency::cpu0.inst 12247651500 # number of overall miss cycles
825system.cpu0.icache.overall_miss_latency::total 12247651500 # number of overall miss cycles
826system.cpu0.icache.ReadReq_accesses::cpu0.inst 121581439 # number of ReadReq accesses(hits+misses)
827system.cpu0.icache.ReadReq_accesses::total 121581439 # number of ReadReq accesses(hits+misses)
828system.cpu0.icache.demand_accesses::cpu0.inst 121581439 # number of demand (read+write) accesses
829system.cpu0.icache.demand_accesses::total 121581439 # number of demand (read+write) accesses
830system.cpu0.icache.overall_accesses::cpu0.inst 121581439 # number of overall (read+write) accesses
831system.cpu0.icache.overall_accesses::total 121581439 # number of overall (read+write) accesses
832system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009440 # miss rate for ReadReq accesses
833system.cpu0.icache.ReadReq_miss_rate::total 0.009440 # miss rate for ReadReq accesses
834system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009440 # miss rate for demand accesses
835system.cpu0.icache.demand_miss_rate::total 0.009440 # miss rate for demand accesses
836system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009440 # miss rate for overall accesses
837system.cpu0.icache.overall_miss_rate::total 0.009440 # miss rate for overall accesses
838system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10670.675108 # average ReadReq miss latency
839system.cpu0.icache.ReadReq_avg_miss_latency::total 10670.675108 # average ReadReq miss latency
840system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10670.675108 # average overall miss latency
841system.cpu0.icache.demand_avg_miss_latency::total 10670.675108 # average overall miss latency
842system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10670.675108 # average overall miss latency
843system.cpu0.icache.overall_avg_miss_latency::total 10670.675108 # average overall miss latency
844system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
845system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
846system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
847system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
848system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
849system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
850system.cpu0.icache.fast_writes 0 # number of fast writes performed
851system.cpu0.icache.cache_copies 0 # number of cache copies performed
852system.cpu0.icache.writebacks::writebacks 1147265 # number of writebacks
853system.cpu0.icache.writebacks::total 1147265 # number of writebacks
854system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147786 # number of ReadReq MSHR misses
855system.cpu0.icache.ReadReq_mshr_misses::total 1147786 # number of ReadReq MSHR misses
856system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147786 # number of demand (read+write) MSHR misses
857system.cpu0.icache.demand_mshr_misses::total 1147786 # number of demand (read+write) MSHR misses
858system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147786 # number of overall MSHR misses
859system.cpu0.icache.overall_mshr_misses::total 1147786 # number of overall MSHR misses
860system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
861system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
862system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
863system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
864system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11673758500 # number of ReadReq MSHR miss cycles
865system.cpu0.icache.ReadReq_mshr_miss_latency::total 11673758500 # number of ReadReq MSHR miss cycles
866system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11673758500 # number of demand (read+write) MSHR miss cycles
867system.cpu0.icache.demand_mshr_miss_latency::total 11673758500 # number of demand (read+write) MSHR miss cycles
868system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11673758500 # number of overall MSHR miss cycles
869system.cpu0.icache.overall_mshr_miss_latency::total 11673758500 # number of overall MSHR miss cycles
870system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles
871system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles
872system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles
873system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles
874system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for ReadReq accesses
875system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009440 # mshr miss rate for ReadReq accesses
876system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for demand accesses
877system.cpu0.icache.demand_mshr_miss_rate::total 0.009440 # mshr miss rate for demand accesses
878system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009440 # mshr miss rate for overall accesses
879system.cpu0.icache.overall_mshr_miss_rate::total 0.009440 # mshr miss rate for overall accesses
880system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average ReadReq mshr miss latency
881system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10170.675108 # average ReadReq mshr miss latency
882system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average overall mshr miss latency
883system.cpu0.icache.demand_avg_mshr_miss_latency::total 10170.675108 # average overall mshr miss latency
884system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10170.675108 # average overall mshr miss latency
885system.cpu0.icache.overall_avg_mshr_miss_latency::total 10170.675108 # average overall mshr miss latency
886system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency
887system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency
888system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency
889system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency
890system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
891system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935691 # number of hwpf issued
892system.cpu0.l2cache.prefetcher.pfIdentified 1935756 # number of prefetch candidates identified
893system.cpu0.l2cache.prefetcher.pfBufferHit 57 # number of redundant prefetches already in prefetch queue
894system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
895system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
896system.cpu0.l2cache.prefetcher.pfSpanPage 245684 # number of prefetches not generated due to page crossing
897system.cpu0.l2cache.tags.replacements 272679 # number of replacements
898system.cpu0.l2cache.tags.tagsinuse 16060.422672 # Cycle average of tags in use
899system.cpu0.l2cache.tags.total_refs 3064880 # Total number of references to valid blocks.
900system.cpu0.l2cache.tags.sampled_refs 288783 # Sample count of references to valid blocks.
901system.cpu0.l2cache.tags.avg_refs 10.613090 # Average number of references to valid blocks.
902system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
903system.cpu0.l2cache.tags.occ_blocks::writebacks 14559.127845 # Average occupied blocks per requestor
904system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.514376 # Average occupied blocks per requestor
905system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.125186 # Average occupied blocks per requestor
906system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1500.655266 # Average occupied blocks per requestor
907system.cpu0.l2cache.tags.occ_percent::writebacks 0.888619 # Average percentage of cache occupancy
908system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000031 # Average percentage of cache occupancy
909system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
910system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.091593 # Average percentage of cache occupancy
911system.cpu0.l2cache.tags.occ_percent::total 0.980250 # Average percentage of cache occupancy
912system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1021 # Occupied blocks per task id
913system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id
914system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15080 # Occupied blocks per task id
915system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
916system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 262 # Occupied blocks per task id
917system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 312 # Occupied blocks per task id
918system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 434 # Occupied blocks per task id
919system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
920system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
921system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
922system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
923system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id
924system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3313 # Occupied blocks per task id
925system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7651 # Occupied blocks per task id
926system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3839 # Occupied blocks per task id
927system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062317 # Percentage of cache occupancy per task id
928system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id
929system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id
930system.cpu0.l2cache.tags.tag_accesses 62824015 # Number of tag accesses
931system.cpu0.l2cache.tags.data_accesses 62824015 # Number of data accesses
932system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10929 # number of ReadReq hits
933system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4820 # number of ReadReq hits
934system.cpu0.l2cache.ReadReq_hits::total 15749 # number of ReadReq hits
935system.cpu0.l2cache.WritebackDirty_hits::writebacks 500939 # number of WritebackDirty hits
936system.cpu0.l2cache.WritebackDirty_hits::total 500939 # number of WritebackDirty hits
937system.cpu0.l2cache.WritebackClean_hits::writebacks 1350193 # number of WritebackClean hits
938system.cpu0.l2cache.WritebackClean_hits::total 1350193 # number of WritebackClean hits
939system.cpu0.l2cache.ReadExReq_hits::cpu0.data 238805 # number of ReadExReq hits
940system.cpu0.l2cache.ReadExReq_hits::total 238805 # number of ReadExReq hits
941system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1101574 # number of ReadCleanReq hits
942system.cpu0.l2cache.ReadCleanReq_hits::total 1101574 # number of ReadCleanReq hits
943system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 411559 # number of ReadSharedReq hits
944system.cpu0.l2cache.ReadSharedReq_hits::total 411559 # number of ReadSharedReq hits
945system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10929 # number of demand (read+write) hits
946system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4820 # number of demand (read+write) hits
947system.cpu0.l2cache.demand_hits::cpu0.inst 1101574 # number of demand (read+write) hits
948system.cpu0.l2cache.demand_hits::cpu0.data 650364 # number of demand (read+write) hits
949system.cpu0.l2cache.demand_hits::total 1767687 # number of demand (read+write) hits
950system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10929 # number of overall hits
951system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4820 # number of overall hits
952system.cpu0.l2cache.overall_hits::cpu0.inst 1101574 # number of overall hits
953system.cpu0.l2cache.overall_hits::cpu0.data 650364 # number of overall hits
954system.cpu0.l2cache.overall_hits::total 1767687 # number of overall hits
955system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 174 # number of ReadReq misses
956system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 78 # number of ReadReq misses
957system.cpu0.l2cache.ReadReq_misses::total 252 # number of ReadReq misses
958system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55084 # number of UpgradeReq misses
959system.cpu0.l2cache.UpgradeReq_misses::total 55084 # number of UpgradeReq misses
960system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19799 # number of SCUpgradeReq misses
961system.cpu0.l2cache.SCUpgradeReq_misses::total 19799 # number of SCUpgradeReq misses
962system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 9 # number of SCUpgradeFailReq misses
963system.cpu0.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses
964system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43776 # number of ReadExReq misses
965system.cpu0.l2cache.ReadExReq_misses::total 43776 # number of ReadExReq misses
966system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46212 # number of ReadCleanReq misses
967system.cpu0.l2cache.ReadCleanReq_misses::total 46212 # number of ReadCleanReq misses
968system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94179 # number of ReadSharedReq misses
969system.cpu0.l2cache.ReadSharedReq_misses::total 94179 # number of ReadSharedReq misses
970system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 174 # number of demand (read+write) misses
971system.cpu0.l2cache.demand_misses::cpu0.itb.walker 78 # number of demand (read+write) misses
972system.cpu0.l2cache.demand_misses::cpu0.inst 46212 # number of demand (read+write) misses
973system.cpu0.l2cache.demand_misses::cpu0.data 137955 # number of demand (read+write) misses
974system.cpu0.l2cache.demand_misses::total 184419 # number of demand (read+write) misses
975system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 174 # number of overall misses
976system.cpu0.l2cache.overall_misses::cpu0.itb.walker 78 # number of overall misses
977system.cpu0.l2cache.overall_misses::cpu0.inst 46212 # number of overall misses
978system.cpu0.l2cache.overall_misses::cpu0.data 137955 # number of overall misses
979system.cpu0.l2cache.overall_misses::total 184419 # number of overall misses
980system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4564500 # number of ReadReq miss cycles
981system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2175000 # number of ReadReq miss cycles
982system.cpu0.l2cache.ReadReq_miss_latency::total 6739500 # number of ReadReq miss cycles
983system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 163061000 # number of UpgradeReq miss cycles
984system.cpu0.l2cache.UpgradeReq_miss_latency::total 163061000 # number of UpgradeReq miss cycles
985system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 40358000 # number of SCUpgradeReq miss cycles
986system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 40358000 # number of SCUpgradeReq miss cycles
987system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1721497 # number of SCUpgradeFailReq miss cycles
988system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1721497 # number of SCUpgradeFailReq miss cycles
989system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2789761000 # number of ReadExReq miss cycles
990system.cpu0.l2cache.ReadExReq_miss_latency::total 2789761000 # number of ReadExReq miss cycles
991system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3290416000 # number of ReadCleanReq miss cycles
992system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3290416000 # number of ReadCleanReq miss cycles
993system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3238432000 # number of ReadSharedReq miss cycles
994system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3238432000 # number of ReadSharedReq miss cycles
995system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4564500 # number of demand (read+write) miss cycles
996system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2175000 # number of demand (read+write) miss cycles
997system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3290416000 # number of demand (read+write) miss cycles
998system.cpu0.l2cache.demand_miss_latency::cpu0.data 6028193000 # number of demand (read+write) miss cycles
999system.cpu0.l2cache.demand_miss_latency::total 9325348500 # number of demand (read+write) miss cycles
1000system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4564500 # number of overall miss cycles
1001system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2175000 # number of overall miss cycles
1002system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3290416000 # number of overall miss cycles
1003system.cpu0.l2cache.overall_miss_latency::cpu0.data 6028193000 # number of overall miss cycles
1004system.cpu0.l2cache.overall_miss_latency::total 9325348500 # number of overall miss cycles
1005system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11103 # number of ReadReq accesses(hits+misses)
1006system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4898 # number of ReadReq accesses(hits+misses)
1007system.cpu0.l2cache.ReadReq_accesses::total 16001 # number of ReadReq accesses(hits+misses)
1008system.cpu0.l2cache.WritebackDirty_accesses::writebacks 500939 # number of WritebackDirty accesses(hits+misses)
1009system.cpu0.l2cache.WritebackDirty_accesses::total 500939 # number of WritebackDirty accesses(hits+misses)
1010system.cpu0.l2cache.WritebackClean_accesses::writebacks 1350193 # number of WritebackClean accesses(hits+misses)
1011system.cpu0.l2cache.WritebackClean_accesses::total 1350193 # number of WritebackClean accesses(hits+misses)
1012system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55084 # number of UpgradeReq accesses(hits+misses)
1013system.cpu0.l2cache.UpgradeReq_accesses::total 55084 # number of UpgradeReq accesses(hits+misses)
1014system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19799 # number of SCUpgradeReq accesses(hits+misses)
1015system.cpu0.l2cache.SCUpgradeReq_accesses::total 19799 # number of SCUpgradeReq accesses(hits+misses)
1016system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 9 # number of SCUpgradeFailReq accesses(hits+misses)
1017system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses)
1018system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 282581 # number of ReadExReq accesses(hits+misses)
1019system.cpu0.l2cache.ReadExReq_accesses::total 282581 # number of ReadExReq accesses(hits+misses)
1020system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1147786 # number of ReadCleanReq accesses(hits+misses)
1021system.cpu0.l2cache.ReadCleanReq_accesses::total 1147786 # number of ReadCleanReq accesses(hits+misses)
1022system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 505738 # number of ReadSharedReq accesses(hits+misses)
1023system.cpu0.l2cache.ReadSharedReq_accesses::total 505738 # number of ReadSharedReq accesses(hits+misses)
1024system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11103 # number of demand (read+write) accesses
1025system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4898 # number of demand (read+write) accesses
1026system.cpu0.l2cache.demand_accesses::cpu0.inst 1147786 # number of demand (read+write) accesses
1027system.cpu0.l2cache.demand_accesses::cpu0.data 788319 # number of demand (read+write) accesses
1028system.cpu0.l2cache.demand_accesses::total 1952106 # number of demand (read+write) accesses
1029system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11103 # number of overall (read+write) accesses
1030system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4898 # number of overall (read+write) accesses
1031system.cpu0.l2cache.overall_accesses::cpu0.inst 1147786 # number of overall (read+write) accesses
1032system.cpu0.l2cache.overall_accesses::cpu0.data 788319 # number of overall (read+write) accesses
1033system.cpu0.l2cache.overall_accesses::total 1952106 # number of overall (read+write) accesses
1034system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.015671 # miss rate for ReadReq accesses
1035system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015925 # miss rate for ReadReq accesses
1036system.cpu0.l2cache.ReadReq_miss_rate::total 0.015749 # miss rate for ReadReq accesses
1037system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses
1038system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1039system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
1040system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1041system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1042system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1043system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154915 # miss rate for ReadExReq accesses
1044system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154915 # miss rate for ReadExReq accesses
1045system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040262 # miss rate for ReadCleanReq accesses
1046system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040262 # miss rate for ReadCleanReq accesses
1047system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186221 # miss rate for ReadSharedReq accesses
1048system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186221 # miss rate for ReadSharedReq accesses
1049system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.015671 # miss rate for demand accesses
1050system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015925 # miss rate for demand accesses
1051system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040262 # miss rate for demand accesses
1052system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.174999 # miss rate for demand accesses
1053system.cpu0.l2cache.demand_miss_rate::total 0.094472 # miss rate for demand accesses
1054system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.015671 # miss rate for overall accesses
1055system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015925 # miss rate for overall accesses
1056system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040262 # miss rate for overall accesses
1057system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.174999 # miss rate for overall accesses
1058system.cpu0.l2cache.overall_miss_rate::total 0.094472 # miss rate for overall accesses
1059system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26232.758621 # average ReadReq miss latency
1060system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 27884.615385 # average ReadReq miss latency
1061system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26744.047619 # average ReadReq miss latency
1062system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 2960.224385 # average UpgradeReq miss latency
1063system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 2960.224385 # average UpgradeReq miss latency
1064system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2038.385777 # average SCUpgradeReq miss latency
1065system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2038.385777 # average SCUpgradeReq miss latency
1066system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 191277.444444 # average SCUpgradeFailReq miss latency
1067system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 191277.444444 # average SCUpgradeFailReq miss latency
1068system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63728.093019 # average ReadExReq miss latency
1069system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63728.093019 # average ReadExReq miss latency
1070system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71202.631351 # average ReadCleanReq miss latency
1071system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71202.631351 # average ReadCleanReq miss latency
1072system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34385.924675 # average ReadSharedReq miss latency
1073system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34385.924675 # average ReadSharedReq miss latency
1074system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26232.758621 # average overall miss latency
1075system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 27884.615385 # average overall miss latency
1076system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71202.631351 # average overall miss latency
1077system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43696.806930 # average overall miss latency
1078system.cpu0.l2cache.demand_avg_miss_latency::total 50566.094058 # average overall miss latency
1079system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26232.758621 # average overall miss latency
1080system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 27884.615385 # average overall miss latency
1081system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71202.631351 # average overall miss latency
1082system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43696.806930 # average overall miss latency
1083system.cpu0.l2cache.overall_avg_miss_latency::total 50566.094058 # average overall miss latency
1084system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1085system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1086system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1087system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1088system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1089system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1090system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1091system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1092system.cpu0.l2cache.writebacks::writebacks 231522 # number of writebacks
1093system.cpu0.l2cache.writebacks::total 231522 # number of writebacks
1094system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1822 # number of ReadExReq MSHR hits
1095system.cpu0.l2cache.ReadExReq_mshr_hits::total 1822 # number of ReadExReq MSHR hits
1096system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 60 # number of ReadSharedReq MSHR hits
1097system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits
1098system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1882 # number of demand (read+write) MSHR hits
1099system.cpu0.l2cache.demand_mshr_hits::total 1882 # number of demand (read+write) MSHR hits
1100system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1882 # number of overall MSHR hits
1101system.cpu0.l2cache.overall_mshr_hits::total 1882 # number of overall MSHR hits
1102system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 174 # number of ReadReq MSHR misses
1103system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 78 # number of ReadReq MSHR misses
1104system.cpu0.l2cache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
1105system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264994 # number of HardPFReq MSHR misses
1106system.cpu0.l2cache.HardPFReq_mshr_misses::total 264994 # number of HardPFReq MSHR misses
1107system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55084 # number of UpgradeReq MSHR misses
1108system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55084 # number of UpgradeReq MSHR misses
1109system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19799 # number of SCUpgradeReq MSHR misses
1110system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19799 # number of SCUpgradeReq MSHR misses
1111system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 9 # number of SCUpgradeFailReq MSHR misses
1112system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses
1113system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41954 # number of ReadExReq MSHR misses
1114system.cpu0.l2cache.ReadExReq_mshr_misses::total 41954 # number of ReadExReq MSHR misses
1115system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46212 # number of ReadCleanReq MSHR misses
1116system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46212 # number of ReadCleanReq MSHR misses
1117system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94119 # number of ReadSharedReq MSHR misses
1118system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94119 # number of ReadSharedReq MSHR misses
1119system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 174 # number of demand (read+write) MSHR misses
1120system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 78 # number of demand (read+write) MSHR misses
1121system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46212 # number of demand (read+write) MSHR misses
1122system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136073 # number of demand (read+write) MSHR misses
1123system.cpu0.l2cache.demand_mshr_misses::total 182537 # number of demand (read+write) MSHR misses
1124system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 174 # number of overall MSHR misses
1125system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 78 # number of overall MSHR misses
1126system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46212 # number of overall MSHR misses
1127system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136073 # number of overall MSHR misses
1128system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264994 # number of overall MSHR misses
1129system.cpu0.l2cache.overall_mshr_misses::total 447531 # number of overall MSHR misses
1130system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
1131system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable
1132system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40842 # number of ReadReq MSHR uncacheable
1133system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
1134system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable
1135system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
1136system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses
1137system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69341 # number of overall MSHR uncacheable misses
1138system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3520500 # number of ReadReq MSHR miss cycles
1139system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1707000 # number of ReadReq MSHR miss cycles
1140system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5227500 # number of ReadReq MSHR miss cycles
1141system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20400229755 # number of HardPFReq MSHR miss cycles
1142system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20400229755 # number of HardPFReq MSHR miss cycles
1143system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1407285500 # number of UpgradeReq MSHR miss cycles
1144system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1407285500 # number of UpgradeReq MSHR miss cycles
1145system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 334701500 # number of SCUpgradeReq MSHR miss cycles
1146system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 334701500 # number of SCUpgradeReq MSHR miss cycles
1147system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1439497 # number of SCUpgradeFailReq MSHR miss cycles
1148system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1439497 # number of SCUpgradeFailReq MSHR miss cycles
1149system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2354527500 # number of ReadExReq MSHR miss cycles
1150system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2354527500 # number of ReadExReq MSHR miss cycles
1151system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3013144000 # number of ReadCleanReq MSHR miss cycles
1152system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3013144000 # number of ReadCleanReq MSHR miss cycles
1153system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2666489000 # number of ReadSharedReq MSHR miss cycles
1154system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2666489000 # number of ReadSharedReq MSHR miss cycles
1155system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3520500 # number of demand (read+write) MSHR miss cycles
1156system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1707000 # number of demand (read+write) MSHR miss cycles
1157system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3013144000 # number of demand (read+write) MSHR miss cycles
1158system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5021016500 # number of demand (read+write) MSHR miss cycles
1159system.cpu0.l2cache.demand_mshr_miss_latency::total 8039388000 # number of demand (read+write) MSHR miss cycles
1160system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3520500 # number of overall MSHR miss cycles
1161system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1707000 # number of overall MSHR miss cycles
1162system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3013144000 # number of overall MSHR miss cycles
1163system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5021016500 # number of overall MSHR miss cycles
1164system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20400229755 # number of overall MSHR miss cycles
1165system.cpu0.l2cache.overall_mshr_miss_latency::total 28439617755 # number of overall MSHR miss cycles
1166system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles
1167system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374077000 # number of ReadReq MSHR uncacheable cycles
1168system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7560288500 # number of ReadReq MSHR uncacheable cycles
1169system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187014000 # number of WriteReq MSHR uncacheable cycles
1170system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187014000 # number of WriteReq MSHR uncacheable cycles
1171system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles
1172system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561091000 # number of overall MSHR uncacheable cycles
1173system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747302500 # number of overall MSHR uncacheable cycles
1174system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for ReadReq accesses
1175system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for ReadReq accesses
1176system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015749 # mshr miss rate for ReadReq accesses
1177system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1178system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1179system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses
1180system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1181system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
1182system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
1183system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1184system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1185system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148467 # mshr miss rate for ReadExReq accesses
1186system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148467 # mshr miss rate for ReadExReq accesses
1187system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for ReadCleanReq accesses
1188system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040262 # mshr miss rate for ReadCleanReq accesses
1189system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186102 # mshr miss rate for ReadSharedReq accesses
1190system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186102 # mshr miss rate for ReadSharedReq accesses
1191system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for demand accesses
1192system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for demand accesses
1193system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for demand accesses
1194system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172612 # mshr miss rate for demand accesses
1195system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093508 # mshr miss rate for demand accesses
1196system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for overall accesses
1197system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for overall accesses
1198system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for overall accesses
1199system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172612 # mshr miss rate for overall accesses
1200system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1201system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229255 # mshr miss rate for overall accesses
1202system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average ReadReq mshr miss latency
1203system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average ReadReq mshr miss latency
1204system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20744.047619 # average ReadReq mshr miss latency
1205system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104 # average HardPFReq mshr miss latency
1206system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76983.742104 # average HardPFReq mshr miss latency
1207system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25547.990342 # average UpgradeReq mshr miss latency
1208system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25547.990342 # average UpgradeReq mshr miss latency
1209system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16904.969948 # average SCUpgradeReq mshr miss latency
1210system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16904.969948 # average SCUpgradeReq mshr miss latency
1211system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 159944.111111 # average SCUpgradeFailReq mshr miss latency
1212system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 159944.111111 # average SCUpgradeFailReq mshr miss latency
1213system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56121.645135 # average ReadExReq mshr miss latency
1214system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56121.645135 # average ReadExReq mshr miss latency
1215system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average ReadCleanReq mshr miss latency
1216system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65202.631351 # average ReadCleanReq mshr miss latency
1217system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28331.038366 # average ReadSharedReq mshr miss latency
1218system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28331.038366 # average ReadSharedReq mshr miss latency
1219system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average overall mshr miss latency
1220system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average overall mshr miss latency
1221system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average overall mshr miss latency
1222system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36899.432657 # average overall mshr miss latency
1223system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44042.511929 # average overall mshr miss latency
1224system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average overall mshr miss latency
1225system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average overall mshr miss latency
1226system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average overall mshr miss latency
1227system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36899.432657 # average overall mshr miss latency
1228system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104 # average overall mshr miss latency
1229system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63547.816252 # average overall mshr miss latency
1230system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency
1231system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200316.687618 # average ReadReq mshr uncacheable latency
1232system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185110.633661 # average ReadReq mshr uncacheable latency
1233system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.877434 # average WriteReq mshr uncacheable latency
1234system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.877434 # average WriteReq mshr uncacheable latency
1235system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency
1236system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191665.826688 # average overall mshr uncacheable latency
1237system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183834.996611 # average overall mshr uncacheable latency
1238system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1239system.cpu0.toL2Bus.snoop_filter.tot_requests 3905249 # Total number of requests made to the snoop filter.
1240system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969182 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1241system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28911 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1242system.cpu0.toL2Bus.snoop_filter.tot_snoops 320342 # Total number of snoops made to the snoop filter.
1243system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316677 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1244system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3665 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1245system.cpu0.toL2Bus.trans_dist::ReadReq 63843 # Transaction distribution
1246system.cpu0.toL2Bus.trans_dist::ReadResp 1765873 # Transaction distribution
1247system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution
1248system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution
1249system.cpu0.toL2Bus.trans_dist::WritebackDirty 732965 # Transaction distribution
1250system.cpu0.toL2Bus.trans_dist::WritebackClean 1379104 # Transaction distribution
1251system.cpu0.toL2Bus.trans_dist::CleanEvict 189043 # Transaction distribution
1252system.cpu0.toL2Bus.trans_dist::HardPFReq 312150 # Transaction distribution
1253system.cpu0.toL2Bus.trans_dist::UpgradeReq 85708 # Transaction distribution
1254system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41941 # Transaction distribution
1255system.cpu0.toL2Bus.trans_dist::UpgradeResp 112560 # Transaction distribution
1256system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
1257system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
1258system.cpu0.toL2Bus.trans_dist::ReadExReq 301555 # Transaction distribution
1259system.cpu0.toL2Bus.trans_dist::ReadExResp 298207 # Transaction distribution
1260system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147786 # Transaction distribution
1261system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575214 # Transaction distribution
1262system.cpu0.toL2Bus.trans_dist::InvalidateReq 3299 # Transaction distribution
1263system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460881 # Packet count per connected master and slave (bytes)
1264system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2681738 # Packet count per connected master and slave (bytes)
1265system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11926 # Packet count per connected master and slave (bytes)
1266system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27058 # Packet count per connected master and slave (bytes)
1267system.cpu0.toL2Bus.pkt_count::total 6181603 # Packet count per connected master and slave (bytes)
1268system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146919352 # Cumulative packet size per connected master and slave (bytes)
1269system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101652834 # Cumulative packet size per connected master and slave (bytes)
1270system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19592 # Cumulative packet size per connected master and slave (bytes)
1271system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44412 # Cumulative packet size per connected master and slave (bytes)
1272system.cpu0.toL2Bus.pkt_size::total 248636190 # Cumulative packet size per connected master and slave (bytes)
1273system.cpu0.toL2Bus.snoops 986669 # Total snoops (count)
1274system.cpu0.toL2Bus.snoop_fanout::samples 2981108 # Request fanout histogram
1275system.cpu0.toL2Bus.snoop_fanout::mean 0.123159 # Request fanout histogram
1276system.cpu0.toL2Bus.snoop_fanout::stdev 0.332339 # Request fanout histogram
1277system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1278system.cpu0.toL2Bus.snoop_fanout::0 2617624 87.81% 87.81% # Request fanout histogram
1279system.cpu0.toL2Bus.snoop_fanout::1 359819 12.07% 99.88% # Request fanout histogram
1280system.cpu0.toL2Bus.snoop_fanout::2 3665 0.12% 100.00% # Request fanout histogram
1281system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1282system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1283system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1284system.cpu0.toL2Bus.snoop_fanout::total 2981108 # Request fanout histogram
1285system.cpu0.toL2Bus.reqLayer0.occupancy 3885976496 # Layer occupancy (ticks)
1286system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1287system.cpu0.toL2Bus.snoopLayer0.occupancy 115188451 # Layer occupancy (ticks)
1288system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1289system.cpu0.toL2Bus.respLayer0.occupancy 1730701000 # Layer occupancy (ticks)
1290system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1291system.cpu0.toL2Bus.respLayer1.occupancy 1266054481 # Layer occupancy (ticks)
1292system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1293system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks)
1294system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1295system.cpu0.toL2Bus.respLayer3.occupancy 15961487 # Layer occupancy (ticks)
1296system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1297system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1298system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1299system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1300system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1301system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1302system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1303system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

1318system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1319system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1320system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1321system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1322system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1323system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1324system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1325system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1326system.cpu1.dtb.walker.walks 2346 # Table walker walks requested
1327system.cpu1.dtb.walker.walksShort 2346 # Table walker walks initiated with short descriptors
1328system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 473 # Level at which table walker walks with short descriptors terminate
1329system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1873 # Level at which table walker walks with short descriptors terminate
1330system.cpu1.dtb.walker.walkWaitTime::samples 2346 # Table walker wait (enqueue to first request) latency
1331system.cpu1.dtb.walker.walkWaitTime::0 2346 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1332system.cpu1.dtb.walker.walkWaitTime::total 2346 # Table walker wait (enqueue to first request) latency
1333system.cpu1.dtb.walker.walkCompletionTime::samples 1700 # Table walker service (enqueue to completion) latency
1334system.cpu1.dtb.walker.walkCompletionTime::mean 11761.764706 # Table walker service (enqueue to completion) latency
1335system.cpu1.dtb.walker.walkCompletionTime::gmean 11073.675458 # Table walker service (enqueue to completion) latency
1336system.cpu1.dtb.walker.walkCompletionTime::stdev 5957.546231 # Table walker service (enqueue to completion) latency
1337system.cpu1.dtb.walker.walkCompletionTime::0-16383 1554 91.41% 91.41% # Table walker service (enqueue to completion) latency
1338system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.94% 99.35% # Table walker service (enqueue to completion) latency
1339system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.65% # Table walker service (enqueue to completion) latency
1340system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.29% 99.94% # Table walker service (enqueue to completion) latency
1341system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency
1342system.cpu1.dtb.walker.walkCompletionTime::total 1700 # Table walker service (enqueue to completion) latency
1343system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution
1344system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution
1345system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution
1346system.cpu1.dtb.walker.walkPageSizes::4K 1227 72.18% 72.18% # Table walker page sizes translated
1347system.cpu1.dtb.walker.walkPageSizes::1M 473 27.82% 100.00% # Table walker page sizes translated
1348system.cpu1.dtb.walker.walkPageSizes::total 1700 # Table walker page sizes translated
1349system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2346 # Table walker requests started/completed, data/inst
1350system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1351system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2346 # Table walker requests started/completed, data/inst
1352system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1700 # Table walker requests started/completed, data/inst
1353system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1354system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1700 # Table walker requests started/completed, data/inst
1355system.cpu1.dtb.walker.walkRequestOrigin::total 4046 # Table walker requests started/completed, data/inst
1356system.cpu1.dtb.inst_hits 0 # ITB inst hits
1357system.cpu1.dtb.inst_misses 0 # ITB inst misses
1358system.cpu1.dtb.read_hits 3334779 # DTB read hits
1359system.cpu1.dtb.read_misses 1954 # DTB read misses
1360system.cpu1.dtb.write_hits 2915242 # DTB write hits
1361system.cpu1.dtb.write_misses 392 # DTB write misses
1362system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1363system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1364system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1365system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1366system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB
1367system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1368system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch
1369system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1370system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions
1371system.cpu1.dtb.read_accesses 3336733 # DTB read accesses
1372system.cpu1.dtb.write_accesses 2915634 # DTB write accesses
1373system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1374system.cpu1.dtb.hits 6250021 # DTB hits
1375system.cpu1.dtb.misses 2346 # DTB misses
1376system.cpu1.dtb.accesses 6252367 # DTB accesses
1377system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1378system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1379system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1380system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1381system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1382system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1383system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1384system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 21 unchanged lines hidden (view full) ---

1406system.cpu1.itb.walker.walks 1376 # Table walker walks requested
1407system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors
1408system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate
1409system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate
1410system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency
1411system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1412system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency
1413system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency
1414system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433 # Table walker service (enqueue to completion) latency
1415system.cpu1.itb.walker.walkCompletionTime::gmean 11288.127256 # Table walker service (enqueue to completion) latency
1416system.cpu1.itb.walker.walkCompletionTime::stdev 5150.797327 # Table walker service (enqueue to completion) latency
1417system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency
1418system.cpu1.itb.walker.walkCompletionTime::8192-12287 577 70.45% 84.62% # Table walker service (enqueue to completion) latency
1419system.cpu1.itb.walker.walkCompletionTime::12288-16383 76 9.28% 93.89% # Table walker service (enqueue to completion) latency
1420system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 94.87% # Table walker service (enqueue to completion) latency
1421system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 95.12% # Table walker service (enqueue to completion) latency
1422system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.80% # Table walker service (enqueue to completion) latency
1423system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 98.78% # Table walker service (enqueue to completion) latency
1424system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency
1425system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency
1426system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency
1427system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.24% 100.00% # Table walker service (enqueue to completion) latency
1428system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency
1429system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution
1430system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution
1431system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution
1432system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated
1433system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated
1434system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated
1435system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1436system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst
1437system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst
1438system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1439system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst
1440system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst
1441system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst
1442system.cpu1.itb.inst_hits 13920333 # ITB inst hits
1443system.cpu1.itb.inst_misses 1376 # ITB inst misses
1444system.cpu1.itb.read_hits 0 # DTB read hits
1445system.cpu1.itb.read_misses 0 # DTB read misses
1446system.cpu1.itb.write_hits 0 # DTB write hits
1447system.cpu1.itb.write_misses 0 # DTB write misses
1448system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1449system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1450system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1451system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1452system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB
1453system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1454system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1455system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1456system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1457system.cpu1.itb.read_accesses 0 # DTB read accesses
1458system.cpu1.itb.write_accesses 0 # DTB write accesses
1459system.cpu1.itb.inst_accesses 13921709 # ITB inst accesses
1460system.cpu1.itb.hits 13920333 # DTB hits
1461system.cpu1.itb.misses 1376 # DTB misses
1462system.cpu1.itb.accesses 13921709 # DTB accesses
1463system.cpu1.numCycles 5742623362 # number of cpu cycles simulated
1464system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1465system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1466system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1467system.cpu1.kern.inst.quiesce 2722 # number of quiesce instructions executed
1468system.cpu1.committedInsts 13721353 # Number of instructions committed
1469system.cpu1.committedOps 16716448 # Number of ops (including micro ops) committed
1470system.cpu1.num_int_alu_accesses 15155011 # Number of integer alu accesses
1471system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
1472system.cpu1.num_func_calls 915079 # number of times a function call or return occured
1473system.cpu1.num_conditional_control_insts 1497955 # number of instructions that are conditional controls
1474system.cpu1.num_int_insts 15155011 # number of integer instructions
1475system.cpu1.num_fp_insts 0 # number of float instructions
1476system.cpu1.num_int_register_reads 27537464 # number of times the integer registers were read
1477system.cpu1.num_int_register_writes 10698089 # number of times the integer registers were written
1478system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
1479system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
1480system.cpu1.num_cc_register_reads 61338598 # number of times the CC registers were read
1481system.cpu1.num_cc_register_writes 5194112 # number of times the CC registers were written
1482system.cpu1.num_mem_refs 6464162 # number of memory refs
1483system.cpu1.num_load_insts 3439477 # Number of load instructions
1484system.cpu1.num_store_insts 3024685 # Number of store instructions
1485system.cpu1.num_idle_cycles 5696031009.438875 # Number of idle cycles
1486system.cpu1.num_busy_cycles 46592352.561125 # Number of busy cycles
1487system.cpu1.not_idle_fraction 0.008113 # Percentage of non-idle cycles
1488system.cpu1.idle_fraction 0.991887 # Percentage of idle cycles
1489system.cpu1.Branches 2464329 # Number of branches fetched
1490system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction
1491system.cpu1.op_class::IntAlu 10543721 61.89% 61.89% # Class of executed instruction
1492system.cpu1.op_class::IntMult 24250 0.14% 62.04% # Class of executed instruction
1493system.cpu1.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction
1494system.cpu1.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction
1495system.cpu1.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction
1496system.cpu1.op_class::FloatCvt 0 0.00% 62.04% # Class of executed instruction
1497system.cpu1.op_class::FloatMult 0 0.00% 62.04% # Class of executed instruction
1498system.cpu1.op_class::FloatDiv 0 0.00% 62.04% # Class of executed instruction
1499system.cpu1.op_class::FloatSqrt 0 0.00% 62.04% # Class of executed instruction
1500system.cpu1.op_class::SimdAdd 0 0.00% 62.04% # Class of executed instruction
1501system.cpu1.op_class::SimdAddAcc 0 0.00% 62.04% # Class of executed instruction
1502system.cpu1.op_class::SimdAlu 0 0.00% 62.04% # Class of executed instruction
1503system.cpu1.op_class::SimdCmp 0 0.00% 62.04% # Class of executed instruction
1504system.cpu1.op_class::SimdCvt 0 0.00% 62.04% # Class of executed instruction
1505system.cpu1.op_class::SimdMisc 0 0.00% 62.04% # Class of executed instruction
1506system.cpu1.op_class::SimdMult 0 0.00% 62.04% # Class of executed instruction
1507system.cpu1.op_class::SimdMultAcc 0 0.00% 62.04% # Class of executed instruction
1508system.cpu1.op_class::SimdShift 0 0.00% 62.04% # Class of executed instruction
1509system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.04% # Class of executed instruction
1510system.cpu1.op_class::SimdSqrt 0 0.00% 62.04% # Class of executed instruction
1511system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.04% # Class of executed instruction
1512system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.04% # Class of executed instruction
1513system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction
1514system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction
1515system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction
1516system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.05% # Class of executed instruction
1517system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction
1518system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction
1519system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction
1520system.cpu1.op_class::MemRead 3439477 20.19% 82.24% # Class of executed instruction
1521system.cpu1.op_class::MemWrite 3024685 17.76% 100.00% # Class of executed instruction
1522system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1523system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1524system.cpu1.op_class::total 17035345 # Class of executed instruction
1525system.cpu1.dcache.tags.replacements 148314 # number of replacements
1526system.cpu1.dcache.tags.tagsinuse 469.091453 # Cycle average of tags in use
1527system.cpu1.dcache.tags.total_refs 6019898 # Total number of references to valid blocks.
1528system.cpu1.dcache.tags.sampled_refs 148666 # Sample count of references to valid blocks.
1529system.cpu1.dcache.tags.avg_refs 40.492769 # Average number of references to valid blocks.
1530system.cpu1.dcache.tags.warmup_cycle 106291978000 # Cycle when the warmup percentage was hit.
1531system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.091453 # Average occupied blocks per requestor
1532system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916194 # Average percentage of cache occupancy
1533system.cpu1.dcache.tags.occ_percent::total 0.916194 # Average percentage of cache occupancy
1534system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id
1535system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id
1536system.cpu1.dcache.tags.age_task_id_blocks_1024::3 33 # Occupied blocks per task id
1537system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
1538system.cpu1.dcache.tags.tag_accesses 12680697 # Number of tag accesses
1539system.cpu1.dcache.tags.data_accesses 12680697 # Number of data accesses
1540system.cpu1.dcache.ReadReq_hits::cpu1.data 3066133 # number of ReadReq hits
1541system.cpu1.dcache.ReadReq_hits::total 3066133 # number of ReadReq hits
1542system.cpu1.dcache.WriteReq_hits::cpu1.data 2748576 # number of WriteReq hits
1543system.cpu1.dcache.WriteReq_hits::total 2748576 # number of WriteReq hits
1544system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41842 # number of SoftPFReq hits
1545system.cpu1.dcache.SoftPFReq_hits::total 41842 # number of SoftPFReq hits
1546system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69851 # number of LoadLockedReq hits
1547system.cpu1.dcache.LoadLockedReq_hits::total 69851 # number of LoadLockedReq hits
1548system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61610 # number of StoreCondReq hits
1549system.cpu1.dcache.StoreCondReq_hits::total 61610 # number of StoreCondReq hits
1550system.cpu1.dcache.demand_hits::cpu1.data 5814709 # number of demand (read+write) hits
1551system.cpu1.dcache.demand_hits::total 5814709 # number of demand (read+write) hits
1552system.cpu1.dcache.overall_hits::cpu1.data 5856551 # number of overall hits
1553system.cpu1.dcache.overall_hits::total 5856551 # number of overall hits
1554system.cpu1.dcache.ReadReq_misses::cpu1.data 112800 # number of ReadReq misses
1555system.cpu1.dcache.ReadReq_misses::total 112800 # number of ReadReq misses
1556system.cpu1.dcache.WriteReq_misses::cpu1.data 79377 # number of WriteReq misses
1557system.cpu1.dcache.WriteReq_misses::total 79377 # number of WriteReq misses
1558system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24461 # number of SoftPFReq misses
1559system.cpu1.dcache.SoftPFReq_misses::total 24461 # number of SoftPFReq misses
1560system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16636 # number of LoadLockedReq misses
1561system.cpu1.dcache.LoadLockedReq_misses::total 16636 # number of LoadLockedReq misses
1562system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23088 # number of StoreCondReq misses
1563system.cpu1.dcache.StoreCondReq_misses::total 23088 # number of StoreCondReq misses
1564system.cpu1.dcache.demand_misses::cpu1.data 192177 # number of demand (read+write) misses
1565system.cpu1.dcache.demand_misses::total 192177 # number of demand (read+write) misses
1566system.cpu1.dcache.overall_misses::cpu1.data 216638 # number of overall misses
1567system.cpu1.dcache.overall_misses::total 216638 # number of overall misses
1568system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1758096000 # number of ReadReq miss cycles
1569system.cpu1.dcache.ReadReq_miss_latency::total 1758096000 # number of ReadReq miss cycles
1570system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2710284000 # number of WriteReq miss cycles
1571system.cpu1.dcache.WriteReq_miss_latency::total 2710284000 # number of WriteReq miss cycles
1572system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320294000 # number of LoadLockedReq miss cycles
1573system.cpu1.dcache.LoadLockedReq_miss_latency::total 320294000 # number of LoadLockedReq miss cycles
1574system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 628163500 # number of StoreCondReq miss cycles
1575system.cpu1.dcache.StoreCondReq_miss_latency::total 628163500 # number of StoreCondReq miss cycles
1576system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3848000 # number of StoreCondFailReq miss cycles
1577system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3848000 # number of StoreCondFailReq miss cycles
1578system.cpu1.dcache.demand_miss_latency::cpu1.data 4468380000 # number of demand (read+write) miss cycles
1579system.cpu1.dcache.demand_miss_latency::total 4468380000 # number of demand (read+write) miss cycles
1580system.cpu1.dcache.overall_miss_latency::cpu1.data 4468380000 # number of overall miss cycles
1581system.cpu1.dcache.overall_miss_latency::total 4468380000 # number of overall miss cycles
1582system.cpu1.dcache.ReadReq_accesses::cpu1.data 3178933 # number of ReadReq accesses(hits+misses)
1583system.cpu1.dcache.ReadReq_accesses::total 3178933 # number of ReadReq accesses(hits+misses)
1584system.cpu1.dcache.WriteReq_accesses::cpu1.data 2827953 # number of WriteReq accesses(hits+misses)
1585system.cpu1.dcache.WriteReq_accesses::total 2827953 # number of WriteReq accesses(hits+misses)
1586system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66303 # number of SoftPFReq accesses(hits+misses)
1587system.cpu1.dcache.SoftPFReq_accesses::total 66303 # number of SoftPFReq accesses(hits+misses)
1588system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86487 # number of LoadLockedReq accesses(hits+misses)
1589system.cpu1.dcache.LoadLockedReq_accesses::total 86487 # number of LoadLockedReq accesses(hits+misses)
1590system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84698 # number of StoreCondReq accesses(hits+misses)
1591system.cpu1.dcache.StoreCondReq_accesses::total 84698 # number of StoreCondReq accesses(hits+misses)
1592system.cpu1.dcache.demand_accesses::cpu1.data 6006886 # number of demand (read+write) accesses
1593system.cpu1.dcache.demand_accesses::total 6006886 # number of demand (read+write) accesses
1594system.cpu1.dcache.overall_accesses::cpu1.data 6073189 # number of overall (read+write) accesses
1595system.cpu1.dcache.overall_accesses::total 6073189 # number of overall (read+write) accesses
1596system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035484 # miss rate for ReadReq accesses
1597system.cpu1.dcache.ReadReq_miss_rate::total 0.035484 # miss rate for ReadReq accesses
1598system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028069 # miss rate for WriteReq accesses
1599system.cpu1.dcache.WriteReq_miss_rate::total 0.028069 # miss rate for WriteReq accesses
1600system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.368927 # miss rate for SoftPFReq accesses
1601system.cpu1.dcache.SoftPFReq_miss_rate::total 0.368927 # miss rate for SoftPFReq accesses
1602system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192353 # miss rate for LoadLockedReq accesses
1603system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192353 # miss rate for LoadLockedReq accesses
1604system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272592 # miss rate for StoreCondReq accesses
1605system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272592 # miss rate for StoreCondReq accesses
1606system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031993 # miss rate for demand accesses
1607system.cpu1.dcache.demand_miss_rate::total 0.031993 # miss rate for demand accesses
1608system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035671 # miss rate for overall accesses
1609system.cpu1.dcache.overall_miss_rate::total 0.035671 # miss rate for overall accesses
1610system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15585.957447 # average ReadReq miss latency
1611system.cpu1.dcache.ReadReq_avg_miss_latency::total 15585.957447 # average ReadReq miss latency
1612system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34144.449904 # average WriteReq miss latency
1613system.cpu1.dcache.WriteReq_avg_miss_latency::total 34144.449904 # average WriteReq miss latency
1614system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19253.065641 # average LoadLockedReq miss latency
1615system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19253.065641 # average LoadLockedReq miss latency
1616system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27207.358801 # average StoreCondReq miss latency
1617system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27207.358801 # average StoreCondReq miss latency
1618system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1619system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1620system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23251.377636 # average overall miss latency
1621system.cpu1.dcache.demand_avg_miss_latency::total 23251.377636 # average overall miss latency
1622system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20626.021289 # average overall miss latency
1623system.cpu1.dcache.overall_avg_miss_latency::total 20626.021289 # average overall miss latency
1624system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1625system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1626system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1627system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1628system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1629system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1630system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1631system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1632system.cpu1.dcache.writebacks::writebacks 148314 # number of writebacks
1633system.cpu1.dcache.writebacks::total 148314 # number of writebacks
1634system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 199 # number of ReadReq MSHR hits
1635system.cpu1.dcache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits
1636system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11732 # number of LoadLockedReq MSHR hits
1637system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11732 # number of LoadLockedReq MSHR hits
1638system.cpu1.dcache.demand_mshr_hits::cpu1.data 199 # number of demand (read+write) MSHR hits
1639system.cpu1.dcache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits
1640system.cpu1.dcache.overall_mshr_hits::cpu1.data 199 # number of overall MSHR hits
1641system.cpu1.dcache.overall_mshr_hits::total 199 # number of overall MSHR hits
1642system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112601 # number of ReadReq MSHR misses
1643system.cpu1.dcache.ReadReq_mshr_misses::total 112601 # number of ReadReq MSHR misses
1644system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79377 # number of WriteReq MSHR misses
1645system.cpu1.dcache.WriteReq_mshr_misses::total 79377 # number of WriteReq MSHR misses
1646system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 24003 # number of SoftPFReq MSHR misses
1647system.cpu1.dcache.SoftPFReq_mshr_misses::total 24003 # number of SoftPFReq MSHR misses
1648system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4904 # number of LoadLockedReq MSHR misses
1649system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4904 # number of LoadLockedReq MSHR misses
1650system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23088 # number of StoreCondReq MSHR misses
1651system.cpu1.dcache.StoreCondReq_mshr_misses::total 23088 # number of StoreCondReq MSHR misses
1652system.cpu1.dcache.demand_mshr_misses::cpu1.data 191978 # number of demand (read+write) MSHR misses
1653system.cpu1.dcache.demand_mshr_misses::total 191978 # number of demand (read+write) MSHR misses
1654system.cpu1.dcache.overall_mshr_misses::cpu1.data 215981 # number of overall MSHR misses
1655system.cpu1.dcache.overall_mshr_misses::total 215981 # number of overall MSHR misses
1656system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3083 # number of ReadReq MSHR uncacheable
1657system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3083 # number of ReadReq MSHR uncacheable
1658system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable
1659system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2425 # number of WriteReq MSHR uncacheable
1660system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5508 # number of overall MSHR uncacheable misses
1661system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5508 # number of overall MSHR uncacheable misses
1662system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1635811500 # number of ReadReq MSHR miss cycles
1663system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1635811500 # number of ReadReq MSHR miss cycles
1664system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2630907000 # number of WriteReq MSHR miss cycles
1665system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2630907000 # number of WriteReq MSHR miss cycles
1666system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 431572500 # number of SoftPFReq MSHR miss cycles
1667system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 431572500 # number of SoftPFReq MSHR miss cycles
1668system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89921000 # number of LoadLockedReq MSHR miss cycles
1669system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89921000 # number of LoadLockedReq MSHR miss cycles
1670system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 605110500 # number of StoreCondReq MSHR miss cycles
1671system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 605110500 # number of StoreCondReq MSHR miss cycles
1672system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3813000 # number of StoreCondFailReq MSHR miss cycles
1673system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3813000 # number of StoreCondFailReq MSHR miss cycles
1674system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4266718500 # number of demand (read+write) MSHR miss cycles
1675system.cpu1.dcache.demand_mshr_miss_latency::total 4266718500 # number of demand (read+write) MSHR miss cycles
1676system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4698291000 # number of overall MSHR miss cycles
1677system.cpu1.dcache.overall_mshr_miss_latency::total 4698291000 # number of overall MSHR miss cycles
1678system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439541500 # number of ReadReq MSHR uncacheable cycles
1679system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439541500 # number of ReadReq MSHR uncacheable cycles
1680system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303268000 # number of WriteReq MSHR uncacheable cycles
1681system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303268000 # number of WriteReq MSHR uncacheable cycles
1682system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742809500 # number of overall MSHR uncacheable cycles
1683system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742809500 # number of overall MSHR uncacheable cycles
1684system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035421 # mshr miss rate for ReadReq accesses
1685system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035421 # mshr miss rate for ReadReq accesses
1686system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028069 # mshr miss rate for WriteReq accesses
1687system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028069 # mshr miss rate for WriteReq accesses
1688system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362020 # mshr miss rate for SoftPFReq accesses
1689system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362020 # mshr miss rate for SoftPFReq accesses
1690system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056702 # mshr miss rate for LoadLockedReq accesses
1691system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056702 # mshr miss rate for LoadLockedReq accesses
1692system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272592 # mshr miss rate for StoreCondReq accesses
1693system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272592 # mshr miss rate for StoreCondReq accesses
1694system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031960 # mshr miss rate for demand accesses
1695system.cpu1.dcache.demand_mshr_miss_rate::total 0.031960 # mshr miss rate for demand accesses
1696system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035563 # mshr miss rate for overall accesses
1697system.cpu1.dcache.overall_mshr_miss_rate::total 0.035563 # mshr miss rate for overall accesses
1698system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14527.504196 # average ReadReq mshr miss latency
1699system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14527.504196 # average ReadReq mshr miss latency
1700system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33144.449904 # average WriteReq mshr miss latency
1701system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33144.449904 # average WriteReq mshr miss latency
1702system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17979.940007 # average SoftPFReq mshr miss latency
1703system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17979.940007 # average SoftPFReq mshr miss latency
1704system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18336.256117 # average LoadLockedReq mshr miss latency
1705system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18336.256117 # average LoadLockedReq mshr miss latency
1706system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26208.874740 # average StoreCondReq mshr miss latency
1707system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26208.874740 # average StoreCondReq mshr miss latency
1708system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1709system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1710system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22225.038807 # average overall mshr miss latency
1711system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22225.038807 # average overall mshr miss latency
1712system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21753.260703 # average overall mshr miss latency
1713system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21753.260703 # average overall mshr miss latency
1714system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142569.412910 # average ReadReq mshr uncacheable latency
1715system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142569.412910 # average ReadReq mshr uncacheable latency
1716system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125058.969072 # average WriteReq mshr uncacheable latency
1717system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125058.969072 # average WriteReq mshr uncacheable latency
1718system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134860.112564 # average overall mshr uncacheable latency
1719system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134860.112564 # average overall mshr uncacheable latency
1720system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1721system.cpu1.icache.tags.replacements 463432 # number of replacements
1722system.cpu1.icache.tags.tagsinuse 498.310833 # Cycle average of tags in use
1723system.cpu1.icache.tags.total_refs 13456384 # Total number of references to valid blocks.
1724system.cpu1.icache.tags.sampled_refs 463944 # Sample count of references to valid blocks.
1725system.cpu1.icache.tags.avg_refs 29.004328 # Average number of references to valid blocks.
1726system.cpu1.icache.tags.warmup_cycle 106360036500 # Cycle when the warmup percentage was hit.
1727system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310833 # Average occupied blocks per requestor
1728system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973263 # Average percentage of cache occupancy
1729system.cpu1.icache.tags.occ_percent::total 0.973263 # Average percentage of cache occupancy
1730system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1731system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id
1732system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id
1733system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id
1734system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1735system.cpu1.icache.tags.tag_accesses 28304600 # Number of tag accesses
1736system.cpu1.icache.tags.data_accesses 28304600 # Number of data accesses
1737system.cpu1.icache.ReadReq_hits::cpu1.inst 13456384 # number of ReadReq hits
1738system.cpu1.icache.ReadReq_hits::total 13456384 # number of ReadReq hits
1739system.cpu1.icache.demand_hits::cpu1.inst 13456384 # number of demand (read+write) hits
1740system.cpu1.icache.demand_hits::total 13456384 # number of demand (read+write) hits
1741system.cpu1.icache.overall_hits::cpu1.inst 13456384 # number of overall hits
1742system.cpu1.icache.overall_hits::total 13456384 # number of overall hits
1743system.cpu1.icache.ReadReq_misses::cpu1.inst 463944 # number of ReadReq misses
1744system.cpu1.icache.ReadReq_misses::total 463944 # number of ReadReq misses
1745system.cpu1.icache.demand_misses::cpu1.inst 463944 # number of demand (read+write) misses
1746system.cpu1.icache.demand_misses::total 463944 # number of demand (read+write) misses
1747system.cpu1.icache.overall_misses::cpu1.inst 463944 # number of overall misses
1748system.cpu1.icache.overall_misses::total 463944 # number of overall misses
1749system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4214272500 # number of ReadReq miss cycles
1750system.cpu1.icache.ReadReq_miss_latency::total 4214272500 # number of ReadReq miss cycles
1751system.cpu1.icache.demand_miss_latency::cpu1.inst 4214272500 # number of demand (read+write) miss cycles
1752system.cpu1.icache.demand_miss_latency::total 4214272500 # number of demand (read+write) miss cycles
1753system.cpu1.icache.overall_miss_latency::cpu1.inst 4214272500 # number of overall miss cycles
1754system.cpu1.icache.overall_miss_latency::total 4214272500 # number of overall miss cycles
1755system.cpu1.icache.ReadReq_accesses::cpu1.inst 13920328 # number of ReadReq accesses(hits+misses)
1756system.cpu1.icache.ReadReq_accesses::total 13920328 # number of ReadReq accesses(hits+misses)
1757system.cpu1.icache.demand_accesses::cpu1.inst 13920328 # number of demand (read+write) accesses
1758system.cpu1.icache.demand_accesses::total 13920328 # number of demand (read+write) accesses
1759system.cpu1.icache.overall_accesses::cpu1.inst 13920328 # number of overall (read+write) accesses
1760system.cpu1.icache.overall_accesses::total 13920328 # number of overall (read+write) accesses
1761system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033329 # miss rate for ReadReq accesses
1762system.cpu1.icache.ReadReq_miss_rate::total 0.033329 # miss rate for ReadReq accesses
1763system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033329 # miss rate for demand accesses
1764system.cpu1.icache.demand_miss_rate::total 0.033329 # miss rate for demand accesses
1765system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033329 # miss rate for overall accesses
1766system.cpu1.icache.overall_miss_rate::total 0.033329 # miss rate for overall accesses
1767system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9083.580130 # average ReadReq miss latency
1768system.cpu1.icache.ReadReq_avg_miss_latency::total 9083.580130 # average ReadReq miss latency
1769system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9083.580130 # average overall miss latency
1770system.cpu1.icache.demand_avg_miss_latency::total 9083.580130 # average overall miss latency
1771system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9083.580130 # average overall miss latency
1772system.cpu1.icache.overall_avg_miss_latency::total 9083.580130 # average overall miss latency
1773system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1774system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1775system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1776system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1777system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1778system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1779system.cpu1.icache.fast_writes 0 # number of fast writes performed
1780system.cpu1.icache.cache_copies 0 # number of cache copies performed
1781system.cpu1.icache.writebacks::writebacks 463432 # number of writebacks
1782system.cpu1.icache.writebacks::total 463432 # number of writebacks
1783system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463944 # number of ReadReq MSHR misses
1784system.cpu1.icache.ReadReq_mshr_misses::total 463944 # number of ReadReq MSHR misses
1785system.cpu1.icache.demand_mshr_misses::cpu1.inst 463944 # number of demand (read+write) MSHR misses
1786system.cpu1.icache.demand_mshr_misses::total 463944 # number of demand (read+write) MSHR misses
1787system.cpu1.icache.overall_mshr_misses::cpu1.inst 463944 # number of overall MSHR misses
1788system.cpu1.icache.overall_mshr_misses::total 463944 # number of overall MSHR misses
1789system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
1790system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
1791system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
1792system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
1793system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3982300500 # number of ReadReq MSHR miss cycles
1794system.cpu1.icache.ReadReq_mshr_miss_latency::total 3982300500 # number of ReadReq MSHR miss cycles
1795system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3982300500 # number of demand (read+write) MSHR miss cycles
1796system.cpu1.icache.demand_mshr_miss_latency::total 3982300500 # number of demand (read+write) MSHR miss cycles
1797system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3982300500 # number of overall MSHR miss cycles
1798system.cpu1.icache.overall_mshr_miss_latency::total 3982300500 # number of overall MSHR miss cycles
1799system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles
1800system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles
1801system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles
1802system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles
1803system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for ReadReq accesses
1804system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033329 # mshr miss rate for ReadReq accesses
1805system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for demand accesses
1806system.cpu1.icache.demand_mshr_miss_rate::total 0.033329 # mshr miss rate for demand accesses
1807system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for overall accesses
1808system.cpu1.icache.overall_mshr_miss_rate::total 0.033329 # mshr miss rate for overall accesses
1809system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average ReadReq mshr miss latency
1810system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8583.580130 # average ReadReq mshr miss latency
1811system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average overall mshr miss latency
1812system.cpu1.icache.demand_avg_mshr_miss_latency::total 8583.580130 # average overall mshr miss latency
1813system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8583.580130 # average overall mshr miss latency
1814system.cpu1.icache.overall_avg_mshr_miss_latency::total 8583.580130 # average overall mshr miss latency
1815system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency
1816system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency
1817system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency
1818system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency
1819system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1820system.cpu1.l2cache.prefetcher.num_hwpf_issued 118303 # number of hwpf issued
1821system.cpu1.l2cache.prefetcher.pfIdentified 118321 # number of prefetch candidates identified
1822system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue
1823system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1824system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1825system.cpu1.l2cache.prefetcher.pfSpanPage 50079 # number of prefetches not generated due to page crossing
1826system.cpu1.l2cache.tags.replacements 31154 # number of replacements
1827system.cpu1.l2cache.tags.tagsinuse 14935.857031 # Cycle average of tags in use
1828system.cpu1.l2cache.tags.total_refs 1041086 # Total number of references to valid blocks.
1829system.cpu1.l2cache.tags.sampled_refs 46286 # Sample count of references to valid blocks.
1830system.cpu1.l2cache.tags.avg_refs 22.492460 # Average number of references to valid blocks.
1831system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1832system.cpu1.l2cache.tags.occ_blocks::writebacks 14446.292104 # Average occupied blocks per requestor
1833system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.202140 # Average occupied blocks per requestor
1834system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.081939 # Average occupied blocks per requestor
1835system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 484.280848 # Average occupied blocks per requestor
1836system.cpu1.l2cache.tags.occ_percent::writebacks 0.881732 # Average percentage of cache occupancy
1837system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000195 # Average percentage of cache occupancy
1838system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy
1839system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.029558 # Average percentage of cache occupancy
1840system.cpu1.l2cache.tags.occ_percent::total 0.911612 # Average percentage of cache occupancy
1841system.cpu1.l2cache.tags.occ_task_id_blocks::1022 981 # Occupied blocks per task id
1842system.cpu1.l2cache.tags.occ_task_id_blocks::1023 38 # Occupied blocks per task id
1843system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14113 # Occupied blocks per task id
1844system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id
1845system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 47 # Occupied blocks per task id
1846system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 926 # Occupied blocks per task id
1847system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
1848system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
1849system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id
1850system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id
1851system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1668 # Occupied blocks per task id
1852system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12049 # Occupied blocks per task id
1853system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059875 # Percentage of cache occupancy per task id
1854system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002319 # Percentage of cache occupancy per task id
1855system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.861389 # Percentage of cache occupancy per task id
1856system.cpu1.l2cache.tags.tag_accesses 21151055 # Number of tag accesses
1857system.cpu1.l2cache.tags.data_accesses 21151055 # Number of data accesses
1858system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2455 # number of ReadReq hits
1859system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1474 # number of ReadReq hits
1860system.cpu1.l2cache.ReadReq_hits::total 3929 # number of ReadReq hits
1861system.cpu1.l2cache.WritebackDirty_hits::writebacks 92001 # number of WritebackDirty hits
1862system.cpu1.l2cache.WritebackDirty_hits::total 92001 # number of WritebackDirty hits
1863system.cpu1.l2cache.WritebackClean_hits::writebacks 509646 # number of WritebackClean hits
1864system.cpu1.l2cache.WritebackClean_hits::total 509646 # number of WritebackClean hits
1865system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18183 # number of ReadExReq hits
1866system.cpu1.l2cache.ReadExReq_hits::total 18183 # number of ReadExReq hits
1867system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 455037 # number of ReadCleanReq hits
1868system.cpu1.l2cache.ReadCleanReq_hits::total 455037 # number of ReadCleanReq hits
1869system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77628 # number of ReadSharedReq hits
1870system.cpu1.l2cache.ReadSharedReq_hits::total 77628 # number of ReadSharedReq hits
1871system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2455 # number of demand (read+write) hits
1872system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1474 # number of demand (read+write) hits
1873system.cpu1.l2cache.demand_hits::cpu1.inst 455037 # number of demand (read+write) hits
1874system.cpu1.l2cache.demand_hits::cpu1.data 95811 # number of demand (read+write) hits
1875system.cpu1.l2cache.demand_hits::total 554777 # number of demand (read+write) hits
1876system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2455 # number of overall hits
1877system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1474 # number of overall hits
1878system.cpu1.l2cache.overall_hits::cpu1.inst 455037 # number of overall hits
1879system.cpu1.l2cache.overall_hits::cpu1.data 95811 # number of overall hits
1880system.cpu1.l2cache.overall_hits::total 554777 # number of overall hits
1881system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses
1882system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 300 # number of ReadReq misses
1883system.cpu1.l2cache.ReadReq_misses::total 648 # number of ReadReq misses
1884system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28973 # number of UpgradeReq misses
1885system.cpu1.l2cache.UpgradeReq_misses::total 28973 # number of UpgradeReq misses
1886system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23087 # number of SCUpgradeReq misses
1887system.cpu1.l2cache.SCUpgradeReq_misses::total 23087 # number of SCUpgradeReq misses
1888system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
1889system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
1890system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32221 # number of ReadExReq misses
1891system.cpu1.l2cache.ReadExReq_misses::total 32221 # number of ReadExReq misses
1892system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8907 # number of ReadCleanReq misses
1893system.cpu1.l2cache.ReadCleanReq_misses::total 8907 # number of ReadCleanReq misses
1894system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63880 # number of ReadSharedReq misses
1895system.cpu1.l2cache.ReadSharedReq_misses::total 63880 # number of ReadSharedReq misses
1896system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses
1897system.cpu1.l2cache.demand_misses::cpu1.itb.walker 300 # number of demand (read+write) misses
1898system.cpu1.l2cache.demand_misses::cpu1.inst 8907 # number of demand (read+write) misses
1899system.cpu1.l2cache.demand_misses::cpu1.data 96101 # number of demand (read+write) misses
1900system.cpu1.l2cache.demand_misses::total 105656 # number of demand (read+write) misses
1901system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses
1902system.cpu1.l2cache.overall_misses::cpu1.itb.walker 300 # number of overall misses
1903system.cpu1.l2cache.overall_misses::cpu1.inst 8907 # number of overall misses
1904system.cpu1.l2cache.overall_misses::cpu1.data 96101 # number of overall misses
1905system.cpu1.l2cache.overall_misses::total 105656 # number of overall misses
1906system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7097500 # number of ReadReq miss cycles
1907system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5968000 # number of ReadReq miss cycles
1908system.cpu1.l2cache.ReadReq_miss_latency::total 13065500 # number of ReadReq miss cycles
1909system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64302000 # number of UpgradeReq miss cycles
1910system.cpu1.l2cache.UpgradeReq_miss_latency::total 64302000 # number of UpgradeReq miss cycles
1911system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 54899500 # number of SCUpgradeReq miss cycles
1912system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 54899500 # number of SCUpgradeReq miss cycles
1913system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3760000 # number of SCUpgradeFailReq miss cycles
1914system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3760000 # number of SCUpgradeFailReq miss cycles
1915system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1640601500 # number of ReadExReq miss cycles
1916system.cpu1.l2cache.ReadExReq_miss_latency::total 1640601500 # number of ReadExReq miss cycles
1917system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 530446000 # number of ReadCleanReq miss cycles
1918system.cpu1.l2cache.ReadCleanReq_miss_latency::total 530446000 # number of ReadCleanReq miss cycles
1919system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1436061500 # number of ReadSharedReq miss cycles
1920system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1436061500 # number of ReadSharedReq miss cycles
1921system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7097500 # number of demand (read+write) miss cycles
1922system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5968000 # number of demand (read+write) miss cycles
1923system.cpu1.l2cache.demand_miss_latency::cpu1.inst 530446000 # number of demand (read+write) miss cycles
1924system.cpu1.l2cache.demand_miss_latency::cpu1.data 3076663000 # number of demand (read+write) miss cycles
1925system.cpu1.l2cache.demand_miss_latency::total 3620174500 # number of demand (read+write) miss cycles
1926system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7097500 # number of overall miss cycles
1927system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5968000 # number of overall miss cycles
1928system.cpu1.l2cache.overall_miss_latency::cpu1.inst 530446000 # number of overall miss cycles
1929system.cpu1.l2cache.overall_miss_latency::cpu1.data 3076663000 # number of overall miss cycles
1930system.cpu1.l2cache.overall_miss_latency::total 3620174500 # number of overall miss cycles
1931system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2803 # number of ReadReq accesses(hits+misses)
1932system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1774 # number of ReadReq accesses(hits+misses)
1933system.cpu1.l2cache.ReadReq_accesses::total 4577 # number of ReadReq accesses(hits+misses)
1934system.cpu1.l2cache.WritebackDirty_accesses::writebacks 92001 # number of WritebackDirty accesses(hits+misses)
1935system.cpu1.l2cache.WritebackDirty_accesses::total 92001 # number of WritebackDirty accesses(hits+misses)
1936system.cpu1.l2cache.WritebackClean_accesses::writebacks 509646 # number of WritebackClean accesses(hits+misses)
1937system.cpu1.l2cache.WritebackClean_accesses::total 509646 # number of WritebackClean accesses(hits+misses)
1938system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28973 # number of UpgradeReq accesses(hits+misses)
1939system.cpu1.l2cache.UpgradeReq_accesses::total 28973 # number of UpgradeReq accesses(hits+misses)
1940system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23087 # number of SCUpgradeReq accesses(hits+misses)
1941system.cpu1.l2cache.SCUpgradeReq_accesses::total 23087 # number of SCUpgradeReq accesses(hits+misses)
1942system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
1943system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
1944system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50404 # number of ReadExReq accesses(hits+misses)
1945system.cpu1.l2cache.ReadExReq_accesses::total 50404 # number of ReadExReq accesses(hits+misses)
1946system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 463944 # number of ReadCleanReq accesses(hits+misses)
1947system.cpu1.l2cache.ReadCleanReq_accesses::total 463944 # number of ReadCleanReq accesses(hits+misses)
1948system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 141508 # number of ReadSharedReq accesses(hits+misses)
1949system.cpu1.l2cache.ReadSharedReq_accesses::total 141508 # number of ReadSharedReq accesses(hits+misses)
1950system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2803 # number of demand (read+write) accesses
1951system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1774 # number of demand (read+write) accesses
1952system.cpu1.l2cache.demand_accesses::cpu1.inst 463944 # number of demand (read+write) accesses
1953system.cpu1.l2cache.demand_accesses::cpu1.data 191912 # number of demand (read+write) accesses
1954system.cpu1.l2cache.demand_accesses::total 660433 # number of demand (read+write) accesses
1955system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2803 # number of overall (read+write) accesses
1956system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1774 # number of overall (read+write) accesses
1957system.cpu1.l2cache.overall_accesses::cpu1.inst 463944 # number of overall (read+write) accesses
1958system.cpu1.l2cache.overall_accesses::cpu1.data 191912 # number of overall (read+write) accesses
1959system.cpu1.l2cache.overall_accesses::total 660433 # number of overall (read+write) accesses
1960system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.124153 # miss rate for ReadReq accesses
1961system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.169109 # miss rate for ReadReq accesses
1962system.cpu1.l2cache.ReadReq_miss_rate::total 0.141577 # miss rate for ReadReq accesses
1963system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
1964system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1965system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
1966system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
1967system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1968system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1969system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.639255 # miss rate for ReadExReq accesses
1970system.cpu1.l2cache.ReadExReq_miss_rate::total 0.639255 # miss rate for ReadExReq accesses
1971system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.019198 # miss rate for ReadCleanReq accesses
1972system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.019198 # miss rate for ReadCleanReq accesses
1973system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.451423 # miss rate for ReadSharedReq accesses
1974system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.451423 # miss rate for ReadSharedReq accesses
1975system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.124153 # miss rate for demand accesses
1976system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.169109 # miss rate for demand accesses
1977system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.019198 # miss rate for demand accesses
1978system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.500756 # miss rate for demand accesses
1979system.cpu1.l2cache.demand_miss_rate::total 0.159980 # miss rate for demand accesses
1980system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.124153 # miss rate for overall accesses
1981system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.169109 # miss rate for overall accesses
1982system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.019198 # miss rate for overall accesses
1983system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.500756 # miss rate for overall accesses
1984system.cpu1.l2cache.overall_miss_rate::total 0.159980 # miss rate for overall accesses
1985system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20395.114943 # average ReadReq miss latency
1986system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19893.333333 # average ReadReq miss latency
1987system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20162.808642 # average ReadReq miss latency
1988system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2219.376661 # average UpgradeReq miss latency
1989system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2219.376661 # average UpgradeReq miss latency
1990system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2377.939966 # average SCUpgradeReq miss latency
1991system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2377.939966 # average SCUpgradeReq miss latency
1992system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3760000 # average SCUpgradeFailReq miss latency
1993system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3760000 # average SCUpgradeFailReq miss latency
1994system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50917.150306 # average ReadExReq miss latency
1995system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50917.150306 # average ReadExReq miss latency
1996system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 59553.834063 # average ReadCleanReq miss latency
1997system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 59553.834063 # average ReadCleanReq miss latency
1998system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22480.612085 # average ReadSharedReq miss latency
1999system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22480.612085 # average ReadSharedReq miss latency
2000system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20395.114943 # average overall miss latency
2001system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19893.333333 # average overall miss latency
2002system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 59553.834063 # average overall miss latency
2003system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32014.890584 # average overall miss latency
2004system.cpu1.l2cache.demand_avg_miss_latency::total 34263.785303 # average overall miss latency
2005system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20395.114943 # average overall miss latency
2006system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19893.333333 # average overall miss latency
2007system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 59553.834063 # average overall miss latency
2008system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32014.890584 # average overall miss latency
2009system.cpu1.l2cache.overall_avg_miss_latency::total 34263.785303 # average overall miss latency
2010system.cpu1.l2cache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
2011system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2012system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
2013system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2014system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26 # average number of cycles each access was blocked
2015system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2016system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2017system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2018system.cpu1.l2cache.writebacks::writebacks 25848 # number of writebacks
2019system.cpu1.l2cache.writebacks::total 25848 # number of writebacks
2020system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 72 # number of ReadExReq MSHR hits
2021system.cpu1.l2cache.ReadExReq_mshr_hits::total 72 # number of ReadExReq MSHR hits
2022system.cpu1.l2cache.demand_mshr_hits::cpu1.data 72 # number of demand (read+write) MSHR hits
2023system.cpu1.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
2024system.cpu1.l2cache.overall_mshr_hits::cpu1.data 72 # number of overall MSHR hits
2025system.cpu1.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits
2026system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 348 # number of ReadReq MSHR misses
2027system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 300 # number of ReadReq MSHR misses
2028system.cpu1.l2cache.ReadReq_mshr_misses::total 648 # number of ReadReq MSHR misses
2029system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 21105 # number of HardPFReq MSHR misses
2030system.cpu1.l2cache.HardPFReq_mshr_misses::total 21105 # number of HardPFReq MSHR misses
2031system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28973 # number of UpgradeReq MSHR misses
2032system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28973 # number of UpgradeReq MSHR misses
2033system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23087 # number of SCUpgradeReq MSHR misses
2034system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23087 # number of SCUpgradeReq MSHR misses
2035system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
2036system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
2037system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32149 # number of ReadExReq MSHR misses
2038system.cpu1.l2cache.ReadExReq_mshr_misses::total 32149 # number of ReadExReq MSHR misses
2039system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8907 # number of ReadCleanReq MSHR misses
2040system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8907 # number of ReadCleanReq MSHR misses
2041system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63880 # number of ReadSharedReq MSHR misses
2042system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63880 # number of ReadSharedReq MSHR misses
2043system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 348 # number of demand (read+write) MSHR misses
2044system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 300 # number of demand (read+write) MSHR misses
2045system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8907 # number of demand (read+write) MSHR misses
2046system.cpu1.l2cache.demand_mshr_misses::cpu1.data 96029 # number of demand (read+write) MSHR misses
2047system.cpu1.l2cache.demand_mshr_misses::total 105584 # number of demand (read+write) MSHR misses
2048system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 348 # number of overall MSHR misses
2049system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 300 # number of overall MSHR misses
2050system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8907 # number of overall MSHR misses
2051system.cpu1.l2cache.overall_mshr_misses::cpu1.data 96029 # number of overall MSHR misses
2052system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 21105 # number of overall MSHR misses
2053system.cpu1.l2cache.overall_mshr_misses::total 126689 # number of overall MSHR misses
2054system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2055system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3083 # number of ReadReq MSHR uncacheable
2056system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3260 # number of ReadReq MSHR uncacheable
2057system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable
2058system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2425 # number of WriteReq MSHR uncacheable
2059system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2060system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5508 # number of overall MSHR uncacheable misses
2061system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5685 # number of overall MSHR uncacheable misses
2062system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5009500 # number of ReadReq MSHR miss cycles
2063system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4168000 # number of ReadReq MSHR miss cycles
2064system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9177500 # number of ReadReq MSHR miss cycles
2065system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 934365172 # number of HardPFReq MSHR miss cycles
2066system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 934365172 # number of HardPFReq MSHR miss cycles
2067system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 576596500 # number of UpgradeReq MSHR miss cycles
2068system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 576596500 # number of UpgradeReq MSHR miss cycles
2069system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 431875500 # number of SCUpgradeReq MSHR miss cycles
2070system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 431875500 # number of SCUpgradeReq MSHR miss cycles
2071system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3550000 # number of SCUpgradeFailReq MSHR miss cycles
2072system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3550000 # number of SCUpgradeFailReq MSHR miss cycles
2073system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1440609000 # number of ReadExReq MSHR miss cycles
2074system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1440609000 # number of ReadExReq MSHR miss cycles
2075system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 477004000 # number of ReadCleanReq MSHR miss cycles
2076system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 477004000 # number of ReadCleanReq MSHR miss cycles
2077system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1052781500 # number of ReadSharedReq MSHR miss cycles
2078system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1052781500 # number of ReadSharedReq MSHR miss cycles
2079system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5009500 # number of demand (read+write) MSHR miss cycles
2080system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4168000 # number of demand (read+write) MSHR miss cycles
2081system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 477004000 # number of demand (read+write) MSHR miss cycles
2082system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2493390500 # number of demand (read+write) MSHR miss cycles
2083system.cpu1.l2cache.demand_mshr_miss_latency::total 2979572000 # number of demand (read+write) MSHR miss cycles
2084system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5009500 # number of overall MSHR miss cycles
2085system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4168000 # number of overall MSHR miss cycles
2086system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 477004000 # number of overall MSHR miss cycles
2087system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2493390500 # number of overall MSHR miss cycles
2088system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 934365172 # number of overall MSHR miss cycles
2089system.cpu1.l2cache.overall_mshr_miss_latency::total 3913937172 # number of overall MSHR miss cycles
2090system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles
2091system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414529000 # number of ReadReq MSHR uncacheable cycles
2092system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436748000 # number of ReadReq MSHR uncacheable cycles
2093system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 285072000 # number of WriteReq MSHR uncacheable cycles
2094system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 285072000 # number of WriteReq MSHR uncacheable cycles
2095system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles
2096system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699601000 # number of overall MSHR uncacheable cycles
2097system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721820000 # number of overall MSHR uncacheable cycles
2098system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for ReadReq accesses
2099system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for ReadReq accesses
2100system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.141577 # mshr miss rate for ReadReq accesses
2101system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2102system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2103system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
2104system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
2105system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2106system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2107system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2108system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2109system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637826 # mshr miss rate for ReadExReq accesses
2110system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637826 # mshr miss rate for ReadExReq accesses
2111system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for ReadCleanReq accesses
2112system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019198 # mshr miss rate for ReadCleanReq accesses
2113system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451423 # mshr miss rate for ReadSharedReq accesses
2114system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451423 # mshr miss rate for ReadSharedReq accesses
2115system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for demand accesses
2116system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for demand accesses
2117system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for demand accesses
2118system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for demand accesses
2119system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159871 # mshr miss rate for demand accesses
2120system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for overall accesses
2121system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for overall accesses
2122system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for overall accesses
2123system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for overall accesses
2124system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2125system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191827 # mshr miss rate for overall accesses
2126system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average ReadReq mshr miss latency
2127system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average ReadReq mshr miss latency
2128system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14162.808642 # average ReadReq mshr miss latency
2129system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average HardPFReq mshr miss latency
2130system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44272.218526 # average HardPFReq mshr miss latency
2131system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19901.166603 # average UpgradeReq mshr miss latency
2132system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19901.166603 # average UpgradeReq mshr miss latency
2133system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18706.436523 # average SCUpgradeReq mshr miss latency
2134system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18706.436523 # average SCUpgradeReq mshr miss latency
2135system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3550000 # average SCUpgradeFailReq mshr miss latency
2136system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3550000 # average SCUpgradeFailReq mshr miss latency
2137system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44810.382905 # average ReadExReq mshr miss latency
2138system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44810.382905 # average ReadExReq mshr miss latency
2139system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average ReadCleanReq mshr miss latency
2140system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53553.834063 # average ReadCleanReq mshr miss latency
2141system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16480.612085 # average ReadSharedReq mshr miss latency
2142system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16480.612085 # average ReadSharedReq mshr miss latency
2143system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency
2144system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency
2145system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency
2146system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency
2147system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28219.919685 # average overall mshr miss latency
2148system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency
2149system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency
2150system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency
2151system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency
2152system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average overall mshr miss latency
2153system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30894.056879 # average overall mshr miss latency
2154system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency
2155system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134456.373662 # average ReadReq mshr uncacheable latency
2156system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133971.779141 # average ReadReq mshr uncacheable latency
2157system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117555.463918 # average WriteReq mshr uncacheable latency
2158system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117555.463918 # average WriteReq mshr uncacheable latency
2159system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency
2160system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127015.432099 # average overall mshr uncacheable latency
2161system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126969.217238 # average overall mshr uncacheable latency
2162system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2163system.cpu1.toL2Bus.snoop_filter.tot_requests 1324645 # Total number of requests made to the snoop filter.
2164system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668824 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2165system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10099 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2166system.cpu1.toL2Bus.snoop_filter.tot_snoops 169409 # Total number of snoops made to the snoop filter.
2167system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166956 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2168system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2453 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2169system.cpu1.toL2Bus.trans_dist::ReadReq 10097 # Transaction distribution
2170system.cpu1.toL2Bus.trans_dist::ReadResp 652790 # Transaction distribution
2171system.cpu1.toL2Bus.trans_dist::WriteReq 2425 # Transaction distribution
2172system.cpu1.toL2Bus.trans_dist::WriteResp 2425 # Transaction distribution
2173system.cpu1.toL2Bus.trans_dist::WritebackDirty 119017 # Transaction distribution
2174system.cpu1.toL2Bus.trans_dist::WritebackClean 519745 # Transaction distribution
2175system.cpu1.toL2Bus.trans_dist::CleanEvict 86537 # Transaction distribution
2176system.cpu1.toL2Bus.trans_dist::HardPFReq 25449 # Transaction distribution
2177system.cpu1.toL2Bus.trans_dist::UpgradeReq 70337 # Transaction distribution
2178system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40896 # Transaction distribution
2179system.cpu1.toL2Bus.trans_dist::UpgradeResp 84740 # Transaction distribution
2180system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
2181system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
2182system.cpu1.toL2Bus.trans_dist::ReadExReq 57665 # Transaction distribution
2183system.cpu1.toL2Bus.trans_dist::ReadExResp 55147 # Transaction distribution
2184system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463944 # Transaction distribution
2185system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215084 # Transaction distribution
2186system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution
2187system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391674 # Packet count per connected master and slave (bytes)
2188system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722021 # Packet count per connected master and slave (bytes)
2189system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4392 # Packet count per connected master and slave (bytes)
2190system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7022 # Packet count per connected master and slave (bytes)
2191system.cpu1.toL2Bus.pkt_count::total 2125109 # Packet count per connected master and slave (bytes)
2192system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59352772 # Cumulative packet size per connected master and slave (bytes)
2193system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24485096 # Cumulative packet size per connected master and slave (bytes)
2194system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7096 # Cumulative packet size per connected master and slave (bytes)
2195system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11212 # Cumulative packet size per connected master and slave (bytes)
2196system.cpu1.toL2Bus.pkt_size::total 83856176 # Cumulative packet size per connected master and slave (bytes)
2197system.cpu1.toL2Bus.snoops 356096 # Total snoops (count)
2198system.cpu1.toL2Bus.snoop_fanout::samples 999531 # Request fanout histogram
2199system.cpu1.toL2Bus.snoop_fanout::mean 0.187033 # Request fanout histogram
2200system.cpu1.toL2Bus.snoop_fanout::stdev 0.396182 # Request fanout histogram
2201system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2202system.cpu1.toL2Bus.snoop_fanout::0 815039 81.54% 81.54% # Request fanout histogram
2203system.cpu1.toL2Bus.snoop_fanout::1 182039 18.21% 99.75% # Request fanout histogram
2204system.cpu1.toL2Bus.snoop_fanout::2 2453 0.25% 100.00% # Request fanout histogram
2205system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2206system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2207system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2208system.cpu1.toL2Bus.snoop_fanout::total 999531 # Request fanout histogram
2209system.cpu1.toL2Bus.reqLayer0.occupancy 1279051999 # Layer occupancy (ticks)
2210system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2211system.cpu1.toL2Bus.snoopLayer0.occupancy 79434008 # Layer occupancy (ticks)
2212system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2213system.cpu1.toL2Bus.respLayer0.occupancy 696093000 # Layer occupancy (ticks)
2214system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2215system.cpu1.toL2Bus.respLayer1.occupancy 318231000 # Layer occupancy (ticks)
2216system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2217system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks)
2218system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2219system.cpu1.toL2Bus.respLayer3.occupancy 4219000 # Layer occupancy (ticks)
2220system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2221system.iobus.trans_dist::ReadReq 31021 # Transaction distribution
2222system.iobus.trans_dist::ReadResp 31021 # Transaction distribution
2223system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
2224system.iobus.trans_dist::WriteResp 59425 # Transaction distribution
2225system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes)
2226system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2227system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2228system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2229system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2230system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)

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2237system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2238system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2239system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2240system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2241system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2242system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2243system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2244system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes)
2245system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
2246system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
2247system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes)
2248system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes)
2249system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2250system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes)
2251system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2252system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2253system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2254system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2255system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)

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2260system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2261system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2262system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2263system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2264system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2265system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2266system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2267system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes)
2268system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
2269system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
2270system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes)
2271system.iobus.reqLayer0.occupancy 48746500 # Layer occupancy (ticks)
2272system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2273system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks)
2274system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2275system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks)
2276system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2277system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks)
2278system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2279system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks)
2280system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
2281system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks)
2282system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2283system.iobus.reqLayer8.occupancy 609000 # Layer occupancy (ticks)
2284system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
2285system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks)
2286system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2287system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks)
2288system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2289system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks)
2290system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2291system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks)
2292system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2293system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks)
2294system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2295system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
2296system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2297system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks)
2298system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2299system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks)
2300system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2301system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks)
2302system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2303system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks)
2304system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2305system.iobus.reqLayer23.occupancy 6162500 # Layer occupancy (ticks)
2306system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2307system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks)
2308system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2309system.iobus.reqLayer25.occupancy 187117449 # Layer occupancy (ticks)
2310system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2311system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks)
2312system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2313system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks)
2314system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2315system.iocache.tags.replacements 36461 # number of replacements
2316system.iocache.tags.tagsinuse 14.380044 # Cycle average of tags in use
2317system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2318system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks.
2319system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2320system.iocache.tags.warmup_cycle 290746348000 # Cycle when the warmup percentage was hit.
2321system.iocache.tags.occ_blocks::realview.ide 14.380044 # Average occupied blocks per requestor
2322system.iocache.tags.occ_percent::realview.ide 0.898753 # Average percentage of cache occupancy
2323system.iocache.tags.occ_percent::total 0.898753 # Average percentage of cache occupancy
2324system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2325system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2326system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2327system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2328system.iocache.tags.data_accesses 328311 # Number of data accesses
2329system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2330system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2331system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
2332system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
2333system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
2334system.iocache.demand_misses::total 255 # number of demand (read+write) misses
2335system.iocache.overall_misses::realview.ide 255 # number of overall misses
2336system.iocache.overall_misses::total 255 # number of overall misses
2337system.iocache.ReadReq_miss_latency::realview.ide 32874877 # number of ReadReq miss cycles
2338system.iocache.ReadReq_miss_latency::total 32874877 # number of ReadReq miss cycles
2339system.iocache.WriteLineReq_miss_latency::realview.ide 4582462572 # number of WriteLineReq miss cycles
2340system.iocache.WriteLineReq_miss_latency::total 4582462572 # number of WriteLineReq miss cycles
2341system.iocache.demand_miss_latency::realview.ide 32874877 # number of demand (read+write) miss cycles
2342system.iocache.demand_miss_latency::total 32874877 # number of demand (read+write) miss cycles
2343system.iocache.overall_miss_latency::realview.ide 32874877 # number of overall miss cycles
2344system.iocache.overall_miss_latency::total 32874877 # number of overall miss cycles
2345system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2346system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2347system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
2348system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
2349system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
2350system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
2351system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
2352system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
2353system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2354system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2355system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
2356system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
2357system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2358system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2359system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2360system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2361system.iocache.ReadReq_avg_miss_latency::realview.ide 128921.086275 # average ReadReq miss latency
2362system.iocache.ReadReq_avg_miss_latency::total 128921.086275 # average ReadReq miss latency
2363system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126503.494148 # average WriteLineReq miss latency
2364system.iocache.WriteLineReq_avg_miss_latency::total 126503.494148 # average WriteLineReq miss latency
2365system.iocache.demand_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency
2366system.iocache.demand_avg_miss_latency::total 128921.086275 # average overall miss latency
2367system.iocache.overall_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency
2368system.iocache.overall_avg_miss_latency::total 128921.086275 # average overall miss latency
2369system.iocache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked
2370system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2371system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked
2372system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2373system.iocache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked
2374system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2375system.iocache.fast_writes 0 # number of fast writes performed
2376system.iocache.cache_copies 0 # number of cache copies performed
2377system.iocache.writebacks::writebacks 36206 # number of writebacks
2378system.iocache.writebacks::total 36206 # number of writebacks
2379system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2380system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2381system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
2382system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
2383system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
2384system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
2385system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
2386system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
2387system.iocache.ReadReq_mshr_miss_latency::realview.ide 20124877 # number of ReadReq MSHR miss cycles
2388system.iocache.ReadReq_mshr_miss_latency::total 20124877 # number of ReadReq MSHR miss cycles
2389system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2769551646 # number of WriteLineReq MSHR miss cycles
2390system.iocache.WriteLineReq_mshr_miss_latency::total 2769551646 # number of WriteLineReq MSHR miss cycles
2391system.iocache.demand_mshr_miss_latency::realview.ide 20124877 # number of demand (read+write) MSHR miss cycles
2392system.iocache.demand_mshr_miss_latency::total 20124877 # number of demand (read+write) MSHR miss cycles
2393system.iocache.overall_mshr_miss_latency::realview.ide 20124877 # number of overall MSHR miss cycles
2394system.iocache.overall_mshr_miss_latency::total 20124877 # number of overall MSHR miss cycles
2395system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2396system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2397system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
2398system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
2399system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2400system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2401system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2402system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2403system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78921.086275 # average ReadReq mshr miss latency
2404system.iocache.ReadReq_avg_mshr_miss_latency::total 78921.086275 # average ReadReq mshr miss latency
2405system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76456.262312 # average WriteLineReq mshr miss latency
2406system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76456.262312 # average WriteLineReq mshr miss latency
2407system.iocache.demand_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency
2408system.iocache.demand_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency
2409system.iocache.overall_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency
2410system.iocache.overall_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency
2411system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2412system.l2c.tags.replacements 123661 # number of replacements
2413system.l2c.tags.tagsinuse 63058.402721 # Cycle average of tags in use
2414system.l2c.tags.total_refs 421257 # Total number of references to valid blocks.
2415system.l2c.tags.sampled_refs 187718 # Sample count of references to valid blocks.
2416system.l2c.tags.avg_refs 2.244095 # Average number of references to valid blocks.
2417system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2418system.l2c.tags.occ_blocks::writebacks 13491.325958 # Average occupied blocks per requestor
2419system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.985555 # Average occupied blocks per requestor
2420system.l2c.tags.occ_blocks::cpu0.itb.walker 0.052859 # Average occupied blocks per requestor
2421system.l2c.tags.occ_blocks::cpu0.inst 7361.006580 # Average occupied blocks per requestor
2422system.l2c.tags.occ_blocks::cpu0.data 2805.566875 # Average occupied blocks per requestor
2423system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35728.682862 # Average occupied blocks per requestor
2424system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954518 # Average occupied blocks per requestor
2425system.l2c.tags.occ_blocks::cpu1.inst 1443.499308 # Average occupied blocks per requestor
2426system.l2c.tags.occ_blocks::cpu1.data 410.819619 # Average occupied blocks per requestor
2427system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1814.508588 # Average occupied blocks per requestor
2428system.l2c.tags.occ_percent::writebacks 0.205861 # Average percentage of cache occupancy
2429system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
2430system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2431system.l2c.tags.occ_percent::cpu0.inst 0.112320 # Average percentage of cache occupancy
2432system.l2c.tags.occ_percent::cpu0.data 0.042810 # Average percentage of cache occupancy
2433system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545176 # Average percentage of cache occupancy
2434system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
2435system.l2c.tags.occ_percent::cpu1.inst 0.022026 # Average percentage of cache occupancy
2436system.l2c.tags.occ_percent::cpu1.data 0.006269 # Average percentage of cache occupancy
2437system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027687 # Average percentage of cache occupancy
2438system.l2c.tags.occ_percent::total 0.962195 # Average percentage of cache occupancy
2439system.l2c.tags.occ_task_id_blocks::1022 32044 # Occupied blocks per task id
2440system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
2441system.l2c.tags.occ_task_id_blocks::1024 32009 # Occupied blocks per task id
2442system.l2c.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id
2443system.l2c.tags.age_task_id_blocks_1022::3 5120 # Occupied blocks per task id
2444system.l2c.tags.age_task_id_blocks_1022::4 26618 # Occupied blocks per task id
2445system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
2446system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
2447system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id
2448system.l2c.tags.age_task_id_blocks_1024::2 402 # Occupied blocks per task id
2449system.l2c.tags.age_task_id_blocks_1024::3 2325 # Occupied blocks per task id
2450system.l2c.tags.age_task_id_blocks_1024::4 29253 # Occupied blocks per task id
2451system.l2c.tags.occ_task_id_percent::1022 0.488953 # Percentage of cache occupancy per task id
2452system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
2453system.l2c.tags.occ_task_id_percent::1024 0.488419 # Percentage of cache occupancy per task id
2454system.l2c.tags.tag_accesses 5830329 # Number of tag accesses
2455system.l2c.tags.data_accesses 5830329 # Number of data accesses
2456system.l2c.WritebackDirty_hits::writebacks 257370 # number of WritebackDirty hits
2457system.l2c.WritebackDirty_hits::total 257370 # number of WritebackDirty hits
2458system.l2c.UpgradeReq_hits::cpu0.data 32263 # number of UpgradeReq hits
2459system.l2c.UpgradeReq_hits::cpu1.data 1924 # number of UpgradeReq hits
2460system.l2c.UpgradeReq_hits::total 34187 # number of UpgradeReq hits
2461system.l2c.SCUpgradeReq_hits::cpu0.data 2044 # number of SCUpgradeReq hits
2462system.l2c.SCUpgradeReq_hits::cpu1.data 899 # number of SCUpgradeReq hits
2463system.l2c.SCUpgradeReq_hits::total 2943 # number of SCUpgradeReq hits
2464system.l2c.ReadExReq_hits::cpu0.data 4115 # number of ReadExReq hits
2465system.l2c.ReadExReq_hits::cpu1.data 1385 # number of ReadExReq hits
2466system.l2c.ReadExReq_hits::total 5500 # number of ReadExReq hits
2467system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 95 # number of ReadSharedReq hits
2468system.l2c.ReadSharedReq_hits::cpu0.itb.walker 72 # number of ReadSharedReq hits
2469system.l2c.ReadSharedReq_hits::cpu0.inst 28709 # number of ReadSharedReq hits
2470system.l2c.ReadSharedReq_hits::cpu0.data 46783 # number of ReadSharedReq hits
2471system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47559 # number of ReadSharedReq hits
2472system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 20 # number of ReadSharedReq hits
2473system.l2c.ReadSharedReq_hits::cpu1.itb.walker 13 # number of ReadSharedReq hits
2474system.l2c.ReadSharedReq_hits::cpu1.inst 6543 # number of ReadSharedReq hits
2475system.l2c.ReadSharedReq_hits::cpu1.data 5065 # number of ReadSharedReq hits
2476system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3419 # number of ReadSharedReq hits
2477system.l2c.ReadSharedReq_hits::total 138278 # number of ReadSharedReq hits
2478system.l2c.demand_hits::cpu0.dtb.walker 95 # number of demand (read+write) hits
2479system.l2c.demand_hits::cpu0.itb.walker 72 # number of demand (read+write) hits
2480system.l2c.demand_hits::cpu0.inst 28709 # number of demand (read+write) hits
2481system.l2c.demand_hits::cpu0.data 50898 # number of demand (read+write) hits
2482system.l2c.demand_hits::cpu0.l2cache.prefetcher 47559 # number of demand (read+write) hits
2483system.l2c.demand_hits::cpu1.dtb.walker 20 # number of demand (read+write) hits
2484system.l2c.demand_hits::cpu1.itb.walker 13 # number of demand (read+write) hits
2485system.l2c.demand_hits::cpu1.inst 6543 # number of demand (read+write) hits
2486system.l2c.demand_hits::cpu1.data 6450 # number of demand (read+write) hits
2487system.l2c.demand_hits::cpu1.l2cache.prefetcher 3419 # number of demand (read+write) hits
2488system.l2c.demand_hits::total 143778 # number of demand (read+write) hits
2489system.l2c.overall_hits::cpu0.dtb.walker 95 # number of overall hits
2490system.l2c.overall_hits::cpu0.itb.walker 72 # number of overall hits
2491system.l2c.overall_hits::cpu0.inst 28709 # number of overall hits
2492system.l2c.overall_hits::cpu0.data 50898 # number of overall hits
2493system.l2c.overall_hits::cpu0.l2cache.prefetcher 47559 # number of overall hits
2494system.l2c.overall_hits::cpu1.dtb.walker 20 # number of overall hits
2495system.l2c.overall_hits::cpu1.itb.walker 13 # number of overall hits
2496system.l2c.overall_hits::cpu1.inst 6543 # number of overall hits
2497system.l2c.overall_hits::cpu1.data 6450 # number of overall hits
2498system.l2c.overall_hits::cpu1.l2cache.prefetcher 3419 # number of overall hits
2499system.l2c.overall_hits::total 143778 # number of overall hits
2500system.l2c.UpgradeReq_misses::cpu0.data 9386 # number of UpgradeReq misses
2501system.l2c.UpgradeReq_misses::cpu1.data 2249 # number of UpgradeReq misses
2502system.l2c.UpgradeReq_misses::total 11635 # number of UpgradeReq misses
2503system.l2c.SCUpgradeReq_misses::cpu0.data 587 # number of SCUpgradeReq misses
2504system.l2c.SCUpgradeReq_misses::cpu1.data 1308 # number of SCUpgradeReq misses
2505system.l2c.SCUpgradeReq_misses::total 1895 # number of SCUpgradeReq misses
2506system.l2c.ReadExReq_misses::cpu0.data 11114 # number of ReadExReq misses
2507system.l2c.ReadExReq_misses::cpu1.data 7777 # number of ReadExReq misses
2508system.l2c.ReadExReq_misses::total 18891 # number of ReadExReq misses
2509system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 5 # number of ReadSharedReq misses
2510system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses
2511system.l2c.ReadSharedReq_misses::cpu0.inst 17503 # number of ReadSharedReq misses
2512system.l2c.ReadSharedReq_misses::cpu0.data 8876 # number of ReadSharedReq misses
2513system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134571 # number of ReadSharedReq misses
2514system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses
2515system.l2c.ReadSharedReq_misses::cpu1.inst 2364 # number of ReadSharedReq misses
2516system.l2c.ReadSharedReq_misses::cpu1.data 804 # number of ReadSharedReq misses
2517system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5455 # number of ReadSharedReq misses
2518system.l2c.ReadSharedReq_misses::total 169581 # number of ReadSharedReq misses
2519system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses
2520system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
2521system.l2c.demand_misses::cpu0.inst 17503 # number of demand (read+write) misses
2522system.l2c.demand_misses::cpu0.data 19990 # number of demand (read+write) misses
2523system.l2c.demand_misses::cpu0.l2cache.prefetcher 134571 # number of demand (read+write) misses
2524system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
2525system.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses
2526system.l2c.demand_misses::cpu1.data 8581 # number of demand (read+write) misses
2527system.l2c.demand_misses::cpu1.l2cache.prefetcher 5455 # number of demand (read+write) misses
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2554system.l2c.ReadSharedReq_miss_latency::cpu1.inst 313582000 # number of ReadSharedReq miss cycles
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2557system.l2c.ReadSharedReq_miss_latency::total 24363127123 # number of ReadSharedReq miss cycles
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2563system.l2c.demand_miss_latency::cpu1.dtb.walker 146500 # number of demand (read+write) miss cycles
2564system.l2c.demand_miss_latency::cpu1.inst 313582000 # number of demand (read+write) miss cycles
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2567system.l2c.demand_miss_latency::total 27000838623 # number of demand (read+write) miss cycles
2568system.l2c.overall_miss_latency::cpu0.dtb.walker 677000 # number of overall miss cycles
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2578system.l2c.WritebackDirty_accesses::writebacks 257370 # number of WritebackDirty accesses(hits+misses)
2579system.l2c.WritebackDirty_accesses::total 257370 # number of WritebackDirty accesses(hits+misses)
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2585system.l2c.SCUpgradeReq_accesses::total 4838 # number of SCUpgradeReq accesses(hits+misses)
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2596system.l2c.ReadSharedReq_accesses::cpu1.inst 8907 # number of ReadSharedReq accesses(hits+misses)
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2598system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8874 # number of ReadSharedReq accesses(hits+misses)
2599system.l2c.ReadSharedReq_accesses::total 307859 # number of ReadSharedReq accesses(hits+misses)
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2621system.l2c.overall_accesses::total 332250 # number of overall (read+write) accesses
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2623system.l2c.UpgradeReq_miss_rate::cpu1.data 0.538941 # miss rate for UpgradeReq accesses
2624system.l2c.UpgradeReq_miss_rate::total 0.253917 # miss rate for UpgradeReq accesses
2625system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.223109 # miss rate for SCUpgradeReq accesses
2626system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.592660 # miss rate for SCUpgradeReq accesses
2627system.l2c.SCUpgradeReq_miss_rate::total 0.391691 # miss rate for SCUpgradeReq accesses
2628system.l2c.ReadExReq_miss_rate::cpu0.data 0.729792 # miss rate for ReadExReq accesses
2629system.l2c.ReadExReq_miss_rate::cpu1.data 0.848832 # miss rate for ReadExReq accesses
2630system.l2c.ReadExReq_miss_rate::total 0.774507 # miss rate for ReadExReq accesses
2631system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.050000 # miss rate for ReadSharedReq accesses
2632system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027027 # miss rate for ReadSharedReq accesses
2633system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.378754 # miss rate for ReadSharedReq accesses
2634system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.159471 # miss rate for ReadSharedReq accesses
2635system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738873 # miss rate for ReadSharedReq accesses
2636system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for ReadSharedReq accesses
2637system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.265409 # miss rate for ReadSharedReq accesses
2638system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.136991 # miss rate for ReadSharedReq accesses
2639system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.614717 # miss rate for ReadSharedReq accesses
2640system.l2c.ReadSharedReq_miss_rate::total 0.550840 # miss rate for ReadSharedReq accesses
2641system.l2c.demand_miss_rate::cpu0.dtb.walker 0.050000 # miss rate for demand accesses
2642system.l2c.demand_miss_rate::cpu0.itb.walker 0.027027 # miss rate for demand accesses
2643system.l2c.demand_miss_rate::cpu0.inst 0.378754 # miss rate for demand accesses
2644system.l2c.demand_miss_rate::cpu0.data 0.281994 # miss rate for demand accesses
2645system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738873 # miss rate for demand accesses
2646system.l2c.demand_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for demand accesses
2647system.l2c.demand_miss_rate::cpu1.inst 0.265409 # miss rate for demand accesses
2648system.l2c.demand_miss_rate::cpu1.data 0.570887 # miss rate for demand accesses
2649system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.614717 # miss rate for demand accesses
2650system.l2c.demand_miss_rate::total 0.567260 # miss rate for demand accesses
2651system.l2c.overall_miss_rate::cpu0.dtb.walker 0.050000 # miss rate for overall accesses
2652system.l2c.overall_miss_rate::cpu0.itb.walker 0.027027 # miss rate for overall accesses
2653system.l2c.overall_miss_rate::cpu0.inst 0.378754 # miss rate for overall accesses
2654system.l2c.overall_miss_rate::cpu0.data 0.281994 # miss rate for overall accesses
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2656system.l2c.overall_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for overall accesses
2657system.l2c.overall_miss_rate::cpu1.inst 0.265409 # miss rate for overall accesses
2658system.l2c.overall_miss_rate::cpu1.data 0.570887 # miss rate for overall accesses
2659system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.614717 # miss rate for overall accesses
2660system.l2c.overall_miss_rate::total 0.567260 # miss rate for overall accesses
2661system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3222.672065 # average UpgradeReq miss latency
2662system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2313.472655 # average UpgradeReq miss latency
2663system.l2c.UpgradeReq_avg_miss_latency::total 3046.927374 # average UpgradeReq miss latency
2664system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6535.775128 # average SCUpgradeReq miss latency
2665system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2084.097859 # average SCUpgradeReq miss latency
2666system.l2c.SCUpgradeReq_avg_miss_latency::total 3463.060686 # average SCUpgradeReq miss latency
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2668system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130850.520766 # average ReadExReq miss latency
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2670system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 135400 # average ReadSharedReq miss latency
2671system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 181000 # average ReadSharedReq miss latency
2672system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131523.224590 # average ReadSharedReq miss latency
2673system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136244.592159 # average ReadSharedReq miss latency
2674system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824 # average ReadSharedReq miss latency
2675system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 146500 # average ReadSharedReq miss latency
2676system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132648.900169 # average ReadSharedReq miss latency
2677system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140690.298507 # average ReadSharedReq miss latency
2678system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368 # average ReadSharedReq miss latency
2679system.l2c.ReadSharedReq_avg_miss_latency::total 143666.608423 # average ReadSharedReq miss latency
2680system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135400 # average overall miss latency
2681system.l2c.demand_avg_miss_latency::cpu0.itb.walker 181000 # average overall miss latency
2682system.l2c.demand_avg_miss_latency::cpu0.inst 131523.224590 # average overall miss latency
2683system.l2c.demand_avg_miss_latency::cpu0.data 141540.470235 # average overall miss latency
2684system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824 # average overall miss latency
2685system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 146500 # average overall miss latency
2686system.l2c.demand_avg_miss_latency::cpu1.inst 132648.900169 # average overall miss latency
2687system.l2c.demand_avg_miss_latency::cpu1.data 131772.462417 # average overall miss latency
2688system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368 # average overall miss latency
2689system.l2c.demand_avg_miss_latency::total 143261.803467 # average overall miss latency
2690system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135400 # average overall miss latency
2691system.l2c.overall_avg_miss_latency::cpu0.itb.walker 181000 # average overall miss latency
2692system.l2c.overall_avg_miss_latency::cpu0.inst 131523.224590 # average overall miss latency
2693system.l2c.overall_avg_miss_latency::cpu0.data 141540.470235 # average overall miss latency
2694system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145401.347824 # average overall miss latency
2695system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 146500 # average overall miss latency
2696system.l2c.overall_avg_miss_latency::cpu1.inst 132648.900169 # average overall miss latency
2697system.l2c.overall_avg_miss_latency::cpu1.data 131772.462417 # average overall miss latency
2698system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 157118.578368 # average overall miss latency
2699system.l2c.overall_avg_miss_latency::total 143261.803467 # average overall miss latency
2700system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2701system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2702system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2703system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2704system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2705system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2706system.l2c.fast_writes 0 # number of fast writes performed
2707system.l2c.cache_copies 0 # number of cache copies performed
2708system.l2c.writebacks::writebacks 96987 # number of writebacks
2709system.l2c.writebacks::total 96987 # number of writebacks
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2715system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
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2718system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits
2719system.l2c.CleanEvict_mshr_misses::writebacks 2809 # number of CleanEvict MSHR misses
2720system.l2c.CleanEvict_mshr_misses::total 2809 # number of CleanEvict MSHR misses
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2724system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 587 # number of SCUpgradeReq MSHR misses
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2733system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8876 # number of ReadSharedReq MSHR misses
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2739system.l2c.ReadSharedReq_mshr_misses::total 169572 # number of ReadSharedReq MSHR misses
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2743system.l2c.demand_mshr_misses::cpu0.data 19990 # number of demand (read+write) MSHR misses
2744system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134571 # number of demand (read+write) MSHR misses
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2747system.l2c.demand_mshr_misses::cpu1.data 8581 # number of demand (read+write) MSHR misses
2748system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5455 # number of demand (read+write) MSHR misses
2749system.l2c.demand_mshr_misses::total 188463 # number of demand (read+write) MSHR misses
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2753system.l2c.overall_mshr_misses::cpu0.data 19990 # number of overall MSHR misses
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2757system.l2c.overall_mshr_misses::cpu1.data 8581 # number of overall MSHR misses
2758system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5455 # number of overall MSHR misses
2759system.l2c.overall_mshr_misses::total 188463 # number of overall MSHR misses
2760system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
2761system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable
2762system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2763system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3080 # number of ReadReq MSHR uncacheable
2764system.l2c.ReadReq_mshr_uncacheable::total 44099 # number of ReadReq MSHR uncacheable
2765system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable
2766system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable
2767system.l2c.WriteReq_mshr_uncacheable::total 30924 # number of WriteReq MSHR uncacheable
2768system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
2769system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses
2770system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2771system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5505 # number of overall MSHR uncacheable misses
2772system.l2c.overall_mshr_uncacheable_misses::total 75023 # number of overall MSHR uncacheable misses
2773system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 682643500 # number of UpgradeReq MSHR miss cycles
2774system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 162589000 # number of UpgradeReq MSHR miss cycles
2775system.l2c.UpgradeReq_mshr_miss_latency::total 845232500 # number of UpgradeReq MSHR miss cycles
2776system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 43754500 # number of SCUpgradeReq MSHR miss cycles
2777system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 96726500 # number of SCUpgradeReq MSHR miss cycles
2778system.l2c.SCUpgradeReq_mshr_miss_latency::total 140481000 # number of SCUpgradeReq MSHR miss cycles
2779system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1508944512 # number of ReadExReq MSHR miss cycles
2780system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 939851506 # number of ReadExReq MSHR miss cycles
2781system.l2c.ReadExReq_mshr_miss_latency::total 2448796018 # number of ReadExReq MSHR miss cycles
2782system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 627000 # number of ReadSharedReq MSHR miss cycles
2783system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 342000 # number of ReadSharedReq MSHR miss cycles
2784system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2126838009 # number of ReadSharedReq MSHR miss cycles
2785system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1120542510 # number of ReadSharedReq MSHR miss cycles
2786system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18221057894 # number of ReadSharedReq MSHR miss cycles
2787system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 136500 # number of ReadSharedReq MSHR miss cycles
2788system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 289400510 # number of ReadSharedReq MSHR miss cycles
2789system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 105072505 # number of ReadSharedReq MSHR miss cycles
2790system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 802516896 # number of ReadSharedReq MSHR miss cycles
2791system.l2c.ReadSharedReq_mshr_miss_latency::total 22666533824 # number of ReadSharedReq MSHR miss cycles
2792system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 627000 # number of demand (read+write) MSHR miss cycles
2793system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 342000 # number of demand (read+write) MSHR miss cycles
2794system.l2c.demand_mshr_miss_latency::cpu0.inst 2126838009 # number of demand (read+write) MSHR miss cycles
2795system.l2c.demand_mshr_miss_latency::cpu0.data 2629487022 # number of demand (read+write) MSHR miss cycles
2796system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18221057894 # number of demand (read+write) MSHR miss cycles
2797system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 136500 # number of demand (read+write) MSHR miss cycles
2798system.l2c.demand_mshr_miss_latency::cpu1.inst 289400510 # number of demand (read+write) MSHR miss cycles
2799system.l2c.demand_mshr_miss_latency::cpu1.data 1044924011 # number of demand (read+write) MSHR miss cycles
2800system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 802516896 # number of demand (read+write) MSHR miss cycles
2801system.l2c.demand_mshr_miss_latency::total 25115329842 # number of demand (read+write) MSHR miss cycles
2802system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 627000 # number of overall MSHR miss cycles
2803system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 342000 # number of overall MSHR miss cycles
2804system.l2c.overall_mshr_miss_latency::cpu0.inst 2126838009 # number of overall MSHR miss cycles
2805system.l2c.overall_mshr_miss_latency::cpu0.data 2629487022 # number of overall MSHR miss cycles
2806system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18221057894 # number of overall MSHR miss cycles
2807system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 136500 # number of overall MSHR miss cycles
2808system.l2c.overall_mshr_miss_latency::cpu1.inst 289400510 # number of overall MSHR miss cycles
2809system.l2c.overall_mshr_miss_latency::cpu1.data 1044924011 # number of overall MSHR miss cycles
2810system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 802516896 # number of overall MSHR miss cycles
2811system.l2c.overall_mshr_miss_latency::total 25115329842 # number of overall MSHR miss cycles
2812system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles
2813system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5801306000 # number of ReadReq MSHR uncacheable cycles
2814system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles
2815system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 359044000 # number of ReadReq MSHR uncacheable cycles
2816system.l2c.ReadReq_mshr_uncacheable_latency::total 7203197500 # number of ReadReq MSHR uncacheable cycles
2817system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702516500 # number of WriteReq MSHR uncacheable cycles
2818system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243805501 # number of WriteReq MSHR uncacheable cycles
2819system.l2c.WriteReq_mshr_uncacheable_latency::total 4946322001 # number of WriteReq MSHR uncacheable cycles
2820system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles
2821system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10503822500 # number of overall MSHR uncacheable cycles
2822system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles
2823system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602849501 # number of overall MSHR uncacheable cycles
2824system.l2c.overall_mshr_uncacheable_latency::total 12149519501 # number of overall MSHR uncacheable cycles
2825system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2826system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2827system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225360 # mshr miss rate for UpgradeReq accesses
2828system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.538941 # mshr miss rate for UpgradeReq accesses
2829system.l2c.UpgradeReq_mshr_miss_rate::total 0.253917 # mshr miss rate for UpgradeReq accesses
2830system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.223109 # mshr miss rate for SCUpgradeReq accesses
2831system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592660 # mshr miss rate for SCUpgradeReq accesses
2832system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.391691 # mshr miss rate for SCUpgradeReq accesses
2833system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.729792 # mshr miss rate for ReadExReq accesses
2834system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.848832 # mshr miss rate for ReadExReq accesses
2835system.l2c.ReadExReq_mshr_miss_rate::total 0.774507 # mshr miss rate for ReadExReq accesses
2836system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for ReadSharedReq accesses
2837system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for ReadSharedReq accesses
2838system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for ReadSharedReq accesses
2839system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.159471 # mshr miss rate for ReadSharedReq accesses
2840system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for ReadSharedReq accesses
2841system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for ReadSharedReq accesses
2842system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for ReadSharedReq accesses
2843system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.136991 # mshr miss rate for ReadSharedReq accesses
2844system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for ReadSharedReq accesses
2845system.l2c.ReadSharedReq_mshr_miss_rate::total 0.550811 # mshr miss rate for ReadSharedReq accesses
2846system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for demand accesses
2847system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for demand accesses
2848system.l2c.demand_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for demand accesses
2849system.l2c.demand_mshr_miss_rate::cpu0.data 0.281994 # mshr miss rate for demand accesses
2850system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for demand accesses
2851system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for demand accesses
2852system.l2c.demand_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for demand accesses
2853system.l2c.demand_mshr_miss_rate::cpu1.data 0.570887 # mshr miss rate for demand accesses
2854system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for demand accesses
2855system.l2c.demand_mshr_miss_rate::total 0.567233 # mshr miss rate for demand accesses
2856system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for overall accesses
2857system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for overall accesses
2858system.l2c.overall_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for overall accesses
2859system.l2c.overall_mshr_miss_rate::cpu0.data 0.281994 # mshr miss rate for overall accesses
2860system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for overall accesses
2861system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for overall accesses
2862system.l2c.overall_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for overall accesses
2863system.l2c.overall_mshr_miss_rate::cpu1.data 0.570887 # mshr miss rate for overall accesses
2864system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for overall accesses
2865system.l2c.overall_mshr_miss_rate::total 0.567233 # mshr miss rate for overall accesses
2866system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72729.970168 # average UpgradeReq mshr miss latency
2867system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72293.908404 # average UpgradeReq mshr miss latency
2868system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72645.681135 # average UpgradeReq mshr miss latency
2869system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74539.182283 # average SCUpgradeReq mshr miss latency
2870system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73949.923547 # average SCUpgradeReq mshr miss latency
2871system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.453826 # average SCUpgradeReq mshr miss latency
2872system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135769.705956 # average ReadExReq mshr miss latency
2873system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120850.135785 # average ReadExReq mshr miss latency
2874system.l2c.ReadExReq_avg_mshr_miss_latency::total 129627.654333 # average ReadExReq mshr miss latency
2875system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average ReadSharedReq mshr miss latency
2876system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average ReadSharedReq mshr miss latency
2877system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average ReadSharedReq mshr miss latency
2878system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126244.086300 # average ReadSharedReq mshr miss latency
2879system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average ReadSharedReq mshr miss latency
2880system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average ReadSharedReq mshr miss latency
2881system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average ReadSharedReq mshr miss latency
2882system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130687.195274 # average ReadSharedReq mshr miss latency
2883system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average ReadSharedReq mshr miss latency
2884system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133669.083481 # average ReadSharedReq mshr miss latency
2885system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency
2886system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency
2887system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency
2888system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency
2889system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency
2890system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency
2891system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency
2892system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency
2893system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency
2894system.l2c.demand_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency
2895system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency
2896system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency
2897system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency
2898system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency
2899system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency
2900system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency
2901system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency
2902system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency
2903system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency
2904system.l2c.overall_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency
2905system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency
2906system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182316.341923 # average ReadReq mshr uncacheable latency
2907system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency
2908system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116572.727273 # average ReadReq mshr uncacheable latency
2909system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163341.515681 # average ReadReq mshr uncacheable latency
2910system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.368645 # average WriteReq mshr uncacheable latency
2911system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100538.350928 # average WriteReq mshr uncacheable latency
2912system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159950.911945 # average WriteReq mshr uncacheable latency
2913system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency
2914system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174137.875296 # average overall mshr uncacheable latency
2915system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency
2916system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109509.446140 # average overall mshr uncacheable latency
2917system.l2c.overall_avg_mshr_uncacheable_latency::total 161943.930541 # average overall mshr uncacheable latency
2918system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2919system.membus.trans_dist::ReadReq 44099 # Transaction distribution
2920system.membus.trans_dist::ReadResp 213926 # Transaction distribution
2921system.membus.trans_dist::WriteReq 30924 # Transaction distribution
2922system.membus.trans_dist::WriteResp 30924 # Transaction distribution
2923system.membus.trans_dist::WritebackDirty 133193 # Transaction distribution
2924system.membus.trans_dist::CleanEvict 14771 # Transaction distribution
2925system.membus.trans_dist::UpgradeReq 73670 # Transaction distribution
2926system.membus.trans_dist::SCUpgradeReq 39871 # Transaction distribution
2927system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
2928system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
2929system.membus.trans_dist::ReadExReq 39385 # Transaction distribution
2930system.membus.trans_dist::ReadExResp 18791 # Transaction distribution
2931system.membus.trans_dist::ReadSharedReq 169827 # Transaction distribution
2932system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
2933system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes)
2934system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
2935system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13776 # Packet count per connected master and slave (bytes)
2936system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650336 # Packet count per connected master and slave (bytes)
2937system.membus.pkt_count_system.l2c.mem_side::total 772080 # Packet count per connected master and slave (bytes)
2938system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes)
2939system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes)
2940system.membus.pkt_count::total 845035 # Packet count per connected master and slave (bytes)
2941system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes)
2942system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
2943system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27552 # Cumulative packet size per connected master and slave (bytes)
2944system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18297804 # Cumulative packet size per connected master and slave (bytes)
2945system.membus.pkt_size_system.l2c.mem_side::total 18488238 # Cumulative packet size per connected master and slave (bytes)
2946system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
2947system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
2948system.membus.pkt_size::total 20806382 # Cumulative packet size per connected master and slave (bytes)
2949system.membus.snoops 121083 # Total snoops (count)
2950system.membus.snoop_fanout::samples 581994 # Request fanout histogram
2951system.membus.snoop_fanout::mean 1 # Request fanout histogram
2952system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2953system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2954system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2955system.membus.snoop_fanout::1 581994 100.00% 100.00% # Request fanout histogram
2956system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2957system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2958system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2959system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2960system.membus.snoop_fanout::total 581994 # Request fanout histogram
2961system.membus.reqLayer0.occupancy 88286500 # Layer occupancy (ticks)
2962system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2963system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks)
2964system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2965system.membus.reqLayer2.occupancy 11391000 # Layer occupancy (ticks)
2966system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2967system.membus.reqLayer5.occupancy 968108262 # Layer occupancy (ticks)
2968system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2969system.membus.respLayer2.occupancy 1106274782 # Layer occupancy (ticks)
2970system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2971system.membus.respLayer3.occupancy 1388877 # Layer occupancy (ticks)
2972system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2973system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
2974system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
2975system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
2976system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
2977system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
2978system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
2979system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA

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3006system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3007system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
3008system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
3009system.realview.ethernet.droppedPackets 0 # number of packets dropped
3010system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3011system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3012system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3013system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3014system.toL2Bus.snoop_filter.tot_requests 960339 # Total number of requests made to the snoop filter.
3015system.toL2Bus.snoop_filter.hit_single_requests 518534 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3016system.toL2Bus.snoop_filter.hit_multi_requests 139328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3017system.toL2Bus.snoop_filter.tot_snoops 20435 # Total number of snoops made to the snoop filter.
3018system.toL2Bus.snoop_filter.hit_single_snoops 19626 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3019system.toL2Bus.snoop_filter.hit_multi_snoops 809 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3020system.toL2Bus.trans_dist::ReadReq 44102 # Transaction distribution
3021system.toL2Bus.trans_dist::ReadResp 468032 # Transaction distribution
3022system.toL2Bus.trans_dist::WriteReq 30924 # Transaction distribution
3023system.toL2Bus.trans_dist::WriteResp 30924 # Transaction distribution
3024system.toL2Bus.trans_dist::WritebackDirty 390589 # Transaction distribution
3025system.toL2Bus.trans_dist::CleanEvict 105128 # Transaction distribution
3026system.toL2Bus.trans_dist::UpgradeReq 107757 # Transaction distribution
3027system.toL2Bus.trans_dist::SCUpgradeReq 42814 # Transaction distribution
3028system.toL2Bus.trans_dist::UpgradeResp 150571 # Transaction distribution
3029system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution
3030system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
3031system.toL2Bus.trans_dist::ReadExReq 50426 # Transaction distribution
3032system.toL2Bus.trans_dist::ReadExResp 50426 # Transaction distribution
3033system.toL2Bus.trans_dist::ReadSharedReq 423945 # Transaction distribution
3034system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
3035system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240075 # Packet count per connected master and slave (bytes)
3036system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253445 # Packet count per connected master and slave (bytes)
3037system.toL2Bus.pkt_count::total 1493520 # Packet count per connected master and slave (bytes)
3038system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34222158 # Cumulative packet size per connected master and slave (bytes)
3039system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3776032 # Cumulative packet size per connected master and slave (bytes)
3040system.toL2Bus.pkt_size::total 37998190 # Cumulative packet size per connected master and slave (bytes)
3041system.toL2Bus.snoops 438746 # Total snoops (count)
3042system.toL2Bus.snoop_fanout::samples 896439 # Request fanout histogram
3043system.toL2Bus.snoop_fanout::mean 0.337268 # Request fanout histogram
3044system.toL2Bus.snoop_fanout::stdev 0.474682 # Request fanout histogram
3045system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3046system.toL2Bus.snoop_fanout::0 594908 66.36% 66.36% # Request fanout histogram
3047system.toL2Bus.snoop_fanout::1 300722 33.55% 99.91% # Request fanout histogram
3048system.toL2Bus.snoop_fanout::2 809 0.09% 100.00% # Request fanout histogram
3049system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3050system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3051system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3052system.toL2Bus.snoop_fanout::total 896439 # Request fanout histogram
3053system.toL2Bus.reqLayer0.occupancy 863728414 # Layer occupancy (ticks)
3054system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3055system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks)
3056system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3057system.toL2Bus.respLayer0.occupancy 645946273 # Layer occupancy (ticks)
3058system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3059system.toL2Bus.respLayer1.occupancy 202615858 # Layer occupancy (ticks)
3060system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3061
3062---------- End Simulation Statistics ----------