1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.868578 # Number of seconds simulated
4sim_ticks 2868577613500 # Number of ticks simulated
5final_tick 2868577613500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 558438 # Simulator instruction rate (inst/s)
8host_op_rate 675477 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 12195118142 # Simulator tick rate (ticks/s)
10host_mem_usage 590596 # Number of bytes of host memory used
11host_seconds 235.22 # Real time elapsed on the host
12sim_insts 131357672 # Number of instructions simulated
13sim_ops 158887964 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1167908 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 1250980 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8365696 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.inst 137236 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.data 508432 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.l2cache.prefetcher 356544 # Number of bytes read from this memory
25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
26system.physmem.bytes_read::total 11788332 # Number of bytes read from this memory
27system.physmem.bytes_inst_read::cpu0.inst 1167908 # Number of instructions bytes read from this memory
28system.physmem.bytes_inst_read::cpu1.inst 137236 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::total 1305144 # Number of instructions bytes read from this memory
30system.physmem.bytes_written::writebacks 8293056 # Number of bytes written to this memory
31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
33system.physmem.bytes_written::total 8310620 # Number of bytes written to this memory
34system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.inst 26702 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.data 20066 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.l2cache.prefetcher 130714 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.inst 2299 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.data 7964 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.l2cache.prefetcher 5571 # Number of read requests responded to by this memory
43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
44system.physmem.num_reads::total 193340 # Number of read requests responded to by this memory
45system.physmem.num_writes::writebacks 129579 # Number of write requests responded to by this memory
46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
48system.physmem.num_writes::total 133970 # Number of write requests responded to by this memory
49system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu0.inst 407138 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.data 436098 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.l2cache.prefetcher 2916322 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu1.inst 47841 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.data 177242 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.l2cache.prefetcher 124293 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::total 4109469 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_inst_read::cpu0.inst 407138 # Instruction read bandwidth from this memory (bytes/s)
61system.physmem.bw_inst_read::cpu1.inst 47841 # Instruction read bandwidth from this memory (bytes/s)
62system.physmem.bw_inst_read::total 454979 # Instruction read bandwidth from this memory (bytes/s)
63system.physmem.bw_write::writebacks 2890999 # Write bandwidth from this memory (bytes/s)
64system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s)
65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
66system.physmem.bw_write::total 2897122 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_total::writebacks 2890999 # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::cpu0.inst 407138 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.data 442207 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.l2cache.prefetcher 2916322 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu1.inst 47841 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu1.data 177256 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.l2cache.prefetcher 124293 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::total 7006592 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.readReqs 193340 # Number of read requests accepted
80system.physmem.writeReqs 170194 # Number of write requests accepted
81system.physmem.readBursts 193340 # Number of DRAM read bursts, including those serviced by the write queue
82system.physmem.writeBursts 170194 # Number of DRAM write bursts, including those merged in the write queue
83system.physmem.bytesReadDRAM 12365312 # Total number of bytes read from DRAM
84system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue
85system.physmem.bytesWritten 9398080 # Total number of bytes written to DRAM
86system.physmem.bytesReadSys 11788332 # Total read bytes from the system interface side
87system.physmem.bytesWrittenSys 10628956 # Total written bytes from the system interface side
88system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue
89system.physmem.mergedWrBursts 23320 # Number of DRAM write bursts merged with an existing one
90system.physmem.neitherReadNorWriteReqs 12970 # Number of requests that are neither read nor write
91system.physmem.perBankRdBursts::0 11741 # Per bank write bursts
92system.physmem.perBankRdBursts::1 11572 # Per bank write bursts
93system.physmem.perBankRdBursts::2 11914 # Per bank write bursts
94system.physmem.perBankRdBursts::3 12194 # Per bank write bursts
95system.physmem.perBankRdBursts::4 20279 # Per bank write bursts
96system.physmem.perBankRdBursts::5 11715 # Per bank write bursts
97system.physmem.perBankRdBursts::6 11292 # Per bank write bursts
98system.physmem.perBankRdBursts::7 11716 # Per bank write bursts
99system.physmem.perBankRdBursts::8 11966 # Per bank write bursts
100system.physmem.perBankRdBursts::9 12328 # Per bank write bursts
101system.physmem.perBankRdBursts::10 11336 # Per bank write bursts
102system.physmem.perBankRdBursts::11 10554 # Per bank write bursts
103system.physmem.perBankRdBursts::12 10992 # Per bank write bursts
104system.physmem.perBankRdBursts::13 11462 # Per bank write bursts
105system.physmem.perBankRdBursts::14 10907 # Per bank write bursts
106system.physmem.perBankRdBursts::15 11240 # Per bank write bursts
107system.physmem.perBankWrBursts::0 9545 # Per bank write bursts
108system.physmem.perBankWrBursts::1 9662 # Per bank write bursts
109system.physmem.perBankWrBursts::2 9792 # Per bank write bursts
110system.physmem.perBankWrBursts::3 9578 # Per bank write bursts
111system.physmem.perBankWrBursts::4 8974 # Per bank write bursts
112system.physmem.perBankWrBursts::5 9217 # Per bank write bursts
113system.physmem.perBankWrBursts::6 9112 # Per bank write bursts
114system.physmem.perBankWrBursts::7 9138 # Per bank write bursts
115system.physmem.perBankWrBursts::8 9280 # Per bank write bursts
116system.physmem.perBankWrBursts::9 9864 # Per bank write bursts
117system.physmem.perBankWrBursts::10 9143 # Per bank write bursts
118system.physmem.perBankWrBursts::11 8671 # Per bank write bursts
119system.physmem.perBankWrBursts::12 8940 # Per bank write bursts
120system.physmem.perBankWrBursts::13 8704 # Per bank write bursts
121system.physmem.perBankWrBursts::14 8686 # Per bank write bursts
122system.physmem.perBankWrBursts::15 8539 # Per bank write bursts
123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
124system.physmem.numWrRetry 53 # Number of times write queue was full causing retry
125system.physmem.totGap 2868577154000 # Total gap between requests
126system.physmem.readPktSize::0 0 # Read request sizes (log2)
127system.physmem.readPktSize::1 0 # Read request sizes (log2)
128system.physmem.readPktSize::2 9731 # Read request sizes (log2)
129system.physmem.readPktSize::3 28 # Read request sizes (log2)
130system.physmem.readPktSize::4 0 # Read request sizes (log2)
131system.physmem.readPktSize::5 0 # Read request sizes (log2)
132system.physmem.readPktSize::6 183581 # Read request sizes (log2)
133system.physmem.writePktSize::0 0 # Write request sizes (log2)
134system.physmem.writePktSize::1 0 # Write request sizes (log2)
135system.physmem.writePktSize::2 4391 # Write request sizes (log2)
136system.physmem.writePktSize::3 0 # Write request sizes (log2)
137system.physmem.writePktSize::4 0 # Write request sizes (log2)
138system.physmem.writePktSize::5 0 # Write request sizes (log2)
139system.physmem.writePktSize::6 165803 # Write request sizes (log2)
140system.physmem.rdQLenPdf::0 135144 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::1 15528 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::2 9961 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::3 8501 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::4 6878 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::5 5365 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::6 4499 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::7 3767 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::8 3282 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::9 113 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::10 82 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::11 47 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::15 5 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
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179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::15 2106 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::16 2367 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::17 3673 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::18 4967 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::19 5739 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::20 5829 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::21 6232 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::22 6545 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::23 7847 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::24 7109 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::25 7142 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::26 8375 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::27 7656 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::28 7408 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::29 10358 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::30 8249 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::31 7648 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::32 7201 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::33 1472 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::34 1047 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::35 1246 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::36 2370 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::37 2353 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::38 1813 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::39 1702 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::40 2465 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::41 1821 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::42 1905 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::43 1828 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::44 2038 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::45 1552 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::46 1283 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::47 1283 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::48 985 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::49 718 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::50 373 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::51 292 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::52 264 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::53 230 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::54 179 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::55 209 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::56 174 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::57 171 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::58 149 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::61 101 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::63 90 # What write queue length does an incoming req see
236system.physmem.bytesPerActivate::samples 83936 # Bytes accessed per row activation
237system.physmem.bytesPerActivate::mean 259.284788 # Bytes accessed per row activation
238system.physmem.bytesPerActivate::gmean 144.169379 # Bytes accessed per row activation
239system.physmem.bytesPerActivate::stdev 318.901486 # Bytes accessed per row activation
240system.physmem.bytesPerActivate::0-127 42814 51.01% 51.01% # Bytes accessed per row activation
241system.physmem.bytesPerActivate::128-255 16839 20.06% 71.07% # Bytes accessed per row activation
242system.physmem.bytesPerActivate::256-383 5671 6.76% 77.83% # Bytes accessed per row activation
243system.physmem.bytesPerActivate::384-511 3554 4.23% 82.06% # Bytes accessed per row activation
244system.physmem.bytesPerActivate::512-639 2350 2.80% 84.86% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::640-767 1452 1.73% 86.59% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::768-895 1048 1.25% 87.84% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::896-1023 956 1.14% 88.98% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::1024-1151 9252 11.02% 100.00% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::total 83936 # Bytes accessed per row activation
250system.physmem.rdPerTurnAround::samples 6009 # Reads before turning the bus around for writes
251system.physmem.rdPerTurnAround::mean 32.152937 # Reads before turning the bus around for writes
252system.physmem.rdPerTurnAround::stdev 562.980980 # Reads before turning the bus around for writes
253system.physmem.rdPerTurnAround::0-2047 6006 99.95% 99.95% # Reads before turning the bus around for writes
254system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::total 6009 # Reads before turning the bus around for writes
257system.physmem.wrPerTurnAround::samples 6009 # Writes before turning the bus around for reads
258system.physmem.wrPerTurnAround::mean 24.437510 # Writes before turning the bus around for reads
259system.physmem.wrPerTurnAround::gmean 18.815074 # Writes before turning the bus around for reads
260system.physmem.wrPerTurnAround::stdev 42.361816 # Writes before turning the bus around for reads
261system.physmem.wrPerTurnAround::16-31 5653 94.08% 94.08% # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::32-47 88 1.46% 95.54% # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::48-63 21 0.35% 95.89% # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::64-79 11 0.18% 96.07% # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::80-95 30 0.50% 96.57% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::96-111 35 0.58% 97.15% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::112-127 32 0.53% 97.69% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::128-143 15 0.25% 97.94% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::144-159 11 0.18% 98.12% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::160-175 9 0.15% 98.27% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::176-191 22 0.37% 98.64% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::192-207 19 0.32% 98.95% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::208-223 8 0.13% 99.08% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::224-239 2 0.03% 99.12% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::240-255 4 0.07% 99.18% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::256-271 3 0.05% 99.23% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::272-287 3 0.05% 99.28% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::288-303 2 0.03% 99.32% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::304-319 5 0.08% 99.40% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::320-335 5 0.08% 99.48% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::336-351 6 0.10% 99.58% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::352-367 6 0.10% 99.68% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::368-383 1 0.02% 99.70% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::416-431 1 0.02% 99.75% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::432-447 2 0.03% 99.78% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::480-495 1 0.02% 99.80% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::496-511 4 0.07% 99.87% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::512-527 2 0.03% 99.90% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::528-543 2 0.03% 99.93% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::656-671 1 0.02% 99.95% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::total 6009 # Writes before turning the bus around for reads
295system.physmem.totQLat 4585121898 # Total ticks spent queuing
296system.physmem.totMemAccLat 8207771898 # Total ticks spent from burst creation until serviced by the DRAM
297system.physmem.totBusLat 966040000 # Total ticks spent in databus transfers
298system.physmem.avgQLat 23731.53 # Average queueing delay per DRAM burst
299system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
300system.physmem.avgMemAccLat 42481.53 # Average memory access latency per DRAM burst
301system.physmem.avgRdBW 4.31 # Average DRAM read bandwidth in MiByte/s
302system.physmem.avgWrBW 3.28 # Average achieved write bandwidth in MiByte/s
303system.physmem.avgRdBWSys 4.11 # Average system read bandwidth in MiByte/s
304system.physmem.avgWrBWSys 3.71 # Average system write bandwidth in MiByte/s
305system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
306system.physmem.busUtil 0.06 # Data bus utilization in percentage
307system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
308system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
309system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
310system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing
311system.physmem.readRowHits 161661 # Number of row buffer hits during reads
312system.physmem.writeRowHits 94455 # Number of row buffer hits during writes
313system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads
314system.physmem.writeRowHitRate 64.31 # Row buffer hit rate for writes
315system.physmem.avgGap 7890808.44 # Average gap between requests
316system.physmem.pageHitRate 75.31 # Row buffer hit rate, read and write combined
317system.physmem_0.actEnergy 329026320 # Energy for activate commands per rank (pJ)
318system.physmem_0.preEnergy 179528250 # Energy for precharge commands per rank (pJ)
319system.physmem_0.readEnergy 798891600 # Energy for read commands per rank (pJ)
320system.physmem_0.writeEnergy 486116640 # Energy for write commands per rank (pJ)
321system.physmem_0.refreshEnergy 187361132400 # Energy for refresh commands per rank (pJ)
322system.physmem_0.actBackEnergy 84057386715 # Energy for active background per rank (pJ)
323system.physmem_0.preBackEnergy 1647408374250 # Energy for precharge background per rank (pJ)
324system.physmem_0.totalEnergy 1920620456175 # Total energy per rank (pJ)
325system.physmem_0.averagePower 669.538978 # Core power per rank (mW)
326system.physmem_0.memoryStateTime::IDLE 2740481725360 # Time in different power states
327system.physmem_0.memoryStateTime::REF 95787900000 # Time in different power states
328system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
329system.physmem_0.memoryStateTime::ACT 32307893640 # Time in different power states
330system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
331system.physmem_1.actEnergy 305529840 # Energy for activate commands per rank (pJ)
332system.physmem_1.preEnergy 166707750 # Energy for precharge commands per rank (pJ)
333system.physmem_1.readEnergy 708123000 # Energy for read commands per rank (pJ)
334system.physmem_1.writeEnergy 465438960 # Energy for write commands per rank (pJ)
335system.physmem_1.refreshEnergy 187361132400 # Energy for refresh commands per rank (pJ)
336system.physmem_1.actBackEnergy 82818901260 # Energy for active background per rank (pJ)
337system.physmem_1.preBackEnergy 1648494765000 # Energy for precharge background per rank (pJ)
338system.physmem_1.totalEnergy 1920320598210 # Total energy per rank (pJ)
339system.physmem_1.averagePower 669.434445 # Core power per rank (mW)
340system.physmem_1.memoryStateTime::IDLE 2742293590423 # Time in different power states
341system.physmem_1.memoryStateTime::REF 95787900000 # Time in different power states
342system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
343system.physmem_1.memoryStateTime::ACT 30490063327 # Time in different power states
344system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
345system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
346system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
347system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
348system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
349system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
350system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
351system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory

--- 39 unchanged lines hidden (view full) ---

391system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
392system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
393system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
394system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
395system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
396system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
397system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
398system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
399system.cpu0.dtb.walker.walks 7618 # Table walker walks requested
400system.cpu0.dtb.walker.walksShort 7618 # Table walker walks initiated with short descriptors
401system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1341 # Level at which table walker walks with short descriptors terminate
402system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6277 # Level at which table walker walks with short descriptors terminate
403system.cpu0.dtb.walker.walkWaitTime::samples 7618 # Table walker wait (enqueue to first request) latency
404system.cpu0.dtb.walker.walkWaitTime::0 7618 100.00% 100.00% # Table walker wait (enqueue to first request) latency
405system.cpu0.dtb.walker.walkWaitTime::total 7618 # Table walker wait (enqueue to first request) latency
406system.cpu0.dtb.walker.walkCompletionTime::samples 6224 # Table walker service (enqueue to completion) latency
407system.cpu0.dtb.walker.walkCompletionTime::mean 9157.575514 # Table walker service (enqueue to completion) latency
408system.cpu0.dtb.walker.walkCompletionTime::gmean 8041.236075 # Table walker service (enqueue to completion) latency
409system.cpu0.dtb.walker.walkCompletionTime::stdev 5531.388532 # Table walker service (enqueue to completion) latency
410system.cpu0.dtb.walker.walkCompletionTime::0-16383 6077 97.64% 97.64% # Table walker service (enqueue to completion) latency
411system.cpu0.dtb.walker.walkCompletionTime::16384-32767 137 2.20% 99.84% # Table walker service (enqueue to completion) latency
412system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.10% 99.94% # Table walker service (enqueue to completion) latency
413system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.95% # Table walker service (enqueue to completion) latency
414system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency
415system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
416system.cpu0.dtb.walker.walkCompletionTime::total 6224 # Table walker service (enqueue to completion) latency
417system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution
418system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution
419system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution
420system.cpu0.dtb.walker.walkPageSizes::4K 4922 79.08% 79.08% # Table walker page sizes translated
421system.cpu0.dtb.walker.walkPageSizes::1M 1302 20.92% 100.00% # Table walker page sizes translated
422system.cpu0.dtb.walker.walkPageSizes::total 6224 # Table walker page sizes translated
423system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7618 # Table walker requests started/completed, data/inst
424system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
425system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7618 # Table walker requests started/completed, data/inst
426system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6224 # Table walker requests started/completed, data/inst
427system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
428system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6224 # Table walker requests started/completed, data/inst
429system.cpu0.dtb.walker.walkRequestOrigin::total 13842 # Table walker requests started/completed, data/inst
430system.cpu0.dtb.inst_hits 0 # ITB inst hits
431system.cpu0.dtb.inst_misses 0 # ITB inst misses
432system.cpu0.dtb.read_hits 25125547 # DTB read hits
433system.cpu0.dtb.read_misses 6527 # DTB read misses
434system.cpu0.dtb.write_hits 18731781 # DTB write hits
435system.cpu0.dtb.write_misses 1091 # DTB write misses
436system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
437system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
438system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
439system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
440system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB
441system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
442system.cpu0.dtb.prefetch_faults 1741 # Number of TLB faults due to prefetch
443system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
444system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
445system.cpu0.dtb.read_accesses 25132074 # DTB read accesses
446system.cpu0.dtb.write_accesses 18732872 # DTB write accesses
447system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
448system.cpu0.dtb.hits 43857328 # DTB hits
449system.cpu0.dtb.misses 7618 # DTB misses
450system.cpu0.dtb.accesses 43864946 # DTB accesses
451system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
455system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
456system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
457system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
458system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 21 unchanged lines hidden (view full) ---

480system.cpu0.itb.walker.walks 3348 # Table walker walks requested
481system.cpu0.itb.walker.walksShort 3348 # Table walker walks initiated with short descriptors
482system.cpu0.itb.walker.walksShortTerminationLevel::Level1 298 # Level at which table walker walks with short descriptors terminate
483system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate
484system.cpu0.itb.walker.walkWaitTime::samples 3348 # Table walker wait (enqueue to first request) latency
485system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency
486system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency
487system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency
488system.cpu0.itb.walker.walkCompletionTime::mean 9422.169811 # Table walker service (enqueue to completion) latency
489system.cpu0.itb.walker.walkCompletionTime::gmean 8126.335555 # Table walker service (enqueue to completion) latency
490system.cpu0.itb.walker.walkCompletionTime::stdev 5925.919906 # Table walker service (enqueue to completion) latency
491system.cpu0.itb.walker.walkCompletionTime::0-8191 980 42.02% 42.02% # Table walker service (enqueue to completion) latency
492system.cpu0.itb.walker.walkCompletionTime::8192-16383 1299 55.70% 97.73% # Table walker service (enqueue to completion) latency
493system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.86% # Table walker service (enqueue to completion) latency
494system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.93% 99.79% # Table walker service (enqueue to completion) latency
495system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.13% 99.91% # Table walker service (enqueue to completion) latency
496system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
497system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
498system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency
499system.cpu0.itb.walker.walksPending::samples 1120687000 # Table walker pending requests distribution
500system.cpu0.itb.walker.walksPending::0 1120687000 100.00% 100.00% # Table walker pending requests distribution
501system.cpu0.itb.walker.walksPending::total 1120687000 # Table walker pending requests distribution
502system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated
503system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated
504system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated
505system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
506system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3348 # Table walker requests started/completed, data/inst
507system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3348 # Table walker requests started/completed, data/inst
508system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
509system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst
510system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst
511system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst
512system.cpu0.itb.inst_hits 118901491 # ITB inst hits
513system.cpu0.itb.inst_misses 3348 # ITB inst misses
514system.cpu0.itb.read_hits 0 # DTB read hits
515system.cpu0.itb.read_misses 0 # DTB read misses
516system.cpu0.itb.write_hits 0 # DTB write hits
517system.cpu0.itb.write_misses 0 # DTB write misses
518system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
519system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
520system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
521system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
522system.cpu0.itb.flush_entries 2150 # Number of entries that have been flushed from TLB
523system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
524system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
525system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
526system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
527system.cpu0.itb.read_accesses 0 # DTB read accesses
528system.cpu0.itb.write_accesses 0 # DTB write accesses
529system.cpu0.itb.inst_accesses 118904839 # ITB inst accesses
530system.cpu0.itb.hits 118901491 # DTB hits
531system.cpu0.itb.misses 3348 # DTB misses
532system.cpu0.itb.accesses 118904839 # DTB accesses
533system.cpu0.numCycles 5737155227 # number of cpu cycles simulated
534system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
535system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
536system.cpu0.committedInsts 115236645 # Number of instructions committed
537system.cpu0.committedOps 139243080 # Number of ops (including micro ops) committed
538system.cpu0.num_int_alu_accesses 123236123 # Number of integer alu accesses
539system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses
540system.cpu0.num_func_calls 12671679 # number of times a function call or return occured
541system.cpu0.num_conditional_control_insts 15683932 # number of instructions that are conditional controls
542system.cpu0.num_int_insts 123236123 # number of integer instructions
543system.cpu0.num_fp_insts 9820 # number of float instructions
544system.cpu0.num_int_register_reads 226877119 # number of times the integer registers were read
545system.cpu0.num_int_register_writes 85629478 # number of times the integer registers were written
546system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read
547system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
548system.cpu0.num_cc_register_reads 504430555 # number of times the CC registers were read
549system.cpu0.num_cc_register_writes 52228186 # number of times the CC registers were written
550system.cpu0.num_mem_refs 44991026 # number of memory refs
551system.cpu0.num_load_insts 25375377 # Number of load instructions
552system.cpu0.num_store_insts 19615649 # Number of store instructions
553system.cpu0.num_idle_cycles 5465784255.910094 # Number of idle cycles
554system.cpu0.num_busy_cycles 271370971.089905 # Number of busy cycles
555system.cpu0.not_idle_fraction 0.047301 # Percentage of non-idle cycles
556system.cpu0.idle_fraction 0.952699 # Percentage of idle cycles
557system.cpu0.Branches 29094451 # Number of branches fetched
558system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
559system.cpu0.op_class::IntAlu 97895605 68.46% 68.46% # Class of executed instruction
560system.cpu0.op_class::IntMult 108367 0.08% 68.53% # Class of executed instruction
561system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction
562system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction
563system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction
564system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction
565system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
566system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction
567system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction
568system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction
569system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction
570system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction
571system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction
572system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction
573system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction
574system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction
575system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction
576system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction
577system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction
578system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction
579system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction
580system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction
581system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction
582system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction
583system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction
584system.cpu0.op_class::SimdFloatMisc 8067 0.01% 68.54% # Class of executed instruction
585system.cpu0.op_class::SimdFloatMult 0 0.00% 68.54% # Class of executed instruction
586system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.54% # Class of executed instruction
587system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.54% # Class of executed instruction
588system.cpu0.op_class::MemRead 25375377 17.74% 86.28% # Class of executed instruction
589system.cpu0.op_class::MemWrite 19615649 13.72% 100.00% # Class of executed instruction
590system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
591system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
592system.cpu0.op_class::total 143005338 # Class of executed instruction
593system.cpu0.kern.inst.arm 0 # number of arm instructions executed
594system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed
595system.cpu0.dcache.tags.replacements 691902 # number of replacements
596system.cpu0.dcache.tags.tagsinuse 493.788529 # Cycle average of tags in use
597system.cpu0.dcache.tags.total_refs 42987184 # Total number of references to valid blocks.
598system.cpu0.dcache.tags.sampled_refs 692414 # Sample count of references to valid blocks.
599system.cpu0.dcache.tags.avg_refs 62.083066 # Average number of references to valid blocks.
600system.cpu0.dcache.tags.warmup_cycle 1147014500 # Cycle when the warmup percentage was hit.
601system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.788529 # Average occupied blocks per requestor
602system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964431 # Average percentage of cache occupancy
603system.cpu0.dcache.tags.occ_percent::total 0.964431 # Average percentage of cache occupancy
604system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
605system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
606system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id
607system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
608system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
609system.cpu0.dcache.tags.tag_accesses 88350780 # Number of tag accesses
610system.cpu0.dcache.tags.data_accesses 88350780 # Number of data accesses
611system.cpu0.dcache.ReadReq_hits::cpu0.data 23864345 # number of ReadReq hits
612system.cpu0.dcache.ReadReq_hits::total 23864345 # number of ReadReq hits
613system.cpu0.dcache.WriteReq_hits::cpu0.data 18002045 # number of WriteReq hits
614system.cpu0.dcache.WriteReq_hits::total 18002045 # number of WriteReq hits
615system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319294 # number of SoftPFReq hits
616system.cpu0.dcache.SoftPFReq_hits::total 319294 # number of SoftPFReq hits
617system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365178 # number of LoadLockedReq hits
618system.cpu0.dcache.LoadLockedReq_hits::total 365178 # number of LoadLockedReq hits
619system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362317 # number of StoreCondReq hits
620system.cpu0.dcache.StoreCondReq_hits::total 362317 # number of StoreCondReq hits
621system.cpu0.dcache.demand_hits::cpu0.data 41866390 # number of demand (read+write) hits
622system.cpu0.dcache.demand_hits::total 41866390 # number of demand (read+write) hits
623system.cpu0.dcache.overall_hits::cpu0.data 42185684 # number of overall hits
624system.cpu0.dcache.overall_hits::total 42185684 # number of overall hits
625system.cpu0.dcache.ReadReq_misses::cpu0.data 396651 # number of ReadReq misses
626system.cpu0.dcache.ReadReq_misses::total 396651 # number of ReadReq misses
627system.cpu0.dcache.WriteReq_misses::cpu0.data 323350 # number of WriteReq misses
628system.cpu0.dcache.WriteReq_misses::total 323350 # number of WriteReq misses
629system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127092 # number of SoftPFReq misses
630system.cpu0.dcache.SoftPFReq_misses::total 127092 # number of SoftPFReq misses
631system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21763 # number of LoadLockedReq misses
632system.cpu0.dcache.LoadLockedReq_misses::total 21763 # number of LoadLockedReq misses
633system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19681 # number of StoreCondReq misses
634system.cpu0.dcache.StoreCondReq_misses::total 19681 # number of StoreCondReq misses
635system.cpu0.dcache.demand_misses::cpu0.data 720001 # number of demand (read+write) misses
636system.cpu0.dcache.demand_misses::total 720001 # number of demand (read+write) misses
637system.cpu0.dcache.overall_misses::cpu0.data 847093 # number of overall misses
638system.cpu0.dcache.overall_misses::total 847093 # number of overall misses
639system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5048891005 # number of ReadReq miss cycles
640system.cpu0.dcache.ReadReq_miss_latency::total 5048891005 # number of ReadReq miss cycles
641system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5105410053 # number of WriteReq miss cycles
642system.cpu0.dcache.WriteReq_miss_latency::total 5105410053 # number of WriteReq miss cycles
643system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330377500 # number of LoadLockedReq miss cycles
644system.cpu0.dcache.LoadLockedReq_miss_latency::total 330377500 # number of LoadLockedReq miss cycles
645system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 436252524 # number of StoreCondReq miss cycles
646system.cpu0.dcache.StoreCondReq_miss_latency::total 436252524 # number of StoreCondReq miss cycles
647system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1279500 # number of StoreCondFailReq miss cycles
648system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1279500 # number of StoreCondFailReq miss cycles
649system.cpu0.dcache.demand_miss_latency::cpu0.data 10154301058 # number of demand (read+write) miss cycles
650system.cpu0.dcache.demand_miss_latency::total 10154301058 # number of demand (read+write) miss cycles
651system.cpu0.dcache.overall_miss_latency::cpu0.data 10154301058 # number of overall miss cycles
652system.cpu0.dcache.overall_miss_latency::total 10154301058 # number of overall miss cycles
653system.cpu0.dcache.ReadReq_accesses::cpu0.data 24260996 # number of ReadReq accesses(hits+misses)
654system.cpu0.dcache.ReadReq_accesses::total 24260996 # number of ReadReq accesses(hits+misses)
655system.cpu0.dcache.WriteReq_accesses::cpu0.data 18325395 # number of WriteReq accesses(hits+misses)
656system.cpu0.dcache.WriteReq_accesses::total 18325395 # number of WriteReq accesses(hits+misses)
657system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446386 # number of SoftPFReq accesses(hits+misses)
658system.cpu0.dcache.SoftPFReq_accesses::total 446386 # number of SoftPFReq accesses(hits+misses)
659system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386941 # number of LoadLockedReq accesses(hits+misses)
660system.cpu0.dcache.LoadLockedReq_accesses::total 386941 # number of LoadLockedReq accesses(hits+misses)
661system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381998 # number of StoreCondReq accesses(hits+misses)
662system.cpu0.dcache.StoreCondReq_accesses::total 381998 # number of StoreCondReq accesses(hits+misses)
663system.cpu0.dcache.demand_accesses::cpu0.data 42586391 # number of demand (read+write) accesses
664system.cpu0.dcache.demand_accesses::total 42586391 # number of demand (read+write) accesses
665system.cpu0.dcache.overall_accesses::cpu0.data 43032777 # number of overall (read+write) accesses
666system.cpu0.dcache.overall_accesses::total 43032777 # number of overall (read+write) accesses
667system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016349 # miss rate for ReadReq accesses
668system.cpu0.dcache.ReadReq_miss_rate::total 0.016349 # miss rate for ReadReq accesses
669system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017645 # miss rate for WriteReq accesses
670system.cpu0.dcache.WriteReq_miss_rate::total 0.017645 # miss rate for WriteReq accesses
671system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.284713 # miss rate for SoftPFReq accesses
672system.cpu0.dcache.SoftPFReq_miss_rate::total 0.284713 # miss rate for SoftPFReq accesses
673system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056244 # miss rate for LoadLockedReq accesses
674system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056244 # miss rate for LoadLockedReq accesses
675system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051521 # miss rate for StoreCondReq accesses
676system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051521 # miss rate for StoreCondReq accesses
677system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016907 # miss rate for demand accesses
678system.cpu0.dcache.demand_miss_rate::total 0.016907 # miss rate for demand accesses
679system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019685 # miss rate for overall accesses
680system.cpu0.dcache.overall_miss_rate::total 0.019685 # miss rate for overall accesses
681system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12728.799385 # average ReadReq miss latency
682system.cpu0.dcache.ReadReq_avg_miss_latency::total 12728.799385 # average ReadReq miss latency
683system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15789.114127 # average WriteReq miss latency
684system.cpu0.dcache.WriteReq_avg_miss_latency::total 15789.114127 # average WriteReq miss latency
685system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15180.696595 # average LoadLockedReq miss latency
686system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15180.696595 # average LoadLockedReq miss latency
687system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22166.176719 # average StoreCondReq miss latency
688system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22166.176719 # average StoreCondReq miss latency
689system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
690system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
691system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14103.176326 # average overall miss latency
692system.cpu0.dcache.demand_avg_miss_latency::total 14103.176326 # average overall miss latency
693system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11987.232875 # average overall miss latency
694system.cpu0.dcache.overall_avg_miss_latency::total 11987.232875 # average overall miss latency
695system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
696system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
697system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
698system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
699system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
700system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
701system.cpu0.dcache.fast_writes 0 # number of fast writes performed
702system.cpu0.dcache.cache_copies 0 # number of cache copies performed
703system.cpu0.dcache.writebacks::writebacks 505765 # number of writebacks
704system.cpu0.dcache.writebacks::total 505765 # number of writebacks
705system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25164 # number of ReadReq MSHR hits
706system.cpu0.dcache.ReadReq_mshr_hits::total 25164 # number of ReadReq MSHR hits
707system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15036 # number of LoadLockedReq MSHR hits
708system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15036 # number of LoadLockedReq MSHR hits
709system.cpu0.dcache.demand_mshr_hits::cpu0.data 25164 # number of demand (read+write) MSHR hits
710system.cpu0.dcache.demand_mshr_hits::total 25164 # number of demand (read+write) MSHR hits
711system.cpu0.dcache.overall_mshr_hits::cpu0.data 25164 # number of overall MSHR hits
712system.cpu0.dcache.overall_mshr_hits::total 25164 # number of overall MSHR hits
713system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371487 # number of ReadReq MSHR misses
714system.cpu0.dcache.ReadReq_mshr_misses::total 371487 # number of ReadReq MSHR misses
715system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323350 # number of WriteReq MSHR misses
716system.cpu0.dcache.WriteReq_mshr_misses::total 323350 # number of WriteReq MSHR misses
717system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100065 # number of SoftPFReq MSHR misses
718system.cpu0.dcache.SoftPFReq_mshr_misses::total 100065 # number of SoftPFReq MSHR misses
719system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6727 # number of LoadLockedReq MSHR misses
720system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6727 # number of LoadLockedReq MSHR misses
721system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19681 # number of StoreCondReq MSHR misses
722system.cpu0.dcache.StoreCondReq_mshr_misses::total 19681 # number of StoreCondReq MSHR misses
723system.cpu0.dcache.demand_mshr_misses::cpu0.data 694837 # number of demand (read+write) MSHR misses
724system.cpu0.dcache.demand_mshr_misses::total 694837 # number of demand (read+write) MSHR misses
725system.cpu0.dcache.overall_mshr_misses::cpu0.data 794902 # number of overall MSHR misses
726system.cpu0.dcache.overall_mshr_misses::total 794902 # number of overall MSHR misses
727system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31775 # number of ReadReq MSHR uncacheable
728system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31775 # number of ReadReq MSHR uncacheable
729system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28452 # number of WriteReq MSHR uncacheable
730system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28452 # number of WriteReq MSHR uncacheable
731system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60227 # number of overall MSHR uncacheable misses
732system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60227 # number of overall MSHR uncacheable misses
733system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4098614569 # number of ReadReq MSHR miss cycles
734system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4098614569 # number of ReadReq MSHR miss cycles
735system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4609386947 # number of WriteReq MSHR miss cycles
736system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4609386947 # number of WriteReq MSHR miss cycles
737system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1545410442 # number of SoftPFReq MSHR miss cycles
738system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1545410442 # number of SoftPFReq MSHR miss cycles
739system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97646500 # number of LoadLockedReq MSHR miss cycles
740system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97646500 # number of LoadLockedReq MSHR miss cycles
741system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 406311476 # number of StoreCondReq MSHR miss cycles
742system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 406311476 # number of StoreCondReq MSHR miss cycles
743system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1224000 # number of StoreCondFailReq MSHR miss cycles
744system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1224000 # number of StoreCondFailReq MSHR miss cycles
745system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8708001516 # number of demand (read+write) MSHR miss cycles
746system.cpu0.dcache.demand_mshr_miss_latency::total 8708001516 # number of demand (read+write) MSHR miss cycles
747system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10253411958 # number of overall MSHR miss cycles
748system.cpu0.dcache.overall_mshr_miss_latency::total 10253411958 # number of overall MSHR miss cycles
749system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6180823750 # number of ReadReq MSHR uncacheable cycles
750system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6180823750 # number of ReadReq MSHR uncacheable cycles
751system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4817819000 # number of WriteReq MSHR uncacheable cycles
752system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4817819000 # number of WriteReq MSHR uncacheable cycles
753system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10998642750 # number of overall MSHR uncacheable cycles
754system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10998642750 # number of overall MSHR uncacheable cycles
755system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015312 # mshr miss rate for ReadReq accesses
756system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015312 # mshr miss rate for ReadReq accesses
757system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017645 # mshr miss rate for WriteReq accesses
758system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017645 # mshr miss rate for WriteReq accesses
759system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224167 # mshr miss rate for SoftPFReq accesses
760system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224167 # mshr miss rate for SoftPFReq accesses
761system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017385 # mshr miss rate for LoadLockedReq accesses
762system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017385 # mshr miss rate for LoadLockedReq accesses
763system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051521 # mshr miss rate for StoreCondReq accesses
764system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051521 # mshr miss rate for StoreCondReq accesses
765system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016316 # mshr miss rate for demand accesses
766system.cpu0.dcache.demand_mshr_miss_rate::total 0.016316 # mshr miss rate for demand accesses
767system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018472 # mshr miss rate for overall accesses
768system.cpu0.dcache.overall_mshr_miss_rate::total 0.018472 # mshr miss rate for overall accesses
769system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11032.995957 # average ReadReq mshr miss latency
770system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11032.995957 # average ReadReq mshr miss latency
771system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14255.101120 # average WriteReq mshr miss latency
772system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14255.101120 # average WriteReq mshr miss latency
773system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15444.065777 # average SoftPFReq mshr miss latency
774system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15444.065777 # average SoftPFReq mshr miss latency
775system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14515.608741 # average LoadLockedReq mshr miss latency
776system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14515.608741 # average LoadLockedReq mshr miss latency
777system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20644.859306 # average StoreCondReq mshr miss latency
778system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20644.859306 # average StoreCondReq mshr miss latency
779system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
780system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
781system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12532.437847 # average overall mshr miss latency
782system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12532.437847 # average overall mshr miss latency
783system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12898.963593 # average overall mshr miss latency
784system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12898.963593 # average overall mshr miss latency
785system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194518.450039 # average ReadReq mshr uncacheable latency
786system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194518.450039 # average ReadReq mshr uncacheable latency
787system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169331.470547 # average WriteReq mshr uncacheable latency
788system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169331.470547 # average WriteReq mshr uncacheable latency
789system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 182619.800920 # average overall mshr uncacheable latency
790system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 182619.800920 # average overall mshr uncacheable latency
791system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
792system.cpu0.icache.tags.replacements 1099684 # number of replacements
793system.cpu0.icache.tags.tagsinuse 511.454126 # Cycle average of tags in use
794system.cpu0.icache.tags.total_refs 117801286 # Total number of references to valid blocks.
795system.cpu0.icache.tags.sampled_refs 1100196 # Sample count of references to valid blocks.
796system.cpu0.icache.tags.avg_refs 107.073000 # Average number of references to valid blocks.
797system.cpu0.icache.tags.warmup_cycle 13491746250 # Cycle when the warmup percentage was hit.
798system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.454126 # Average occupied blocks per requestor
799system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998934 # Average percentage of cache occupancy
800system.cpu0.icache.tags.occ_percent::total 0.998934 # Average percentage of cache occupancy
801system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
802system.cpu0.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
803system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
804system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id
805system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
806system.cpu0.icache.tags.tag_accesses 238903187 # Number of tag accesses
807system.cpu0.icache.tags.data_accesses 238903187 # Number of data accesses
808system.cpu0.icache.ReadReq_hits::cpu0.inst 117801286 # number of ReadReq hits
809system.cpu0.icache.ReadReq_hits::total 117801286 # number of ReadReq hits
810system.cpu0.icache.demand_hits::cpu0.inst 117801286 # number of demand (read+write) hits
811system.cpu0.icache.demand_hits::total 117801286 # number of demand (read+write) hits
812system.cpu0.icache.overall_hits::cpu0.inst 117801286 # number of overall hits
813system.cpu0.icache.overall_hits::total 117801286 # number of overall hits
814system.cpu0.icache.ReadReq_misses::cpu0.inst 1100205 # number of ReadReq misses
815system.cpu0.icache.ReadReq_misses::total 1100205 # number of ReadReq misses
816system.cpu0.icache.demand_misses::cpu0.inst 1100205 # number of demand (read+write) misses
817system.cpu0.icache.demand_misses::total 1100205 # number of demand (read+write) misses
818system.cpu0.icache.overall_misses::cpu0.inst 1100205 # number of overall misses
819system.cpu0.icache.overall_misses::total 1100205 # number of overall misses
820system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10864366523 # number of ReadReq miss cycles
821system.cpu0.icache.ReadReq_miss_latency::total 10864366523 # number of ReadReq miss cycles
822system.cpu0.icache.demand_miss_latency::cpu0.inst 10864366523 # number of demand (read+write) miss cycles
823system.cpu0.icache.demand_miss_latency::total 10864366523 # number of demand (read+write) miss cycles
824system.cpu0.icache.overall_miss_latency::cpu0.inst 10864366523 # number of overall miss cycles
825system.cpu0.icache.overall_miss_latency::total 10864366523 # number of overall miss cycles
826system.cpu0.icache.ReadReq_accesses::cpu0.inst 118901491 # number of ReadReq accesses(hits+misses)
827system.cpu0.icache.ReadReq_accesses::total 118901491 # number of ReadReq accesses(hits+misses)
828system.cpu0.icache.demand_accesses::cpu0.inst 118901491 # number of demand (read+write) accesses
829system.cpu0.icache.demand_accesses::total 118901491 # number of demand (read+write) accesses
830system.cpu0.icache.overall_accesses::cpu0.inst 118901491 # number of overall (read+write) accesses
831system.cpu0.icache.overall_accesses::total 118901491 # number of overall (read+write) accesses
832system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009253 # miss rate for ReadReq accesses
833system.cpu0.icache.ReadReq_miss_rate::total 0.009253 # miss rate for ReadReq accesses
834system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009253 # miss rate for demand accesses
835system.cpu0.icache.demand_miss_rate::total 0.009253 # miss rate for demand accesses
836system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009253 # miss rate for overall accesses
837system.cpu0.icache.overall_miss_rate::total 0.009253 # miss rate for overall accesses
838system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9874.856525 # average ReadReq miss latency
839system.cpu0.icache.ReadReq_avg_miss_latency::total 9874.856525 # average ReadReq miss latency
840system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9874.856525 # average overall miss latency
841system.cpu0.icache.demand_avg_miss_latency::total 9874.856525 # average overall miss latency
842system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9874.856525 # average overall miss latency
843system.cpu0.icache.overall_avg_miss_latency::total 9874.856525 # average overall miss latency
844system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
845system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
846system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
847system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
848system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
849system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
850system.cpu0.icache.fast_writes 0 # number of fast writes performed
851system.cpu0.icache.cache_copies 0 # number of cache copies performed
852system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100205 # number of ReadReq MSHR misses
853system.cpu0.icache.ReadReq_mshr_misses::total 1100205 # number of ReadReq MSHR misses
854system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100205 # number of demand (read+write) MSHR misses
855system.cpu0.icache.demand_mshr_misses::total 1100205 # number of demand (read+write) MSHR misses
856system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100205 # number of overall MSHR misses
857system.cpu0.icache.overall_mshr_misses::total 1100205 # number of overall MSHR misses
858system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
859system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
860system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
861system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
862system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9757723477 # number of ReadReq MSHR miss cycles
863system.cpu0.icache.ReadReq_mshr_miss_latency::total 9757723477 # number of ReadReq MSHR miss cycles
864system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9757723477 # number of demand (read+write) MSHR miss cycles
865system.cpu0.icache.demand_mshr_miss_latency::total 9757723477 # number of demand (read+write) MSHR miss cycles
866system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9757723477 # number of overall MSHR miss cycles
867system.cpu0.icache.overall_mshr_miss_latency::total 9757723477 # number of overall MSHR miss cycles
868system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 802157500 # number of ReadReq MSHR uncacheable cycles
869system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 802157500 # number of ReadReq MSHR uncacheable cycles
870system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 802157500 # number of overall MSHR uncacheable cycles
871system.cpu0.icache.overall_mshr_uncacheable_latency::total 802157500 # number of overall MSHR uncacheable cycles
872system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009253 # mshr miss rate for ReadReq accesses
873system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009253 # mshr miss rate for ReadReq accesses
874system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009253 # mshr miss rate for demand accesses
875system.cpu0.icache.demand_mshr_miss_rate::total 0.009253 # mshr miss rate for demand accesses
876system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009253 # mshr miss rate for overall accesses
877system.cpu0.icache.overall_mshr_miss_rate::total 0.009253 # mshr miss rate for overall accesses
878system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8869.004846 # average ReadReq mshr miss latency
879system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8869.004846 # average ReadReq mshr miss latency
880system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8869.004846 # average overall mshr miss latency
881system.cpu0.icache.demand_avg_mshr_miss_latency::total 8869.004846 # average overall mshr miss latency
882system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8869.004846 # average overall mshr miss latency
883system.cpu0.icache.overall_avg_mshr_miss_latency::total 8869.004846 # average overall mshr miss latency
884system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88911.272445 # average ReadReq mshr uncacheable latency
885system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88911.272445 # average ReadReq mshr uncacheable latency
886system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88911.272445 # average overall mshr uncacheable latency
887system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88911.272445 # average overall mshr uncacheable latency
888system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
889system.cpu0.l2cache.prefetcher.num_hwpf_issued 1850277 # number of hwpf issued
890system.cpu0.l2cache.prefetcher.pfIdentified 1850277 # number of prefetch candidates identified
891system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
892system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
893system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
894system.cpu0.l2cache.prefetcher.pfSpanPage 235795 # number of prefetches not generated due to page crossing
895system.cpu0.l2cache.tags.replacements 266928 # number of replacements
896system.cpu0.l2cache.tags.tagsinuse 16114.496747 # Cycle average of tags in use
897system.cpu0.l2cache.tags.total_refs 1972101 # Total number of references to valid blocks.
898system.cpu0.l2cache.tags.sampled_refs 283159 # Sample count of references to valid blocks.
899system.cpu0.l2cache.tags.avg_refs 6.964642 # Average number of references to valid blocks.
900system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
901system.cpu0.l2cache.tags.occ_blocks::writebacks 7721.313532 # Average occupied blocks per requestor
902system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.317590 # Average occupied blocks per requestor
903system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.113534 # Average occupied blocks per requestor
904system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4537.329831 # Average occupied blocks per requestor
905system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1964.577716 # Average occupied blocks per requestor
906system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1889.844545 # Average occupied blocks per requestor
907system.cpu0.l2cache.tags.occ_percent::writebacks 0.471272 # Average percentage of cache occupancy
908system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000080 # Average percentage of cache occupancy
909system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy
910system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276937 # Average percentage of cache occupancy
911system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119908 # Average percentage of cache occupancy
912system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.115347 # Average percentage of cache occupancy
913system.cpu0.l2cache.tags.occ_percent::total 0.983551 # Average percentage of cache occupancy
914system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1123 # Occupied blocks per task id
915system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
916system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15100 # Occupied blocks per task id
917system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id
918system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id
919system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 368 # Occupied blocks per task id
920system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 474 # Occupied blocks per task id
921system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
922system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
923system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
924system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
925system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
926system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3254 # Occupied blocks per task id
927system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7638 # Occupied blocks per task id
928system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4052 # Occupied blocks per task id
929system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068542 # Percentage of cache occupancy per task id
930system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id
931system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921631 # Percentage of cache occupancy per task id
932system.cpu0.l2cache.tags.tag_accesses 39669375 # Number of tag accesses
933system.cpu0.l2cache.tags.data_accesses 39669375 # Number of data accesses
934system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7528 # number of ReadReq hits
935system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3363 # number of ReadReq hits
936system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1053127 # number of ReadReq hits
937system.cpu0.l2cache.ReadReq_hits::cpu0.data 384165 # number of ReadReq hits
938system.cpu0.l2cache.ReadReq_hits::total 1448183 # number of ReadReq hits
939system.cpu0.l2cache.Writeback_hits::writebacks 505760 # number of Writeback hits
940system.cpu0.l2cache.Writeback_hits::total 505760 # number of Writeback hits
941system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28149 # number of UpgradeReq hits
942system.cpu0.l2cache.UpgradeReq_hits::total 28149 # number of UpgradeReq hits
943system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1715 # number of SCUpgradeReq hits
944system.cpu0.l2cache.SCUpgradeReq_hits::total 1715 # number of SCUpgradeReq hits
945system.cpu0.l2cache.ReadExReq_hits::cpu0.data 225012 # number of ReadExReq hits
946system.cpu0.l2cache.ReadExReq_hits::total 225012 # number of ReadExReq hits
947system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7528 # number of demand (read+write) hits
948system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3363 # number of demand (read+write) hits
949system.cpu0.l2cache.demand_hits::cpu0.inst 1053127 # number of demand (read+write) hits
950system.cpu0.l2cache.demand_hits::cpu0.data 609177 # number of demand (read+write) hits
951system.cpu0.l2cache.demand_hits::total 1673195 # number of demand (read+write) hits
952system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7528 # number of overall hits
953system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3363 # number of overall hits
954system.cpu0.l2cache.overall_hits::cpu0.inst 1053127 # number of overall hits
955system.cpu0.l2cache.overall_hits::cpu0.data 609177 # number of overall hits
956system.cpu0.l2cache.overall_hits::total 1673195 # number of overall hits
957system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 209 # number of ReadReq misses
958system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses
959system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47078 # number of ReadReq misses
960system.cpu0.l2cache.ReadReq_misses::cpu0.data 94114 # number of ReadReq misses
961system.cpu0.l2cache.ReadReq_misses::total 141524 # number of ReadReq misses
962system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26175 # number of UpgradeReq misses
963system.cpu0.l2cache.UpgradeReq_misses::total 26175 # number of UpgradeReq misses
964system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17961 # number of SCUpgradeReq misses
965system.cpu0.l2cache.SCUpgradeReq_misses::total 17961 # number of SCUpgradeReq misses
966system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
967system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
968system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44014 # number of ReadExReq misses
969system.cpu0.l2cache.ReadExReq_misses::total 44014 # number of ReadExReq misses
970system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 209 # number of demand (read+write) misses
971system.cpu0.l2cache.demand_misses::cpu0.itb.walker 123 # number of demand (read+write) misses
972system.cpu0.l2cache.demand_misses::cpu0.inst 47078 # number of demand (read+write) misses
973system.cpu0.l2cache.demand_misses::cpu0.data 138128 # number of demand (read+write) misses
974system.cpu0.l2cache.demand_misses::total 185538 # number of demand (read+write) misses
975system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 209 # number of overall misses
976system.cpu0.l2cache.overall_misses::cpu0.itb.walker 123 # number of overall misses
977system.cpu0.l2cache.overall_misses::cpu0.inst 47078 # number of overall misses
978system.cpu0.l2cache.overall_misses::cpu0.data 138128 # number of overall misses
979system.cpu0.l2cache.overall_misses::total 185538 # number of overall misses
980system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4805250 # number of ReadReq miss cycles
981system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2807500 # number of ReadReq miss cycles
982system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2358005477 # number of ReadReq miss cycles
983system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2765454494 # number of ReadReq miss cycles
984system.cpu0.l2cache.ReadReq_miss_latency::total 5131072721 # number of ReadReq miss cycles
985system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 482009840 # number of UpgradeReq miss cycles
986system.cpu0.l2cache.UpgradeReq_miss_latency::total 482009840 # number of UpgradeReq miss cycles
987system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365934287 # number of SCUpgradeReq miss cycles
988system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365934287 # number of SCUpgradeReq miss cycles
989system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1185998 # number of SCUpgradeFailReq miss cycles
990system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1185998 # number of SCUpgradeFailReq miss cycles
991system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1958932743 # number of ReadExReq miss cycles
992system.cpu0.l2cache.ReadExReq_miss_latency::total 1958932743 # number of ReadExReq miss cycles
993system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4805250 # number of demand (read+write) miss cycles
994system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2807500 # number of demand (read+write) miss cycles
995system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2358005477 # number of demand (read+write) miss cycles
996system.cpu0.l2cache.demand_miss_latency::cpu0.data 4724387237 # number of demand (read+write) miss cycles
997system.cpu0.l2cache.demand_miss_latency::total 7090005464 # number of demand (read+write) miss cycles
998system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4805250 # number of overall miss cycles
999system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2807500 # number of overall miss cycles
1000system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2358005477 # number of overall miss cycles
1001system.cpu0.l2cache.overall_miss_latency::cpu0.data 4724387237 # number of overall miss cycles
1002system.cpu0.l2cache.overall_miss_latency::total 7090005464 # number of overall miss cycles
1003system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7737 # number of ReadReq accesses(hits+misses)
1004system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3486 # number of ReadReq accesses(hits+misses)
1005system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1100205 # number of ReadReq accesses(hits+misses)
1006system.cpu0.l2cache.ReadReq_accesses::cpu0.data 478279 # number of ReadReq accesses(hits+misses)
1007system.cpu0.l2cache.ReadReq_accesses::total 1589707 # number of ReadReq accesses(hits+misses)
1008system.cpu0.l2cache.Writeback_accesses::writebacks 505760 # number of Writeback accesses(hits+misses)
1009system.cpu0.l2cache.Writeback_accesses::total 505760 # number of Writeback accesses(hits+misses)
1010system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54324 # number of UpgradeReq accesses(hits+misses)
1011system.cpu0.l2cache.UpgradeReq_accesses::total 54324 # number of UpgradeReq accesses(hits+misses)
1012system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19676 # number of SCUpgradeReq accesses(hits+misses)
1013system.cpu0.l2cache.SCUpgradeReq_accesses::total 19676 # number of SCUpgradeReq accesses(hits+misses)
1014system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
1015system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
1016system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269026 # number of ReadExReq accesses(hits+misses)
1017system.cpu0.l2cache.ReadExReq_accesses::total 269026 # number of ReadExReq accesses(hits+misses)
1018system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7737 # number of demand (read+write) accesses
1019system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3486 # number of demand (read+write) accesses
1020system.cpu0.l2cache.demand_accesses::cpu0.inst 1100205 # number of demand (read+write) accesses
1021system.cpu0.l2cache.demand_accesses::cpu0.data 747305 # number of demand (read+write) accesses
1022system.cpu0.l2cache.demand_accesses::total 1858733 # number of demand (read+write) accesses
1023system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7737 # number of overall (read+write) accesses
1024system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3486 # number of overall (read+write) accesses
1025system.cpu0.l2cache.overall_accesses::cpu0.inst 1100205 # number of overall (read+write) accesses
1026system.cpu0.l2cache.overall_accesses::cpu0.data 747305 # number of overall (read+write) accesses
1027system.cpu0.l2cache.overall_accesses::total 1858733 # number of overall (read+write) accesses
1028system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027013 # miss rate for ReadReq accesses
1029system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035284 # miss rate for ReadReq accesses
1030system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042790 # miss rate for ReadReq accesses
1031system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.196776 # miss rate for ReadReq accesses
1032system.cpu0.l2cache.ReadReq_miss_rate::total 0.089025 # miss rate for ReadReq accesses
1033system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.481831 # miss rate for UpgradeReq accesses
1034system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.481831 # miss rate for UpgradeReq accesses
1035system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.912838 # miss rate for SCUpgradeReq accesses
1036system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.912838 # miss rate for SCUpgradeReq accesses
1037system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1038system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1039system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.163605 # miss rate for ReadExReq accesses
1040system.cpu0.l2cache.ReadExReq_miss_rate::total 0.163605 # miss rate for ReadExReq accesses
1041system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027013 # miss rate for demand accesses
1042system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035284 # miss rate for demand accesses
1043system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042790 # miss rate for demand accesses
1044system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.184835 # miss rate for demand accesses
1045system.cpu0.l2cache.demand_miss_rate::total 0.099820 # miss rate for demand accesses
1046system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027013 # miss rate for overall accesses
1047system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035284 # miss rate for overall accesses
1048system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042790 # miss rate for overall accesses
1049system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.184835 # miss rate for overall accesses
1050system.cpu0.l2cache.overall_miss_rate::total 0.099820 # miss rate for overall accesses
1051system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22991.626794 # average ReadReq miss latency
1052system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22825.203252 # average ReadReq miss latency
1053system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 50087.205850 # average ReadReq miss latency
1054system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29384.092632 # average ReadReq miss latency
1055system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36255.848626 # average ReadReq miss latency
1056system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18414.893601 # average UpgradeReq miss latency
1057system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18414.893601 # average UpgradeReq miss latency
1058system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20373.825901 # average SCUpgradeReq miss latency
1059system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20373.825901 # average SCUpgradeReq miss latency
1060system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 237199.600000 # average SCUpgradeFailReq miss latency
1061system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 237199.600000 # average SCUpgradeFailReq miss latency
1062system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44507.037374 # average ReadExReq miss latency
1063system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 44507.037374 # average ReadExReq miss latency
1064system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22991.626794 # average overall miss latency
1065system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22825.203252 # average overall miss latency
1066system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 50087.205850 # average overall miss latency
1067system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34202.965633 # average overall miss latency
1068system.cpu0.l2cache.demand_avg_miss_latency::total 38213.225668 # average overall miss latency
1069system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22991.626794 # average overall miss latency
1070system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22825.203252 # average overall miss latency
1071system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 50087.205850 # average overall miss latency
1072system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34202.965633 # average overall miss latency
1073system.cpu0.l2cache.overall_avg_miss_latency::total 38213.225668 # average overall miss latency
1074system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1075system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1076system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1077system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1078system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1079system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1080system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1081system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1082system.cpu0.l2cache.writebacks::writebacks 194963 # number of writebacks
1083system.cpu0.l2cache.writebacks::total 194963 # number of writebacks
1084system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 34 # number of ReadReq MSHR hits
1085system.cpu0.l2cache.ReadReq_mshr_hits::total 34 # number of ReadReq MSHR hits
1086system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1200 # number of ReadExReq MSHR hits
1087system.cpu0.l2cache.ReadExReq_mshr_hits::total 1200 # number of ReadExReq MSHR hits
1088system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1234 # number of demand (read+write) MSHR hits
1089system.cpu0.l2cache.demand_mshr_hits::total 1234 # number of demand (read+write) MSHR hits
1090system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1234 # number of overall MSHR hits
1091system.cpu0.l2cache.overall_mshr_hits::total 1234 # number of overall MSHR hits
1092system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 209 # number of ReadReq MSHR misses
1093system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 123 # number of ReadReq MSHR misses
1094system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47078 # number of ReadReq MSHR misses
1095system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94080 # number of ReadReq MSHR misses
1096system.cpu0.l2cache.ReadReq_mshr_misses::total 141490 # number of ReadReq MSHR misses
1097system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 245498 # number of HardPFReq MSHR misses
1098system.cpu0.l2cache.HardPFReq_mshr_misses::total 245498 # number of HardPFReq MSHR misses
1099system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26175 # number of UpgradeReq MSHR misses
1100system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26175 # number of UpgradeReq MSHR misses
1101system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17961 # number of SCUpgradeReq MSHR misses
1102system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17961 # number of SCUpgradeReq MSHR misses
1103system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
1104system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
1105system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42814 # number of ReadExReq MSHR misses
1106system.cpu0.l2cache.ReadExReq_mshr_misses::total 42814 # number of ReadExReq MSHR misses
1107system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 209 # number of demand (read+write) MSHR misses
1108system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 123 # number of demand (read+write) MSHR misses
1109system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47078 # number of demand (read+write) MSHR misses
1110system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136894 # number of demand (read+write) MSHR misses
1111system.cpu0.l2cache.demand_mshr_misses::total 184304 # number of demand (read+write) MSHR misses
1112system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 209 # number of overall MSHR misses
1113system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 123 # number of overall MSHR misses
1114system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47078 # number of overall MSHR misses
1115system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136894 # number of overall MSHR misses
1116system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 245498 # number of overall MSHR misses
1117system.cpu0.l2cache.overall_mshr_misses::total 429802 # number of overall MSHR misses
1118system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
1119system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31775 # number of ReadReq MSHR uncacheable
1120system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40797 # number of ReadReq MSHR uncacheable
1121system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28452 # number of WriteReq MSHR uncacheable
1122system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28452 # number of WriteReq MSHR uncacheable
1123system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
1124system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60227 # number of overall MSHR uncacheable misses
1125system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69249 # number of overall MSHR uncacheable misses
1126system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3446250 # number of ReadReq MSHR miss cycles
1127system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2008000 # number of ReadReq MSHR miss cycles
1128system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2045556523 # number of ReadReq MSHR miss cycles
1129system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2147080077 # number of ReadReq MSHR miss cycles
1130system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4198090850 # number of ReadReq MSHR miss cycles
1131system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13523341666 # number of HardPFReq MSHR miss cycles
1132system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13523341666 # number of HardPFReq MSHR miss cycles
1133system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 511152796 # number of UpgradeReq MSHR miss cycles
1134system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 511152796 # number of UpgradeReq MSHR miss cycles
1135system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 258980524 # number of SCUpgradeReq MSHR miss cycles
1136system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 258980524 # number of SCUpgradeReq MSHR miss cycles
1137system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 945498 # number of SCUpgradeFailReq MSHR miss cycles
1138system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 945498 # number of SCUpgradeFailReq MSHR miss cycles
1139system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1561585422 # number of ReadExReq MSHR miss cycles
1140system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1561585422 # number of ReadExReq MSHR miss cycles
1141system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3446250 # number of demand (read+write) MSHR miss cycles
1142system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2008000 # number of demand (read+write) MSHR miss cycles
1143system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2045556523 # number of demand (read+write) MSHR miss cycles
1144system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3708665499 # number of demand (read+write) MSHR miss cycles
1145system.cpu0.l2cache.demand_mshr_miss_latency::total 5759676272 # number of demand (read+write) MSHR miss cycles
1146system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3446250 # number of overall MSHR miss cycles
1147system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2008000 # number of overall MSHR miss cycles
1148system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2045556523 # number of overall MSHR miss cycles
1149system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3708665499 # number of overall MSHR miss cycles
1150system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13523341666 # number of overall MSHR miss cycles
1151system.cpu0.l2cache.overall_mshr_miss_latency::total 19283017938 # number of overall MSHR miss cycles
1152system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 730253500 # number of ReadReq MSHR uncacheable cycles
1153system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5926417500 # number of ReadReq MSHR uncacheable cycles
1154system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6656671000 # number of ReadReq MSHR uncacheable cycles
1155system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4604429000 # number of WriteReq MSHR uncacheable cycles
1156system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4604429000 # number of WriteReq MSHR uncacheable cycles
1157system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 730253500 # number of overall MSHR uncacheable cycles
1158system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10530846500 # number of overall MSHR uncacheable cycles
1159system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11261100000 # number of overall MSHR uncacheable cycles
1160system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.027013 # mshr miss rate for ReadReq accesses
1161system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.035284 # mshr miss rate for ReadReq accesses
1162system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042790 # mshr miss rate for ReadReq accesses
1163system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.196705 # mshr miss rate for ReadReq accesses
1164system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089004 # mshr miss rate for ReadReq accesses
1165system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1166system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1167system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.481831 # mshr miss rate for UpgradeReq accesses
1168system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.481831 # mshr miss rate for UpgradeReq accesses
1169system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.912838 # mshr miss rate for SCUpgradeReq accesses
1170system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.912838 # mshr miss rate for SCUpgradeReq accesses
1171system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1172system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1173system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159144 # mshr miss rate for ReadExReq accesses
1174system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159144 # mshr miss rate for ReadExReq accesses
1175system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.027013 # mshr miss rate for demand accesses
1176system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.035284 # mshr miss rate for demand accesses
1177system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042790 # mshr miss rate for demand accesses
1178system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.183184 # mshr miss rate for demand accesses
1179system.cpu0.l2cache.demand_mshr_miss_rate::total 0.099156 # mshr miss rate for demand accesses
1180system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.027013 # mshr miss rate for overall accesses
1181system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.035284 # mshr miss rate for overall accesses
1182system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042790 # mshr miss rate for overall accesses
1183system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.183184 # mshr miss rate for overall accesses
1184system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1185system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231234 # mshr miss rate for overall accesses
1186system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450 # average ReadReq mshr miss latency
1187system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252 # average ReadReq mshr miss latency
1188system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average ReadReq mshr miss latency
1189system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22821.854560 # average ReadReq mshr miss latency
1190system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29670.583433 # average ReadReq mshr miss latency
1191system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530 # average HardPFReq mshr miss latency
1192system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55085.343530 # average HardPFReq mshr miss latency
1193system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19528.282560 # average UpgradeReq mshr miss latency
1194system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19528.282560 # average UpgradeReq mshr miss latency
1195system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14419.048160 # average SCUpgradeReq mshr miss latency
1196system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14419.048160 # average SCUpgradeReq mshr miss latency
1197system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 189099.600000 # average SCUpgradeFailReq mshr miss latency
1198system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 189099.600000 # average SCUpgradeFailReq mshr miss latency
1199system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36473.710048 # average ReadExReq mshr miss latency
1200system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36473.710048 # average ReadExReq mshr miss latency
1201system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450 # average overall mshr miss latency
1202system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252 # average overall mshr miss latency
1203system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average overall mshr miss latency
1204system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27091.512404 # average overall mshr miss latency
1205system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31250.956420 # average overall mshr miss latency
1206system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16489.234450 # average overall mshr miss latency
1207system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16325.203252 # average overall mshr miss latency
1208system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average overall mshr miss latency
1209system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27091.512404 # average overall mshr miss latency
1210system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55085.343530 # average overall mshr miss latency
1211system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44864.886478 # average overall mshr miss latency
1212system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971 # average ReadReq mshr uncacheable latency
1213system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186511.959087 # average ReadReq mshr uncacheable latency
1214system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163165.698458 # average ReadReq mshr uncacheable latency
1215system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161831.470547 # average WriteReq mshr uncacheable latency
1216system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161831.470547 # average WriteReq mshr uncacheable latency
1217system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80941.420971 # average overall mshr uncacheable latency
1218system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 174852.582729 # average overall mshr uncacheable latency
1219system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 162617.510722 # average overall mshr uncacheable latency
1220system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1221system.cpu0.toL2Bus.trans_dist::ReadReq 1738254 # Transaction distribution
1222system.cpu0.toL2Bus.trans_dist::ReadResp 1687491 # Transaction distribution
1223system.cpu0.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution
1224system.cpu0.toL2Bus.trans_dist::WriteResp 28452 # Transaction distribution
1225system.cpu0.toL2Bus.trans_dist::Writeback 505760 # Transaction distribution
1226system.cpu0.toL2Bus.trans_dist::HardPFReq 309559 # Transaction distribution
1227system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution
1228system.cpu0.toL2Bus.trans_dist::UpgradeReq 88185 # Transaction distribution
1229system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42256 # Transaction distribution
1230system.cpu0.toL2Bus.trans_dist::UpgradeResp 111549 # Transaction distribution
1231system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution
1232system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
1233system.cpu0.toL2Bus.trans_dist::ReadExReq 297072 # Transaction distribution
1234system.cpu0.toL2Bus.trans_dist::ReadExResp 284592 # Transaction distribution
1235system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218454 # Packet count per connected master and slave (bytes)
1236system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2369943 # Packet count per connected master and slave (bytes)
1237system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9884 # Packet count per connected master and slave (bytes)
1238system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21632 # Packet count per connected master and slave (bytes)
1239system.cpu0.toL2Bus.pkt_count::total 4619913 # Packet count per connected master and slave (bytes)
1240system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70449208 # Cumulative packet size per connected master and slave (bytes)
1241system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84455860 # Cumulative packet size per connected master and slave (bytes)
1242system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13944 # Cumulative packet size per connected master and slave (bytes)
1243system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 30948 # Cumulative packet size per connected master and slave (bytes)
1244system.cpu0.toL2Bus.pkt_size::total 154949960 # Cumulative packet size per connected master and slave (bytes)
1245system.cpu0.toL2Bus.snoops 641653 # Total snoops (count)
1246system.cpu0.toL2Bus.snoop_fanout::samples 3048291 # Request fanout histogram
1247system.cpu0.toL2Bus.snoop_fanout::mean 1.181009 # Request fanout histogram
1248system.cpu0.toL2Bus.snoop_fanout::stdev 0.385025 # Request fanout histogram
1249system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1250system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1251system.cpu0.toL2Bus.snoop_fanout::1 2496524 81.90% 81.90% # Request fanout histogram
1252system.cpu0.toL2Bus.snoop_fanout::2 551767 18.10% 100.00% # Request fanout histogram
1253system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1254system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1255system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1256system.cpu0.toL2Bus.snoop_fanout::total 3048291 # Request fanout histogram
1257system.cpu0.toL2Bus.reqLayer0.occupancy 1778395498 # Layer occupancy (ticks)
1258system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1259system.cpu0.toL2Bus.snoopLayer0.occupancy 114075998 # Layer occupancy (ticks)
1260system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1261system.cpu0.toL2Bus.respLayer0.occupancy 1664668023 # Layer occupancy (ticks)
1262system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1263system.cpu0.toL2Bus.respLayer1.occupancy 1210905566 # Layer occupancy (ticks)
1264system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1265system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks)
1266system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1267system.cpu0.toL2Bus.respLayer3.occupancy 13895250 # Layer occupancy (ticks)
1268system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1269system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1270system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1271system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1272system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1273system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1274system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1275system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

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1290system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1291system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1292system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1293system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1294system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1295system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1296system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1297system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1298system.cpu1.dtb.walker.walks 3295 # Table walker walks requested
1299system.cpu1.dtb.walker.walksShort 3295 # Table walker walks initiated with short descriptors
1300system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 601 # Level at which table walker walks with short descriptors terminate
1301system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate
1302system.cpu1.dtb.walker.walkWaitTime::samples 3295 # Table walker wait (enqueue to first request) latency
1303system.cpu1.dtb.walker.walkWaitTime::0 3295 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1304system.cpu1.dtb.walker.walkWaitTime::total 3295 # Table walker wait (enqueue to first request) latency
1305system.cpu1.dtb.walker.walkCompletionTime::samples 2525 # Table walker service (enqueue to completion) latency
1306system.cpu1.dtb.walker.walkCompletionTime::mean 9355.742574 # Table walker service (enqueue to completion) latency
1307system.cpu1.dtb.walker.walkCompletionTime::gmean 8433.023249 # Table walker service (enqueue to completion) latency
1308system.cpu1.dtb.walker.walkCompletionTime::stdev 5123.717679 # Table walker service (enqueue to completion) latency
1309system.cpu1.dtb.walker.walkCompletionTime::0-8191 905 35.84% 35.84% # Table walker service (enqueue to completion) latency
1310system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1497 59.29% 95.13% # Table walker service (enqueue to completion) latency
1311system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.46% 97.58% # Table walker service (enqueue to completion) latency
1312system.cpu1.dtb.walker.walkCompletionTime::24576-32767 54 2.14% 99.72% # Table walker service (enqueue to completion) latency
1313system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.08% 99.80% # Table walker service (enqueue to completion) latency
1314system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.16% 99.96% # Table walker service (enqueue to completion) latency
1315system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
1316system.cpu1.dtb.walker.walkCompletionTime::total 2525 # Table walker service (enqueue to completion) latency
1317system.cpu1.dtb.walker.walksPending::samples 1642630968 # Table walker pending requests distribution
1318system.cpu1.dtb.walker.walksPending::0 1642630968 100.00% 100.00% # Table walker pending requests distribution
1319system.cpu1.dtb.walker.walksPending::total 1642630968 # Table walker pending requests distribution
1320system.cpu1.dtb.walker.walkPageSizes::4K 1932 76.51% 76.51% # Table walker page sizes translated
1321system.cpu1.dtb.walker.walkPageSizes::1M 593 23.49% 100.00% # Table walker page sizes translated
1322system.cpu1.dtb.walker.walkPageSizes::total 2525 # Table walker page sizes translated
1323system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3295 # Table walker requests started/completed, data/inst
1324system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1325system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3295 # Table walker requests started/completed, data/inst
1326system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2525 # Table walker requests started/completed, data/inst
1327system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1328system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2525 # Table walker requests started/completed, data/inst
1329system.cpu1.dtb.walker.walkRequestOrigin::total 5820 # Table walker requests started/completed, data/inst
1330system.cpu1.dtb.inst_hits 0 # ITB inst hits
1331system.cpu1.dtb.inst_misses 0 # ITB inst misses
1332system.cpu1.dtb.read_hits 3921520 # DTB read hits
1333system.cpu1.dtb.read_misses 2787 # DTB read misses
1334system.cpu1.dtb.write_hits 3403460 # DTB write hits
1335system.cpu1.dtb.write_misses 508 # DTB write misses
1336system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1337system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1338system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1339system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1340system.cpu1.dtb.flush_entries 2006 # Number of entries that have been flushed from TLB
1341system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1342system.cpu1.dtb.prefetch_faults 344 # Number of TLB faults due to prefetch
1343system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1344system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
1345system.cpu1.dtb.read_accesses 3924307 # DTB read accesses
1346system.cpu1.dtb.write_accesses 3403968 # DTB write accesses
1347system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1348system.cpu1.dtb.hits 7324980 # DTB hits
1349system.cpu1.dtb.misses 3295 # DTB misses
1350system.cpu1.dtb.accesses 7328275 # DTB accesses
1351system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1352system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1353system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1354system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1355system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1356system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1357system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1358system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 21 unchanged lines hidden (view full) ---

1380system.cpu1.itb.walker.walks 1740 # Table walker walks requested
1381system.cpu1.itb.walker.walksShort 1740 # Table walker walks initiated with short descriptors
1382system.cpu1.itb.walker.walksShortTerminationLevel::Level1 164 # Level at which table walker walks with short descriptors terminate
1383system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1576 # Level at which table walker walks with short descriptors terminate
1384system.cpu1.itb.walker.walkWaitTime::samples 1740 # Table walker wait (enqueue to first request) latency
1385system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency
1386system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency
1387system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency
1388system.cpu1.itb.walker.walkCompletionTime::mean 9831.970936 # Table walker service (enqueue to completion) latency
1389system.cpu1.itb.walker.walkCompletionTime::gmean 8728.225186 # Table walker service (enqueue to completion) latency
1390system.cpu1.itb.walker.walkCompletionTime::stdev 5541.612386 # Table walker service (enqueue to completion) latency
1391system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.71% 16.71% # Table walker service (enqueue to completion) latency
1392system.cpu1.itb.walker.walkCompletionTime::4096-8191 162 14.71% 31.43% # Table walker service (enqueue to completion) latency
1393system.cpu1.itb.walker.walkCompletionTime::8192-12287 497 45.14% 76.57% # Table walker service (enqueue to completion) latency
1394system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.10% # Table walker service (enqueue to completion) latency
1395system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.19% # Table walker service (enqueue to completion) latency
1396system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.28% # Table walker service (enqueue to completion) latency
1397system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.54% 97.82% # Table walker service (enqueue to completion) latency
1398system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.73% 99.55% # Table walker service (enqueue to completion) latency
1399system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.82% # Table walker service (enqueue to completion) latency
1400system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency
1401system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency
1402system.cpu1.itb.walker.walksPending::samples 1642083968 # Table walker pending requests distribution
1403system.cpu1.itb.walker.walksPending::0 1642083968 100.00% 100.00% # Table walker pending requests distribution
1404system.cpu1.itb.walker.walksPending::total 1642083968 # Table walker pending requests distribution
1405system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated
1406system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated
1407system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated
1408system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1409system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1740 # Table walker requests started/completed, data/inst
1410system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1740 # Table walker requests started/completed, data/inst
1411system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1412system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst
1413system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst
1414system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst
1415system.cpu1.itb.inst_hits 16475856 # ITB inst hits
1416system.cpu1.itb.inst_misses 1740 # ITB inst misses
1417system.cpu1.itb.read_hits 0 # DTB read hits
1418system.cpu1.itb.read_misses 0 # DTB read misses
1419system.cpu1.itb.write_hits 0 # DTB write hits
1420system.cpu1.itb.write_misses 0 # DTB write misses
1421system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1422system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1423system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1424system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1425system.cpu1.itb.flush_entries 1142 # Number of entries that have been flushed from TLB
1426system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1427system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1428system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1429system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1430system.cpu1.itb.read_accesses 0 # DTB read accesses
1431system.cpu1.itb.write_accesses 0 # DTB write accesses
1432system.cpu1.itb.inst_accesses 16477596 # ITB inst accesses
1433system.cpu1.itb.hits 16475856 # DTB hits
1434system.cpu1.itb.misses 1740 # DTB misses
1435system.cpu1.itb.accesses 16477596 # DTB accesses
1436system.cpu1.numCycles 5736236800 # number of cpu cycles simulated
1437system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1438system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1439system.cpu1.committedInsts 16121027 # Number of instructions committed
1440system.cpu1.committedOps 19644884 # Number of ops (including micro ops) committed
1441system.cpu1.num_int_alu_accesses 17715670 # Number of integer alu accesses
1442system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses
1443system.cpu1.num_func_calls 1024357 # number of times a function call or return occured
1444system.cpu1.num_conditional_control_insts 1805296 # number of instructions that are conditional controls
1445system.cpu1.num_int_insts 17715670 # number of integer instructions
1446system.cpu1.num_fp_insts 1857 # number of float instructions
1447system.cpu1.num_int_register_reads 32157611 # number of times the integer registers were read
1448system.cpu1.num_int_register_writes 12423544 # number of times the integer registers were written
1449system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read
1450system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
1451system.cpu1.num_cc_register_reads 71811842 # number of times the CC registers were read
1452system.cpu1.num_cc_register_writes 6390929 # number of times the CC registers were written
1453system.cpu1.num_mem_refs 7557236 # number of memory refs
1454system.cpu1.num_load_insts 4032278 # Number of load instructions
1455system.cpu1.num_store_insts 3524958 # Number of store instructions
1456system.cpu1.num_idle_cycles 5685648636.968273 # Number of idle cycles
1457system.cpu1.num_busy_cycles 50588163.031727 # Number of busy cycles
1458system.cpu1.not_idle_fraction 0.008819 # Percentage of non-idle cycles
1459system.cpu1.idle_fraction 0.991181 # Percentage of idle cycles
1460system.cpu1.Branches 2908306 # Number of branches fetched
1461system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
1462system.cpu1.op_class::IntAlu 12407832 62.06% 62.06% # Class of executed instruction
1463system.cpu1.op_class::IntMult 25890 0.13% 62.19% # Class of executed instruction
1464system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction
1465system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction
1466system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction
1467system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction
1468system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction
1469system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction
1470system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction
1471system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction
1472system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction
1473system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction
1474system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction
1475system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction
1476system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction
1477system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction
1478system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction
1479system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction
1480system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction
1481system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction
1482system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction
1483system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction
1484system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction
1485system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction
1486system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction
1487system.cpu1.op_class::SimdFloatMisc 3309 0.02% 62.20% # Class of executed instruction
1488system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction
1489system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction
1490system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction
1491system.cpu1.op_class::MemRead 4032278 20.17% 82.37% # Class of executed instruction
1492system.cpu1.op_class::MemWrite 3524958 17.63% 100.00% # Class of executed instruction
1493system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1494system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1495system.cpu1.op_class::total 19994333 # Class of executed instruction
1496system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1497system.cpu1.kern.inst.quiesce 2782 # number of quiesce instructions executed
1498system.cpu1.dcache.tags.replacements 185399 # number of replacements
1499system.cpu1.dcache.tags.tagsinuse 466.419324 # Cycle average of tags in use
1500system.cpu1.dcache.tags.total_refs 7065195 # Total number of references to valid blocks.
1501system.cpu1.dcache.tags.sampled_refs 185751 # Sample count of references to valid blocks.
1502system.cpu1.dcache.tags.avg_refs 38.035838 # Average number of references to valid blocks.
1503system.cpu1.dcache.tags.warmup_cycle 104846956000 # Cycle when the warmup percentage was hit.
1504system.cpu1.dcache.tags.occ_blocks::cpu1.data 466.419324 # Average occupied blocks per requestor
1505system.cpu1.dcache.tags.occ_percent::cpu1.data 0.910975 # Average percentage of cache occupancy
1506system.cpu1.dcache.tags.occ_percent::total 0.910975 # Average percentage of cache occupancy
1507system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id
1508system.cpu1.dcache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id
1509system.cpu1.dcache.tags.age_task_id_blocks_1024::3 84 # Occupied blocks per task id
1510system.cpu1.dcache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
1511system.cpu1.dcache.tags.tag_accesses 14867676 # Number of tag accesses
1512system.cpu1.dcache.tags.data_accesses 14867676 # Number of data accesses
1513system.cpu1.dcache.ReadReq_hits::cpu1.data 3611065 # number of ReadReq hits
1514system.cpu1.dcache.ReadReq_hits::total 3611065 # number of ReadReq hits
1515system.cpu1.dcache.WriteReq_hits::cpu1.data 3216741 # number of WriteReq hits
1516system.cpu1.dcache.WriteReq_hits::total 3216741 # number of WriteReq hits
1517system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48524 # number of SoftPFReq hits
1518system.cpu1.dcache.SoftPFReq_hits::total 48524 # number of SoftPFReq hits
1519system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78212 # number of LoadLockedReq hits
1520system.cpu1.dcache.LoadLockedReq_hits::total 78212 # number of LoadLockedReq hits
1521system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70143 # number of StoreCondReq hits
1522system.cpu1.dcache.StoreCondReq_hits::total 70143 # number of StoreCondReq hits
1523system.cpu1.dcache.demand_hits::cpu1.data 6827806 # number of demand (read+write) hits
1524system.cpu1.dcache.demand_hits::total 6827806 # number of demand (read+write) hits
1525system.cpu1.dcache.overall_hits::cpu1.data 6876330 # number of overall hits
1526system.cpu1.dcache.overall_hits::total 6876330 # number of overall hits
1527system.cpu1.dcache.ReadReq_misses::cpu1.data 133141 # number of ReadReq misses
1528system.cpu1.dcache.ReadReq_misses::total 133141 # number of ReadReq misses
1529system.cpu1.dcache.WriteReq_misses::cpu1.data 90456 # number of WriteReq misses
1530system.cpu1.dcache.WriteReq_misses::total 90456 # number of WriteReq misses
1531system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30283 # number of SoftPFReq misses
1532system.cpu1.dcache.SoftPFReq_misses::total 30283 # number of SoftPFReq misses
1533system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17238 # number of LoadLockedReq misses
1534system.cpu1.dcache.LoadLockedReq_misses::total 17238 # number of LoadLockedReq misses
1535system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23491 # number of StoreCondReq misses
1536system.cpu1.dcache.StoreCondReq_misses::total 23491 # number of StoreCondReq misses
1537system.cpu1.dcache.demand_misses::cpu1.data 223597 # number of demand (read+write) misses
1538system.cpu1.dcache.demand_misses::total 223597 # number of demand (read+write) misses
1539system.cpu1.dcache.overall_misses::cpu1.data 253880 # number of overall misses
1540system.cpu1.dcache.overall_misses::total 253880 # number of overall misses
1541system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1928381738 # number of ReadReq miss cycles
1542system.cpu1.dcache.ReadReq_miss_latency::total 1928381738 # number of ReadReq miss cycles
1543system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2296114353 # number of WriteReq miss cycles
1544system.cpu1.dcache.WriteReq_miss_latency::total 2296114353 # number of WriteReq miss cycles
1545system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 319996750 # number of LoadLockedReq miss cycles
1546system.cpu1.dcache.LoadLockedReq_miss_latency::total 319996750 # number of LoadLockedReq miss cycles
1547system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 553086757 # number of StoreCondReq miss cycles
1548system.cpu1.dcache.StoreCondReq_miss_latency::total 553086757 # number of StoreCondReq miss cycles
1549system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2433500 # number of StoreCondFailReq miss cycles
1550system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2433500 # number of StoreCondFailReq miss cycles
1551system.cpu1.dcache.demand_miss_latency::cpu1.data 4224496091 # number of demand (read+write) miss cycles
1552system.cpu1.dcache.demand_miss_latency::total 4224496091 # number of demand (read+write) miss cycles
1553system.cpu1.dcache.overall_miss_latency::cpu1.data 4224496091 # number of overall miss cycles
1554system.cpu1.dcache.overall_miss_latency::total 4224496091 # number of overall miss cycles
1555system.cpu1.dcache.ReadReq_accesses::cpu1.data 3744206 # number of ReadReq accesses(hits+misses)
1556system.cpu1.dcache.ReadReq_accesses::total 3744206 # number of ReadReq accesses(hits+misses)
1557system.cpu1.dcache.WriteReq_accesses::cpu1.data 3307197 # number of WriteReq accesses(hits+misses)
1558system.cpu1.dcache.WriteReq_accesses::total 3307197 # number of WriteReq accesses(hits+misses)
1559system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 78807 # number of SoftPFReq accesses(hits+misses)
1560system.cpu1.dcache.SoftPFReq_accesses::total 78807 # number of SoftPFReq accesses(hits+misses)
1561system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95450 # number of LoadLockedReq accesses(hits+misses)
1562system.cpu1.dcache.LoadLockedReq_accesses::total 95450 # number of LoadLockedReq accesses(hits+misses)
1563system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93634 # number of StoreCondReq accesses(hits+misses)
1564system.cpu1.dcache.StoreCondReq_accesses::total 93634 # number of StoreCondReq accesses(hits+misses)
1565system.cpu1.dcache.demand_accesses::cpu1.data 7051403 # number of demand (read+write) accesses
1566system.cpu1.dcache.demand_accesses::total 7051403 # number of demand (read+write) accesses
1567system.cpu1.dcache.overall_accesses::cpu1.data 7130210 # number of overall (read+write) accesses
1568system.cpu1.dcache.overall_accesses::total 7130210 # number of overall (read+write) accesses
1569system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035559 # miss rate for ReadReq accesses
1570system.cpu1.dcache.ReadReq_miss_rate::total 0.035559 # miss rate for ReadReq accesses
1571system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027351 # miss rate for WriteReq accesses
1572system.cpu1.dcache.WriteReq_miss_rate::total 0.027351 # miss rate for WriteReq accesses
1573system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.384268 # miss rate for SoftPFReq accesses
1574system.cpu1.dcache.SoftPFReq_miss_rate::total 0.384268 # miss rate for SoftPFReq accesses
1575system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.180597 # miss rate for LoadLockedReq accesses
1576system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.180597 # miss rate for LoadLockedReq accesses
1577system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250881 # miss rate for StoreCondReq accesses
1578system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250881 # miss rate for StoreCondReq accesses
1579system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031710 # miss rate for demand accesses
1580system.cpu1.dcache.demand_miss_rate::total 0.031710 # miss rate for demand accesses
1581system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035606 # miss rate for overall accesses
1582system.cpu1.dcache.overall_miss_rate::total 0.035606 # miss rate for overall accesses
1583system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14483.755853 # average ReadReq miss latency
1584system.cpu1.dcache.ReadReq_avg_miss_latency::total 14483.755853 # average ReadReq miss latency
1585system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25383.770596 # average WriteReq miss latency
1586system.cpu1.dcache.WriteReq_avg_miss_latency::total 25383.770596 # average WriteReq miss latency
1587system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18563.449936 # average LoadLockedReq miss latency
1588system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18563.449936 # average LoadLockedReq miss latency
1589system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23544.623771 # average StoreCondReq miss latency
1590system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23544.623771 # average StoreCondReq miss latency
1591system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1592system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1593system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18893.348708 # average overall miss latency
1594system.cpu1.dcache.demand_avg_miss_latency::total 18893.348708 # average overall miss latency
1595system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16639.735666 # average overall miss latency
1596system.cpu1.dcache.overall_avg_miss_latency::total 16639.735666 # average overall miss latency
1597system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1598system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1599system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1600system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1601system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1602system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1603system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1604system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1605system.cpu1.dcache.writebacks::writebacks 114520 # number of writebacks
1606system.cpu1.dcache.writebacks::total 114520 # number of writebacks
1607system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 275 # number of ReadReq MSHR hits
1608system.cpu1.dcache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits
1609system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12066 # number of LoadLockedReq MSHR hits
1610system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12066 # number of LoadLockedReq MSHR hits
1611system.cpu1.dcache.demand_mshr_hits::cpu1.data 275 # number of demand (read+write) MSHR hits
1612system.cpu1.dcache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits
1613system.cpu1.dcache.overall_mshr_hits::cpu1.data 275 # number of overall MSHR hits
1614system.cpu1.dcache.overall_mshr_hits::total 275 # number of overall MSHR hits
1615system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 132866 # number of ReadReq MSHR misses
1616system.cpu1.dcache.ReadReq_mshr_misses::total 132866 # number of ReadReq MSHR misses
1617system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90456 # number of WriteReq MSHR misses
1618system.cpu1.dcache.WriteReq_mshr_misses::total 90456 # number of WriteReq MSHR misses
1619system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29572 # number of SoftPFReq MSHR misses
1620system.cpu1.dcache.SoftPFReq_mshr_misses::total 29572 # number of SoftPFReq MSHR misses
1621system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5172 # number of LoadLockedReq MSHR misses
1622system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5172 # number of LoadLockedReq MSHR misses
1623system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23491 # number of StoreCondReq MSHR misses
1624system.cpu1.dcache.StoreCondReq_mshr_misses::total 23491 # number of StoreCondReq MSHR misses
1625system.cpu1.dcache.demand_mshr_misses::cpu1.data 223322 # number of demand (read+write) MSHR misses
1626system.cpu1.dcache.demand_mshr_misses::total 223322 # number of demand (read+write) MSHR misses
1627system.cpu1.dcache.overall_mshr_misses::cpu1.data 252894 # number of overall MSHR misses
1628system.cpu1.dcache.overall_mshr_misses::total 252894 # number of overall MSHR misses
1629system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3084 # number of ReadReq MSHR uncacheable
1630system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3084 # number of ReadReq MSHR uncacheable
1631system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2437 # number of WriteReq MSHR uncacheable
1632system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2437 # number of WriteReq MSHR uncacheable
1633system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5521 # number of overall MSHR uncacheable misses
1634system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5521 # number of overall MSHR uncacheable misses
1635system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1717533750 # number of ReadReq MSHR miss cycles
1636system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1717533750 # number of ReadReq MSHR miss cycles
1637system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2155103647 # number of WriteReq MSHR miss cycles
1638system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2155103647 # number of WriteReq MSHR miss cycles
1639system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 472304765 # number of SoftPFReq MSHR miss cycles
1640system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 472304765 # number of SoftPFReq MSHR miss cycles
1641system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84734500 # number of LoadLockedReq MSHR miss cycles
1642system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84734500 # number of LoadLockedReq MSHR miss cycles
1643system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 516677243 # number of StoreCondReq MSHR miss cycles
1644system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 516677243 # number of StoreCondReq MSHR miss cycles
1645system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2366000 # number of StoreCondFailReq MSHR miss cycles
1646system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2366000 # number of StoreCondFailReq MSHR miss cycles
1647system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3872637397 # number of demand (read+write) MSHR miss cycles
1648system.cpu1.dcache.demand_mshr_miss_latency::total 3872637397 # number of demand (read+write) MSHR miss cycles
1649system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344942162 # number of overall MSHR miss cycles
1650system.cpu1.dcache.overall_mshr_miss_latency::total 4344942162 # number of overall MSHR miss cycles
1651system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406850750 # number of ReadReq MSHR uncacheable cycles
1652system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406850750 # number of ReadReq MSHR uncacheable cycles
1653system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 279944500 # number of WriteReq MSHR uncacheable cycles
1654system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279944500 # number of WriteReq MSHR uncacheable cycles
1655system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 686795250 # number of overall MSHR uncacheable cycles
1656system.cpu1.dcache.overall_mshr_uncacheable_latency::total 686795250 # number of overall MSHR uncacheable cycles
1657system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035486 # mshr miss rate for ReadReq accesses
1658system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035486 # mshr miss rate for ReadReq accesses
1659system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027351 # mshr miss rate for WriteReq accesses
1660system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027351 # mshr miss rate for WriteReq accesses
1661system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.375246 # mshr miss rate for SoftPFReq accesses
1662system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.375246 # mshr miss rate for SoftPFReq accesses
1663system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054185 # mshr miss rate for LoadLockedReq accesses
1664system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054185 # mshr miss rate for LoadLockedReq accesses
1665system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250881 # mshr miss rate for StoreCondReq accesses
1666system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250881 # mshr miss rate for StoreCondReq accesses
1667system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031671 # mshr miss rate for demand accesses
1668system.cpu1.dcache.demand_mshr_miss_rate::total 0.031671 # mshr miss rate for demand accesses
1669system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035468 # mshr miss rate for overall accesses
1670system.cpu1.dcache.overall_mshr_miss_rate::total 0.035468 # mshr miss rate for overall accesses
1671system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12926.811600 # average ReadReq mshr miss latency
1672system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12926.811600 # average ReadReq mshr miss latency
1673system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23824.883336 # average WriteReq mshr miss latency
1674system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23824.883336 # average WriteReq mshr miss latency
1675system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15971.350095 # average SoftPFReq mshr miss latency
1676system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15971.350095 # average SoftPFReq mshr miss latency
1677system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.313998 # average LoadLockedReq mshr miss latency
1678system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.313998 # average LoadLockedReq mshr miss latency
1679system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.689158 # average StoreCondReq mshr miss latency
1680system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.689158 # average StoreCondReq mshr miss latency
1681system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1682system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1683system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17341.047443 # average overall mshr miss latency
1684system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17341.047443 # average overall mshr miss latency
1685system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17180.882749 # average overall mshr miss latency
1686system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17180.882749 # average overall mshr miss latency
1687system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131923.070687 # average ReadReq mshr uncacheable latency
1688system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131923.070687 # average ReadReq mshr uncacheable latency
1689system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114872.589249 # average WriteReq mshr uncacheable latency
1690system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114872.589249 # average WriteReq mshr uncacheable latency
1691system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124396.893679 # average overall mshr uncacheable latency
1692system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124396.893679 # average overall mshr uncacheable latency
1693system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1694system.cpu1.icache.tags.replacements 502966 # number of replacements
1695system.cpu1.icache.tags.tagsinuse 498.575795 # Cycle average of tags in use
1696system.cpu1.icache.tags.total_refs 15972373 # Total number of references to valid blocks.
1697system.cpu1.icache.tags.sampled_refs 503478 # Sample count of references to valid blocks.
1698system.cpu1.icache.tags.avg_refs 31.724073 # Average number of references to valid blocks.
1699system.cpu1.icache.tags.warmup_cycle 84694032500 # Cycle when the warmup percentage was hit.
1700system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.575795 # Average occupied blocks per requestor
1701system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973781 # Average percentage of cache occupancy
1702system.cpu1.icache.tags.occ_percent::total 0.973781 # Average percentage of cache occupancy
1703system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1704system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
1705system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id
1706system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
1707system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1708system.cpu1.icache.tags.tag_accesses 33455180 # Number of tag accesses
1709system.cpu1.icache.tags.data_accesses 33455180 # Number of data accesses
1710system.cpu1.icache.ReadReq_hits::cpu1.inst 15972373 # number of ReadReq hits
1711system.cpu1.icache.ReadReq_hits::total 15972373 # number of ReadReq hits
1712system.cpu1.icache.demand_hits::cpu1.inst 15972373 # number of demand (read+write) hits
1713system.cpu1.icache.demand_hits::total 15972373 # number of demand (read+write) hits
1714system.cpu1.icache.overall_hits::cpu1.inst 15972373 # number of overall hits
1715system.cpu1.icache.overall_hits::total 15972373 # number of overall hits
1716system.cpu1.icache.ReadReq_misses::cpu1.inst 503478 # number of ReadReq misses
1717system.cpu1.icache.ReadReq_misses::total 503478 # number of ReadReq misses
1718system.cpu1.icache.demand_misses::cpu1.inst 503478 # number of demand (read+write) misses
1719system.cpu1.icache.demand_misses::total 503478 # number of demand (read+write) misses
1720system.cpu1.icache.overall_misses::cpu1.inst 503478 # number of overall misses
1721system.cpu1.icache.overall_misses::total 503478 # number of overall misses
1722system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4406075262 # number of ReadReq miss cycles
1723system.cpu1.icache.ReadReq_miss_latency::total 4406075262 # number of ReadReq miss cycles
1724system.cpu1.icache.demand_miss_latency::cpu1.inst 4406075262 # number of demand (read+write) miss cycles
1725system.cpu1.icache.demand_miss_latency::total 4406075262 # number of demand (read+write) miss cycles
1726system.cpu1.icache.overall_miss_latency::cpu1.inst 4406075262 # number of overall miss cycles
1727system.cpu1.icache.overall_miss_latency::total 4406075262 # number of overall miss cycles
1728system.cpu1.icache.ReadReq_accesses::cpu1.inst 16475851 # number of ReadReq accesses(hits+misses)
1729system.cpu1.icache.ReadReq_accesses::total 16475851 # number of ReadReq accesses(hits+misses)
1730system.cpu1.icache.demand_accesses::cpu1.inst 16475851 # number of demand (read+write) accesses
1731system.cpu1.icache.demand_accesses::total 16475851 # number of demand (read+write) accesses
1732system.cpu1.icache.overall_accesses::cpu1.inst 16475851 # number of overall (read+write) accesses
1733system.cpu1.icache.overall_accesses::total 16475851 # number of overall (read+write) accesses
1734system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030559 # miss rate for ReadReq accesses
1735system.cpu1.icache.ReadReq_miss_rate::total 0.030559 # miss rate for ReadReq accesses
1736system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030559 # miss rate for demand accesses
1737system.cpu1.icache.demand_miss_rate::total 0.030559 # miss rate for demand accesses
1738system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030559 # miss rate for overall accesses
1739system.cpu1.icache.overall_miss_rate::total 0.030559 # miss rate for overall accesses
1740system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8751.276644 # average ReadReq miss latency
1741system.cpu1.icache.ReadReq_avg_miss_latency::total 8751.276644 # average ReadReq miss latency
1742system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8751.276644 # average overall miss latency
1743system.cpu1.icache.demand_avg_miss_latency::total 8751.276644 # average overall miss latency
1744system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8751.276644 # average overall miss latency
1745system.cpu1.icache.overall_avg_miss_latency::total 8751.276644 # average overall miss latency
1746system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1747system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1748system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1749system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1750system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1751system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1752system.cpu1.icache.fast_writes 0 # number of fast writes performed
1753system.cpu1.icache.cache_copies 0 # number of cache copies performed
1754system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 503478 # number of ReadReq MSHR misses
1755system.cpu1.icache.ReadReq_mshr_misses::total 503478 # number of ReadReq MSHR misses
1756system.cpu1.icache.demand_mshr_misses::cpu1.inst 503478 # number of demand (read+write) MSHR misses
1757system.cpu1.icache.demand_mshr_misses::total 503478 # number of demand (read+write) MSHR misses
1758system.cpu1.icache.overall_mshr_misses::cpu1.inst 503478 # number of overall MSHR misses
1759system.cpu1.icache.overall_mshr_misses::total 503478 # number of overall MSHR misses
1760system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
1761system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
1762system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
1763system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
1764system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3901799738 # number of ReadReq MSHR miss cycles
1765system.cpu1.icache.ReadReq_mshr_miss_latency::total 3901799738 # number of ReadReq MSHR miss cycles
1766system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3901799738 # number of demand (read+write) MSHR miss cycles
1767system.cpu1.icache.demand_mshr_miss_latency::total 3901799738 # number of demand (read+write) MSHR miss cycles
1768system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3901799738 # number of overall MSHR miss cycles
1769system.cpu1.icache.overall_mshr_miss_latency::total 3901799738 # number of overall MSHR miss cycles
1770system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15252750 # number of ReadReq MSHR uncacheable cycles
1771system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15252750 # number of ReadReq MSHR uncacheable cycles
1772system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15252750 # number of overall MSHR uncacheable cycles
1773system.cpu1.icache.overall_mshr_uncacheable_latency::total 15252750 # number of overall MSHR uncacheable cycles
1774system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030559 # mshr miss rate for ReadReq accesses
1775system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030559 # mshr miss rate for ReadReq accesses
1776system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030559 # mshr miss rate for demand accesses
1777system.cpu1.icache.demand_mshr_miss_rate::total 0.030559 # mshr miss rate for demand accesses
1778system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030559 # mshr miss rate for overall accesses
1779system.cpu1.icache.overall_mshr_miss_rate::total 0.030559 # mshr miss rate for overall accesses
1780system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7749.692614 # average ReadReq mshr miss latency
1781system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7749.692614 # average ReadReq mshr miss latency
1782system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7749.692614 # average overall mshr miss latency
1783system.cpu1.icache.demand_avg_mshr_miss_latency::total 7749.692614 # average overall mshr miss latency
1784system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7749.692614 # average overall mshr miss latency
1785system.cpu1.icache.overall_avg_mshr_miss_latency::total 7749.692614 # average overall mshr miss latency
1786system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814 # average ReadReq mshr uncacheable latency
1787system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86173.728814 # average ReadReq mshr uncacheable latency
1788system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814 # average overall mshr uncacheable latency
1789system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86173.728814 # average overall mshr uncacheable latency
1790system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1791system.cpu1.l2cache.prefetcher.num_hwpf_issued 195194 # number of hwpf issued
1792system.cpu1.l2cache.prefetcher.pfIdentified 195194 # number of prefetch candidates identified
1793system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
1794system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1795system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1796system.cpu1.l2cache.prefetcher.pfSpanPage 57534 # number of prefetches not generated due to page crossing
1797system.cpu1.l2cache.tags.replacements 39835 # number of replacements
1798system.cpu1.l2cache.tags.tagsinuse 14698.947760 # Cycle average of tags in use
1799system.cpu1.l2cache.tags.total_refs 703731 # Total number of references to valid blocks.
1800system.cpu1.l2cache.tags.sampled_refs 54406 # Sample count of references to valid blocks.
1801system.cpu1.l2cache.tags.avg_refs 12.934805 # Average number of references to valid blocks.
1802system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1803system.cpu1.l2cache.tags.occ_blocks::writebacks 8839.546228 # Average occupied blocks per requestor
1804system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.119643 # Average occupied blocks per requestor
1805system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.076473 # Average occupied blocks per requestor
1806system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3192.274029 # Average occupied blocks per requestor
1807system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1936.419828 # Average occupied blocks per requestor
1808system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 726.511560 # Average occupied blocks per requestor
1809system.cpu1.l2cache.tags.occ_percent::writebacks 0.539523 # Average percentage of cache occupancy
1810system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000129 # Average percentage of cache occupancy
1811system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy
1812system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.194841 # Average percentage of cache occupancy
1813system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.118190 # Average percentage of cache occupancy
1814system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.044343 # Average percentage of cache occupancy
1815system.cpu1.l2cache.tags.occ_percent::total 0.897153 # Average percentage of cache occupancy
1816system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1124 # Occupied blocks per task id
1817system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id
1818system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13429 # Occupied blocks per task id
1819system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id
1820system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 25 # Occupied blocks per task id
1821system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1096 # Occupied blocks per task id
1822system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
1823system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
1824system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 296 # Occupied blocks per task id
1825system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1612 # Occupied blocks per task id
1826system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11521 # Occupied blocks per task id
1827system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068604 # Percentage of cache occupancy per task id
1828system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id
1829system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.819641 # Percentage of cache occupancy per task id
1830system.cpu1.l2cache.tags.tag_accesses 14679345 # Number of tag accesses
1831system.cpu1.l2cache.tags.data_accesses 14679345 # Number of data accesses
1832system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3122 # number of ReadReq hits
1833system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1719 # number of ReadReq hits
1834system.cpu1.l2cache.ReadReq_hits::cpu1.inst 490518 # number of ReadReq hits
1835system.cpu1.l2cache.ReadReq_hits::cpu1.data 100742 # number of ReadReq hits
1836system.cpu1.l2cache.ReadReq_hits::total 596101 # number of ReadReq hits
1837system.cpu1.l2cache.Writeback_hits::writebacks 114520 # number of Writeback hits
1838system.cpu1.l2cache.Writeback_hits::total 114520 # number of Writeback hits
1839system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1111 # number of UpgradeReq hits
1840system.cpu1.l2cache.UpgradeReq_hits::total 1111 # number of UpgradeReq hits
1841system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 866 # number of SCUpgradeReq hits
1842system.cpu1.l2cache.SCUpgradeReq_hits::total 866 # number of SCUpgradeReq hits
1843system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27369 # number of ReadExReq hits
1844system.cpu1.l2cache.ReadExReq_hits::total 27369 # number of ReadExReq hits
1845system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3122 # number of demand (read+write) hits
1846system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1719 # number of demand (read+write) hits
1847system.cpu1.l2cache.demand_hits::cpu1.inst 490518 # number of demand (read+write) hits
1848system.cpu1.l2cache.demand_hits::cpu1.data 128111 # number of demand (read+write) hits
1849system.cpu1.l2cache.demand_hits::total 623470 # number of demand (read+write) hits
1850system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3122 # number of overall hits
1851system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1719 # number of overall hits
1852system.cpu1.l2cache.overall_hits::cpu1.inst 490518 # number of overall hits
1853system.cpu1.l2cache.overall_hits::cpu1.data 128111 # number of overall hits
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1855system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 318 # number of ReadReq misses
1856system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses
1857system.cpu1.l2cache.ReadReq_misses::cpu1.inst 12960 # number of ReadReq misses
1858system.cpu1.l2cache.ReadReq_misses::cpu1.data 66868 # number of ReadReq misses
1859system.cpu1.l2cache.ReadReq_misses::total 80413 # number of ReadReq misses
1860system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27915 # number of UpgradeReq misses
1861system.cpu1.l2cache.UpgradeReq_misses::total 27915 # number of UpgradeReq misses
1862system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22615 # number of SCUpgradeReq misses
1863system.cpu1.l2cache.SCUpgradeReq_misses::total 22615 # number of SCUpgradeReq misses
1864system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 10 # number of SCUpgradeFailReq misses
1865system.cpu1.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses
1866system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34061 # number of ReadExReq misses
1867system.cpu1.l2cache.ReadExReq_misses::total 34061 # number of ReadExReq misses
1868system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 318 # number of demand (read+write) misses
1869system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses
1870system.cpu1.l2cache.demand_misses::cpu1.inst 12960 # number of demand (read+write) misses
1871system.cpu1.l2cache.demand_misses::cpu1.data 100929 # number of demand (read+write) misses
1872system.cpu1.l2cache.demand_misses::total 114474 # number of demand (read+write) misses
1873system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 318 # number of overall misses
1874system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses
1875system.cpu1.l2cache.overall_misses::cpu1.inst 12960 # number of overall misses
1876system.cpu1.l2cache.overall_misses::cpu1.data 100929 # number of overall misses
1877system.cpu1.l2cache.overall_misses::total 114474 # number of overall misses
1878system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6443750 # number of ReadReq miss cycles
1879system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5338500 # number of ReadReq miss cycles
1880system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 460251238 # number of ReadReq miss cycles
1881system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1451446014 # number of ReadReq miss cycles
1882system.cpu1.l2cache.ReadReq_miss_latency::total 1923479502 # number of ReadReq miss cycles
1883system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 535355877 # number of UpgradeReq miss cycles
1884system.cpu1.l2cache.UpgradeReq_miss_latency::total 535355877 # number of UpgradeReq miss cycles
1885system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 456012560 # number of SCUpgradeReq miss cycles
1886system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 456012560 # number of SCUpgradeReq miss cycles
1887system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2321000 # number of SCUpgradeFailReq miss cycles
1888system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2321000 # number of SCUpgradeFailReq miss cycles
1889system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1258488445 # number of ReadExReq miss cycles
1890system.cpu1.l2cache.ReadExReq_miss_latency::total 1258488445 # number of ReadExReq miss cycles
1891system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6443750 # number of demand (read+write) miss cycles
1892system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5338500 # number of demand (read+write) miss cycles
1893system.cpu1.l2cache.demand_miss_latency::cpu1.inst 460251238 # number of demand (read+write) miss cycles
1894system.cpu1.l2cache.demand_miss_latency::cpu1.data 2709934459 # number of demand (read+write) miss cycles
1895system.cpu1.l2cache.demand_miss_latency::total 3181967947 # number of demand (read+write) miss cycles
1896system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6443750 # number of overall miss cycles
1897system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5338500 # number of overall miss cycles
1898system.cpu1.l2cache.overall_miss_latency::cpu1.inst 460251238 # number of overall miss cycles
1899system.cpu1.l2cache.overall_miss_latency::cpu1.data 2709934459 # number of overall miss cycles
1900system.cpu1.l2cache.overall_miss_latency::total 3181967947 # number of overall miss cycles
1901system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3440 # number of ReadReq accesses(hits+misses)
1902system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1986 # number of ReadReq accesses(hits+misses)
1903system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 503478 # number of ReadReq accesses(hits+misses)
1904system.cpu1.l2cache.ReadReq_accesses::cpu1.data 167610 # number of ReadReq accesses(hits+misses)
1905system.cpu1.l2cache.ReadReq_accesses::total 676514 # number of ReadReq accesses(hits+misses)
1906system.cpu1.l2cache.Writeback_accesses::writebacks 114520 # number of Writeback accesses(hits+misses)
1907system.cpu1.l2cache.Writeback_accesses::total 114520 # number of Writeback accesses(hits+misses)
1908system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29026 # number of UpgradeReq accesses(hits+misses)
1909system.cpu1.l2cache.UpgradeReq_accesses::total 29026 # number of UpgradeReq accesses(hits+misses)
1910system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23481 # number of SCUpgradeReq accesses(hits+misses)
1911system.cpu1.l2cache.SCUpgradeReq_accesses::total 23481 # number of SCUpgradeReq accesses(hits+misses)
1912system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 10 # number of SCUpgradeFailReq accesses(hits+misses)
1913system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses)
1914system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61430 # number of ReadExReq accesses(hits+misses)
1915system.cpu1.l2cache.ReadExReq_accesses::total 61430 # number of ReadExReq accesses(hits+misses)
1916system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3440 # number of demand (read+write) accesses
1917system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1986 # number of demand (read+write) accesses
1918system.cpu1.l2cache.demand_accesses::cpu1.inst 503478 # number of demand (read+write) accesses
1919system.cpu1.l2cache.demand_accesses::cpu1.data 229040 # number of demand (read+write) accesses
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1921system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3440 # number of overall (read+write) accesses
1922system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1986 # number of overall (read+write) accesses
1923system.cpu1.l2cache.overall_accesses::cpu1.inst 503478 # number of overall (read+write) accesses
1924system.cpu1.l2cache.overall_accesses::cpu1.data 229040 # number of overall (read+write) accesses
1925system.cpu1.l2cache.overall_accesses::total 737944 # number of overall (read+write) accesses
1926system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.092442 # miss rate for ReadReq accesses
1927system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.134441 # miss rate for ReadReq accesses
1928system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.025741 # miss rate for ReadReq accesses
1929system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.398950 # miss rate for ReadReq accesses
1930system.cpu1.l2cache.ReadReq_miss_rate::total 0.118864 # miss rate for ReadReq accesses
1931system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.961724 # miss rate for UpgradeReq accesses
1932system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.961724 # miss rate for UpgradeReq accesses
1933system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.963119 # miss rate for SCUpgradeReq accesses
1934system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.963119 # miss rate for SCUpgradeReq accesses
1935system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1936system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1937system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.554469 # miss rate for ReadExReq accesses
1938system.cpu1.l2cache.ReadExReq_miss_rate::total 0.554469 # miss rate for ReadExReq accesses
1939system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.092442 # miss rate for demand accesses
1940system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.134441 # miss rate for demand accesses
1941system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025741 # miss rate for demand accesses
1942system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.440661 # miss rate for demand accesses
1943system.cpu1.l2cache.demand_miss_rate::total 0.155126 # miss rate for demand accesses
1944system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.092442 # miss rate for overall accesses
1945system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.134441 # miss rate for overall accesses
1946system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025741 # miss rate for overall accesses
1947system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.440661 # miss rate for overall accesses
1948system.cpu1.l2cache.overall_miss_rate::total 0.155126 # miss rate for overall accesses
1949system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20263.364780 # average ReadReq miss latency
1950system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19994.382022 # average ReadReq miss latency
1951system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35513.212809 # average ReadReq miss latency
1952system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21706.137674 # average ReadReq miss latency
1953system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23920.006740 # average ReadReq miss latency
1954system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19178.071897 # average UpgradeReq miss latency
1955system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19178.071897 # average UpgradeReq miss latency
1956system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20164.163608 # average SCUpgradeReq miss latency
1957system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20164.163608 # average SCUpgradeReq miss latency
1958system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 232100 # average SCUpgradeFailReq miss latency
1959system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 232100 # average SCUpgradeFailReq miss latency
1960system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36948.076833 # average ReadExReq miss latency
1961system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36948.076833 # average ReadExReq miss latency
1962system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20263.364780 # average overall miss latency
1963system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19994.382022 # average overall miss latency
1964system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35513.212809 # average overall miss latency
1965system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26849.908936 # average overall miss latency
1966system.cpu1.l2cache.demand_avg_miss_latency::total 27796.424926 # average overall miss latency
1967system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20263.364780 # average overall miss latency
1968system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19994.382022 # average overall miss latency
1969system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35513.212809 # average overall miss latency
1970system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26849.908936 # average overall miss latency
1971system.cpu1.l2cache.overall_avg_miss_latency::total 27796.424926 # average overall miss latency
1972system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1973system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1974system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1975system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1976system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1977system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1978system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
1979system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
1980system.cpu1.l2cache.writebacks::writebacks 25678 # number of writebacks
1981system.cpu1.l2cache.writebacks::total 25678 # number of writebacks
1982system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 69 # number of ReadExReq MSHR hits
1983system.cpu1.l2cache.ReadExReq_mshr_hits::total 69 # number of ReadExReq MSHR hits
1984system.cpu1.l2cache.demand_mshr_hits::cpu1.data 69 # number of demand (read+write) MSHR hits
1985system.cpu1.l2cache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
1986system.cpu1.l2cache.overall_mshr_hits::cpu1.data 69 # number of overall MSHR hits
1987system.cpu1.l2cache.overall_mshr_hits::total 69 # number of overall MSHR hits
1988system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 318 # number of ReadReq MSHR misses
1989system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 267 # number of ReadReq MSHR misses
1990system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 12960 # number of ReadReq MSHR misses
1991system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66868 # number of ReadReq MSHR misses
1992system.cpu1.l2cache.ReadReq_mshr_misses::total 80413 # number of ReadReq MSHR misses
1993system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 22290 # number of HardPFReq MSHR misses
1994system.cpu1.l2cache.HardPFReq_mshr_misses::total 22290 # number of HardPFReq MSHR misses
1995system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27915 # number of UpgradeReq MSHR misses
1996system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27915 # number of UpgradeReq MSHR misses
1997system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22615 # number of SCUpgradeReq MSHR misses
1998system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22615 # number of SCUpgradeReq MSHR misses
1999system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 10 # number of SCUpgradeFailReq MSHR misses
2000system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses
2001system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33992 # number of ReadExReq MSHR misses
2002system.cpu1.l2cache.ReadExReq_mshr_misses::total 33992 # number of ReadExReq MSHR misses
2003system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 318 # number of demand (read+write) MSHR misses
2004system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 267 # number of demand (read+write) MSHR misses
2005system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 12960 # number of demand (read+write) MSHR misses
2006system.cpu1.l2cache.demand_mshr_misses::cpu1.data 100860 # number of demand (read+write) MSHR misses
2007system.cpu1.l2cache.demand_mshr_misses::total 114405 # number of demand (read+write) MSHR misses
2008system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 318 # number of overall MSHR misses
2009system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 267 # number of overall MSHR misses
2010system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 12960 # number of overall MSHR misses
2011system.cpu1.l2cache.overall_mshr_misses::cpu1.data 100860 # number of overall MSHR misses
2012system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 22290 # number of overall MSHR misses
2013system.cpu1.l2cache.overall_mshr_misses::total 136695 # number of overall MSHR misses
2014system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable
2015system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3084 # number of ReadReq MSHR uncacheable
2016system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3261 # number of ReadReq MSHR uncacheable
2017system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2437 # number of WriteReq MSHR uncacheable
2018system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2437 # number of WriteReq MSHR uncacheable
2019system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses
2020system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5521 # number of overall MSHR uncacheable misses
2021system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5698 # number of overall MSHR uncacheable misses
2022system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4376250 # number of ReadReq MSHR miss cycles
2023system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3603000 # number of ReadReq MSHR miss cycles
2024system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 375210762 # number of ReadReq MSHR miss cycles
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2026system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1399818998 # number of ReadReq MSHR miss cycles
2027system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 742843274 # number of HardPFReq MSHR miss cycles
2028system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 742843274 # number of HardPFReq MSHR miss cycles
2029system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 439552298 # number of UpgradeReq MSHR miss cycles
2030system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 439552298 # number of UpgradeReq MSHR miss cycles
2031system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 340829757 # number of SCUpgradeReq MSHR miss cycles
2032system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 340829757 # number of SCUpgradeReq MSHR miss cycles
2033system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2028500 # number of SCUpgradeFailReq MSHR miss cycles
2034system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2028500 # number of SCUpgradeFailReq MSHR miss cycles
2035system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1027563755 # number of ReadExReq MSHR miss cycles
2036system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1027563755 # number of ReadExReq MSHR miss cycles
2037system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4376250 # number of demand (read+write) MSHR miss cycles
2038system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3603000 # number of demand (read+write) MSHR miss cycles
2039system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 375210762 # number of demand (read+write) MSHR miss cycles
2040system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2044192741 # number of demand (read+write) MSHR miss cycles
2041system.cpu1.l2cache.demand_mshr_miss_latency::total 2427382753 # number of demand (read+write) MSHR miss cycles
2042system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4376250 # number of overall MSHR miss cycles
2043system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3603000 # number of overall MSHR miss cycles
2044system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 375210762 # number of overall MSHR miss cycles
2045system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2044192741 # number of overall MSHR miss cycles
2046system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 742843274 # number of overall MSHR miss cycles
2047system.cpu1.l2cache.overall_mshr_miss_latency::total 3170226027 # number of overall MSHR miss cycles
2048system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13847750 # number of ReadReq MSHR uncacheable cycles
2049system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 382171500 # number of ReadReq MSHR uncacheable cycles
2050system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 396019250 # number of ReadReq MSHR uncacheable cycles
2051system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 261667000 # number of WriteReq MSHR uncacheable cycles
2052system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 261667000 # number of WriteReq MSHR uncacheable cycles
2053system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13847750 # number of overall MSHR uncacheable cycles
2054system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 643838500 # number of overall MSHR uncacheable cycles
2055system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 657686250 # number of overall MSHR uncacheable cycles
2056system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092442 # mshr miss rate for ReadReq accesses
2057system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.134441 # mshr miss rate for ReadReq accesses
2058system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.025741 # mshr miss rate for ReadReq accesses
2059system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.398950 # mshr miss rate for ReadReq accesses
2060system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.118864 # mshr miss rate for ReadReq accesses
2061system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2062system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2063system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.961724 # mshr miss rate for UpgradeReq accesses
2064system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.961724 # mshr miss rate for UpgradeReq accesses
2065system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.963119 # mshr miss rate for SCUpgradeReq accesses
2066system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.963119 # mshr miss rate for SCUpgradeReq accesses
2067system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2068system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2069system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.553345 # mshr miss rate for ReadExReq accesses
2070system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.553345 # mshr miss rate for ReadExReq accesses
2071system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.092442 # mshr miss rate for demand accesses
2072system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.134441 # mshr miss rate for demand accesses
2073system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.025741 # mshr miss rate for demand accesses
2074system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440360 # mshr miss rate for demand accesses
2075system.cpu1.l2cache.demand_mshr_miss_rate::total 0.155032 # mshr miss rate for demand accesses
2076system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.092442 # mshr miss rate for overall accesses
2077system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.134441 # mshr miss rate for overall accesses
2078system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.025741 # mshr miss rate for overall accesses
2079system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440360 # mshr miss rate for overall accesses
2080system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2081system.cpu1.l2cache.overall_mshr_miss_rate::total 0.185238 # mshr miss rate for overall accesses
2082system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average ReadReq mshr miss latency
2083system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average ReadReq mshr miss latency
2084system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average ReadReq mshr miss latency
2085system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15203.520159 # average ReadReq mshr miss latency
2086system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17407.869349 # average ReadReq mshr miss latency
2087system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109 # average HardPFReq mshr miss latency
2088system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33326.302109 # average HardPFReq mshr miss latency
2089system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15746.097009 # average UpgradeReq mshr miss latency
2090system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15746.097009 # average UpgradeReq mshr miss latency
2091system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15070.959850 # average SCUpgradeReq mshr miss latency
2092system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15070.959850 # average SCUpgradeReq mshr miss latency
2093system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 202850 # average SCUpgradeFailReq mshr miss latency
2094system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 202850 # average SCUpgradeFailReq mshr miss latency
2095system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30229.576224 # average ReadExReq mshr miss latency
2096system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30229.576224 # average ReadExReq mshr miss latency
2097system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average overall mshr miss latency
2098system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average overall mshr miss latency
2099system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average overall mshr miss latency
2100system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20267.625828 # average overall mshr miss latency
2101system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21217.453372 # average overall mshr miss latency
2102system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average overall mshr miss latency
2103system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average overall mshr miss latency
2104system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average overall mshr miss latency
2105system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20267.625828 # average overall mshr miss latency
2106system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109 # average overall mshr miss latency
2107system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23191.967716 # average overall mshr miss latency
2108system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706 # average ReadReq mshr uncacheable latency
2109system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 123920.719844 # average ReadReq mshr uncacheable latency
2110system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 121441.045692 # average ReadReq mshr uncacheable latency
2111system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107372.589249 # average WriteReq mshr uncacheable latency
2112system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107372.589249 # average WriteReq mshr uncacheable latency
2113system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706 # average overall mshr uncacheable latency
2114system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116616.283282 # average overall mshr uncacheable latency
2115system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 115424.052299 # average overall mshr uncacheable latency
2116system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2117system.cpu1.toL2Bus.trans_dist::ReadReq 1060646 # Transaction distribution
2118system.cpu1.toL2Bus.trans_dist::ReadResp 722071 # Transaction distribution
2119system.cpu1.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution
2120system.cpu1.toL2Bus.trans_dist::WriteResp 2437 # Transaction distribution
2121system.cpu1.toL2Bus.trans_dist::Writeback 114520 # Transaction distribution
2122system.cpu1.toL2Bus.trans_dist::HardPFReq 27384 # Transaction distribution
2123system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution
2124system.cpu1.toL2Bus.trans_dist::UpgradeReq 75380 # Transaction distribution
2125system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41410 # Transaction distribution
2126system.cpu1.toL2Bus.trans_dist::UpgradeResp 85537 # Transaction distribution
2127system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution
2128system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
2129system.cpu1.toL2Bus.trans_dist::ReadExReq 84086 # Transaction distribution
2130system.cpu1.toL2Bus.trans_dist::ReadExResp 66129 # Transaction distribution
2131system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1007310 # Packet count per connected master and slave (bytes)
2132system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 764894 # Packet count per connected master and slave (bytes)
2133system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5302 # Packet count per connected master and slave (bytes)
2134system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9429 # Packet count per connected master and slave (bytes)
2135system.cpu1.toL2Bus.pkt_count::total 1786935 # Packet count per connected master and slave (bytes)
2136system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32223300 # Cumulative packet size per connected master and slave (bytes)
2137system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24770860 # Cumulative packet size per connected master and slave (bytes)
2138system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7944 # Cumulative packet size per connected master and slave (bytes)
2139system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13760 # Cumulative packet size per connected master and slave (bytes)
2140system.cpu1.toL2Bus.pkt_size::total 57015864 # Cumulative packet size per connected master and slave (bytes)
2141system.cpu1.toL2Bus.snoops 636167 # Total snoops (count)
2142system.cpu1.toL2Bus.snoop_fanout::samples 1470628 # Request fanout histogram
2143system.cpu1.toL2Bus.snoop_fanout::mean 1.384445 # Request fanout histogram
2144system.cpu1.toL2Bus.snoop_fanout::stdev 0.486464 # Request fanout histogram
2145system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2146system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2147system.cpu1.toL2Bus.snoop_fanout::1 905253 61.56% 61.56% # Request fanout histogram
2148system.cpu1.toL2Bus.snoop_fanout::2 565375 38.44% 100.00% # Request fanout histogram
2149system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2150system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2151system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2152system.cpu1.toL2Bus.snoop_fanout::total 1470628 # Request fanout histogram
2153system.cpu1.toL2Bus.reqLayer0.occupancy 573017999 # Layer occupancy (ticks)
2154system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2155system.cpu1.toL2Bus.snoopLayer0.occupancy 81259000 # Layer occupancy (ticks)
2156system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2157system.cpu1.toL2Bus.respLayer0.occupancy 755831512 # Layer occupancy (ticks)
2158system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2159system.cpu1.toL2Bus.respLayer1.occupancy 377529095 # Layer occupancy (ticks)
2160system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2161system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks)
2162system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2163system.cpu1.toL2Bus.respLayer3.occupancy 5989250 # Layer occupancy (ticks)
2164system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2165system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
2166system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
2167system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
2168system.iobus.trans_dist::WriteResp 23198 # Transaction distribution
2169system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
2170system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
2171system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
2172system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
2173system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
2174system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
2175system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
2176system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
2177system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2178system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)

--- 4 unchanged lines hidden (view full) ---

2183system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2184system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2185system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2186system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2187system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2188system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2189system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2190system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2191system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
2192system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
2193system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
2194system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes)
2195system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
2196system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2197system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2198system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2199system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2200system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
2201system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2202system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2203system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)

--- 4 unchanged lines hidden (view full) ---

2208system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2209system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2210system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2211system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2212system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
2213system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2214system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
2215system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2216system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
2217system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
2218system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
2219system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes)
2220system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks)
2221system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2222system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
2223system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2224system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
2225system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2226system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
2227system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2228system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)

--- 23 unchanged lines hidden (view full) ---

2252system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
2253system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2254system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
2255system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2256system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
2257system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2258system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
2259system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2260system.iobus.reqLayer27.occupancy 199086925 # Layer occupancy (ticks)
2261system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2262system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2263system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2264system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
2265system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2266system.iobus.respLayer3.occupancy 36785519 # Layer occupancy (ticks)
2267system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2268system.iocache.tags.replacements 36445 # number of replacements
2269system.iocache.tags.tagsinuse 14.391068 # Cycle average of tags in use
2270system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2271system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
2272system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2273system.iocache.tags.warmup_cycle 288263513000 # Cycle when the warmup percentage was hit.
2274system.iocache.tags.occ_blocks::realview.ide 14.391068 # Average occupied blocks per requestor
2275system.iocache.tags.occ_percent::realview.ide 0.899442 # Average percentage of cache occupancy
2276system.iocache.tags.occ_percent::total 0.899442 # Average percentage of cache occupancy
2277system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2278system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2279system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2280system.iocache.tags.tag_accesses 328311 # Number of tag accesses
2281system.iocache.tags.data_accesses 328311 # Number of data accesses
2282system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses
2283system.iocache.ReadReq_misses::total 255 # number of ReadReq misses
2284system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
2285system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
2286system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses
2287system.iocache.demand_misses::total 255 # number of demand (read+write) misses
2288system.iocache.overall_misses::realview.ide 255 # number of overall misses
2289system.iocache.overall_misses::total 255 # number of overall misses
2290system.iocache.ReadReq_miss_latency::realview.ide 32671377 # number of ReadReq miss cycles
2291system.iocache.ReadReq_miss_latency::total 32671377 # number of ReadReq miss cycles
2292system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6655899029 # number of WriteInvalidateReq miss cycles
2293system.iocache.WriteInvalidateReq_miss_latency::total 6655899029 # number of WriteInvalidateReq miss cycles
2294system.iocache.demand_miss_latency::realview.ide 32671377 # number of demand (read+write) miss cycles
2295system.iocache.demand_miss_latency::total 32671377 # number of demand (read+write) miss cycles
2296system.iocache.overall_miss_latency::realview.ide 32671377 # number of overall miss cycles
2297system.iocache.overall_miss_latency::total 32671377 # number of overall miss cycles
2298system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses)
2299system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses)
2300system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
2301system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
2302system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses
2303system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses
2304system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses
2305system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses
2306system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2307system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2308system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
2309system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
2310system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2311system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2312system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2313system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2314system.iocache.ReadReq_avg_miss_latency::realview.ide 128123.047059 # average ReadReq miss latency
2315system.iocache.ReadReq_avg_miss_latency::total 128123.047059 # average ReadReq miss latency
2316system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183742.795633 # average WriteInvalidateReq miss latency
2317system.iocache.WriteInvalidateReq_avg_miss_latency::total 183742.795633 # average WriteInvalidateReq miss latency
2318system.iocache.demand_avg_miss_latency::realview.ide 128123.047059 # average overall miss latency
2319system.iocache.demand_avg_miss_latency::total 128123.047059 # average overall miss latency
2320system.iocache.overall_avg_miss_latency::realview.ide 128123.047059 # average overall miss latency
2321system.iocache.overall_avg_miss_latency::total 128123.047059 # average overall miss latency
2322system.iocache.blocked_cycles::no_mshrs 23173 # number of cycles access was blocked
2323system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2324system.iocache.blocked::no_mshrs 3543 # number of cycles access was blocked
2325system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2326system.iocache.avg_blocked_cycles::no_mshrs 6.540502 # average number of cycles each access was blocked
2327system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2328system.iocache.fast_writes 0 # number of fast writes performed
2329system.iocache.cache_copies 0 # number of cache copies performed
2330system.iocache.writebacks::writebacks 36190 # number of writebacks
2331system.iocache.writebacks::total 36190 # number of writebacks
2332system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses
2333system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses
2334system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
2335system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
2336system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses
2337system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses
2338system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses
2339system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses
2340system.iocache.ReadReq_mshr_miss_latency::realview.ide 19404377 # number of ReadReq MSHR miss cycles
2341system.iocache.ReadReq_mshr_miss_latency::total 19404377 # number of ReadReq MSHR miss cycles
2342system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772213067 # number of WriteInvalidateReq MSHR miss cycles
2343system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772213067 # number of WriteInvalidateReq MSHR miss cycles
2344system.iocache.demand_mshr_miss_latency::realview.ide 19404377 # number of demand (read+write) MSHR miss cycles
2345system.iocache.demand_mshr_miss_latency::total 19404377 # number of demand (read+write) MSHR miss cycles
2346system.iocache.overall_mshr_miss_latency::realview.ide 19404377 # number of overall MSHR miss cycles
2347system.iocache.overall_mshr_miss_latency::total 19404377 # number of overall MSHR miss cycles
2348system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2349system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2350system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
2351system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
2352system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2353system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2354system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2355system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2356system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76095.596078 # average ReadReq mshr miss latency
2357system.iocache.ReadReq_avg_mshr_miss_latency::total 76095.596078 # average ReadReq mshr miss latency
2358system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131741.747653 # average WriteInvalidateReq mshr miss latency
2359system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131741.747653 # average WriteInvalidateReq mshr miss latency
2360system.iocache.demand_avg_mshr_miss_latency::realview.ide 76095.596078 # average overall mshr miss latency
2361system.iocache.demand_avg_mshr_miss_latency::total 76095.596078 # average overall mshr miss latency
2362system.iocache.overall_avg_mshr_miss_latency::realview.ide 76095.596078 # average overall mshr miss latency
2363system.iocache.overall_avg_mshr_miss_latency::total 76095.596078 # average overall mshr miss latency
2364system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2365system.l2c.tags.replacements 122211 # number of replacements
2366system.l2c.tags.tagsinuse 63914.238063 # Cycle average of tags in use
2367system.l2c.tags.total_refs 336222 # Total number of references to valid blocks.
2368system.l2c.tags.sampled_refs 186592 # Sample count of references to valid blocks.
2369system.l2c.tags.avg_refs 1.801910 # Average number of references to valid blocks.
2370system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2371system.l2c.tags.occ_blocks::writebacks 11496.547602 # Average occupied blocks per requestor
2372system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.049900 # Average occupied blocks per requestor
2373system.l2c.tags.occ_blocks::cpu0.itb.walker 0.062133 # Average occupied blocks per requestor
2374system.l2c.tags.occ_blocks::cpu0.inst 7182.549375 # Average occupied blocks per requestor
2375system.l2c.tags.occ_blocks::cpu0.data 2988.985612 # Average occupied blocks per requestor
2376system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38830.864169 # Average occupied blocks per requestor
2377system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955834 # Average occupied blocks per requestor
2378system.l2c.tags.occ_blocks::cpu1.inst 1379.188596 # Average occupied blocks per requestor
2379system.l2c.tags.occ_blocks::cpu1.data 342.352201 # Average occupied blocks per requestor
2380system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1689.682641 # Average occupied blocks per requestor
2381system.l2c.tags.occ_percent::writebacks 0.175423 # Average percentage of cache occupancy
2382system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000047 # Average percentage of cache occupancy
2383system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2384system.l2c.tags.occ_percent::cpu0.inst 0.109597 # Average percentage of cache occupancy
2385system.l2c.tags.occ_percent::cpu0.data 0.045608 # Average percentage of cache occupancy
2386system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.592512 # Average percentage of cache occupancy
2387system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
2388system.l2c.tags.occ_percent::cpu1.inst 0.021045 # Average percentage of cache occupancy
2389system.l2c.tags.occ_percent::cpu1.data 0.005224 # Average percentage of cache occupancy
2390system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025783 # Average percentage of cache occupancy
2391system.l2c.tags.occ_percent::total 0.975254 # Average percentage of cache occupancy
2392system.l2c.tags.occ_task_id_blocks::1022 32922 # Occupied blocks per task id
2393system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
2394system.l2c.tags.occ_task_id_blocks::1024 31453 # Occupied blocks per task id
2395system.l2c.tags.age_task_id_blocks_1022::2 129 # Occupied blocks per task id
2396system.l2c.tags.age_task_id_blocks_1022::3 4653 # Occupied blocks per task id
2397system.l2c.tags.age_task_id_blocks_1022::4 28140 # Occupied blocks per task id
2398system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
2399system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
2400system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
2401system.l2c.tags.age_task_id_blocks_1024::2 241 # Occupied blocks per task id
2402system.l2c.tags.age_task_id_blocks_1024::3 1916 # Occupied blocks per task id
2403system.l2c.tags.age_task_id_blocks_1024::4 29284 # Occupied blocks per task id
2404system.l2c.tags.occ_task_id_percent::1022 0.502350 # Percentage of cache occupancy per task id
2405system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
2406system.l2c.tags.occ_task_id_percent::1024 0.479935 # Percentage of cache occupancy per task id
2407system.l2c.tags.tag_accesses 4784413 # Number of tag accesses
2408system.l2c.tags.data_accesses 4784413 # Number of data accesses
2409system.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits
2410system.l2c.ReadReq_hits::cpu0.itb.walker 62 # number of ReadReq hits
2411system.l2c.ReadReq_hits::cpu0.inst 29385 # number of ReadReq hits
2412system.l2c.ReadReq_hits::cpu0.data 44972 # number of ReadReq hits
2413system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45934 # number of ReadReq hits
2414system.l2c.ReadReq_hits::cpu1.dtb.walker 27 # number of ReadReq hits
2415system.l2c.ReadReq_hits::cpu1.itb.walker 29 # number of ReadReq hits
2416system.l2c.ReadReq_hits::cpu1.inst 10817 # number of ReadReq hits
2417system.l2c.ReadReq_hits::cpu1.data 7566 # number of ReadReq hits
2418system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4637 # number of ReadReq hits
2419system.l2c.ReadReq_hits::total 143498 # number of ReadReq hits
2420system.l2c.Writeback_hits::writebacks 220641 # number of Writeback hits
2421system.l2c.Writeback_hits::total 220641 # number of Writeback hits
2422system.l2c.UpgradeReq_hits::cpu0.data 2604 # number of UpgradeReq hits
2423system.l2c.UpgradeReq_hits::cpu1.data 702 # number of UpgradeReq hits
2424system.l2c.UpgradeReq_hits::total 3306 # number of UpgradeReq hits
2425system.l2c.SCUpgradeReq_hits::cpu0.data 145 # number of SCUpgradeReq hits
2426system.l2c.SCUpgradeReq_hits::cpu1.data 242 # number of SCUpgradeReq hits
2427system.l2c.SCUpgradeReq_hits::total 387 # number of SCUpgradeReq hits
2428system.l2c.ReadExReq_hits::cpu0.data 4135 # number of ReadExReq hits
2429system.l2c.ReadExReq_hits::cpu1.data 1764 # number of ReadExReq hits
2430system.l2c.ReadExReq_hits::total 5899 # number of ReadExReq hits
2431system.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits
2432system.l2c.demand_hits::cpu0.itb.walker 62 # number of demand (read+write) hits
2433system.l2c.demand_hits::cpu0.inst 29385 # number of demand (read+write) hits
2434system.l2c.demand_hits::cpu0.data 49107 # number of demand (read+write) hits
2435system.l2c.demand_hits::cpu0.l2cache.prefetcher 45934 # number of demand (read+write) hits
2436system.l2c.demand_hits::cpu1.dtb.walker 27 # number of demand (read+write) hits
2437system.l2c.demand_hits::cpu1.itb.walker 29 # number of demand (read+write) hits
2438system.l2c.demand_hits::cpu1.inst 10817 # number of demand (read+write) hits
2439system.l2c.demand_hits::cpu1.data 9330 # number of demand (read+write) hits
2440system.l2c.demand_hits::cpu1.l2cache.prefetcher 4637 # number of demand (read+write) hits
2441system.l2c.demand_hits::total 149397 # number of demand (read+write) hits
2442system.l2c.overall_hits::cpu0.dtb.walker 69 # number of overall hits
2443system.l2c.overall_hits::cpu0.itb.walker 62 # number of overall hits
2444system.l2c.overall_hits::cpu0.inst 29385 # number of overall hits
2445system.l2c.overall_hits::cpu0.data 49107 # number of overall hits
2446system.l2c.overall_hits::cpu0.l2cache.prefetcher 45934 # number of overall hits
2447system.l2c.overall_hits::cpu1.dtb.walker 27 # number of overall hits
2448system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits
2449system.l2c.overall_hits::cpu1.inst 10817 # number of overall hits
2450system.l2c.overall_hits::cpu1.data 9330 # number of overall hits
2451system.l2c.overall_hits::cpu1.l2cache.prefetcher 4637 # number of overall hits
2452system.l2c.overall_hits::total 149397 # number of overall hits
2453system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses
2454system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
2455system.l2c.ReadReq_misses::cpu0.inst 17693 # number of ReadReq misses
2456system.l2c.ReadReq_misses::cpu0.data 8817 # number of ReadReq misses
2457system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130884 # number of ReadReq misses
2458system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
2459system.l2c.ReadReq_misses::cpu1.inst 2143 # number of ReadReq misses
2460system.l2c.ReadReq_misses::cpu1.data 691 # number of ReadReq misses
2461system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5571 # number of ReadReq misses
2462system.l2c.ReadReq_misses::total 165808 # number of ReadReq misses
2463system.l2c.UpgradeReq_misses::cpu0.data 8462 # number of UpgradeReq misses
2464system.l2c.UpgradeReq_misses::cpu1.data 2686 # number of UpgradeReq misses
2465system.l2c.UpgradeReq_misses::total 11148 # number of UpgradeReq misses
2466system.l2c.SCUpgradeReq_misses::cpu0.data 478 # number of SCUpgradeReq misses
2467system.l2c.SCUpgradeReq_misses::cpu1.data 1247 # number of SCUpgradeReq misses
2468system.l2c.SCUpgradeReq_misses::total 1725 # number of SCUpgradeReq misses
2469system.l2c.ReadExReq_misses::cpu0.data 10966 # number of ReadExReq misses
2470system.l2c.ReadExReq_misses::cpu1.data 7268 # number of ReadExReq misses
2471system.l2c.ReadExReq_misses::total 18234 # number of ReadExReq misses
2472system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses
2473system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
2474system.l2c.demand_misses::cpu0.inst 17693 # number of demand (read+write) misses
2475system.l2c.demand_misses::cpu0.data 19783 # number of demand (read+write) misses
2476system.l2c.demand_misses::cpu0.l2cache.prefetcher 130884 # number of demand (read+write) misses
2477system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
2478system.l2c.demand_misses::cpu1.inst 2143 # number of demand (read+write) misses
2479system.l2c.demand_misses::cpu1.data 7959 # number of demand (read+write) misses
2480system.l2c.demand_misses::cpu1.l2cache.prefetcher 5571 # number of demand (read+write) misses
2481system.l2c.demand_misses::total 184042 # number of demand (read+write) misses
2482system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses
2483system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
2484system.l2c.overall_misses::cpu0.inst 17693 # number of overall misses
2485system.l2c.overall_misses::cpu0.data 19783 # number of overall misses
2486system.l2c.overall_misses::cpu0.l2cache.prefetcher 130884 # number of overall misses
2487system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
2488system.l2c.overall_misses::cpu1.inst 2143 # number of overall misses
2489system.l2c.overall_misses::cpu1.data 7959 # number of overall misses
2490system.l2c.overall_misses::cpu1.l2cache.prefetcher 5571 # number of overall misses
2491system.l2c.overall_misses::total 184042 # number of overall misses
2492system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 466750 # number of ReadReq miss cycles
2493system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165000 # number of ReadReq miss cycles
2494system.l2c.ReadReq_miss_latency::cpu0.inst 1430972014 # number of ReadReq miss cycles
2495system.l2c.ReadReq_miss_latency::cpu0.data 766150824 # number of ReadReq miss cycles
2496system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 12775683388 # number of ReadReq miss cycles
2497system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 96750 # number of ReadReq miss cycles
2498system.l2c.ReadReq_miss_latency::cpu1.inst 177373250 # number of ReadReq miss cycles
2499system.l2c.ReadReq_miss_latency::cpu1.data 73282238 # number of ReadReq miss cycles
2500system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 648312983 # number of ReadReq miss cycles
2501system.l2c.ReadReq_miss_latency::total 15872503197 # number of ReadReq miss cycles
2502system.l2c.UpgradeReq_miss_latency::cpu0.data 11409175 # number of UpgradeReq miss cycles
2503system.l2c.UpgradeReq_miss_latency::cpu1.data 2717413 # number of UpgradeReq miss cycles
2504system.l2c.UpgradeReq_miss_latency::total 14126588 # number of UpgradeReq miss cycles
2505system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1225466 # number of SCUpgradeReq miss cycles
2506system.l2c.SCUpgradeReq_miss_latency::cpu1.data 966969 # number of SCUpgradeReq miss cycles
2507system.l2c.SCUpgradeReq_miss_latency::total 2192435 # number of SCUpgradeReq miss cycles
2508system.l2c.ReadExReq_miss_latency::cpu0.data 964303159 # number of ReadExReq miss cycles
2509system.l2c.ReadExReq_miss_latency::cpu1.data 590306733 # number of ReadExReq miss cycles
2510system.l2c.ReadExReq_miss_latency::total 1554609892 # number of ReadExReq miss cycles
2511system.l2c.demand_miss_latency::cpu0.dtb.walker 466750 # number of demand (read+write) miss cycles
2512system.l2c.demand_miss_latency::cpu0.itb.walker 165000 # number of demand (read+write) miss cycles
2513system.l2c.demand_miss_latency::cpu0.inst 1430972014 # number of demand (read+write) miss cycles
2514system.l2c.demand_miss_latency::cpu0.data 1730453983 # number of demand (read+write) miss cycles
2515system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12775683388 # number of demand (read+write) miss cycles
2516system.l2c.demand_miss_latency::cpu1.dtb.walker 96750 # number of demand (read+write) miss cycles
2517system.l2c.demand_miss_latency::cpu1.inst 177373250 # number of demand (read+write) miss cycles
2518system.l2c.demand_miss_latency::cpu1.data 663588971 # number of demand (read+write) miss cycles
2519system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 648312983 # number of demand (read+write) miss cycles
2520system.l2c.demand_miss_latency::total 17427113089 # number of demand (read+write) miss cycles
2521system.l2c.overall_miss_latency::cpu0.dtb.walker 466750 # number of overall miss cycles
2522system.l2c.overall_miss_latency::cpu0.itb.walker 165000 # number of overall miss cycles
2523system.l2c.overall_miss_latency::cpu0.inst 1430972014 # number of overall miss cycles
2524system.l2c.overall_miss_latency::cpu0.data 1730453983 # number of overall miss cycles
2525system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12775683388 # number of overall miss cycles
2526system.l2c.overall_miss_latency::cpu1.dtb.walker 96750 # number of overall miss cycles
2527system.l2c.overall_miss_latency::cpu1.inst 177373250 # number of overall miss cycles
2528system.l2c.overall_miss_latency::cpu1.data 663588971 # number of overall miss cycles
2529system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 648312983 # number of overall miss cycles
2530system.l2c.overall_miss_latency::total 17427113089 # number of overall miss cycles
2531system.l2c.ReadReq_accesses::cpu0.dtb.walker 75 # number of ReadReq accesses(hits+misses)
2532system.l2c.ReadReq_accesses::cpu0.itb.walker 64 # number of ReadReq accesses(hits+misses)
2533system.l2c.ReadReq_accesses::cpu0.inst 47078 # number of ReadReq accesses(hits+misses)
2534system.l2c.ReadReq_accesses::cpu0.data 53789 # number of ReadReq accesses(hits+misses)
2535system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 176818 # number of ReadReq accesses(hits+misses)
2536system.l2c.ReadReq_accesses::cpu1.dtb.walker 28 # number of ReadReq accesses(hits+misses)
2537system.l2c.ReadReq_accesses::cpu1.itb.walker 29 # number of ReadReq accesses(hits+misses)
2538system.l2c.ReadReq_accesses::cpu1.inst 12960 # number of ReadReq accesses(hits+misses)
2539system.l2c.ReadReq_accesses::cpu1.data 8257 # number of ReadReq accesses(hits+misses)
2540system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 10208 # number of ReadReq accesses(hits+misses)
2541system.l2c.ReadReq_accesses::total 309306 # number of ReadReq accesses(hits+misses)
2542system.l2c.Writeback_accesses::writebacks 220641 # number of Writeback accesses(hits+misses)
2543system.l2c.Writeback_accesses::total 220641 # number of Writeback accesses(hits+misses)
2544system.l2c.UpgradeReq_accesses::cpu0.data 11066 # number of UpgradeReq accesses(hits+misses)
2545system.l2c.UpgradeReq_accesses::cpu1.data 3388 # number of UpgradeReq accesses(hits+misses)
2546system.l2c.UpgradeReq_accesses::total 14454 # number of UpgradeReq accesses(hits+misses)
2547system.l2c.SCUpgradeReq_accesses::cpu0.data 623 # number of SCUpgradeReq accesses(hits+misses)
2548system.l2c.SCUpgradeReq_accesses::cpu1.data 1489 # number of SCUpgradeReq accesses(hits+misses)
2549system.l2c.SCUpgradeReq_accesses::total 2112 # number of SCUpgradeReq accesses(hits+misses)
2550system.l2c.ReadExReq_accesses::cpu0.data 15101 # number of ReadExReq accesses(hits+misses)
2551system.l2c.ReadExReq_accesses::cpu1.data 9032 # number of ReadExReq accesses(hits+misses)
2552system.l2c.ReadExReq_accesses::total 24133 # number of ReadExReq accesses(hits+misses)
2553system.l2c.demand_accesses::cpu0.dtb.walker 75 # number of demand (read+write) accesses
2554system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses
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2558system.l2c.demand_accesses::cpu1.dtb.walker 28 # number of demand (read+write) accesses
2559system.l2c.demand_accesses::cpu1.itb.walker 29 # number of demand (read+write) accesses
2560system.l2c.demand_accesses::cpu1.inst 12960 # number of demand (read+write) accesses
2561system.l2c.demand_accesses::cpu1.data 17289 # number of demand (read+write) accesses
2562system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10208 # number of demand (read+write) accesses
2563system.l2c.demand_accesses::total 333439 # number of demand (read+write) accesses
2564system.l2c.overall_accesses::cpu0.dtb.walker 75 # number of overall (read+write) accesses
2565system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses
2566system.l2c.overall_accesses::cpu0.inst 47078 # number of overall (read+write) accesses
2567system.l2c.overall_accesses::cpu0.data 68890 # number of overall (read+write) accesses
2568system.l2c.overall_accesses::cpu0.l2cache.prefetcher 176818 # number of overall (read+write) accesses
2569system.l2c.overall_accesses::cpu1.dtb.walker 28 # number of overall (read+write) accesses
2570system.l2c.overall_accesses::cpu1.itb.walker 29 # number of overall (read+write) accesses
2571system.l2c.overall_accesses::cpu1.inst 12960 # number of overall (read+write) accesses
2572system.l2c.overall_accesses::cpu1.data 17289 # number of overall (read+write) accesses
2573system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10208 # number of overall (read+write) accesses
2574system.l2c.overall_accesses::total 333439 # number of overall (read+write) accesses
2575system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.080000 # miss rate for ReadReq accesses
2576system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.031250 # miss rate for ReadReq accesses
2577system.l2c.ReadReq_miss_rate::cpu0.inst 0.375823 # miss rate for ReadReq accesses
2578system.l2c.ReadReq_miss_rate::cpu0.data 0.163918 # miss rate for ReadReq accesses
2579system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.740219 # miss rate for ReadReq accesses
2580system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for ReadReq accesses
2581system.l2c.ReadReq_miss_rate::cpu1.inst 0.165355 # miss rate for ReadReq accesses
2582system.l2c.ReadReq_miss_rate::cpu1.data 0.083687 # miss rate for ReadReq accesses
2583system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.545748 # miss rate for ReadReq accesses
2584system.l2c.ReadReq_miss_rate::total 0.536065 # miss rate for ReadReq accesses
2585system.l2c.UpgradeReq_miss_rate::cpu0.data 0.764685 # miss rate for UpgradeReq accesses
2586system.l2c.UpgradeReq_miss_rate::cpu1.data 0.792798 # miss rate for UpgradeReq accesses
2587system.l2c.UpgradeReq_miss_rate::total 0.771274 # miss rate for UpgradeReq accesses
2588system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.767255 # miss rate for SCUpgradeReq accesses
2589system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.837475 # miss rate for SCUpgradeReq accesses
2590system.l2c.SCUpgradeReq_miss_rate::total 0.816761 # miss rate for SCUpgradeReq accesses
2591system.l2c.ReadExReq_miss_rate::cpu0.data 0.726177 # miss rate for ReadExReq accesses
2592system.l2c.ReadExReq_miss_rate::cpu1.data 0.804694 # miss rate for ReadExReq accesses
2593system.l2c.ReadExReq_miss_rate::total 0.755563 # miss rate for ReadExReq accesses
2594system.l2c.demand_miss_rate::cpu0.dtb.walker 0.080000 # miss rate for demand accesses
2595system.l2c.demand_miss_rate::cpu0.itb.walker 0.031250 # miss rate for demand accesses
2596system.l2c.demand_miss_rate::cpu0.inst 0.375823 # miss rate for demand accesses
2597system.l2c.demand_miss_rate::cpu0.data 0.287168 # miss rate for demand accesses
2598system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.740219 # miss rate for demand accesses
2599system.l2c.demand_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for demand accesses
2600system.l2c.demand_miss_rate::cpu1.inst 0.165355 # miss rate for demand accesses
2601system.l2c.demand_miss_rate::cpu1.data 0.460351 # miss rate for demand accesses
2602system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.545748 # miss rate for demand accesses
2603system.l2c.demand_miss_rate::total 0.551951 # miss rate for demand accesses
2604system.l2c.overall_miss_rate::cpu0.dtb.walker 0.080000 # miss rate for overall accesses
2605system.l2c.overall_miss_rate::cpu0.itb.walker 0.031250 # miss rate for overall accesses
2606system.l2c.overall_miss_rate::cpu0.inst 0.375823 # miss rate for overall accesses
2607system.l2c.overall_miss_rate::cpu0.data 0.287168 # miss rate for overall accesses
2608system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.740219 # miss rate for overall accesses
2609system.l2c.overall_miss_rate::cpu1.dtb.walker 0.035714 # miss rate for overall accesses
2610system.l2c.overall_miss_rate::cpu1.inst 0.165355 # miss rate for overall accesses
2611system.l2c.overall_miss_rate::cpu1.data 0.460351 # miss rate for overall accesses
2612system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.545748 # miss rate for overall accesses
2613system.l2c.overall_miss_rate::total 0.551951 # miss rate for overall accesses
2614system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77791.666667 # average ReadReq miss latency
2615system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency
2616system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80877.862092 # average ReadReq miss latency
2617system.l2c.ReadReq_avg_miss_latency::cpu0.data 86894.728819 # average ReadReq miss latency
2618system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605 # average ReadReq miss latency
2619system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 96750 # average ReadReq miss latency
2620system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82768.665422 # average ReadReq miss latency
2621system.l2c.ReadReq_avg_miss_latency::cpu1.data 106052.442836 # average ReadReq miss latency
2622system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499 # average ReadReq miss latency
2623system.l2c.ReadReq_avg_miss_latency::total 95728.210925 # average ReadReq miss latency
2624system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1348.283503 # average UpgradeReq miss latency
2625system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1011.695086 # average UpgradeReq miss latency
2626system.l2c.UpgradeReq_avg_miss_latency::total 1267.185863 # average UpgradeReq miss latency
2627system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2563.736402 # average SCUpgradeReq miss latency
2628system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 775.436247 # average SCUpgradeReq miss latency
2629system.l2c.SCUpgradeReq_avg_miss_latency::total 1270.976812 # average SCUpgradeReq miss latency
2630system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87935.724877 # average ReadExReq miss latency
2631system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81219.968767 # average ReadExReq miss latency
2632system.l2c.ReadExReq_avg_miss_latency::total 85258.851157 # average ReadExReq miss latency
2633system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77791.666667 # average overall miss latency
2634system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency
2635system.l2c.demand_avg_miss_latency::cpu0.inst 80877.862092 # average overall miss latency
2636system.l2c.demand_avg_miss_latency::cpu0.data 87471.767831 # average overall miss latency
2637system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605 # average overall miss latency
2638system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 96750 # average overall miss latency
2639system.l2c.demand_avg_miss_latency::cpu1.inst 82768.665422 # average overall miss latency
2640system.l2c.demand_avg_miss_latency::cpu1.data 83375.922980 # average overall miss latency
2641system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499 # average overall miss latency
2642system.l2c.demand_avg_miss_latency::total 94690.956896 # average overall miss latency
2643system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77791.666667 # average overall miss latency
2644system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency
2645system.l2c.overall_avg_miss_latency::cpu0.inst 80877.862092 # average overall miss latency
2646system.l2c.overall_avg_miss_latency::cpu0.data 87471.767831 # average overall miss latency
2647system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97610.734605 # average overall miss latency
2648system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 96750 # average overall miss latency
2649system.l2c.overall_avg_miss_latency::cpu1.inst 82768.665422 # average overall miss latency
2650system.l2c.overall_avg_miss_latency::cpu1.data 83375.922980 # average overall miss latency
2651system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116372.820499 # average overall miss latency
2652system.l2c.overall_avg_miss_latency::total 94690.956896 # average overall miss latency
2653system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2654system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2655system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
2656system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2657system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2658system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2659system.l2c.fast_writes 0 # number of fast writes performed
2660system.l2c.cache_copies 0 # number of cache copies performed
2661system.l2c.writebacks::writebacks 93389 # number of writebacks
2662system.l2c.writebacks::total 93389 # number of writebacks
2663system.l2c.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits
2664system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits
2665system.l2c.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits
2666system.l2c.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits
2667system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits
2668system.l2c.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits
2669system.l2c.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits
2670system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits
2671system.l2c.overall_mshr_hits::total 15 # number of overall MSHR hits
2672system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadReq MSHR misses
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2681system.l2c.ReadReq_mshr_misses::total 165793 # number of ReadReq MSHR misses
2682system.l2c.UpgradeReq_mshr_misses::cpu0.data 8462 # number of UpgradeReq MSHR misses
2683system.l2c.UpgradeReq_mshr_misses::cpu1.data 2686 # number of UpgradeReq MSHR misses
2684system.l2c.UpgradeReq_mshr_misses::total 11148 # number of UpgradeReq MSHR misses
2685system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 478 # number of SCUpgradeReq MSHR misses
2686system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1247 # number of SCUpgradeReq MSHR misses
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2710system.l2c.overall_mshr_misses::total 184027 # number of overall MSHR misses
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2714system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3080 # number of ReadReq MSHR uncacheable
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2729system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 83750 # number of ReadReq MSHR miss cycles
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2735system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47855180 # number of UpgradeReq MSHR miss cycles
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2737system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8594976 # number of SCUpgradeReq MSHR miss cycles
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2753system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 391750 # number of overall MSHR miss cycles
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2766system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 321686500 # number of ReadReq MSHR uncacheable cycles
2767system.l2c.ReadReq_mshr_uncacheable_latency::total 6187851250 # number of ReadReq MSHR uncacheable cycles
2768system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4077783000 # number of WriteReq MSHR uncacheable cycles
2769system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 216378500 # number of WriteReq MSHR uncacheable cycles
2770system.l2c.WriteReq_mshr_uncacheable_latency::total 4294161500 # number of WriteReq MSHR uncacheable cycles
2771system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 549810500 # number of overall MSHR uncacheable cycles
2772system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9383826500 # number of overall MSHR uncacheable cycles
2773system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10310750 # number of overall MSHR uncacheable cycles
2774system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538065000 # number of overall MSHR uncacheable cycles
2775system.l2c.overall_mshr_uncacheable_latency::total 10482012750 # number of overall MSHR uncacheable cycles
2776system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.080000 # mshr miss rate for ReadReq accesses
2777system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.031250 # mshr miss rate for ReadReq accesses
2778system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.375696 # mshr miss rate for ReadReq accesses
2779system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163918 # mshr miss rate for ReadReq accesses
2780system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740219 # mshr miss rate for ReadReq accesses
2781system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for ReadReq accesses
2782system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.164660 # mshr miss rate for ReadReq accesses
2783system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083687 # mshr miss rate for ReadReq accesses
2784system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545748 # mshr miss rate for ReadReq accesses
2785system.l2c.ReadReq_mshr_miss_rate::total 0.536016 # mshr miss rate for ReadReq accesses
2786system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.764685 # mshr miss rate for UpgradeReq accesses
2787system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.792798 # mshr miss rate for UpgradeReq accesses
2788system.l2c.UpgradeReq_mshr_miss_rate::total 0.771274 # mshr miss rate for UpgradeReq accesses
2789system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.767255 # mshr miss rate for SCUpgradeReq accesses
2790system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.837475 # mshr miss rate for SCUpgradeReq accesses
2791system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.816761 # mshr miss rate for SCUpgradeReq accesses
2792system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.726177 # mshr miss rate for ReadExReq accesses
2793system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.804694 # mshr miss rate for ReadExReq accesses
2794system.l2c.ReadExReq_mshr_miss_rate::total 0.755563 # mshr miss rate for ReadExReq accesses
2795system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.080000 # mshr miss rate for demand accesses
2796system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.031250 # mshr miss rate for demand accesses
2797system.l2c.demand_mshr_miss_rate::cpu0.inst 0.375696 # mshr miss rate for demand accesses
2798system.l2c.demand_mshr_miss_rate::cpu0.data 0.287168 # mshr miss rate for demand accesses
2799system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740219 # mshr miss rate for demand accesses
2800system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for demand accesses
2801system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164660 # mshr miss rate for demand accesses
2802system.l2c.demand_mshr_miss_rate::cpu1.data 0.460351 # mshr miss rate for demand accesses
2803system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545748 # mshr miss rate for demand accesses
2804system.l2c.demand_mshr_miss_rate::total 0.551906 # mshr miss rate for demand accesses
2805system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.080000 # mshr miss rate for overall accesses
2806system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.031250 # mshr miss rate for overall accesses
2807system.l2c.overall_mshr_miss_rate::cpu0.inst 0.375696 # mshr miss rate for overall accesses
2808system.l2c.overall_mshr_miss_rate::cpu0.data 0.287168 # mshr miss rate for overall accesses
2809system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.740219 # mshr miss rate for overall accesses
2810system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.035714 # mshr miss rate for overall accesses
2811system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164660 # mshr miss rate for overall accesses
2812system.l2c.overall_mshr_miss_rate::cpu1.data 0.460351 # mshr miss rate for overall accesses
2813system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.545748 # mshr miss rate for overall accesses
2814system.l2c.overall_mshr_miss_rate::total 0.551906 # mshr miss rate for overall accesses
2815system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average ReadReq mshr miss latency
2816system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency
2817system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average ReadReq mshr miss latency
2818system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74381.215379 # average ReadReq mshr miss latency
2819system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average ReadReq mshr miss latency
2820system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average ReadReq mshr miss latency
2821system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average ReadReq mshr miss latency
2822system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 93514.850941 # average ReadReq mshr miss latency
2823system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average ReadReq mshr miss latency
2824system.l2c.ReadReq_avg_mshr_miss_latency::total 83357.845597 # average ReadReq mshr miss latency
2825system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17858.360080 # average UpgradeReq mshr miss latency
2826system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17816.522710 # average UpgradeReq mshr miss latency
2827system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17848.279781 # average UpgradeReq mshr miss latency
2828system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17981.121339 # average SCUpgradeReq mshr miss latency
2829system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.105052 # average SCUpgradeReq mshr miss latency
2830system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17847.373333 # average SCUpgradeReq mshr miss latency
2831system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75573.120646 # average ReadExReq mshr miss latency
2832system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68714.125894 # average ReadExReq mshr miss latency
2833system.l2c.ReadExReq_avg_mshr_miss_latency::total 72839.152572 # average ReadExReq mshr miss latency
2834system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average overall mshr miss latency
2835system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
2836system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average overall mshr miss latency
2837system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75041.905525 # average overall mshr miss latency
2838system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average overall mshr miss latency
2839system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average overall mshr miss latency
2840system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average overall mshr miss latency
2841system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70867.323659 # average overall mshr miss latency
2842system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average overall mshr miss latency
2843system.l2c.demand_avg_mshr_miss_latency::total 82315.618920 # average overall mshr miss latency
2844system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average overall mshr miss latency
2845system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
2846system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average overall mshr miss latency
2847system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75041.905525 # average overall mshr miss latency
2848system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average overall mshr miss latency
2849system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average overall mshr miss latency
2850system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average overall mshr miss latency
2851system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70867.323659 # average overall mshr miss latency
2852system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average overall mshr miss latency
2853system.l2c.overall_avg_mshr_miss_latency::total 82315.618920 # average overall mshr miss latency
2854system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450 # average ReadReq mshr uncacheable latency
2855system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166987.993706 # average ReadReq mshr uncacheable latency
2856system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859 # average ReadReq mshr uncacheable latency
2857system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104443.668831 # average ReadReq mshr uncacheable latency
2858system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 140460.599492 # average ReadReq mshr uncacheable latency
2859system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143321.488823 # average WriteReq mshr uncacheable latency
2860system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88788.879770 # average WriteReq mshr uncacheable latency
2861system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 139019.116838 # average WriteReq mshr uncacheable latency
2862system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450 # average overall mshr uncacheable latency
2863system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155807.636110 # average overall mshr uncacheable latency
2864system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859 # average overall mshr uncacheable latency
2865system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97528.548124 # average overall mshr uncacheable latency
2866system.l2c.overall_avg_mshr_uncacheable_latency::total 139866.468516 # average overall mshr uncacheable latency
2867system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2868system.membus.trans_dist::ReadReq 210102 # Transaction distribution
2869system.membus.trans_dist::ReadResp 210102 # Transaction distribution
2870system.membus.trans_dist::WriteReq 30889 # Transaction distribution
2871system.membus.trans_dist::WriteResp 30889 # Transaction distribution
2872system.membus.trans_dist::Writeback 129579 # Transaction distribution
2873system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
2874system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
2875system.membus.trans_dist::UpgradeReq 77022 # Transaction distribution
2876system.membus.trans_dist::SCUpgradeReq 40122 # Transaction distribution
2877system.membus.trans_dist::UpgradeResp 12986 # Transaction distribution
2878system.membus.trans_dist::SCUpgradeFailReq 33 # Transaction distribution
2879system.membus.trans_dist::ReadExReq 38648 # Transaction distribution
2880system.membus.trans_dist::ReadExResp 18121 # Transaction distribution
2881system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
2882system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
2883system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13636 # Packet count per connected master and slave (bytes)
2884system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 639843 # Packet count per connected master and slave (bytes)
2885system.membus.pkt_count_system.l2c.mem_side::total 761429 # Packet count per connected master and slave (bytes)
2886system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes)
2887system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes)
2888system.membus.pkt_count::total 870337 # Packet count per connected master and slave (bytes)
2889system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
2890system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
2891system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27272 # Cumulative packet size per connected master and slave (bytes)
2892system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17781832 # Cumulative packet size per connected master and slave (bytes)
2893system.membus.pkt_size_system.l2c.mem_side::total 17971968 # Cumulative packet size per connected master and slave (bytes)
2894system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
2895system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
2896system.membus.pkt_size::total 22607424 # Cumulative packet size per connected master and slave (bytes)
2897system.membus.snoops 125322 # Total snoops (count)
2898system.membus.snoop_fanout::samples 562672 # Request fanout histogram
2899system.membus.snoop_fanout::mean 1 # Request fanout histogram
2900system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2901system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2902system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2903system.membus.snoop_fanout::1 562672 100.00% 100.00% # Request fanout histogram
2904system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2905system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2906system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2907system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2908system.membus.snoop_fanout::total 562672 # Request fanout histogram
2909system.membus.reqLayer0.occupancy 88118500 # Layer occupancy (ticks)
2910system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2911system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks)
2912system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2913system.membus.reqLayer2.occupancy 11425000 # Layer occupancy (ticks)
2914system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2915system.membus.reqLayer5.occupancy 1114763998 # Layer occupancy (ticks)
2916system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
2917system.membus.respLayer2.occupancy 1110191376 # Layer occupancy (ticks)
2918system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
2919system.membus.respLayer3.occupancy 37521481 # Layer occupancy (ticks)
2920system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2921system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2922system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2923system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2924system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2925system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2926system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2927system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR

--- 16 unchanged lines hidden (view full) ---

2944system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
2945system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2946system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2947system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2948system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2949system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2950system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
2951system.realview.ethernet.droppedPackets 0 # number of packets dropped
2952system.toL2Bus.trans_dist::ReadReq 475433 # Transaction distribution
2953system.toL2Bus.trans_dist::ReadResp 475418 # Transaction distribution
2954system.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution
2955system.toL2Bus.trans_dist::WriteResp 30889 # Transaction distribution
2956system.toL2Bus.trans_dist::Writeback 220641 # Transaction distribution
2957system.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution
2958system.toL2Bus.trans_dist::UpgradeReq 80215 # Transaction distribution
2959system.toL2Bus.trans_dist::SCUpgradeReq 40509 # Transaction distribution
2960system.toL2Bus.trans_dist::UpgradeResp 120724 # Transaction distribution
2961system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution
2962system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
2963system.toL2Bus.trans_dist::ReadExReq 50702 # Transaction distribution
2964system.toL2Bus.trans_dist::ReadExResp 50702 # Transaction distribution
2965system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1061225 # Packet count per connected master and slave (bytes)
2966system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 262179 # Packet count per connected master and slave (bytes)
2967system.toL2Bus.pkt_count::total 1323404 # Packet count per connected master and slave (bytes)
2968system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31467168 # Cumulative packet size per connected master and slave (bytes)
2969system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4256160 # Cumulative packet size per connected master and slave (bytes)
2970system.toL2Bus.pkt_size::total 35723328 # Cumulative packet size per connected master and slave (bytes)
2971system.toL2Bus.snoops 289388 # Total snoops (count)
2972system.toL2Bus.snoop_fanout::samples 934737 # Request fanout histogram
2973system.toL2Bus.snoop_fanout::mean 1.039071 # Request fanout histogram
2974system.toL2Bus.snoop_fanout::stdev 0.193764 # Request fanout histogram
2975system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2976system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2977system.toL2Bus.snoop_fanout::1 898216 96.09% 96.09% # Request fanout histogram
2978system.toL2Bus.snoop_fanout::2 36521 3.91% 100.00% # Request fanout histogram
2979system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2980system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2981system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2982system.toL2Bus.snoop_fanout::total 934737 # Request fanout histogram
2983system.toL2Bus.reqLayer0.occupancy 749457686 # Layer occupancy (ticks)
2984system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2985system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks)
2986system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2987system.toL2Bus.respLayer0.occupancy 652203239 # Layer occupancy (ticks)
2988system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2989system.toL2Bus.respLayer1.occupancy 220037759 # Layer occupancy (ticks)
2990system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2991
2992---------- End Simulation Statistics ----------