1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.866913 # Number of seconds simulated
4sim_ticks 2866913114000 # Number of ticks simulated
5final_tick 2866913114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 786450 # Simulator instruction rate (inst/s)
8host_op_rate 951292 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 17090693254 # Simulator tick rate (ticks/s)
10host_mem_usage 609256 # Number of bytes of host memory used
11host_seconds 167.75 # Real time elapsed on the host
12sim_insts 131924636 # Number of instructions simulated
13sim_ops 159576421 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 236004 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 838784 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 9619456 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 50964 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 440736 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 1362944 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
27system.physmem.bytes_read::total 12550680 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 236004 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 50964 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 286968 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 6395008 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
34system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
35system.physmem.bytes_written::total 8731088 # Number of bytes written to this memory
36system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.inst 12141 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.data 13632 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu0.l2cache.prefetcher 150304 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.inst 951 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.data 6910 # Number of read requests responded to by this memory
45system.physmem.num_reads::cpu1.l2cache.prefetcher 21296 # Number of read requests responded to by this memory
46system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
47system.physmem.num_reads::total 205262 # Number of read requests responded to by this memory
48system.physmem.num_writes::writebacks 99922 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
50system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
51system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
52system.physmem.num_writes::total 140582 # Number of write requests responded to by this memory
53system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.inst 82320 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu0.data 292574 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu0.l2cache.prefetcher 3355336 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.inst 17777 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::cpu1.data 153732 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::cpu1.l2cache.prefetcher 475405 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_read::total 4377768 # Total read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::cpu0.inst 82320 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_inst_read::cpu1.inst 17777 # Instruction read bandwidth from this memory (bytes/s)
67system.physmem.bw_inst_read::total 100097 # Instruction read bandwidth from this memory (bytes/s)
68system.physmem.bw_write::writebacks 2230625 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
71system.physmem.bw_write::realview.ide 808652 # Write bandwidth from this memory (bytes/s)
72system.physmem.bw_write::total 3045467 # Write bandwidth from this memory (bytes/s)
73system.physmem.bw_total::writebacks 2230625 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu0.inst 82320 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu0.data 298749 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu0.l2cache.prefetcher 3355336 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::cpu1.inst 17777 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::cpu1.data 153746 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::cpu1.l2cache.prefetcher 475405 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.bw_total::realview.ide 808987 # Total bandwidth to/from this memory (bytes/s)
85system.physmem.bw_total::total 7423234 # Total bandwidth to/from this memory (bytes/s)
86system.physmem.readReqs 205263 # Number of read requests accepted
87system.physmem.writeReqs 140582 # Number of write requests accepted
88system.physmem.readBursts 205263 # Number of DRAM read bursts, including those serviced by the write queue
89system.physmem.writeBursts 140582 # Number of DRAM write bursts, including those merged in the write queue
90system.physmem.bytesReadDRAM 13120768 # Total number of bytes read from DRAM
91system.physmem.bytesReadWrQ 16064 # Total number of bytes read from write queue
92system.physmem.bytesWritten 8744768 # Total number of bytes written to DRAM
93system.physmem.bytesReadSys 12550744 # Total read bytes from the system interface side
94system.physmem.bytesWrittenSys 8731088 # Total written bytes from the system interface side
95system.physmem.servicedByWrQ 251 # Number of DRAM read bursts serviced by the write queue
96system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one
97system.physmem.neitherReadNorWriteReqs 15112 # Number of requests that are neither read nor write
98system.physmem.perBankRdBursts::0 12846 # Per bank write bursts
99system.physmem.perBankRdBursts::1 12299 # Per bank write bursts
100system.physmem.perBankRdBursts::2 13037 # Per bank write bursts
101system.physmem.perBankRdBursts::3 12736 # Per bank write bursts
102system.physmem.perBankRdBursts::4 21227 # Per bank write bursts
103system.physmem.perBankRdBursts::5 12513 # Per bank write bursts
104system.physmem.perBankRdBursts::6 12853 # Per bank write bursts
105system.physmem.perBankRdBursts::7 12957 # Per bank write bursts
106system.physmem.perBankRdBursts::8 12050 # Per bank write bursts
107system.physmem.perBankRdBursts::9 12106 # Per bank write bursts
108system.physmem.perBankRdBursts::10 12270 # Per bank write bursts
109system.physmem.perBankRdBursts::11 11010 # Per bank write bursts
110system.physmem.perBankRdBursts::12 11804 # Per bank write bursts
111system.physmem.perBankRdBursts::13 12158 # Per bank write bursts
112system.physmem.perBankRdBursts::14 11709 # Per bank write bursts
113system.physmem.perBankRdBursts::15 11437 # Per bank write bursts
114system.physmem.perBankWrBursts::0 8735 # Per bank write bursts
115system.physmem.perBankWrBursts::1 8638 # Per bank write bursts
116system.physmem.perBankWrBursts::2 9213 # Per bank write bursts
117system.physmem.perBankWrBursts::3 8824 # Per bank write bursts
118system.physmem.perBankWrBursts::4 8594 # Per bank write bursts
119system.physmem.perBankWrBursts::5 8713 # Per bank write bursts
120system.physmem.perBankWrBursts::6 8840 # Per bank write bursts
121system.physmem.perBankWrBursts::7 8875 # Per bank write bursts
122system.physmem.perBankWrBursts::8 8399 # Per bank write bursts
123system.physmem.perBankWrBursts::9 8546 # Per bank write bursts
124system.physmem.perBankWrBursts::10 8611 # Per bank write bursts
125system.physmem.perBankWrBursts::11 8118 # Per bank write bursts
126system.physmem.perBankWrBursts::12 8409 # Per bank write bursts
127system.physmem.perBankWrBursts::13 8327 # Per bank write bursts
128system.physmem.perBankWrBursts::14 8185 # Per bank write bursts
129system.physmem.perBankWrBursts::15 7610 # Per bank write bursts
130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
131system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
132system.physmem.totGap 2866912757000 # Total gap between requests
133system.physmem.readPktSize::0 0 # Read request sizes (log2)
134system.physmem.readPktSize::1 0 # Read request sizes (log2)
135system.physmem.readPktSize::2 9742 # Read request sizes (log2)
136system.physmem.readPktSize::3 28 # Read request sizes (log2)
137system.physmem.readPktSize::4 0 # Read request sizes (log2)
138system.physmem.readPktSize::5 0 # Read request sizes (log2)
139system.physmem.readPktSize::6 195493 # Read request sizes (log2)
140system.physmem.writePktSize::0 0 # Write request sizes (log2)
141system.physmem.writePktSize::1 0 # Write request sizes (log2)
142system.physmem.writePktSize::2 4436 # Write request sizes (log2)
143system.physmem.writePktSize::3 0 # Write request sizes (log2)
144system.physmem.writePktSize::4 0 # Write request sizes (log2)
145system.physmem.writePktSize::5 0 # Write request sizes (log2)
146system.physmem.writePktSize::6 136146 # Write request sizes (log2)
147system.physmem.rdQLenPdf::0 121382 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::1 21626 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::2 13280 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::3 11136 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::4 9518 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::5 8180 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::6 7045 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::7 6231 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::8 5373 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::9 545 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::10 257 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::12 124 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::13 75 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::14 45 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::15 20 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see
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186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::15 2735 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::16 3299 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::17 4161 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::18 5644 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::19 6286 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::21 7599 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::22 8387 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::23 9040 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::24 10168 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::25 9789 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::26 9520 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::27 9266 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::28 9593 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::29 7897 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::30 7694 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::31 7605 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::32 7159 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::33 409 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::34 348 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::37 196 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::38 201 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::43 128 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::44 116 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::49 101 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::50 91 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::52 66 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::54 60 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::58 26 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see
240system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see
241system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see
242system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see
243system.physmem.bytesPerActivate::samples 80938 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::mean 270.150881 # Bytes accessed per row activation
245system.physmem.bytesPerActivate::gmean 152.124225 # Bytes accessed per row activation
246system.physmem.bytesPerActivate::stdev 319.049708 # Bytes accessed per row activation
247system.physmem.bytesPerActivate::0-127 39103 48.31% 48.31% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::128-255 16130 19.93% 68.24% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::256-383 6485 8.01% 76.25% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::384-511 3355 4.15% 80.40% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::512-639 3128 3.86% 84.26% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::640-767 1920 2.37% 86.64% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::768-895 1075 1.33% 87.96% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::896-1023 1014 1.25% 89.22% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::1024-1151 8728 10.78% 100.00% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::total 80938 # Bytes accessed per row activation
257system.physmem.rdPerTurnAround::samples 6722 # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::mean 30.497025 # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::stdev 543.729847 # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::0-2047 6720 99.97% 99.97% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
262system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
263system.physmem.rdPerTurnAround::total 6722 # Reads before turning the bus around for writes
264system.physmem.wrPerTurnAround::samples 6722 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::mean 20.326837 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::gmean 18.830242 # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::stdev 11.742760 # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::16-19 5511 81.98% 81.98% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::20-23 381 5.67% 87.65% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::24-27 92 1.37% 89.02% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::28-31 211 3.14% 92.16% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::32-35 209 3.11% 95.27% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::36-39 21 0.31% 95.58% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::40-43 13 0.19% 95.78% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::44-47 14 0.21% 95.98% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::48-51 24 0.36% 96.34% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::52-55 8 0.12% 96.46% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::56-59 5 0.07% 96.53% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::60-63 4 0.06% 96.59% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::64-67 163 2.42% 99.02% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::68-71 8 0.12% 99.14% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::72-75 4 0.06% 99.20% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::80-83 17 0.25% 99.49% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::84-87 1 0.01% 99.51% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::88-91 1 0.01% 99.52% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::108-111 3 0.04% 99.69% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::112-115 7 0.10% 99.79% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::116-119 2 0.03% 99.82% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::152-155 1 0.01% 100.00% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::total 6722 # Writes before turning the bus around for reads
297system.physmem.totQLat 5976562250 # Total ticks spent queuing
298system.physmem.totMemAccLat 9820537250 # Total ticks spent from burst creation until serviced by the DRAM
299system.physmem.totBusLat 1025060000 # Total ticks spent in databus transfers
300system.physmem.avgQLat 29152.26 # Average queueing delay per DRAM burst
301system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
302system.physmem.avgMemAccLat 47902.26 # Average memory access latency per DRAM burst
303system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s
304system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s
305system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s
306system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s
307system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
308system.physmem.busUtil 0.06 # Data bus utilization in percentage
309system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
310system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
311system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing
312system.physmem.avgWrQLen 23.80 # Average write queue length when enqueuing
313system.physmem.readRowHits 175010 # Number of row buffer hits during reads
314system.physmem.writeRowHits 85700 # Number of row buffer hits during writes
315system.physmem.readRowHitRate 85.37 # Row buffer hit rate for reads
316system.physmem.writeRowHitRate 62.71 # Row buffer hit rate for writes
317system.physmem.avgGap 8289588.56 # Average gap between requests
318system.physmem.pageHitRate 76.30 # Row buffer hit rate, read and write combined
319system.physmem.memoryStateTime::IDLE 2731202883250 # Time in different power states
320system.physmem.memoryStateTime::REF 95732520000 # Time in different power states
321system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
322system.physmem.memoryStateTime::ACT 39977707750 # Time in different power states
323system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
324system.physmem.actEnergy::0 322237440 # Energy for activate commands per rank (pJ)
325system.physmem.actEnergy::1 289653840 # Energy for activate commands per rank (pJ)
326system.physmem.preEnergy::0 175824000 # Energy for precharge commands per rank (pJ)
327system.physmem.preEnergy::1 158045250 # Energy for precharge commands per rank (pJ)
328system.physmem.readEnergy::0 861650400 # Energy for read commands per rank (pJ)
329system.physmem.readEnergy::1 737435400 # Energy for read commands per rank (pJ)
330system.physmem.writeEnergy::0 456399360 # Energy for write commands per rank (pJ)
331system.physmem.writeEnergy::1 429008400 # Energy for write commands per rank (pJ)
332system.physmem.refreshEnergy::0 187252809120 # Energy for refresh commands per rank (pJ)
333system.physmem.refreshEnergy::1 187252809120 # Energy for refresh commands per rank (pJ)
334system.physmem.actBackEnergy::0 82565899920 # Energy for active background per rank (pJ)
335system.physmem.actBackEnergy::1 81397166220 # Energy for active background per rank (pJ)
336system.physmem.preBackEnergy::0 1647721613250 # Energy for precharge background per rank (pJ)
337system.physmem.preBackEnergy::1 1648746818250 # Energy for precharge background per rank (pJ)
338system.physmem.totalEnergy::0 1919356433490 # Total energy per rank (pJ)
339system.physmem.totalEnergy::1 1919010936480 # Total energy per rank (pJ)
340system.physmem.averagePower::0 669.485397 # Core power per rank (mW)
341system.physmem.averagePower::1 669.364885 # Core power per rank (mW)
342system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
343system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
344system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
345system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
346system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
347system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
348system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
349system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
350system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
351system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
352system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s)
353system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s)
354system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
355system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s)
356system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s)
357system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
358system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
359system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
360system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
361system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
362system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
363system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
364system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
365system.cf0.dma_write_txs 631 # Number of DMA write transactions.
366system.cpu_clk_domain.clock 500 # Clock period in ticks
367system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
368system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
369system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
370system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
371system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
372system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
373system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
374system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 7 unchanged lines hidden (view full) ---

382system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
383system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
384system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
385system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
386system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
387system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
388system.cpu0.dtb.inst_hits 0 # ITB inst hits
389system.cpu0.dtb.inst_misses 0 # ITB inst misses
390system.cpu0.dtb.read_hits 24351477 # DTB read hits
391system.cpu0.dtb.read_misses 6408 # DTB read misses
392system.cpu0.dtb.write_hits 18124986 # DTB write hits
393system.cpu0.dtb.write_misses 1114 # DTB write misses
394system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
395system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
396system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
397system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
398system.cpu0.dtb.flush_entries 3406 # Number of entries that have been flushed from TLB
399system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
400system.cpu0.dtb.prefetch_faults 1440 # Number of TLB faults due to prefetch
401system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
402system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
403system.cpu0.dtb.read_accesses 24357885 # DTB read accesses
404system.cpu0.dtb.write_accesses 18126100 # DTB write accesses
405system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
406system.cpu0.dtb.hits 42476463 # DTB hits
407system.cpu0.dtb.misses 7522 # DTB misses
408system.cpu0.dtb.accesses 42483985 # DTB accesses
409system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
410system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
411system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
412system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
413system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
414system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
415system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
416system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

422system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
423system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
424system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
425system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
426system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
427system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
428system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
429system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
430system.cpu0.itb.inst_hits 115065570 # ITB inst hits
431system.cpu0.itb.inst_misses 3350 # ITB inst misses
432system.cpu0.itb.read_hits 0 # DTB read hits
433system.cpu0.itb.read_misses 0 # DTB read misses
434system.cpu0.itb.write_hits 0 # DTB write hits
435system.cpu0.itb.write_misses 0 # DTB write misses
436system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
437system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
438system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
439system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
440system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB
441system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
442system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
443system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
444system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
445system.cpu0.itb.read_accesses 0 # DTB read accesses
446system.cpu0.itb.write_accesses 0 # DTB write accesses
447system.cpu0.itb.inst_accesses 115068920 # ITB inst accesses
448system.cpu0.itb.hits 115065570 # DTB hits
449system.cpu0.itb.misses 3350 # DTB misses
450system.cpu0.itb.accesses 115068920 # DTB accesses
451system.cpu0.numCycles 5733826228 # number of cpu cycles simulated
452system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
453system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
454system.cpu0.committedInsts 111421445 # Number of instructions committed
455system.cpu0.committedOps 134708041 # Number of ops (including micro ops) committed
456system.cpu0.num_int_alu_accesses 119418221 # Number of integer alu accesses
457system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
458system.cpu0.num_func_calls 12527454 # number of times a function call or return occured
459system.cpu0.num_conditional_control_insts 14979151 # number of instructions that are conditional controls
460system.cpu0.num_int_insts 119418221 # number of integer instructions
461system.cpu0.num_fp_insts 9755 # number of float instructions
462system.cpu0.num_int_register_reads 220362058 # number of times the integer registers were read
463system.cpu0.num_int_register_writes 83043778 # number of times the integer registers were written
464system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
465system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
466system.cpu0.num_cc_register_reads 488373650 # number of times the CC registers were read
467system.cpu0.num_cc_register_writes 49988627 # number of times the CC registers were written
468system.cpu0.num_mem_refs 43585923 # number of memory refs
469system.cpu0.num_load_insts 24597873 # Number of load instructions
470system.cpu0.num_store_insts 18988050 # Number of store instructions
471system.cpu0.num_idle_cycles 5477680330.504089 # Number of idle cycles
472system.cpu0.num_busy_cycles 256145897.495911 # Number of busy cycles
473system.cpu0.not_idle_fraction 0.044673 # Percentage of non-idle cycles
474system.cpu0.idle_fraction 0.955327 # Percentage of idle cycles
475system.cpu0.Branches 28215151 # Number of branches fetched
476system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction
477system.cpu0.op_class::IntAlu 94727035 68.43% 68.43% # Class of executed instruction
478system.cpu0.op_class::IntMult 104174 0.08% 68.51% # Class of executed instruction
479system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction
480system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction
481system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction
482system.cpu0.op_class::FloatCvt 0 0.00% 68.51% # Class of executed instruction
483system.cpu0.op_class::FloatMult 0 0.00% 68.51% # Class of executed instruction
484system.cpu0.op_class::FloatDiv 0 0.00% 68.51% # Class of executed instruction
485system.cpu0.op_class::FloatSqrt 0 0.00% 68.51% # Class of executed instruction
486system.cpu0.op_class::SimdAdd 0 0.00% 68.51% # Class of executed instruction

--- 7 unchanged lines hidden (view full) ---

494system.cpu0.op_class::SimdShift 0 0.00% 68.51% # Class of executed instruction
495system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.51% # Class of executed instruction
496system.cpu0.op_class::SimdSqrt 0 0.00% 68.51% # Class of executed instruction
497system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.51% # Class of executed instruction
498system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.51% # Class of executed instruction
499system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction
500system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction
501system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction
502system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction
503system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction
504system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction
505system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction
506system.cpu0.op_class::MemRead 24597873 17.77% 86.28% # Class of executed instruction
507system.cpu0.op_class::MemWrite 18988050 13.72% 100.00% # Class of executed instruction
508system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
509system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
510system.cpu0.op_class::total 138426785 # Class of executed instruction
511system.cpu0.kern.inst.arm 0 # number of arm instructions executed
512system.cpu0.kern.inst.quiesce 2075 # number of quiesce instructions executed
513system.cpu0.dcache.tags.replacements 658574 # number of replacements
514system.cpu0.dcache.tags.tagsinuse 484.573597 # Cycle average of tags in use
515system.cpu0.dcache.tags.total_refs 41679745 # Total number of references to valid blocks.
516system.cpu0.dcache.tags.sampled_refs 659086 # Sample count of references to valid blocks.
517system.cpu0.dcache.tags.avg_refs 63.238705 # Average number of references to valid blocks.
518system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit.
519system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.573597 # Average occupied blocks per requestor
520system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946433 # Average percentage of cache occupancy
521system.cpu0.dcache.tags.occ_percent::total 0.946433 # Average percentage of cache occupancy
522system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
523system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
524system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
525system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id
526system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
527system.cpu0.dcache.tags.tag_accesses 85564578 # Number of tag accesses
528system.cpu0.dcache.tags.data_accesses 85564578 # Number of data accesses
529system.cpu0.dcache.ReadReq_hits::cpu0.data 23153254 # number of ReadReq hits
530system.cpu0.dcache.ReadReq_hits::total 23153254 # number of ReadReq hits
531system.cpu0.dcache.WriteReq_hits::cpu0.data 17430094 # number of WriteReq hits
532system.cpu0.dcache.WriteReq_hits::total 17430094 # number of WriteReq hits
533system.cpu0.dcache.SoftPFReq_hits::cpu0.data 323112 # number of SoftPFReq hits
534system.cpu0.dcache.SoftPFReq_hits::total 323112 # number of SoftPFReq hits
535system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358254 # number of LoadLockedReq hits
536system.cpu0.dcache.LoadLockedReq_hits::total 358254 # number of LoadLockedReq hits
537system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353760 # number of StoreCondReq hits
538system.cpu0.dcache.StoreCondReq_hits::total 353760 # number of StoreCondReq hits
539system.cpu0.dcache.demand_hits::cpu0.data 40583348 # number of demand (read+write) hits
540system.cpu0.dcache.demand_hits::total 40583348 # number of demand (read+write) hits
541system.cpu0.dcache.overall_hits::cpu0.data 40906460 # number of overall hits
542system.cpu0.dcache.overall_hits::total 40906460 # number of overall hits
543system.cpu0.dcache.ReadReq_misses::cpu0.data 360294 # number of ReadReq misses
544system.cpu0.dcache.ReadReq_misses::total 360294 # number of ReadReq misses
545system.cpu0.dcache.WriteReq_misses::cpu0.data 297575 # number of WriteReq misses
546system.cpu0.dcache.WriteReq_misses::total 297575 # number of WriteReq misses
547system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106237 # number of SoftPFReq misses
548system.cpu0.dcache.SoftPFReq_misses::total 106237 # number of SoftPFReq misses
549system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21398 # number of LoadLockedReq misses
550system.cpu0.dcache.LoadLockedReq_misses::total 21398 # number of LoadLockedReq misses
551system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21370 # number of StoreCondReq misses
552system.cpu0.dcache.StoreCondReq_misses::total 21370 # number of StoreCondReq misses
553system.cpu0.dcache.demand_misses::cpu0.data 657869 # number of demand (read+write) misses
554system.cpu0.dcache.demand_misses::total 657869 # number of demand (read+write) misses
555system.cpu0.dcache.overall_misses::cpu0.data 764106 # number of overall misses
556system.cpu0.dcache.overall_misses::total 764106 # number of overall misses
557system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4477052020 # number of ReadReq miss cycles
558system.cpu0.dcache.ReadReq_miss_latency::total 4477052020 # number of ReadReq miss cycles
559system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4450265428 # number of WriteReq miss cycles
560system.cpu0.dcache.WriteReq_miss_latency::total 4450265428 # number of WriteReq miss cycles
561system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 335153501 # number of LoadLockedReq miss cycles
562system.cpu0.dcache.LoadLockedReq_miss_latency::total 335153501 # number of LoadLockedReq miss cycles
563system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 473430117 # number of StoreCondReq miss cycles
564system.cpu0.dcache.StoreCondReq_miss_latency::total 473430117 # number of StoreCondReq miss cycles
565system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1336000 # number of StoreCondFailReq miss cycles
566system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1336000 # number of StoreCondFailReq miss cycles
567system.cpu0.dcache.demand_miss_latency::cpu0.data 8927317448 # number of demand (read+write) miss cycles
568system.cpu0.dcache.demand_miss_latency::total 8927317448 # number of demand (read+write) miss cycles
569system.cpu0.dcache.overall_miss_latency::cpu0.data 8927317448 # number of overall miss cycles
570system.cpu0.dcache.overall_miss_latency::total 8927317448 # number of overall miss cycles
571system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513548 # number of ReadReq accesses(hits+misses)
572system.cpu0.dcache.ReadReq_accesses::total 23513548 # number of ReadReq accesses(hits+misses)
573system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727669 # number of WriteReq accesses(hits+misses)
574system.cpu0.dcache.WriteReq_accesses::total 17727669 # number of WriteReq accesses(hits+misses)
575system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429349 # number of SoftPFReq accesses(hits+misses)
576system.cpu0.dcache.SoftPFReq_accesses::total 429349 # number of SoftPFReq accesses(hits+misses)
577system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379652 # number of LoadLockedReq accesses(hits+misses)
578system.cpu0.dcache.LoadLockedReq_accesses::total 379652 # number of LoadLockedReq accesses(hits+misses)
579system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375130 # number of StoreCondReq accesses(hits+misses)
580system.cpu0.dcache.StoreCondReq_accesses::total 375130 # number of StoreCondReq accesses(hits+misses)
581system.cpu0.dcache.demand_accesses::cpu0.data 41241217 # number of demand (read+write) accesses
582system.cpu0.dcache.demand_accesses::total 41241217 # number of demand (read+write) accesses
583system.cpu0.dcache.overall_accesses::cpu0.data 41670566 # number of overall (read+write) accesses
584system.cpu0.dcache.overall_accesses::total 41670566 # number of overall (read+write) accesses
585system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015323 # miss rate for ReadReq accesses
586system.cpu0.dcache.ReadReq_miss_rate::total 0.015323 # miss rate for ReadReq accesses
587system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016786 # miss rate for WriteReq accesses
588system.cpu0.dcache.WriteReq_miss_rate::total 0.016786 # miss rate for WriteReq accesses
589system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247437 # miss rate for SoftPFReq accesses
590system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247437 # miss rate for SoftPFReq accesses
591system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056362 # miss rate for LoadLockedReq accesses
592system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056362 # miss rate for LoadLockedReq accesses
593system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056967 # miss rate for StoreCondReq accesses
594system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056967 # miss rate for StoreCondReq accesses
595system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015952 # miss rate for demand accesses
596system.cpu0.dcache.demand_miss_rate::total 0.015952 # miss rate for demand accesses
597system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018337 # miss rate for overall accesses
598system.cpu0.dcache.overall_miss_rate::total 0.018337 # miss rate for overall accesses
599system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12426.107623 # average ReadReq miss latency
600system.cpu0.dcache.ReadReq_avg_miss_latency::total 12426.107623 # average ReadReq miss latency
601system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14955.105194 # average WriteReq miss latency
602system.cpu0.dcache.WriteReq_avg_miss_latency::total 14955.105194 # average WriteReq miss latency
603system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15662.842368 # average LoadLockedReq miss latency
604system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15662.842368 # average LoadLockedReq miss latency
605system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.959616 # average StoreCondReq miss latency
606system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.959616 # average StoreCondReq miss latency
607system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
608system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
609system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13570.053381 # average overall miss latency
610system.cpu0.dcache.demand_avg_miss_latency::total 13570.053381 # average overall miss latency
611system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11683.349493 # average overall miss latency
612system.cpu0.dcache.overall_avg_miss_latency::total 11683.349493 # average overall miss latency
613system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
614system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
615system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
616system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
617system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
618system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
619system.cpu0.dcache.fast_writes 0 # number of fast writes performed
620system.cpu0.dcache.cache_copies 0 # number of cache copies performed
621system.cpu0.dcache.writebacks::writebacks 483361 # number of writebacks
622system.cpu0.dcache.writebacks::total 483361 # number of writebacks
623system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7378 # number of ReadReq MSHR hits
624system.cpu0.dcache.ReadReq_mshr_hits::total 7378 # number of ReadReq MSHR hits
625system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15071 # number of LoadLockedReq MSHR hits
626system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15071 # number of LoadLockedReq MSHR hits
627system.cpu0.dcache.demand_mshr_hits::cpu0.data 7378 # number of demand (read+write) MSHR hits
628system.cpu0.dcache.demand_mshr_hits::total 7378 # number of demand (read+write) MSHR hits
629system.cpu0.dcache.overall_mshr_hits::cpu0.data 7378 # number of overall MSHR hits
630system.cpu0.dcache.overall_mshr_hits::total 7378 # number of overall MSHR hits
631system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 352916 # number of ReadReq MSHR misses
632system.cpu0.dcache.ReadReq_mshr_misses::total 352916 # number of ReadReq MSHR misses
633system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297575 # number of WriteReq MSHR misses
634system.cpu0.dcache.WriteReq_mshr_misses::total 297575 # number of WriteReq MSHR misses
635system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 96924 # number of SoftPFReq MSHR misses
636system.cpu0.dcache.SoftPFReq_mshr_misses::total 96924 # number of SoftPFReq MSHR misses
637system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6327 # number of LoadLockedReq MSHR misses
638system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6327 # number of LoadLockedReq MSHR misses
639system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21370 # number of StoreCondReq MSHR misses
640system.cpu0.dcache.StoreCondReq_mshr_misses::total 21370 # number of StoreCondReq MSHR misses
641system.cpu0.dcache.demand_mshr_misses::cpu0.data 650491 # number of demand (read+write) MSHR misses
642system.cpu0.dcache.demand_mshr_misses::total 650491 # number of demand (read+write) MSHR misses
643system.cpu0.dcache.overall_mshr_misses::cpu0.data 747415 # number of overall MSHR misses
644system.cpu0.dcache.overall_mshr_misses::total 747415 # number of overall MSHR misses
645system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3678269480 # number of ReadReq MSHR miss cycles
646system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3678269480 # number of ReadReq MSHR miss cycles
647system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3844865572 # number of WriteReq MSHR miss cycles
648system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3844865572 # number of WriteReq MSHR miss cycles
649system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1196073992 # number of SoftPFReq MSHR miss cycles
650system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1196073992 # number of SoftPFReq MSHR miss cycles
651system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89532500 # number of LoadLockedReq MSHR miss cycles
652system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89532500 # number of LoadLockedReq MSHR miss cycles
653system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429878883 # number of StoreCondReq MSHR miss cycles
654system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429878883 # number of StoreCondReq MSHR miss cycles
655system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1262000 # number of StoreCondFailReq MSHR miss cycles
656system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1262000 # number of StoreCondFailReq MSHR miss cycles
657system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523135052 # number of demand (read+write) MSHR miss cycles
658system.cpu0.dcache.demand_mshr_miss_latency::total 7523135052 # number of demand (read+write) MSHR miss cycles
659system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8719209044 # number of overall MSHR miss cycles
660system.cpu0.dcache.overall_mshr_miss_latency::total 8719209044 # number of overall MSHR miss cycles
661system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564453750 # number of ReadReq MSHR uncacheable cycles
662system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564453750 # number of ReadReq MSHR uncacheable cycles
663system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183862994 # number of WriteReq MSHR uncacheable cycles
664system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183862994 # number of WriteReq MSHR uncacheable cycles
665system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748316744 # number of overall MSHR uncacheable cycles
666system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748316744 # number of overall MSHR uncacheable cycles
667system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015009 # mshr miss rate for ReadReq accesses
668system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015009 # mshr miss rate for ReadReq accesses
669system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016786 # mshr miss rate for WriteReq accesses
670system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016786 # mshr miss rate for WriteReq accesses
671system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225746 # mshr miss rate for SoftPFReq accesses
672system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225746 # mshr miss rate for SoftPFReq accesses
673system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016665 # mshr miss rate for LoadLockedReq accesses
674system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016665 # mshr miss rate for LoadLockedReq accesses
675system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056967 # mshr miss rate for StoreCondReq accesses
676system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056967 # mshr miss rate for StoreCondReq accesses
677system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015773 # mshr miss rate for demand accesses
678system.cpu0.dcache.demand_mshr_miss_rate::total 0.015773 # mshr miss rate for demand accesses
679system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017936 # mshr miss rate for overall accesses
680system.cpu0.dcache.overall_mshr_miss_rate::total 0.017936 # mshr miss rate for overall accesses
681system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10422.506999 # average ReadReq mshr miss latency
682system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999 # average ReadReq mshr miss latency
683system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12920.660580 # average WriteReq mshr miss latency
684system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12920.660580 # average WriteReq mshr miss latency
685system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12340.328422 # average SoftPFReq mshr miss latency
686system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422 # average SoftPFReq mshr miss latency
687system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14150.861388 # average LoadLockedReq mshr miss latency
688system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388 # average LoadLockedReq mshr miss latency
689system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20115.998269 # average StoreCondReq mshr miss latency
690system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269 # average StoreCondReq mshr miss latency
691system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
692system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
693system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11565.317663 # average overall mshr miss latency
694system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663 # average overall mshr miss latency
695system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11665.820252 # average overall mshr miss latency
696system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11665.820252 # average overall mshr miss latency
697system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
698system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
699system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
700system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
701system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
702system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
703system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
704system.cpu0.icache.tags.replacements 1061124 # number of replacements
705system.cpu0.icache.tags.tagsinuse 511.483230 # Cycle average of tags in use
706system.cpu0.icache.tags.total_refs 114003925 # Total number of references to valid blocks.
707system.cpu0.icache.tags.sampled_refs 1061636 # Sample count of references to valid blocks.
708system.cpu0.icache.tags.avg_refs 107.385135 # Average number of references to valid blocks.
709system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit.
710system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483230 # Average occupied blocks per requestor
711system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy
712system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy
713system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
714system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
715system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
716system.cpu0.icache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id
717system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
718system.cpu0.icache.tags.tag_accesses 231192785 # Number of tag accesses
719system.cpu0.icache.tags.data_accesses 231192785 # Number of data accesses
720system.cpu0.icache.ReadReq_hits::cpu0.inst 114003925 # number of ReadReq hits
721system.cpu0.icache.ReadReq_hits::total 114003925 # number of ReadReq hits
722system.cpu0.icache.demand_hits::cpu0.inst 114003925 # number of demand (read+write) hits
723system.cpu0.icache.demand_hits::total 114003925 # number of demand (read+write) hits
724system.cpu0.icache.overall_hits::cpu0.inst 114003925 # number of overall hits
725system.cpu0.icache.overall_hits::total 114003925 # number of overall hits
726system.cpu0.icache.ReadReq_misses::cpu0.inst 1061645 # number of ReadReq misses
727system.cpu0.icache.ReadReq_misses::total 1061645 # number of ReadReq misses
728system.cpu0.icache.demand_misses::cpu0.inst 1061645 # number of demand (read+write) misses
729system.cpu0.icache.demand_misses::total 1061645 # number of demand (read+write) misses
730system.cpu0.icache.overall_misses::cpu0.inst 1061645 # number of overall misses
731system.cpu0.icache.overall_misses::total 1061645 # number of overall misses
732system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9000982497 # number of ReadReq miss cycles
733system.cpu0.icache.ReadReq_miss_latency::total 9000982497 # number of ReadReq miss cycles
734system.cpu0.icache.demand_miss_latency::cpu0.inst 9000982497 # number of demand (read+write) miss cycles
735system.cpu0.icache.demand_miss_latency::total 9000982497 # number of demand (read+write) miss cycles
736system.cpu0.icache.overall_miss_latency::cpu0.inst 9000982497 # number of overall miss cycles
737system.cpu0.icache.overall_miss_latency::total 9000982497 # number of overall miss cycles
738system.cpu0.icache.ReadReq_accesses::cpu0.inst 115065570 # number of ReadReq accesses(hits+misses)
739system.cpu0.icache.ReadReq_accesses::total 115065570 # number of ReadReq accesses(hits+misses)
740system.cpu0.icache.demand_accesses::cpu0.inst 115065570 # number of demand (read+write) accesses
741system.cpu0.icache.demand_accesses::total 115065570 # number of demand (read+write) accesses
742system.cpu0.icache.overall_accesses::cpu0.inst 115065570 # number of overall (read+write) accesses
743system.cpu0.icache.overall_accesses::total 115065570 # number of overall (read+write) accesses
744system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009226 # miss rate for ReadReq accesses
745system.cpu0.icache.ReadReq_miss_rate::total 0.009226 # miss rate for ReadReq accesses
746system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009226 # miss rate for demand accesses
747system.cpu0.icache.demand_miss_rate::total 0.009226 # miss rate for demand accesses
748system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009226 # miss rate for overall accesses
749system.cpu0.icache.overall_miss_rate::total 0.009226 # miss rate for overall accesses
750system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8478.335505 # average ReadReq miss latency
751system.cpu0.icache.ReadReq_avg_miss_latency::total 8478.335505 # average ReadReq miss latency
752system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency
753system.cpu0.icache.demand_avg_miss_latency::total 8478.335505 # average overall miss latency
754system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8478.335505 # average overall miss latency
755system.cpu0.icache.overall_avg_miss_latency::total 8478.335505 # average overall miss latency
756system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
757system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
758system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
759system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
760system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
761system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
762system.cpu0.icache.fast_writes 0 # number of fast writes performed
763system.cpu0.icache.cache_copies 0 # number of cache copies performed
764system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1061645 # number of ReadReq MSHR misses
765system.cpu0.icache.ReadReq_mshr_misses::total 1061645 # number of ReadReq MSHR misses
766system.cpu0.icache.demand_mshr_misses::cpu0.inst 1061645 # number of demand (read+write) MSHR misses
767system.cpu0.icache.demand_mshr_misses::total 1061645 # number of demand (read+write) MSHR misses
768system.cpu0.icache.overall_mshr_misses::cpu0.inst 1061645 # number of overall MSHR misses
769system.cpu0.icache.overall_mshr_misses::total 1061645 # number of overall MSHR misses
770system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7407816003 # number of ReadReq MSHR miss cycles
771system.cpu0.icache.ReadReq_mshr_miss_latency::total 7407816003 # number of ReadReq MSHR miss cycles
772system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7407816003 # number of demand (read+write) MSHR miss cycles
773system.cpu0.icache.demand_mshr_miss_latency::total 7407816003 # number of demand (read+write) MSHR miss cycles
774system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7407816003 # number of overall MSHR miss cycles
775system.cpu0.icache.overall_mshr_miss_latency::total 7407816003 # number of overall MSHR miss cycles
776system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles
777system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles
778system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles
779system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles
780system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for ReadReq accesses
781system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009226 # mshr miss rate for ReadReq accesses
782system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for demand accesses
783system.cpu0.icache.demand_mshr_miss_rate::total 0.009226 # mshr miss rate for demand accesses
784system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009226 # mshr miss rate for overall accesses
785system.cpu0.icache.overall_mshr_miss_rate::total 0.009226 # mshr miss rate for overall accesses
786system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average ReadReq mshr miss latency
787system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6977.677098 # average ReadReq mshr miss latency
788system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency
789system.cpu0.icache.demand_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency
790system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6977.677098 # average overall mshr miss latency
791system.cpu0.icache.overall_avg_mshr_miss_latency::total 6977.677098 # average overall mshr miss latency
792system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
793system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
794system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
795system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
796system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
797system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 9923384 # number of hwpf identified
798system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 228338 # number of hwpf that were already in mshr
799system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 9249316 # number of hwpf that were already in the cache
800system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 376 # number of hwpf that were already in the prefetch queue
801system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
802system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 35 # number of hwpf removed because MSHR allocated
803system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 445319 # number of hwpf issued
804system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 778112 # number of hwpf spanning a virtual page
805system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
806system.cpu0.l2cache.tags.replacements 357554 # number of replacements
807system.cpu0.l2cache.tags.tagsinuse 16100.801595 # Cycle average of tags in use
808system.cpu0.l2cache.tags.total_refs 1935390 # Total number of references to valid blocks.
809system.cpu0.l2cache.tags.sampled_refs 373791 # Sample count of references to valid blocks.
810system.cpu0.l2cache.tags.avg_refs 5.177733 # Average number of references to valid blocks.
811system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
812system.cpu0.l2cache.tags.occ_blocks::writebacks 6719.608952 # Average occupied blocks per requestor
813system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.125628 # Average occupied blocks per requestor
814system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.135893 # Average occupied blocks per requestor
815system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 793.879272 # Average occupied blocks per requestor
816system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1140.668616 # Average occupied blocks per requestor
817system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 7443.383233 # Average occupied blocks per requestor
818system.cpu0.l2cache.tags.occ_percent::writebacks 0.410132 # Average percentage of cache occupancy
819system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000191 # Average percentage of cache occupancy
820system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy
821system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.048455 # Average percentage of cache occupancy
822system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.069621 # Average percentage of cache occupancy
823system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.454308 # Average percentage of cache occupancy
824system.cpu0.l2cache.tags.occ_percent::total 0.982715 # Average percentage of cache occupancy
825system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7987 # Occupied blocks per task id
826system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
827system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8246 # Occupied blocks per task id
828system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 35 # Occupied blocks per task id
829system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 107 # Occupied blocks per task id
830system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 1881 # Occupied blocks per task id
831system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4986 # Occupied blocks per task id
832system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 978 # Occupied blocks per task id
833system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
834system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
835system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
836system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2886 # Occupied blocks per task id
837system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4666 # Occupied blocks per task id
838system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 532 # Occupied blocks per task id
839system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.487488 # Percentage of cache occupancy per task id
840system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id
841system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.503296 # Percentage of cache occupancy per task id
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952system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.062665 # miss rate for demand accesses
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957system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.062665 # miss rate for overall accesses
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987system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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1058system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5328411497 # number of ReadReq MSHR uncacheable cycles
1059system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5975619997 # number of ReadReq MSHR uncacheable cycles
1060system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3986952006 # number of WriteReq MSHR uncacheable cycles
1061system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3986952006 # number of WriteReq MSHR uncacheable cycles
1062system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647208500 # number of overall MSHR uncacheable cycles
1063system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9315363503 # number of overall MSHR uncacheable cycles
1064system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9962572003 # number of overall MSHR uncacheable cycles
1065system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for ReadReq accesses
1066system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for ReadReq accesses
1067system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for ReadReq accesses
1068system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.177578 # mshr miss rate for ReadReq accesses
1069system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062036 # mshr miss rate for ReadReq accesses
1070system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1071system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1072system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.746942 # mshr miss rate for UpgradeReq accesses
1073system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.746942 # mshr miss rate for UpgradeReq accesses
1074system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.903848 # mshr miss rate for SCUpgradeReq accesses
1075system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.903848 # mshr miss rate for SCUpgradeReq accesses
1076system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1077system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1078system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.169597 # mshr miss rate for ReadExReq accesses
1079system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.169597 # mshr miss rate for ReadExReq accesses
1080system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for demand accesses
1081system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for demand accesses
1082system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for demand accesses
1083system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for demand accesses
1084system.cpu0.l2cache.demand_mshr_miss_rate::total 0.077552 # mshr miss rate for demand accesses
1085system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for overall accesses
1086system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for overall accesses
1087system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for overall accesses
1088system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for overall accesses
1089system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1090system.cpu0.l2cache.overall_mshr_miss_rate::total 0.326857 # mshr miss rate for overall accesses
1091system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average ReadReq mshr miss latency
1092system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average ReadReq mshr miss latency
1093system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average ReadReq mshr miss latency
1094system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704 # average ReadReq mshr miss latency
1095system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056 # average ReadReq mshr miss latency
1096system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average HardPFReq mshr miss latency
1097system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701 # average HardPFReq mshr miss latency
1098system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537 # average UpgradeReq mshr miss latency
1099system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537 # average UpgradeReq mshr miss latency
1100system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143 # average SCUpgradeReq mshr miss latency
1101system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143 # average SCUpgradeReq mshr miss latency
1102system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000 # average SCUpgradeFailReq mshr miss latency
1103system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000 # average SCUpgradeFailReq mshr miss latency
1104system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111 # average ReadExReq mshr miss latency
1105system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111 # average ReadExReq mshr miss latency
1106system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency
1107system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency
1108system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency
1109system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency
1110system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743 # average overall mshr miss latency
1111system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency
1112system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency
1113system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency
1114system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency
1115system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average overall mshr miss latency
1116system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487 # average overall mshr miss latency
1117system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1118system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1119system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1120system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1121system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1122system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1123system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1124system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1125system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1126system.cpu0.toL2Bus.trans_dist::ReadReq 1734345 # Transaction distribution
1127system.cpu0.toL2Bus.trans_dist::ReadResp 1628634 # Transaction distribution
1128system.cpu0.toL2Bus.trans_dist::WriteReq 26254 # Transaction distribution
1129system.cpu0.toL2Bus.trans_dist::WriteResp 26254 # Transaction distribution
1130system.cpu0.toL2Bus.trans_dist::Writeback 483361 # Transaction distribution
1131system.cpu0.toL2Bus.trans_dist::HardPFReq 595652 # Transaction distribution
1132system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
1133system.cpu0.toL2Bus.trans_dist::UpgradeReq 80946 # Transaction distribution
1134system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43669 # Transaction distribution
1135system.cpu0.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution
1136system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
1137system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
1138system.cpu0.toL2Bus.trans_dist::ReadExReq 279437 # Transaction distribution
1139system.cpu0.toL2Bus.trans_dist::ReadExResp 269063 # Transaction distribution
1140system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141334 # Packet count per connected master and slave (bytes)
1141system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2249028 # Packet count per connected master and slave (bytes)
1142system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9800 # Packet count per connected master and slave (bytes)
1143system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21070 # Packet count per connected master and slave (bytes)
1144system.cpu0.toL2Bus.pkt_count::total 4421232 # Packet count per connected master and slave (bytes)
1145system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981368 # Cumulative packet size per connected master and slave (bytes)
1146system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80878536 # Cumulative packet size per connected master and slave (bytes)
1147system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13596 # Cumulative packet size per connected master and slave (bytes)
1148system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29396 # Cumulative packet size per connected master and slave (bytes)
1149system.cpu0.toL2Bus.pkt_size::total 148902896 # Cumulative packet size per connected master and slave (bytes)
1150system.cpu0.toL2Bus.snoops 988296 # Total snoops (count)
1151system.cpu0.toL2Bus.snoop_fanout::samples 3215199 # Request fanout histogram
1152system.cpu0.toL2Bus.snoop_fanout::mean 5.272128 # Request fanout histogram
1153system.cpu0.toL2Bus.snoop_fanout::stdev 0.445055 # Request fanout histogram
1154system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1155system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1156system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1157system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1158system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1159system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1160system.cpu0.toL2Bus.snoop_fanout::5 2340254 72.79% 72.79% # Request fanout histogram
1161system.cpu0.toL2Bus.snoop_fanout::6 874945 27.21% 100.00% # Request fanout histogram
1162system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1163system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1164system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1165system.cpu0.toL2Bus.snoop_fanout::total 3215199 # Request fanout histogram
1166system.cpu0.toL2Bus.reqLayer0.occupancy 1699304627 # Layer occupancy (ticks)
1167system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1168system.cpu0.toL2Bus.snoopLayer0.occupancy 115610498 # Layer occupancy (ticks)
1169system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1170system.cpu0.toL2Bus.respLayer0.occupancy 1603950497 # Layer occupancy (ticks)
1171system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
1172system.cpu0.toL2Bus.respLayer1.occupancy 1150471329 # Layer occupancy (ticks)
1173system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1174system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks)
1175system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1176system.cpu0.toL2Bus.respLayer3.occupancy 13721750 # Layer occupancy (ticks)
1177system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1178system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1179system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1180system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1181system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1182system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1183system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1184system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed

--- 8 unchanged lines hidden (view full) ---

1193system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1194system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1195system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1196system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1197system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1198system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1199system.cpu1.dtb.inst_hits 0 # ITB inst hits
1200system.cpu1.dtb.inst_misses 0 # ITB inst misses
1201system.cpu1.dtb.read_hits 4826061 # DTB read hits
1202system.cpu1.dtb.read_misses 2744 # DTB read misses
1203system.cpu1.dtb.write_hits 4130169 # DTB write hits
1204system.cpu1.dtb.write_misses 524 # DTB write misses
1205system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
1206system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1207system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1208system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1209system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB
1210system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
1211system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch
1212system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1213system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
1214system.cpu1.dtb.read_accesses 4828805 # DTB read accesses
1215system.cpu1.dtb.write_accesses 4130693 # DTB write accesses
1216system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1217system.cpu1.dtb.hits 8956230 # DTB hits
1218system.cpu1.dtb.misses 3268 # DTB misses
1219system.cpu1.dtb.accesses 8959498 # DTB accesses
1220system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1221system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1222system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1223system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1224system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1225system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1226system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1227system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

1233system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1234system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1235system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1236system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1237system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1238system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1239system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1240system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1241system.cpu1.itb.inst_hits 20883965 # ITB inst hits
1242system.cpu1.itb.inst_misses 1747 # ITB inst misses
1243system.cpu1.itb.read_hits 0 # DTB read hits
1244system.cpu1.itb.read_misses 0 # DTB read misses
1245system.cpu1.itb.write_hits 0 # DTB write hits
1246system.cpu1.itb.write_misses 0 # DTB write misses
1247system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
1248system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
1249system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
1250system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
1251system.cpu1.itb.flush_entries 1149 # Number of entries that have been flushed from TLB
1252system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1253system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1254system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1255system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1256system.cpu1.itb.read_accesses 0 # DTB read accesses
1257system.cpu1.itb.write_accesses 0 # DTB write accesses
1258system.cpu1.itb.inst_accesses 20885712 # ITB inst accesses
1259system.cpu1.itb.hits 20883965 # DTB hits
1260system.cpu1.itb.misses 1747 # DTB misses
1261system.cpu1.itb.accesses 20885712 # DTB accesses
1262system.cpu1.numCycles 5732918807 # number of cpu cycles simulated
1263system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1264system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1265system.cpu1.committedInsts 20503191 # Number of instructions committed
1266system.cpu1.committedOps 24868380 # Number of ops (including micro ops) committed
1267system.cpu1.num_int_alu_accesses 22184707 # Number of integer alu accesses
1268system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
1269system.cpu1.num_func_calls 1209330 # number of times a function call or return occured
1270system.cpu1.num_conditional_control_insts 2571856 # number of instructions that are conditional controls
1271system.cpu1.num_int_insts 22184707 # number of integer instructions
1272system.cpu1.num_fp_insts 1792 # number of float instructions
1273system.cpu1.num_int_register_reads 39845208 # number of times the integer registers were read
1274system.cpu1.num_int_register_writes 15444901 # number of times the integer registers were written
1275system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
1276system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
1277system.cpu1.num_cc_register_reads 90439564 # number of times the CC registers were read
1278system.cpu1.num_cc_register_writes 8859928 # number of times the CC registers were written
1279system.cpu1.num_mem_refs 9245671 # number of memory refs
1280system.cpu1.num_load_insts 4945342 # Number of load instructions
1281system.cpu1.num_store_insts 4300329 # Number of store instructions
1282system.cpu1.num_idle_cycles 5671530100.732908 # Number of idle cycles
1283system.cpu1.num_busy_cycles 61388706.267092 # Number of busy cycles
1284system.cpu1.not_idle_fraction 0.010708 # Percentage of non-idle cycles
1285system.cpu1.idle_fraction 0.989292 # Percentage of idle cycles
1286system.cpu1.Branches 3891928 # Number of branches fetched
1287system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction
1288system.cpu1.op_class::IntAlu 16013514 63.30% 63.30% # Class of executed instruction
1289system.cpu1.op_class::IntMult 33536 0.13% 63.44% # Class of executed instruction
1290system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction
1291system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction
1292system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction
1293system.cpu1.op_class::FloatCvt 0 0.00% 63.44% # Class of executed instruction
1294system.cpu1.op_class::FloatMult 0 0.00% 63.44% # Class of executed instruction
1295system.cpu1.op_class::FloatDiv 0 0.00% 63.44% # Class of executed instruction
1296system.cpu1.op_class::FloatSqrt 0 0.00% 63.44% # Class of executed instruction
1297system.cpu1.op_class::SimdAdd 0 0.00% 63.44% # Class of executed instruction

--- 7 unchanged lines hidden (view full) ---

1305system.cpu1.op_class::SimdShift 0 0.00% 63.44% # Class of executed instruction
1306system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.44% # Class of executed instruction
1307system.cpu1.op_class::SimdSqrt 0 0.00% 63.44% # Class of executed instruction
1308system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.44% # Class of executed instruction
1309system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.44% # Class of executed instruction
1310system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction
1311system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction
1312system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction
1313system.cpu1.op_class::SimdFloatMisc 4037 0.02% 63.45% # Class of executed instruction
1314system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction
1315system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction
1316system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction
1317system.cpu1.op_class::MemRead 4945342 19.55% 83.00% # Class of executed instruction
1318system.cpu1.op_class::MemWrite 4300329 17.00% 100.00% # Class of executed instruction
1319system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
1320system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
1321system.cpu1.op_class::total 25296825 # Class of executed instruction
1322system.cpu1.kern.inst.arm 0 # number of arm instructions executed
1323system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed
1324system.cpu1.dcache.tags.replacements 218952 # number of replacements
1325system.cpu1.dcache.tags.tagsinuse 479.963069 # Cycle average of tags in use
1326system.cpu1.dcache.tags.total_refs 8650768 # Total number of references to valid blocks.
1327system.cpu1.dcache.tags.sampled_refs 219309 # Sample count of references to valid blocks.
1328system.cpu1.dcache.tags.avg_refs 39.445568 # Average number of references to valid blocks.
1329system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit.
1330system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.963069 # Average occupied blocks per requestor
1331system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937428 # Average percentage of cache occupancy
1332system.cpu1.dcache.tags.occ_percent::total 0.937428 # Average percentage of cache occupancy
1333system.cpu1.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id
1334system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id
1335system.cpu1.dcache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id
1336system.cpu1.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id
1337system.cpu1.dcache.tags.tag_accesses 18157371 # Number of tag accesses
1338system.cpu1.dcache.tags.data_accesses 18157371 # Number of data accesses
1339system.cpu1.dcache.ReadReq_hits::cpu1.data 4461777 # number of ReadReq hits
1340system.cpu1.dcache.ReadReq_hits::total 4461777 # number of ReadReq hits
1341system.cpu1.dcache.WriteReq_hits::cpu1.data 3918409 # number of WriteReq hits
1342system.cpu1.dcache.WriteReq_hits::total 3918409 # number of WriteReq hits
1343system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64134 # number of SoftPFReq hits
1344system.cpu1.dcache.SoftPFReq_hits::total 64134 # number of SoftPFReq hits
1345system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87180 # number of LoadLockedReq hits
1346system.cpu1.dcache.LoadLockedReq_hits::total 87180 # number of LoadLockedReq hits
1347system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79638 # number of StoreCondReq hits
1348system.cpu1.dcache.StoreCondReq_hits::total 79638 # number of StoreCondReq hits
1349system.cpu1.dcache.demand_hits::cpu1.data 8380186 # number of demand (read+write) hits
1350system.cpu1.dcache.demand_hits::total 8380186 # number of demand (read+write) hits
1351system.cpu1.dcache.overall_hits::cpu1.data 8444320 # number of overall hits
1352system.cpu1.dcache.overall_hits::total 8444320 # number of overall hits
1353system.cpu1.dcache.ReadReq_misses::cpu1.data 155208 # number of ReadReq misses
1354system.cpu1.dcache.ReadReq_misses::total 155208 # number of ReadReq misses
1355system.cpu1.dcache.WriteReq_misses::cpu1.data 103786 # number of WriteReq misses
1356system.cpu1.dcache.WriteReq_misses::total 103786 # number of WriteReq misses
1357system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34227 # number of SoftPFReq misses
1358system.cpu1.dcache.SoftPFReq_misses::total 34227 # number of SoftPFReq misses
1359system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17933 # number of LoadLockedReq misses
1360system.cpu1.dcache.LoadLockedReq_misses::total 17933 # number of LoadLockedReq misses
1361system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23205 # number of StoreCondReq misses
1362system.cpu1.dcache.StoreCondReq_misses::total 23205 # number of StoreCondReq misses
1363system.cpu1.dcache.demand_misses::cpu1.data 258994 # number of demand (read+write) misses
1364system.cpu1.dcache.demand_misses::total 258994 # number of demand (read+write) misses
1365system.cpu1.dcache.overall_misses::cpu1.data 293221 # number of overall misses
1366system.cpu1.dcache.overall_misses::total 293221 # number of overall misses
1367system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2219053526 # number of ReadReq miss cycles
1368system.cpu1.dcache.ReadReq_miss_latency::total 2219053526 # number of ReadReq miss cycles
1369system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2269605832 # number of WriteReq miss cycles
1370system.cpu1.dcache.WriteReq_miss_latency::total 2269605832 # number of WriteReq miss cycles
1371system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325236501 # number of LoadLockedReq miss cycles
1372system.cpu1.dcache.LoadLockedReq_miss_latency::total 325236501 # number of LoadLockedReq miss cycles
1373system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 538183221 # number of StoreCondReq miss cycles
1374system.cpu1.dcache.StoreCondReq_miss_latency::total 538183221 # number of StoreCondReq miss cycles
1375system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1673500 # number of StoreCondFailReq miss cycles
1376system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1673500 # number of StoreCondFailReq miss cycles
1377system.cpu1.dcache.demand_miss_latency::cpu1.data 4488659358 # number of demand (read+write) miss cycles
1378system.cpu1.dcache.demand_miss_latency::total 4488659358 # number of demand (read+write) miss cycles
1379system.cpu1.dcache.overall_miss_latency::cpu1.data 4488659358 # number of overall miss cycles
1380system.cpu1.dcache.overall_miss_latency::total 4488659358 # number of overall miss cycles
1381system.cpu1.dcache.ReadReq_accesses::cpu1.data 4616985 # number of ReadReq accesses(hits+misses)
1382system.cpu1.dcache.ReadReq_accesses::total 4616985 # number of ReadReq accesses(hits+misses)
1383system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022195 # number of WriteReq accesses(hits+misses)
1384system.cpu1.dcache.WriteReq_accesses::total 4022195 # number of WriteReq accesses(hits+misses)
1385system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98361 # number of SoftPFReq accesses(hits+misses)
1386system.cpu1.dcache.SoftPFReq_accesses::total 98361 # number of SoftPFReq accesses(hits+misses)
1387system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105113 # number of LoadLockedReq accesses(hits+misses)
1388system.cpu1.dcache.LoadLockedReq_accesses::total 105113 # number of LoadLockedReq accesses(hits+misses)
1389system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102843 # number of StoreCondReq accesses(hits+misses)
1390system.cpu1.dcache.StoreCondReq_accesses::total 102843 # number of StoreCondReq accesses(hits+misses)
1391system.cpu1.dcache.demand_accesses::cpu1.data 8639180 # number of demand (read+write) accesses
1392system.cpu1.dcache.demand_accesses::total 8639180 # number of demand (read+write) accesses
1393system.cpu1.dcache.overall_accesses::cpu1.data 8737541 # number of overall (read+write) accesses
1394system.cpu1.dcache.overall_accesses::total 8737541 # number of overall (read+write) accesses
1395system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033617 # miss rate for ReadReq accesses
1396system.cpu1.dcache.ReadReq_miss_rate::total 0.033617 # miss rate for ReadReq accesses
1397system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025803 # miss rate for WriteReq accesses
1398system.cpu1.dcache.WriteReq_miss_rate::total 0.025803 # miss rate for WriteReq accesses
1399system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347973 # miss rate for SoftPFReq accesses
1400system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347973 # miss rate for SoftPFReq accesses
1401system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170607 # miss rate for LoadLockedReq accesses
1402system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170607 # miss rate for LoadLockedReq accesses
1403system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225635 # miss rate for StoreCondReq accesses
1404system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225635 # miss rate for StoreCondReq accesses
1405system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029979 # miss rate for demand accesses
1406system.cpu1.dcache.demand_miss_rate::total 0.029979 # miss rate for demand accesses
1407system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033559 # miss rate for overall accesses
1408system.cpu1.dcache.overall_miss_rate::total 0.033559 # miss rate for overall accesses
1409system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14297.288323 # average ReadReq miss latency
1410system.cpu1.dcache.ReadReq_avg_miss_latency::total 14297.288323 # average ReadReq miss latency
1411system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21868.130885 # average WriteReq miss latency
1412system.cpu1.dcache.WriteReq_avg_miss_latency::total 21868.130885 # average WriteReq miss latency
1413system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18136.201472 # average LoadLockedReq miss latency
1414system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18136.201472 # average LoadLockedReq miss latency
1415system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23192.554234 # average StoreCondReq miss latency
1416system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23192.554234 # average StoreCondReq miss latency
1417system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1418system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1419system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17331.132605 # average overall miss latency
1420system.cpu1.dcache.demand_avg_miss_latency::total 17331.132605 # average overall miss latency
1421system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15308.110122 # average overall miss latency
1422system.cpu1.dcache.overall_avg_miss_latency::total 15308.110122 # average overall miss latency
1423system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1424system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1425system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
1426system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
1427system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1428system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1429system.cpu1.dcache.fast_writes 0 # number of fast writes performed
1430system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1431system.cpu1.dcache.writebacks::writebacks 135060 # number of writebacks
1432system.cpu1.dcache.writebacks::total 135060 # number of writebacks
1433system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 314 # number of ReadReq MSHR hits
1434system.cpu1.dcache.ReadReq_mshr_hits::total 314 # number of ReadReq MSHR hits
1435system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1 # number of WriteReq MSHR hits
1436system.cpu1.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
1437system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12325 # number of LoadLockedReq MSHR hits
1438system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12325 # number of LoadLockedReq MSHR hits
1439system.cpu1.dcache.demand_mshr_hits::cpu1.data 315 # number of demand (read+write) MSHR hits
1440system.cpu1.dcache.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits
1441system.cpu1.dcache.overall_mshr_hits::cpu1.data 315 # number of overall MSHR hits
1442system.cpu1.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits
1443system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154894 # number of ReadReq MSHR misses
1444system.cpu1.dcache.ReadReq_mshr_misses::total 154894 # number of ReadReq MSHR misses
1445system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103785 # number of WriteReq MSHR misses
1446system.cpu1.dcache.WriteReq_mshr_misses::total 103785 # number of WriteReq MSHR misses
1447system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 33053 # number of SoftPFReq MSHR misses
1448system.cpu1.dcache.SoftPFReq_mshr_misses::total 33053 # number of SoftPFReq MSHR misses
1449system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5608 # number of LoadLockedReq MSHR misses
1450system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5608 # number of LoadLockedReq MSHR misses
1451system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23205 # number of StoreCondReq MSHR misses
1452system.cpu1.dcache.StoreCondReq_mshr_misses::total 23205 # number of StoreCondReq MSHR misses
1453system.cpu1.dcache.demand_mshr_misses::cpu1.data 258679 # number of demand (read+write) MSHR misses
1454system.cpu1.dcache.demand_mshr_misses::total 258679 # number of demand (read+write) MSHR misses
1455system.cpu1.dcache.overall_mshr_misses::cpu1.data 291732 # number of overall MSHR misses
1456system.cpu1.dcache.overall_mshr_misses::total 291732 # number of overall MSHR misses
1457system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1899677974 # number of ReadReq MSHR miss cycles
1458system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1899677974 # number of ReadReq MSHR miss cycles
1459system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2055753168 # number of WriteReq MSHR miss cycles
1460system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2055753168 # number of WriteReq MSHR miss cycles
1461system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 496489496 # number of SoftPFReq MSHR miss cycles
1462system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 496489496 # number of SoftPFReq MSHR miss cycles
1463system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84032750 # number of LoadLockedReq MSHR miss cycles
1464system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84032750 # number of LoadLockedReq MSHR miss cycles
1465system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 490566779 # number of StoreCondReq MSHR miss cycles
1466system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 490566779 # number of StoreCondReq MSHR miss cycles
1467system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1599500 # number of StoreCondFailReq MSHR miss cycles
1468system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1599500 # number of StoreCondFailReq MSHR miss cycles
1469system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3955431142 # number of demand (read+write) MSHR miss cycles
1470system.cpu1.dcache.demand_mshr_miss_latency::total 3955431142 # number of demand (read+write) MSHR miss cycles
1471system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4451920638 # number of overall MSHR miss cycles
1472system.cpu1.dcache.overall_mshr_miss_latency::total 4451920638 # number of overall MSHR miss cycles
1473system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 961065499 # number of ReadReq MSHR uncacheable cycles
1474system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 961065499 # number of ReadReq MSHR uncacheable cycles
1475system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833382997 # number of WriteReq MSHR uncacheable cycles
1476system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833382997 # number of WriteReq MSHR uncacheable cycles
1477system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794448496 # number of overall MSHR uncacheable cycles
1478system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794448496 # number of overall MSHR uncacheable cycles
1479system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033549 # mshr miss rate for ReadReq accesses
1480system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033549 # mshr miss rate for ReadReq accesses
1481system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025803 # mshr miss rate for WriteReq accesses
1482system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025803 # mshr miss rate for WriteReq accesses
1483system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.336038 # mshr miss rate for SoftPFReq accesses
1484system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.336038 # mshr miss rate for SoftPFReq accesses
1485system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053352 # mshr miss rate for LoadLockedReq accesses
1486system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053352 # mshr miss rate for LoadLockedReq accesses
1487system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225635 # mshr miss rate for StoreCondReq accesses
1488system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225635 # mshr miss rate for StoreCondReq accesses
1489system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses
1490system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses
1491system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033388 # mshr miss rate for overall accesses
1492system.cpu1.dcache.overall_mshr_miss_rate::total 0.033388 # mshr miss rate for overall accesses
1493system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12264.374178 # average ReadReq mshr miss latency
1494system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12264.374178 # average ReadReq mshr miss latency
1495system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19807.806215 # average WriteReq mshr miss latency
1496system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19807.806215 # average WriteReq mshr miss latency
1497system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15021.011587 # average SoftPFReq mshr miss latency
1498system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15021.011587 # average SoftPFReq mshr miss latency
1499system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14984.441869 # average LoadLockedReq mshr miss latency
1500system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869 # average LoadLockedReq mshr miss latency
1501system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21140.563629 # average StoreCondReq mshr miss latency
1502system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629 # average StoreCondReq mshr miss latency
1503system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
1504system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1505system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15290.886164 # average overall mshr miss latency
1506system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15290.886164 # average overall mshr miss latency
1507system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15260.309592 # average overall mshr miss latency
1508system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15260.309592 # average overall mshr miss latency
1509system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1510system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1511system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1512system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1513system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1514system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1515system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1516system.cpu1.icache.tags.replacements 565004 # number of replacements
1517system.cpu1.icache.tags.tagsinuse 498.690467 # Cycle average of tags in use
1518system.cpu1.icache.tags.total_refs 20318443 # Total number of references to valid blocks.
1519system.cpu1.icache.tags.sampled_refs 565516 # Sample count of references to valid blocks.
1520system.cpu1.icache.tags.avg_refs 35.929033 # Average number of references to valid blocks.
1521system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit.
1522system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690467 # Average occupied blocks per requestor
1523system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy
1524system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy
1525system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1526system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id
1527system.cpu1.icache.tags.age_task_id_blocks_1024::3 110 # Occupied blocks per task id
1528system.cpu1.icache.tags.age_task_id_blocks_1024::4 5 # Occupied blocks per task id
1529system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1530system.cpu1.icache.tags.tag_accesses 42333437 # Number of tag accesses
1531system.cpu1.icache.tags.data_accesses 42333437 # Number of data accesses
1532system.cpu1.icache.ReadReq_hits::cpu1.inst 20318443 # number of ReadReq hits
1533system.cpu1.icache.ReadReq_hits::total 20318443 # number of ReadReq hits
1534system.cpu1.icache.demand_hits::cpu1.inst 20318443 # number of demand (read+write) hits
1535system.cpu1.icache.demand_hits::total 20318443 # number of demand (read+write) hits
1536system.cpu1.icache.overall_hits::cpu1.inst 20318443 # number of overall hits
1537system.cpu1.icache.overall_hits::total 20318443 # number of overall hits
1538system.cpu1.icache.ReadReq_misses::cpu1.inst 565517 # number of ReadReq misses
1539system.cpu1.icache.ReadReq_misses::total 565517 # number of ReadReq misses
1540system.cpu1.icache.demand_misses::cpu1.inst 565517 # number of demand (read+write) misses
1541system.cpu1.icache.demand_misses::total 565517 # number of demand (read+write) misses
1542system.cpu1.icache.overall_misses::cpu1.inst 565517 # number of overall misses
1543system.cpu1.icache.overall_misses::total 565517 # number of overall misses
1544system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4683990281 # number of ReadReq miss cycles
1545system.cpu1.icache.ReadReq_miss_latency::total 4683990281 # number of ReadReq miss cycles
1546system.cpu1.icache.demand_miss_latency::cpu1.inst 4683990281 # number of demand (read+write) miss cycles
1547system.cpu1.icache.demand_miss_latency::total 4683990281 # number of demand (read+write) miss cycles
1548system.cpu1.icache.overall_miss_latency::cpu1.inst 4683990281 # number of overall miss cycles
1549system.cpu1.icache.overall_miss_latency::total 4683990281 # number of overall miss cycles
1550system.cpu1.icache.ReadReq_accesses::cpu1.inst 20883960 # number of ReadReq accesses(hits+misses)
1551system.cpu1.icache.ReadReq_accesses::total 20883960 # number of ReadReq accesses(hits+misses)
1552system.cpu1.icache.demand_accesses::cpu1.inst 20883960 # number of demand (read+write) accesses
1553system.cpu1.icache.demand_accesses::total 20883960 # number of demand (read+write) accesses
1554system.cpu1.icache.overall_accesses::cpu1.inst 20883960 # number of overall (read+write) accesses
1555system.cpu1.icache.overall_accesses::total 20883960 # number of overall (read+write) accesses
1556system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027079 # miss rate for ReadReq accesses
1557system.cpu1.icache.ReadReq_miss_rate::total 0.027079 # miss rate for ReadReq accesses
1558system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027079 # miss rate for demand accesses
1559system.cpu1.icache.demand_miss_rate::total 0.027079 # miss rate for demand accesses
1560system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027079 # miss rate for overall accesses
1561system.cpu1.icache.overall_miss_rate::total 0.027079 # miss rate for overall accesses
1562system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8282.669276 # average ReadReq miss latency
1563system.cpu1.icache.ReadReq_avg_miss_latency::total 8282.669276 # average ReadReq miss latency
1564system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency
1565system.cpu1.icache.demand_avg_miss_latency::total 8282.669276 # average overall miss latency
1566system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8282.669276 # average overall miss latency
1567system.cpu1.icache.overall_avg_miss_latency::total 8282.669276 # average overall miss latency
1568system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1569system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1570system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
1571system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
1572system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1573system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1574system.cpu1.icache.fast_writes 0 # number of fast writes performed
1575system.cpu1.icache.cache_copies 0 # number of cache copies performed
1576system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 565517 # number of ReadReq MSHR misses
1577system.cpu1.icache.ReadReq_mshr_misses::total 565517 # number of ReadReq MSHR misses
1578system.cpu1.icache.demand_mshr_misses::cpu1.inst 565517 # number of demand (read+write) MSHR misses
1579system.cpu1.icache.demand_mshr_misses::total 565517 # number of demand (read+write) MSHR misses
1580system.cpu1.icache.overall_mshr_misses::cpu1.inst 565517 # number of overall MSHR misses
1581system.cpu1.icache.overall_mshr_misses::total 565517 # number of overall MSHR misses
1582system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3835548219 # number of ReadReq MSHR miss cycles
1583system.cpu1.icache.ReadReq_mshr_miss_latency::total 3835548219 # number of ReadReq MSHR miss cycles
1584system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3835548219 # number of demand (read+write) MSHR miss cycles
1585system.cpu1.icache.demand_mshr_miss_latency::total 3835548219 # number of demand (read+write) MSHR miss cycles
1586system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3835548219 # number of overall MSHR miss cycles
1587system.cpu1.icache.overall_mshr_miss_latency::total 3835548219 # number of overall MSHR miss cycles
1588system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13880000 # number of ReadReq MSHR uncacheable cycles
1589system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13880000 # number of ReadReq MSHR uncacheable cycles
1590system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13880000 # number of overall MSHR uncacheable cycles
1591system.cpu1.icache.overall_mshr_uncacheable_latency::total 13880000 # number of overall MSHR uncacheable cycles
1592system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for ReadReq accesses
1593system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027079 # mshr miss rate for ReadReq accesses
1594system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for demand accesses
1595system.cpu1.icache.demand_mshr_miss_rate::total 0.027079 # mshr miss rate for demand accesses
1596system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027079 # mshr miss rate for overall accesses
1597system.cpu1.icache.overall_mshr_miss_rate::total 0.027079 # mshr miss rate for overall accesses
1598system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average ReadReq mshr miss latency
1599system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6782.374746 # average ReadReq mshr miss latency
1600system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency
1601system.cpu1.icache.demand_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency
1602system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6782.374746 # average overall mshr miss latency
1603system.cpu1.icache.overall_avg_mshr_miss_latency::total 6782.374746 # average overall mshr miss latency
1604system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1605system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1606system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1607system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1608system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1609system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4611088 # number of hwpf identified
1610system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 22954 # number of hwpf that were already in mshr
1611system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4468812 # number of hwpf that were already in the cache
1612system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 204 # number of hwpf that were already in the prefetch queue
1613system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
1614system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 20 # number of hwpf removed because MSHR allocated
1615system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 119098 # number of hwpf issued
1616system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 522488 # number of hwpf spanning a virtual page
1617system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
1618system.cpu1.l2cache.tags.replacements 85089 # number of replacements
1619system.cpu1.l2cache.tags.tagsinuse 15598.515375 # Cycle average of tags in use
1620system.cpu1.l2cache.tags.total_refs 830428 # Total number of references to valid blocks.
1621system.cpu1.l2cache.tags.sampled_refs 100250 # Sample count of references to valid blocks.
1622system.cpu1.l2cache.tags.avg_refs 8.283571 # Average number of references to valid blocks.
1623system.cpu1.l2cache.tags.warmup_cycle 2855976531500 # Cycle when the warmup percentage was hit.
1624system.cpu1.l2cache.tags.occ_blocks::writebacks 4729.771122 # Average occupied blocks per requestor
1625system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.150877 # Average occupied blocks per requestor
1626system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.487977 # Average occupied blocks per requestor
1627system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 867.406317 # Average occupied blocks per requestor
1628system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1520.802657 # Average occupied blocks per requestor
1629system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8476.896425 # Average occupied blocks per requestor
1630system.cpu1.l2cache.tags.occ_percent::writebacks 0.288682 # Average percentage of cache occupancy
1631system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy
1632system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000030 # Average percentage of cache occupancy
1633system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.052942 # Average percentage of cache occupancy
1634system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.092822 # Average percentage of cache occupancy
1635system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.517389 # Average percentage of cache occupancy
1636system.cpu1.l2cache.tags.occ_percent::total 0.952058 # Average percentage of cache occupancy
1637system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9282 # Occupied blocks per task id
1638system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
1639system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5865 # Occupied blocks per task id
1640system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 69 # Occupied blocks per task id
1641system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1139 # Occupied blocks per task id
1642system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 8074 # Occupied blocks per task id
1643system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id
1644system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
1645system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id
1646system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1132 # Occupied blocks per task id
1647system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4460 # Occupied blocks per task id
1648system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.566528 # Percentage of cache occupancy per task id
1649system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
1650system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.357971 # Percentage of cache occupancy per task id
1651system.cpu1.l2cache.tags.tag_accesses 16688806 # Number of tag accesses
1652system.cpu1.l2cache.tags.data_accesses 16688806 # Number of data accesses
1653system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2996 # number of ReadReq hits
1654system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1704 # number of ReadReq hits
1655system.cpu1.l2cache.ReadReq_hits::cpu1.inst 559876 # number of ReadReq hits
1656system.cpu1.l2cache.ReadReq_hits::cpu1.data 123244 # number of ReadReq hits
1657system.cpu1.l2cache.ReadReq_hits::total 687820 # number of ReadReq hits
1658system.cpu1.l2cache.Writeback_hits::writebacks 135060 # number of Writeback hits
1659system.cpu1.l2cache.Writeback_hits::total 135060 # number of Writeback hits
1660system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1609 # number of UpgradeReq hits
1661system.cpu1.l2cache.UpgradeReq_hits::total 1609 # number of UpgradeReq hits
1662system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 861 # number of SCUpgradeReq hits
1663system.cpu1.l2cache.SCUpgradeReq_hits::total 861 # number of SCUpgradeReq hits
1664system.cpu1.l2cache.ReadExReq_hits::cpu1.data 39179 # number of ReadExReq hits
1665system.cpu1.l2cache.ReadExReq_hits::total 39179 # number of ReadExReq hits
1666system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2996 # number of demand (read+write) hits
1667system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1704 # number of demand (read+write) hits
1668system.cpu1.l2cache.demand_hits::cpu1.inst 559876 # number of demand (read+write) hits
1669system.cpu1.l2cache.demand_hits::cpu1.data 162423 # number of demand (read+write) hits
1670system.cpu1.l2cache.demand_hits::total 726999 # number of demand (read+write) hits
1671system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2996 # number of overall hits
1672system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1704 # number of overall hits
1673system.cpu1.l2cache.overall_hits::cpu1.inst 559876 # number of overall hits
1674system.cpu1.l2cache.overall_hits::cpu1.data 162423 # number of overall hits
1675system.cpu1.l2cache.overall_hits::total 726999 # number of overall hits
1676system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses
1677system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses
1678system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5641 # number of ReadReq misses
1679system.cpu1.l2cache.ReadReq_misses::cpu1.data 70311 # number of ReadReq misses
1680system.cpu1.l2cache.ReadReq_misses::total 76567 # number of ReadReq misses
1681system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29399 # number of UpgradeReq misses
1682system.cpu1.l2cache.UpgradeReq_misses::total 29399 # number of UpgradeReq misses
1683system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22337 # number of SCUpgradeReq misses
1684system.cpu1.l2cache.SCUpgradeReq_misses::total 22337 # number of SCUpgradeReq misses
1685system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 7 # number of SCUpgradeFailReq misses
1686system.cpu1.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses
1687system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33598 # number of ReadExReq misses
1688system.cpu1.l2cache.ReadExReq_misses::total 33598 # number of ReadExReq misses
1689system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses
1690system.cpu1.l2cache.demand_misses::cpu1.itb.walker 277 # number of demand (read+write) misses
1691system.cpu1.l2cache.demand_misses::cpu1.inst 5641 # number of demand (read+write) misses
1692system.cpu1.l2cache.demand_misses::cpu1.data 103909 # number of demand (read+write) misses
1693system.cpu1.l2cache.demand_misses::total 110165 # number of demand (read+write) misses
1694system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses
1695system.cpu1.l2cache.overall_misses::cpu1.itb.walker 277 # number of overall misses
1696system.cpu1.l2cache.overall_misses::cpu1.inst 5641 # number of overall misses
1697system.cpu1.l2cache.overall_misses::cpu1.data 103909 # number of overall misses
1698system.cpu1.l2cache.overall_misses::total 110165 # number of overall misses
1699system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6952000 # number of ReadReq miss cycles
1700system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5546000 # number of ReadReq miss cycles
1701system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 192723218 # number of ReadReq miss cycles
1702system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1546712890 # number of ReadReq miss cycles
1703system.cpu1.l2cache.ReadReq_miss_latency::total 1751934108 # number of ReadReq miss cycles
1704system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 537154147 # number of UpgradeReq miss cycles
1705system.cpu1.l2cache.UpgradeReq_miss_latency::total 537154147 # number of UpgradeReq miss cycles
1706system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 436854563 # number of SCUpgradeReq miss cycles
1707system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 436854563 # number of SCUpgradeReq miss cycles
1708system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1562500 # number of SCUpgradeFailReq miss cycles
1709system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1562500 # number of SCUpgradeFailReq miss cycles
1710system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1072389357 # number of ReadExReq miss cycles
1711system.cpu1.l2cache.ReadExReq_miss_latency::total 1072389357 # number of ReadExReq miss cycles
1712system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6952000 # number of demand (read+write) miss cycles
1713system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5546000 # number of demand (read+write) miss cycles
1714system.cpu1.l2cache.demand_miss_latency::cpu1.inst 192723218 # number of demand (read+write) miss cycles
1715system.cpu1.l2cache.demand_miss_latency::cpu1.data 2619102247 # number of demand (read+write) miss cycles
1716system.cpu1.l2cache.demand_miss_latency::total 2824323465 # number of demand (read+write) miss cycles
1717system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6952000 # number of overall miss cycles
1718system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5546000 # number of overall miss cycles
1719system.cpu1.l2cache.overall_miss_latency::cpu1.inst 192723218 # number of overall miss cycles
1720system.cpu1.l2cache.overall_miss_latency::cpu1.data 2619102247 # number of overall miss cycles
1721system.cpu1.l2cache.overall_miss_latency::total 2824323465 # number of overall miss cycles
1722system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3334 # number of ReadReq accesses(hits+misses)
1723system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1981 # number of ReadReq accesses(hits+misses)
1724system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 565517 # number of ReadReq accesses(hits+misses)
1725system.cpu1.l2cache.ReadReq_accesses::cpu1.data 193555 # number of ReadReq accesses(hits+misses)
1726system.cpu1.l2cache.ReadReq_accesses::total 764387 # number of ReadReq accesses(hits+misses)
1727system.cpu1.l2cache.Writeback_accesses::writebacks 135060 # number of Writeback accesses(hits+misses)
1728system.cpu1.l2cache.Writeback_accesses::total 135060 # number of Writeback accesses(hits+misses)
1729system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31008 # number of UpgradeReq accesses(hits+misses)
1730system.cpu1.l2cache.UpgradeReq_accesses::total 31008 # number of UpgradeReq accesses(hits+misses)
1731system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23198 # number of SCUpgradeReq accesses(hits+misses)
1732system.cpu1.l2cache.SCUpgradeReq_accesses::total 23198 # number of SCUpgradeReq accesses(hits+misses)
1733system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 7 # number of SCUpgradeFailReq accesses(hits+misses)
1734system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses)
1735system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 72777 # number of ReadExReq accesses(hits+misses)
1736system.cpu1.l2cache.ReadExReq_accesses::total 72777 # number of ReadExReq accesses(hits+misses)
1737system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3334 # number of demand (read+write) accesses
1738system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1981 # number of demand (read+write) accesses
1739system.cpu1.l2cache.demand_accesses::cpu1.inst 565517 # number of demand (read+write) accesses
1740system.cpu1.l2cache.demand_accesses::cpu1.data 266332 # number of demand (read+write) accesses
1741system.cpu1.l2cache.demand_accesses::total 837164 # number of demand (read+write) accesses
1742system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3334 # number of overall (read+write) accesses
1743system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1981 # number of overall (read+write) accesses
1744system.cpu1.l2cache.overall_accesses::cpu1.inst 565517 # number of overall (read+write) accesses
1745system.cpu1.l2cache.overall_accesses::cpu1.data 266332 # number of overall (read+write) accesses
1746system.cpu1.l2cache.overall_accesses::total 837164 # number of overall (read+write) accesses
1747system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for ReadReq accesses
1748system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.139828 # miss rate for ReadReq accesses
1749system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.009975 # miss rate for ReadReq accesses
1750system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.363261 # miss rate for ReadReq accesses
1751system.cpu1.l2cache.ReadReq_miss_rate::total 0.100168 # miss rate for ReadReq accesses
1752system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.948110 # miss rate for UpgradeReq accesses
1753system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.948110 # miss rate for UpgradeReq accesses
1754system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962885 # miss rate for SCUpgradeReq accesses
1755system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962885 # miss rate for SCUpgradeReq accesses
1756system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
1757system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1758system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.461657 # miss rate for ReadExReq accesses
1759system.cpu1.l2cache.ReadExReq_miss_rate::total 0.461657 # miss rate for ReadExReq accesses
1760system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for demand accesses
1761system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.139828 # miss rate for demand accesses
1762system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.009975 # miss rate for demand accesses
1763system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.390148 # miss rate for demand accesses
1764system.cpu1.l2cache.demand_miss_rate::total 0.131593 # miss rate for demand accesses
1765system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.101380 # miss rate for overall accesses
1766system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.139828 # miss rate for overall accesses
1767system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.009975 # miss rate for overall accesses
1768system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.390148 # miss rate for overall accesses
1769system.cpu1.l2cache.overall_miss_rate::total 0.131593 # miss rate for overall accesses
1770system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average ReadReq miss latency
1771system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20021.660650 # average ReadReq miss latency
1772system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34164.725758 # average ReadReq miss latency
1773system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21998.163730 # average ReadReq miss latency
1774system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22881.059830 # average ReadReq miss latency
1775system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18271.170686 # average UpgradeReq miss latency
1776system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18271.170686 # average UpgradeReq miss latency
1777system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19557.441151 # average SCUpgradeReq miss latency
1778system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19557.441151 # average SCUpgradeReq miss latency
1779system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 223214.285714 # average SCUpgradeFailReq miss latency
1780system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223214.285714 # average SCUpgradeFailReq miss latency
1781system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 31918.249807 # average ReadExReq miss latency
1782system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 31918.249807 # average ReadExReq miss latency
1783system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency
1784system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency
1785system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency
1786system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency
1787system.cpu1.l2cache.demand_avg_miss_latency::total 25637.212046 # average overall miss latency
1788system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20568.047337 # average overall miss latency
1789system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20021.660650 # average overall miss latency
1790system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34164.725758 # average overall miss latency
1791system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 25205.730466 # average overall miss latency
1792system.cpu1.l2cache.overall_avg_miss_latency::total 25637.212046 # average overall miss latency
1793system.cpu1.l2cache.blocked_cycles::no_mshrs 1642 # number of cycles access was blocked
1794system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1795system.cpu1.l2cache.blocked::no_mshrs 35 # number of cycles access was blocked
1796system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1797system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 46.914286 # average number of cycles each access was blocked
1798system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1799system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
1800system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
1801system.cpu1.l2cache.writebacks::writebacks 35198 # number of writebacks
1802system.cpu1.l2cache.writebacks::total 35198 # number of writebacks
1803system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 739 # number of ReadReq MSHR hits
1804system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 100 # number of ReadReq MSHR hits
1805system.cpu1.l2cache.ReadReq_mshr_hits::total 839 # number of ReadReq MSHR hits
1806system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 193 # number of ReadExReq MSHR hits
1807system.cpu1.l2cache.ReadExReq_mshr_hits::total 193 # number of ReadExReq MSHR hits
1808system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 739 # number of demand (read+write) MSHR hits
1809system.cpu1.l2cache.demand_mshr_hits::cpu1.data 293 # number of demand (read+write) MSHR hits
1810system.cpu1.l2cache.demand_mshr_hits::total 1032 # number of demand (read+write) MSHR hits
1811system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 739 # number of overall MSHR hits
1812system.cpu1.l2cache.overall_mshr_hits::cpu1.data 293 # number of overall MSHR hits
1813system.cpu1.l2cache.overall_mshr_hits::total 1032 # number of overall MSHR hits
1814system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 338 # number of ReadReq MSHR misses
1815system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 277 # number of ReadReq MSHR misses
1816system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 4902 # number of ReadReq MSHR misses
1817system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70211 # number of ReadReq MSHR misses
1818system.cpu1.l2cache.ReadReq_mshr_misses::total 75728 # number of ReadReq MSHR misses
1819system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of HardPFReq MSHR misses
1820system.cpu1.l2cache.HardPFReq_mshr_misses::total 119097 # number of HardPFReq MSHR misses
1821system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29399 # number of UpgradeReq MSHR misses
1822system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29399 # number of UpgradeReq MSHR misses
1823system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22337 # number of SCUpgradeReq MSHR misses
1824system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22337 # number of SCUpgradeReq MSHR misses
1825system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 7 # number of SCUpgradeFailReq MSHR misses
1826system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses
1827system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33405 # number of ReadExReq MSHR misses
1828system.cpu1.l2cache.ReadExReq_mshr_misses::total 33405 # number of ReadExReq MSHR misses
1829system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 338 # number of demand (read+write) MSHR misses
1830system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 277 # number of demand (read+write) MSHR misses
1831system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 4902 # number of demand (read+write) MSHR misses
1832system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103616 # number of demand (read+write) MSHR misses
1833system.cpu1.l2cache.demand_mshr_misses::total 109133 # number of demand (read+write) MSHR misses
1834system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 338 # number of overall MSHR misses
1835system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 277 # number of overall MSHR misses
1836system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 4902 # number of overall MSHR misses
1837system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103616 # number of overall MSHR misses
1838system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 119097 # number of overall MSHR misses
1839system.cpu1.l2cache.overall_mshr_misses::total 228230 # number of overall MSHR misses
1840system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of ReadReq MSHR miss cycles
1841system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3607000 # number of ReadReq MSHR miss cycles
1842system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 143902025 # number of ReadReq MSHR miss cycles
1843system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1053014200 # number of ReadReq MSHR miss cycles
1844system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1205109225 # number of ReadReq MSHR miss cycles
1845system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of HardPFReq MSHR miss cycles
1846system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 3247389638 # number of HardPFReq MSHR miss cycles
1847system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 430450689 # number of UpgradeReq MSHR miss cycles
1848system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 430450689 # number of UpgradeReq MSHR miss cycles
1849system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306453691 # number of SCUpgradeReq MSHR miss cycles
1850system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306453691 # number of SCUpgradeReq MSHR miss cycles
1851system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1303500 # number of SCUpgradeFailReq MSHR miss cycles
1852system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1303500 # number of SCUpgradeFailReq MSHR miss cycles
1853system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 820460623 # number of ReadExReq MSHR miss cycles
1854system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 820460623 # number of ReadExReq MSHR miss cycles
1855system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of demand (read+write) MSHR miss cycles
1856system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3607000 # number of demand (read+write) MSHR miss cycles
1857system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 143902025 # number of demand (read+write) MSHR miss cycles
1858system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1873474823 # number of demand (read+write) MSHR miss cycles
1859system.cpu1.l2cache.demand_mshr_miss_latency::total 2025569848 # number of demand (read+write) MSHR miss cycles
1860system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4586000 # number of overall MSHR miss cycles
1861system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3607000 # number of overall MSHR miss cycles
1862system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 143902025 # number of overall MSHR miss cycles
1863system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1873474823 # number of overall MSHR miss cycles
1864system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 3247389638 # number of overall MSHR miss cycles
1865system.cpu1.l2cache.overall_mshr_miss_latency::total 5272959486 # number of overall MSHR miss cycles
1866system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12475500 # number of ReadReq MSHR uncacheable cycles
1867system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 916023500 # number of ReadReq MSHR uncacheable cycles
1868system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 928499000 # number of ReadReq MSHR uncacheable cycles
1869system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 796472502 # number of WriteReq MSHR uncacheable cycles
1870system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 796472502 # number of WriteReq MSHR uncacheable cycles
1871system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12475500 # number of overall MSHR uncacheable cycles
1872system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712496002 # number of overall MSHR uncacheable cycles
1873system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1724971502 # number of overall MSHR uncacheable cycles
1874system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for ReadReq accesses
1875system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for ReadReq accesses
1876system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for ReadReq accesses
1877system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.362744 # mshr miss rate for ReadReq accesses
1878system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.099070 # mshr miss rate for ReadReq accesses
1879system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1880system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1881system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.948110 # mshr miss rate for UpgradeReq accesses
1882system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.948110 # mshr miss rate for UpgradeReq accesses
1883system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962885 # mshr miss rate for SCUpgradeReq accesses
1884system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962885 # mshr miss rate for SCUpgradeReq accesses
1885system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1886system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1887system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.459005 # mshr miss rate for ReadExReq accesses
1888system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.459005 # mshr miss rate for ReadExReq accesses
1889system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for demand accesses
1890system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for demand accesses
1891system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for demand accesses
1892system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for demand accesses
1893system.cpu1.l2cache.demand_mshr_miss_rate::total 0.130360 # mshr miss rate for demand accesses
1894system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.101380 # mshr miss rate for overall accesses
1895system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.139828 # mshr miss rate for overall accesses
1896system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.008668 # mshr miss rate for overall accesses
1897system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.389048 # mshr miss rate for overall accesses
1898system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
1899system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272623 # mshr miss rate for overall accesses
1900system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average ReadReq mshr miss latency
1901system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average ReadReq mshr miss latency
1902system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average ReadReq mshr miss latency
1903system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188 # average ReadReq mshr miss latency
1904system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461 # average ReadReq mshr miss latency
1905system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average HardPFReq mshr miss latency
1906system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706 # average HardPFReq mshr miss latency
1907system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914 # average UpgradeReq mshr miss latency
1908system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914 # average UpgradeReq mshr miss latency
1909system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596 # average SCUpgradeReq mshr miss latency
1910system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596 # average SCUpgradeReq mshr miss latency
1911system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714 # average SCUpgradeFailReq mshr miss latency
1912system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714 # average SCUpgradeFailReq mshr miss latency
1913system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513 # average ReadExReq mshr miss latency
1914system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513 # average ReadExReq mshr miss latency
1915system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency
1916system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency
1917system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency
1918system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency
1919system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323 # average overall mshr miss latency
1920system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency
1921system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency
1922system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency
1923system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency
1924system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average overall mshr miss latency
1925system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916 # average overall mshr miss latency
1926system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
1927system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
1928system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1929system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
1930system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1931system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
1932system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
1933system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1934system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1935system.cpu1.toL2Bus.trans_dist::ReadReq 1205511 # Transaction distribution
1936system.cpu1.toL2Bus.trans_dist::ReadResp 816520 # Transaction distribution
1937system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution
1938system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution
1939system.cpu1.toL2Bus.trans_dist::Writeback 135060 # Transaction distribution
1940system.cpu1.toL2Bus.trans_dist::HardPFReq 171236 # Transaction distribution
1941system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
1942system.cpu1.toL2Bus.trans_dist::UpgradeReq 86319 # Transaction distribution
1943system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42477 # Transaction distribution
1944system.cpu1.toL2Bus.trans_dist::UpgradeResp 89729 # Transaction distribution
1945system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
1946system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
1947system.cpu1.toL2Bus.trans_dist::ReadExReq 90979 # Transaction distribution
1948system.cpu1.toL2Bus.trans_dist::ReadExResp 78176 # Transaction distribution
1949system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131388 # Packet count per connected master and slave (bytes)
1950system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880635 # Packet count per connected master and slave (bytes)
1951system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes)
1952system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9255 # Packet count per connected master and slave (bytes)
1953system.cpu1.toL2Bus.pkt_count::total 2026584 # Packet count per connected master and slave (bytes)
1954system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36193796 # Cumulative packet size per connected master and slave (bytes)
1955system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28781627 # Cumulative packet size per connected master and slave (bytes)
1956system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes)
1957system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13336 # Cumulative packet size per connected master and slave (bytes)
1958system.cpu1.toL2Bus.pkt_size::total 64996683 # Cumulative packet size per connected master and slave (bytes)
1959system.cpu1.toL2Bus.snoops 818999 # Total snoops (count)
1960system.cpu1.toL2Bus.snoop_fanout::samples 1762052 # Request fanout histogram
1961system.cpu1.toL2Bus.snoop_fanout::mean 5.415245 # Request fanout histogram
1962system.cpu1.toL2Bus.snoop_fanout::stdev 0.492764 # Request fanout histogram
1963system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1964system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1965system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1966system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1967system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1968system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1969system.cpu1.toL2Bus.snoop_fanout::5 1030369 58.48% 58.48% # Request fanout histogram
1970system.cpu1.toL2Bus.snoop_fanout::6 731683 41.52% 100.00% # Request fanout histogram
1971system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1972system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1973system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1974system.cpu1.toL2Bus.snoop_fanout::total 1762052 # Request fanout histogram
1975system.cpu1.toL2Bus.reqLayer0.occupancy 658210715 # Layer occupancy (ticks)
1976system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1977system.cpu1.toL2Bus.snoopLayer0.occupancy 89516500 # Layer occupancy (ticks)
1978system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1979system.cpu1.toL2Bus.respLayer0.occupancy 848574281 # Layer occupancy (ticks)
1980system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1981system.cpu1.toL2Bus.respLayer1.occupancy 438678337 # Layer occupancy (ticks)
1982system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1983system.cpu1.toL2Bus.respLayer2.occupancy 3325000 # Layer occupancy (ticks)
1984system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1985system.cpu1.toL2Bus.respLayer3.occupancy 5921000 # Layer occupancy (ticks)
1986system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1987system.iobus.trans_dist::ReadReq 31019 # Transaction distribution
1988system.iobus.trans_dist::ReadResp 31019 # Transaction distribution
1989system.iobus.trans_dist::WriteReq 59407 # Transaction distribution
1990system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
1991system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution
1992system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
1993system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
1994system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
1995system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
1996system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
1997system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes)
1998system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
1999system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2000system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2001system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2002system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
2003system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2004system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
2005system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
2006system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
2007system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
2008system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
2009system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2010system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
2011system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2012system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2013system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes)
2014system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes)
2015system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes)
2016system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes)
2017system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
2018system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
2019system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
2020system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
2021system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
2022system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes)
2023system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
2024system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2025system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2026system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2027system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
2028system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2029system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2030system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
2031system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
2032system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2033system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
2034system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
2035system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
2036system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
2037system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2038system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes)
2039system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes)
2040system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes)
2041system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes)
2042system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
2043system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2044system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
2045system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2046system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
2047system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2048system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
2049system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2050system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
2051system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
2052system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks)
2053system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
2054system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
2055system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2056system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2057system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2058system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
2059system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2060system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
2061system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2062system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
2063system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2064system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2065system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2066system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
2067system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
2068system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
2069system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
2070system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
2071system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
2072system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
2073system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
2074system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
2075system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2076system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
2077system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2078system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
2079system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2080system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
2081system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2082system.iobus.reqLayer27.occupancy 326671825 # Layer occupancy (ticks)
2083system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2084system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2085system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2086system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks)
2087system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2088system.iobus.respLayer3.occupancy 36845580 # Layer occupancy (ticks)
2089system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2090system.iocache.tags.replacements 36443 # number of replacements
2091system.iocache.tags.tagsinuse 14.446794 # Cycle average of tags in use
2092system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
2093system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks.
2094system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
2095system.iocache.tags.warmup_cycle 277163106000 # Cycle when the warmup percentage was hit.
2096system.iocache.tags.occ_blocks::realview.ide 14.446794 # Average occupied blocks per requestor
2097system.iocache.tags.occ_percent::realview.ide 0.902925 # Average percentage of cache occupancy
2098system.iocache.tags.occ_percent::total 0.902925 # Average percentage of cache occupancy
2099system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2100system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2101system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2102system.iocache.tags.tag_accesses 328557 # Number of tag accesses
2103system.iocache.tags.data_accesses 328557 # Number of data accesses
2104system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
2105system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
2106system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses
2107system.iocache.ReadReq_misses::total 253 # number of ReadReq misses
2108system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses
2109system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses
2110system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses
2111system.iocache.demand_misses::total 253 # number of demand (read+write) misses
2112system.iocache.overall_misses::realview.ide 253 # number of overall misses
2113system.iocache.overall_misses::total 253 # number of overall misses
2114system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles
2115system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles
2116system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles
2117system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles
2118system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles
2119system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles
2120system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses)
2121system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses)
2122system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses)
2123system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses)
2124system.iocache.demand_accesses::realview.ide 253 # number of demand (read+write) accesses
2125system.iocache.demand_accesses::total 253 # number of demand (read+write) accesses
2126system.iocache.overall_accesses::realview.ide 253 # number of overall (read+write) accesses
2127system.iocache.overall_accesses::total 253 # number of overall (read+write) accesses
2128system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2129system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2130system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses
2131system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses
2132system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2133system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2134system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2135system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2136system.iocache.ReadReq_avg_miss_latency::realview.ide 124938.249012 # average ReadReq miss latency
2137system.iocache.ReadReq_avg_miss_latency::total 124938.249012 # average ReadReq miss latency
2138system.iocache.demand_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency
2139system.iocache.demand_avg_miss_latency::total 124938.249012 # average overall miss latency
2140system.iocache.overall_avg_miss_latency::realview.ide 124938.249012 # average overall miss latency
2141system.iocache.overall_avg_miss_latency::total 124938.249012 # average overall miss latency
2142system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
2143system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2144system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
2145system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2146system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
2147system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2148system.iocache.fast_writes 36224 # number of fast writes performed
2149system.iocache.cache_copies 0 # number of cache copies performed
2150system.iocache.ReadReq_mshr_misses::realview.ide 253 # number of ReadReq MSHR misses
2151system.iocache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses
2152system.iocache.demand_mshr_misses::realview.ide 253 # number of demand (read+write) MSHR misses
2153system.iocache.demand_mshr_misses::total 253 # number of demand (read+write) MSHR misses
2154system.iocache.overall_mshr_misses::realview.ide 253 # number of overall MSHR misses
2155system.iocache.overall_mshr_misses::total 253 # number of overall MSHR misses
2156system.iocache.ReadReq_mshr_miss_latency::realview.ide 18452377 # number of ReadReq MSHR miss cycles
2157system.iocache.ReadReq_mshr_miss_latency::total 18452377 # number of ReadReq MSHR miss cycles
2158system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2250014028 # number of WriteInvalidateReq MSHR miss cycles
2159system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2250014028 # number of WriteInvalidateReq MSHR miss cycles
2160system.iocache.demand_mshr_miss_latency::realview.ide 18452377 # number of demand (read+write) MSHR miss cycles
2161system.iocache.demand_mshr_miss_latency::total 18452377 # number of demand (read+write) MSHR miss cycles
2162system.iocache.overall_mshr_miss_latency::realview.ide 18452377 # number of overall MSHR miss cycles
2163system.iocache.overall_mshr_miss_latency::total 18452377 # number of overall MSHR miss cycles
2164system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2165system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2166system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2167system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2168system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2169system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2170system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72934.296443 # average ReadReq mshr miss latency
2171system.iocache.ReadReq_avg_mshr_miss_latency::total 72934.296443 # average ReadReq mshr miss latency
2172system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
2173system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
2174system.iocache.demand_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency
2175system.iocache.demand_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency
2176system.iocache.overall_avg_mshr_miss_latency::realview.ide 72934.296443 # average overall mshr miss latency
2177system.iocache.overall_avg_mshr_miss_latency::total 72934.296443 # average overall mshr miss latency
2178system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2179system.l2c.tags.replacements 132935 # number of replacements
2180system.l2c.tags.tagsinuse 64217.518730 # Cycle average of tags in use
2181system.l2c.tags.total_refs 488817 # Total number of references to valid blocks.
2182system.l2c.tags.sampled_refs 197475 # Sample count of references to valid blocks.
2183system.l2c.tags.avg_refs 2.475336 # Average number of references to valid blocks.
2184system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2185system.l2c.tags.occ_blocks::writebacks 12771.193603 # Average occupied blocks per requestor
2186system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.858844 # Average occupied blocks per requestor
2187system.l2c.tags.occ_blocks::cpu0.itb.walker 0.037003 # Average occupied blocks per requestor
2188system.l2c.tags.occ_blocks::cpu0.inst 1138.507599 # Average occupied blocks per requestor
2189system.l2c.tags.occ_blocks::cpu0.data 1415.888274 # Average occupied blocks per requestor
2190system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38649.791796 # Average occupied blocks per requestor
2191system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.641656 # Average occupied blocks per requestor
2192system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor
2193system.l2c.tags.occ_blocks::cpu1.inst 536.042723 # Average occupied blocks per requestor
2194system.l2c.tags.occ_blocks::cpu1.data 904.271560 # Average occupied blocks per requestor
2195system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8794.277876 # Average occupied blocks per requestor
2196system.l2c.tags.occ_percent::writebacks 0.194873 # Average percentage of cache occupancy
2197system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy
2198system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
2199system.l2c.tags.occ_percent::cpu0.inst 0.017372 # Average percentage of cache occupancy
2200system.l2c.tags.occ_percent::cpu0.data 0.021605 # Average percentage of cache occupancy
2201system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.589749 # Average percentage of cache occupancy
2202system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000040 # Average percentage of cache occupancy
2203system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
2204system.l2c.tags.occ_percent::cpu1.inst 0.008179 # Average percentage of cache occupancy
2205system.l2c.tags.occ_percent::cpu1.data 0.013798 # Average percentage of cache occupancy
2206system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.134190 # Average percentage of cache occupancy
2207system.l2c.tags.occ_percent::total 0.979882 # Average percentage of cache occupancy
2208system.l2c.tags.occ_task_id_blocks::1022 44757 # Occupied blocks per task id
2209system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
2210system.l2c.tags.occ_task_id_blocks::1024 19776 # Occupied blocks per task id
2211system.l2c.tags.age_task_id_blocks_1022::2 193 # Occupied blocks per task id
2212system.l2c.tags.age_task_id_blocks_1022::3 5076 # Occupied blocks per task id
2213system.l2c.tags.age_task_id_blocks_1022::4 39488 # Occupied blocks per task id
2214system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
2215system.l2c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
2216system.l2c.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
2217system.l2c.tags.age_task_id_blocks_1024::3 1542 # Occupied blocks per task id
2218system.l2c.tags.age_task_id_blocks_1024::4 18030 # Occupied blocks per task id
2219system.l2c.tags.occ_task_id_percent::1022 0.682938 # Percentage of cache occupancy per task id
2220system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id
2221system.l2c.tags.occ_task_id_percent::1024 0.301758 # Percentage of cache occupancy per task id
2222system.l2c.tags.tag_accesses 6143442 # Number of tag accesses
2223system.l2c.tags.data_accesses 6143442 # Number of data accesses
2224system.l2c.ReadReq_hits::cpu0.dtb.walker 146 # number of ReadReq hits
2225system.l2c.ReadReq_hits::cpu0.itb.walker 155 # number of ReadReq hits
2226system.l2c.ReadReq_hits::cpu0.inst 10201 # number of ReadReq hits
2227system.l2c.ReadReq_hits::cpu0.data 29439 # number of ReadReq hits
2228system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 168037 # number of ReadReq hits
2229system.l2c.ReadReq_hits::cpu1.dtb.walker 53 # number of ReadReq hits
2230system.l2c.ReadReq_hits::cpu1.itb.walker 44 # number of ReadReq hits
2231system.l2c.ReadReq_hits::cpu1.inst 4112 # number of ReadReq hits
2232system.l2c.ReadReq_hits::cpu1.data 10373 # number of ReadReq hits
2233system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47653 # number of ReadReq hits
2234system.l2c.ReadReq_hits::total 270213 # number of ReadReq hits
2235system.l2c.Writeback_hits::writebacks 240423 # number of Writeback hits
2236system.l2c.Writeback_hits::total 240423 # number of Writeback hits
2237system.l2c.UpgradeReq_hits::cpu0.data 9633 # number of UpgradeReq hits
2238system.l2c.UpgradeReq_hits::cpu1.data 1000 # number of UpgradeReq hits
2239system.l2c.UpgradeReq_hits::total 10633 # number of UpgradeReq hits
2240system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits
2241system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits
2242system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits
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2254system.l2c.demand_hits::cpu1.data 12939 # number of demand (read+write) hits
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2256system.l2c.demand_hits::total 276883 # number of demand (read+write) hits
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2259system.l2c.overall_hits::cpu0.inst 10201 # number of overall hits
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2261system.l2c.overall_hits::cpu0.l2cache.prefetcher 168037 # number of overall hits
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2265system.l2c.overall_hits::cpu1.data 12939 # number of overall hits
2266system.l2c.overall_hits::cpu1.l2cache.prefetcher 47653 # number of overall hits
2267system.l2c.overall_hits::total 276883 # number of overall hits
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2278system.l2c.ReadReq_misses::total 183916 # number of ReadReq misses
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2281system.l2c.UpgradeReq_misses::total 12745 # number of UpgradeReq misses
2282system.l2c.SCUpgradeReq_misses::cpu0.data 893 # number of SCUpgradeReq misses
2283system.l2c.SCUpgradeReq_misses::cpu1.data 1293 # number of SCUpgradeReq misses
2284system.l2c.SCUpgradeReq_misses::total 2186 # number of SCUpgradeReq misses
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2286system.l2c.ReadExReq_misses::cpu1.data 5553 # number of ReadExReq misses
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2289system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
2290system.l2c.demand_misses::cpu0.inst 3124 # number of demand (read+write) misses
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2292system.l2c.demand_misses::cpu0.l2cache.prefetcher 150306 # number of demand (read+write) misses
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2296system.l2c.demand_misses::cpu1.data 6953 # number of demand (read+write) misses
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2298system.l2c.demand_misses::total 195660 # number of demand (read+write) misses
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2309system.l2c.overall_misses::total 195660 # number of overall misses
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2311system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles
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2315system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 223500 # number of ReadReq miss cycles
2316system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles
2317system.l2c.ReadReq_miss_latency::cpu1.inst 71055248 # number of ReadReq miss cycles
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2320system.l2c.ReadReq_miss_latency::total 18387871837 # number of ReadReq miss cycles
2321system.l2c.UpgradeReq_miss_latency::cpu0.data 9302615 # number of UpgradeReq miss cycles
2322system.l2c.UpgradeReq_miss_latency::cpu1.data 9559091 # number of UpgradeReq miss cycles
2323system.l2c.UpgradeReq_miss_latency::total 18861706 # number of UpgradeReq miss cycles
2324system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1287445 # number of SCUpgradeReq miss cycles
2325system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2175907 # number of SCUpgradeReq miss cycles
2326system.l2c.SCUpgradeReq_miss_latency::total 3463352 # number of SCUpgradeReq miss cycles
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2328system.l2c.ReadExReq_miss_latency::cpu1.data 403495431 # number of ReadExReq miss cycles
2329system.l2c.ReadExReq_miss_latency::total 895071068 # number of ReadExReq miss cycles
2330system.l2c.demand_miss_latency::cpu0.dtb.walker 598250 # number of demand (read+write) miss cycles
2331system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles
2332system.l2c.demand_miss_latency::cpu0.inst 271876998 # number of demand (read+write) miss cycles
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2335system.l2c.demand_miss_latency::cpu1.dtb.walker 223500 # number of demand (read+write) miss cycles
2336system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles
2337system.l2c.demand_miss_latency::cpu1.inst 71055248 # number of demand (read+write) miss cycles
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2339system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of demand (read+write) miss cycles
2340system.l2c.demand_miss_latency::total 19282942905 # number of demand (read+write) miss cycles
2341system.l2c.overall_miss_latency::cpu0.dtb.walker 598250 # number of overall miss cycles
2342system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles
2343system.l2c.overall_miss_latency::cpu0.inst 271876998 # number of overall miss cycles
2344system.l2c.overall_miss_latency::cpu0.data 1061951136 # number of overall miss cycles
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2346system.l2c.overall_miss_latency::cpu1.dtb.walker 223500 # number of overall miss cycles
2347system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles
2348system.l2c.overall_miss_latency::cpu1.inst 71055248 # number of overall miss cycles
2349system.l2c.overall_miss_latency::cpu1.data 522722930 # number of overall miss cycles
2350system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2276558323 # number of overall miss cycles
2351system.l2c.overall_miss_latency::total 19282942905 # number of overall miss cycles
2352system.l2c.ReadReq_accesses::cpu0.dtb.walker 154 # number of ReadReq accesses(hits+misses)
2353system.l2c.ReadReq_accesses::cpu0.itb.walker 156 # number of ReadReq accesses(hits+misses)
2354system.l2c.ReadReq_accesses::cpu0.inst 13325 # number of ReadReq accesses(hits+misses)
2355system.l2c.ReadReq_accesses::cpu0.data 36430 # number of ReadReq accesses(hits+misses)
2356system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 318343 # number of ReadReq accesses(hits+misses)
2357system.l2c.ReadReq_accesses::cpu1.dtb.walker 56 # number of ReadReq accesses(hits+misses)
2358system.l2c.ReadReq_accesses::cpu1.itb.walker 45 # number of ReadReq accesses(hits+misses)
2359system.l2c.ReadReq_accesses::cpu1.inst 4898 # number of ReadReq accesses(hits+misses)
2360system.l2c.ReadReq_accesses::cpu1.data 11773 # number of ReadReq accesses(hits+misses)
2361system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 68949 # number of ReadReq accesses(hits+misses)
2362system.l2c.ReadReq_accesses::total 454129 # number of ReadReq accesses(hits+misses)
2363system.l2c.Writeback_accesses::writebacks 240423 # number of Writeback accesses(hits+misses)
2364system.l2c.Writeback_accesses::total 240423 # number of Writeback accesses(hits+misses)
2365system.l2c.UpgradeReq_accesses::cpu0.data 18187 # number of UpgradeReq accesses(hits+misses)
2366system.l2c.UpgradeReq_accesses::cpu1.data 5191 # number of UpgradeReq accesses(hits+misses)
2367system.l2c.UpgradeReq_accesses::total 23378 # number of UpgradeReq accesses(hits+misses)
2368system.l2c.SCUpgradeReq_accesses::cpu0.data 1140 # number of SCUpgradeReq accesses(hits+misses)
2369system.l2c.SCUpgradeReq_accesses::cpu1.data 1430 # number of SCUpgradeReq accesses(hits+misses)
2370system.l2c.SCUpgradeReq_accesses::total 2570 # number of SCUpgradeReq accesses(hits+misses)
2371system.l2c.ReadExReq_accesses::cpu0.data 10295 # number of ReadExReq accesses(hits+misses)
2372system.l2c.ReadExReq_accesses::cpu1.data 8119 # number of ReadExReq accesses(hits+misses)
2373system.l2c.ReadExReq_accesses::total 18414 # number of ReadExReq accesses(hits+misses)
2374system.l2c.demand_accesses::cpu0.dtb.walker 154 # number of demand (read+write) accesses
2375system.l2c.demand_accesses::cpu0.itb.walker 156 # number of demand (read+write) accesses
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2377system.l2c.demand_accesses::cpu0.data 46725 # number of demand (read+write) accesses
2378system.l2c.demand_accesses::cpu0.l2cache.prefetcher 318343 # number of demand (read+write) accesses
2379system.l2c.demand_accesses::cpu1.dtb.walker 56 # number of demand (read+write) accesses
2380system.l2c.demand_accesses::cpu1.itb.walker 45 # number of demand (read+write) accesses
2381system.l2c.demand_accesses::cpu1.inst 4898 # number of demand (read+write) accesses
2382system.l2c.demand_accesses::cpu1.data 19892 # number of demand (read+write) accesses
2383system.l2c.demand_accesses::cpu1.l2cache.prefetcher 68949 # number of demand (read+write) accesses
2384system.l2c.demand_accesses::total 472543 # number of demand (read+write) accesses
2385system.l2c.overall_accesses::cpu0.dtb.walker 154 # number of overall (read+write) accesses
2386system.l2c.overall_accesses::cpu0.itb.walker 156 # number of overall (read+write) accesses
2387system.l2c.overall_accesses::cpu0.inst 13325 # number of overall (read+write) accesses
2388system.l2c.overall_accesses::cpu0.data 46725 # number of overall (read+write) accesses
2389system.l2c.overall_accesses::cpu0.l2cache.prefetcher 318343 # number of overall (read+write) accesses
2390system.l2c.overall_accesses::cpu1.dtb.walker 56 # number of overall (read+write) accesses
2391system.l2c.overall_accesses::cpu1.itb.walker 45 # number of overall (read+write) accesses
2392system.l2c.overall_accesses::cpu1.inst 4898 # number of overall (read+write) accesses
2393system.l2c.overall_accesses::cpu1.data 19892 # number of overall (read+write) accesses
2394system.l2c.overall_accesses::cpu1.l2cache.prefetcher 68949 # number of overall (read+write) accesses
2395system.l2c.overall_accesses::total 472543 # number of overall (read+write) accesses
2396system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for ReadReq accesses
2397system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.006410 # miss rate for ReadReq accesses
2398system.l2c.ReadReq_miss_rate::cpu0.inst 0.234447 # miss rate for ReadReq accesses
2399system.l2c.ReadReq_miss_rate::cpu0.data 0.191902 # miss rate for ReadReq accesses
2400system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for ReadReq accesses
2401system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for ReadReq accesses
2402system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.022222 # miss rate for ReadReq accesses
2403system.l2c.ReadReq_miss_rate::cpu1.inst 0.160474 # miss rate for ReadReq accesses
2404system.l2c.ReadReq_miss_rate::cpu1.data 0.118916 # miss rate for ReadReq accesses
2405system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for ReadReq accesses
2406system.l2c.ReadReq_miss_rate::total 0.404986 # miss rate for ReadReq accesses
2407system.l2c.UpgradeReq_miss_rate::cpu0.data 0.470336 # miss rate for UpgradeReq accesses
2408system.l2c.UpgradeReq_miss_rate::cpu1.data 0.807359 # miss rate for UpgradeReq accesses
2409system.l2c.UpgradeReq_miss_rate::total 0.545171 # miss rate for UpgradeReq accesses
2410system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.783333 # miss rate for SCUpgradeReq accesses
2411system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.904196 # miss rate for SCUpgradeReq accesses
2412system.l2c.SCUpgradeReq_miss_rate::total 0.850584 # miss rate for SCUpgradeReq accesses
2413system.l2c.ReadExReq_miss_rate::cpu0.data 0.601360 # miss rate for ReadExReq accesses
2414system.l2c.ReadExReq_miss_rate::cpu1.data 0.683951 # miss rate for ReadExReq accesses
2415system.l2c.ReadExReq_miss_rate::total 0.637776 # miss rate for ReadExReq accesses
2416system.l2c.demand_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for demand accesses
2417system.l2c.demand_miss_rate::cpu0.itb.walker 0.006410 # miss rate for demand accesses
2418system.l2c.demand_miss_rate::cpu0.inst 0.234447 # miss rate for demand accesses
2419system.l2c.demand_miss_rate::cpu0.data 0.282119 # miss rate for demand accesses
2420system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for demand accesses
2421system.l2c.demand_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for demand accesses
2422system.l2c.demand_miss_rate::cpu1.itb.walker 0.022222 # miss rate for demand accesses
2423system.l2c.demand_miss_rate::cpu1.inst 0.160474 # miss rate for demand accesses
2424system.l2c.demand_miss_rate::cpu1.data 0.349538 # miss rate for demand accesses
2425system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for demand accesses
2426system.l2c.demand_miss_rate::total 0.414058 # miss rate for demand accesses
2427system.l2c.overall_miss_rate::cpu0.dtb.walker 0.051948 # miss rate for overall accesses
2428system.l2c.overall_miss_rate::cpu0.itb.walker 0.006410 # miss rate for overall accesses
2429system.l2c.overall_miss_rate::cpu0.inst 0.234447 # miss rate for overall accesses
2430system.l2c.overall_miss_rate::cpu0.data 0.282119 # miss rate for overall accesses
2431system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.472151 # miss rate for overall accesses
2432system.l2c.overall_miss_rate::cpu1.dtb.walker 0.053571 # miss rate for overall accesses
2433system.l2c.overall_miss_rate::cpu1.itb.walker 0.022222 # miss rate for overall accesses
2434system.l2c.overall_miss_rate::cpu1.inst 0.160474 # miss rate for overall accesses
2435system.l2c.overall_miss_rate::cpu1.data 0.349538 # miss rate for overall accesses
2436system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.308866 # miss rate for overall accesses
2437system.l2c.overall_miss_rate::total 0.414058 # miss rate for overall accesses
2438system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average ReadReq miss latency
2439system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency
2440system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87028.488476 # average ReadReq miss latency
2441system.l2c.ReadReq_avg_miss_latency::cpu0.data 81587.111858 # average ReadReq miss latency
2442system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average ReadReq miss latency
2443system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency
2444system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency
2445system.l2c.ReadReq_avg_miss_latency::cpu1.inst 90401.078880 # average ReadReq miss latency
2446system.l2c.ReadReq_avg_miss_latency::cpu1.data 85162.499286 # average ReadReq miss latency
2447system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average ReadReq miss latency
2448system.l2c.ReadReq_avg_miss_latency::total 99979.728990 # average ReadReq miss latency
2449system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1087.516367 # average UpgradeReq miss latency
2450system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2280.861608 # average UpgradeReq miss latency
2451system.l2c.UpgradeReq_avg_miss_latency::total 1479.929855 # average UpgradeReq miss latency
2452system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1441.707727 # average SCUpgradeReq miss latency
2453system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1682.836040 # average SCUpgradeReq miss latency
2454system.l2c.SCUpgradeReq_avg_miss_latency::total 1584.333028 # average SCUpgradeReq miss latency
2455system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79401.653529 # average ReadExReq miss latency
2456system.l2c.ReadExReq_avg_miss_latency::cpu1.data 72662.602377 # average ReadExReq miss latency
2457system.l2c.ReadExReq_avg_miss_latency::total 76215.179496 # average ReadExReq miss latency
2458system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency
2459system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
2460system.l2c.demand_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency
2461system.l2c.demand_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency
2462system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency
2463system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
2464system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
2465system.l2c.demand_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency
2466system.l2c.demand_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency
2467system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency
2468system.l2c.demand_avg_miss_latency::total 98553.321604 # average overall miss latency
2469system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74781.250000 # average overall miss latency
2470system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
2471system.l2c.overall_avg_miss_latency::cpu0.inst 87028.488476 # average overall miss latency
2472system.l2c.overall_avg_miss_latency::cpu0.data 80560.699135 # average overall miss latency
2473system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 100314.072758 # average overall miss latency
2474system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
2475system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency
2476system.l2c.overall_avg_miss_latency::cpu1.inst 90401.078880 # average overall miss latency
2477system.l2c.overall_avg_miss_latency::cpu1.data 75179.480800 # average overall miss latency
2478system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 106900.747699 # average overall miss latency
2479system.l2c.overall_avg_miss_latency::total 98553.321604 # average overall miss latency
2480system.l2c.blocked_cycles::no_mshrs 370 # number of cycles access was blocked
2481system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
2482system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked
2483system.l2c.blocked::no_targets 0 # number of cycles access was blocked
2484system.l2c.avg_blocked_cycles::no_mshrs 46.250000 # average number of cycles each access was blocked
2485system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2486system.l2c.fast_writes 0 # number of fast writes performed
2487system.l2c.cache_copies 0 # number of cache copies performed
2488system.l2c.writebacks::writebacks 99922 # number of writebacks
2489system.l2c.writebacks::total 99922 # number of writebacks
2490system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadReq MSHR hits
2491system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
2492system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
2493system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
2494system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits
2495system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits
2496system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 8 # number of ReadReq MSHR misses
2497system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses
2498system.l2c.ReadReq_mshr_misses::cpu0.inst 3124 # number of ReadReq MSHR misses
2499system.l2c.ReadReq_mshr_misses::cpu0.data 6991 # number of ReadReq MSHR misses
2500system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of ReadReq MSHR misses
2501system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses
2502system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
2503system.l2c.ReadReq_mshr_misses::cpu1.inst 786 # number of ReadReq MSHR misses
2504system.l2c.ReadReq_mshr_misses::cpu1.data 1400 # number of ReadReq MSHR misses
2505system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of ReadReq MSHR misses
2506system.l2c.ReadReq_mshr_misses::total 183915 # number of ReadReq MSHR misses
2507system.l2c.UpgradeReq_mshr_misses::cpu0.data 8554 # number of UpgradeReq MSHR misses
2508system.l2c.UpgradeReq_mshr_misses::cpu1.data 4191 # number of UpgradeReq MSHR misses
2509system.l2c.UpgradeReq_mshr_misses::total 12745 # number of UpgradeReq MSHR misses
2510system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 893 # number of SCUpgradeReq MSHR misses
2511system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1293 # number of SCUpgradeReq MSHR misses
2512system.l2c.SCUpgradeReq_mshr_misses::total 2186 # number of SCUpgradeReq MSHR misses
2513system.l2c.ReadExReq_mshr_misses::cpu0.data 6191 # number of ReadExReq MSHR misses
2514system.l2c.ReadExReq_mshr_misses::cpu1.data 5553 # number of ReadExReq MSHR misses
2515system.l2c.ReadExReq_mshr_misses::total 11744 # number of ReadExReq MSHR misses
2516system.l2c.demand_mshr_misses::cpu0.dtb.walker 8 # number of demand (read+write) MSHR misses
2517system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses
2518system.l2c.demand_mshr_misses::cpu0.inst 3124 # number of demand (read+write) MSHR misses
2519system.l2c.demand_mshr_misses::cpu0.data 13182 # number of demand (read+write) MSHR misses
2520system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of demand (read+write) MSHR misses
2521system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses
2522system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
2523system.l2c.demand_mshr_misses::cpu1.inst 786 # number of demand (read+write) MSHR misses
2524system.l2c.demand_mshr_misses::cpu1.data 6953 # number of demand (read+write) MSHR misses
2525system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of demand (read+write) MSHR misses
2526system.l2c.demand_mshr_misses::total 195659 # number of demand (read+write) MSHR misses
2527system.l2c.overall_mshr_misses::cpu0.dtb.walker 8 # number of overall MSHR misses
2528system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses
2529system.l2c.overall_mshr_misses::cpu0.inst 3124 # number of overall MSHR misses
2530system.l2c.overall_mshr_misses::cpu0.data 13182 # number of overall MSHR misses
2531system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 150305 # number of overall MSHR misses
2532system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses
2533system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
2534system.l2c.overall_mshr_misses::cpu1.inst 786 # number of overall MSHR misses
2535system.l2c.overall_mshr_misses::cpu1.data 6953 # number of overall MSHR misses
2536system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 21296 # number of overall MSHR misses
2537system.l2c.overall_mshr_misses::total 195659 # number of overall MSHR misses
2538system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 498750 # number of ReadReq MSHR miss cycles
2539system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles
2540system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 233055498 # number of ReadReq MSHR miss cycles
2541system.l2c.ReadReq_mshr_miss_latency::cpu0.data 483422499 # number of ReadReq MSHR miss cycles
2542system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of ReadReq MSHR miss cycles
2543system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 187500 # number of ReadReq MSHR miss cycles
2544system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles
2545system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 61295748 # number of ReadReq MSHR miss cycles
2546system.l2c.ReadReq_mshr_miss_latency::cpu1.data 101745999 # number of ReadReq MSHR miss cycles
2547system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of ReadReq MSHR miss cycles
2548system.l2c.ReadReq_mshr_miss_latency::total 16105922337 # number of ReadReq MSHR miss cycles
2549system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86281499 # number of UpgradeReq MSHR miss cycles
2550system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42154679 # number of UpgradeReq MSHR miss cycles
2551system.l2c.UpgradeReq_mshr_miss_latency::total 128436178 # number of UpgradeReq MSHR miss cycles
2552system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8967891 # number of SCUpgradeReq MSHR miss cycles
2553system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12981791 # number of SCUpgradeReq MSHR miss cycles
2554system.l2c.SCUpgradeReq_mshr_miss_latency::total 21949682 # number of SCUpgradeReq MSHR miss cycles
2555system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 414199861 # number of ReadExReq MSHR miss cycles
2556system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 333199069 # number of ReadExReq MSHR miss cycles
2557system.l2c.ReadExReq_mshr_miss_latency::total 747398930 # number of ReadExReq MSHR miss cycles
2558system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 498750 # number of demand (read+write) MSHR miss cycles
2559system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
2560system.l2c.demand_mshr_miss_latency::cpu0.inst 233055498 # number of demand (read+write) MSHR miss cycles
2561system.l2c.demand_mshr_miss_latency::cpu0.data 897622360 # number of demand (read+write) MSHR miss cycles
2562system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of demand (read+write) MSHR miss cycles
2563system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 187500 # number of demand (read+write) MSHR miss cycles
2564system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
2565system.l2c.demand_mshr_miss_latency::cpu1.inst 61295748 # number of demand (read+write) MSHR miss cycles
2566system.l2c.demand_mshr_miss_latency::cpu1.data 434945068 # number of demand (read+write) MSHR miss cycles
2567system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of demand (read+write) MSHR miss cycles
2568system.l2c.demand_mshr_miss_latency::total 16853321267 # number of demand (read+write) MSHR miss cycles
2569system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 498750 # number of overall MSHR miss cycles
2570system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles
2571system.l2c.overall_mshr_miss_latency::cpu0.inst 233055498 # number of overall MSHR miss cycles
2572system.l2c.overall_mshr_miss_latency::cpu0.data 897622360 # number of overall MSHR miss cycles
2573system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13209375020 # number of overall MSHR miss cycles
2574system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 187500 # number of overall MSHR miss cycles
2575system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
2576system.l2c.overall_mshr_miss_latency::cpu1.inst 61295748 # number of overall MSHR miss cycles
2577system.l2c.overall_mshr_miss_latency::cpu1.data 434945068 # number of overall MSHR miss cycles
2578system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2016216323 # number of overall MSHR miss cycles
2579system.l2c.overall_mshr_miss_latency::total 16853321267 # number of overall MSHR miss cycles
2580system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476661000 # number of ReadReq MSHR uncacheable cycles
2581system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4796922003 # number of ReadReq MSHR uncacheable cycles
2582system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9143000 # number of ReadReq MSHR uncacheable cycles
2583system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 814310000 # number of ReadReq MSHR uncacheable cycles
2584system.l2c.ReadReq_mshr_uncacheable_latency::total 6097036003 # number of ReadReq MSHR uncacheable cycles
2585system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3540062000 # number of WriteReq MSHR uncacheable cycles
2586system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712612000 # number of WriteReq MSHR uncacheable cycles
2587system.l2c.WriteReq_mshr_uncacheable_latency::total 4252674000 # number of WriteReq MSHR uncacheable cycles
2588system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles
2589system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8336984003 # number of overall MSHR uncacheable cycles
2590system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles
2591system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526922000 # number of overall MSHR uncacheable cycles
2592system.l2c.overall_mshr_uncacheable_latency::total 10349710003 # number of overall MSHR uncacheable cycles
2593system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for ReadReq accesses
2594system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for ReadReq accesses
2595system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for ReadReq accesses
2596system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191902 # mshr miss rate for ReadReq accesses
2597system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for ReadReq accesses
2598system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for ReadReq accesses
2599system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for ReadReq accesses
2600system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for ReadReq accesses
2601system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.118916 # mshr miss rate for ReadReq accesses
2602system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for ReadReq accesses
2603system.l2c.ReadReq_mshr_miss_rate::total 0.404984 # mshr miss rate for ReadReq accesses
2604system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.470336 # mshr miss rate for UpgradeReq accesses
2605system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.807359 # mshr miss rate for UpgradeReq accesses
2606system.l2c.UpgradeReq_mshr_miss_rate::total 0.545171 # mshr miss rate for UpgradeReq accesses
2607system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783333 # mshr miss rate for SCUpgradeReq accesses
2608system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.904196 # mshr miss rate for SCUpgradeReq accesses
2609system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850584 # mshr miss rate for SCUpgradeReq accesses
2610system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.601360 # mshr miss rate for ReadExReq accesses
2611system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.683951 # mshr miss rate for ReadExReq accesses
2612system.l2c.ReadExReq_mshr_miss_rate::total 0.637776 # mshr miss rate for ReadExReq accesses
2613system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for demand accesses
2614system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for demand accesses
2615system.l2c.demand_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for demand accesses
2616system.l2c.demand_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for demand accesses
2617system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for demand accesses
2618system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for demand accesses
2619system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for demand accesses
2620system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for demand accesses
2621system.l2c.demand_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for demand accesses
2622system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for demand accesses
2623system.l2c.demand_mshr_miss_rate::total 0.414055 # mshr miss rate for demand accesses
2624system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for overall accesses
2625system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for overall accesses
2626system.l2c.overall_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for overall accesses
2627system.l2c.overall_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for overall accesses
2628system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for overall accesses
2629system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for overall accesses
2630system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for overall accesses
2631system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for overall accesses
2632system.l2c.overall_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for overall accesses
2633system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for overall accesses
2634system.l2c.overall_mshr_miss_rate::total 0.414055 # mshr miss rate for overall accesses
2635system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average ReadReq mshr miss latency
2636system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
2637system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average ReadReq mshr miss latency
2638system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69149.263196 # average ReadReq mshr miss latency
2639system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average ReadReq mshr miss latency
2640system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
2641system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
2642system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average ReadReq mshr miss latency
2643system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72675.713571 # average ReadReq mshr miss latency
2644system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average ReadReq mshr miss latency
2645system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367 # average ReadReq mshr miss latency
2646system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475 # average UpgradeReq mshr miss latency
2647system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009 # average UpgradeReq mshr miss latency
2648system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638 # average UpgradeReq mshr miss latency
2649system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131 # average SCUpgradeReq mshr miss latency
2650system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911 # average SCUpgradeReq mshr miss latency
2651system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618 # average SCUpgradeReq mshr miss latency
2652system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246 # average ReadExReq mshr miss latency
2653system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000 # average ReadExReq mshr miss latency
2654system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064 # average ReadExReq mshr miss latency
2655system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency
2656system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
2657system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency
2658system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency
2659system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency
2660system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
2661system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
2662system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency
2663system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency
2664system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency
2665system.l2c.demand_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency
2666system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency
2667system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
2668system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency
2669system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency
2670system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency
2671system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
2672system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
2673system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency
2674system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency
2675system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency
2676system.l2c.overall_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency
2677system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
2678system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
2679system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2680system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2681system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2682system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
2683system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2684system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2685system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
2686system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
2687system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2688system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2689system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2690system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
2691system.membus.trans_dist::ReadReq 228475 # Transaction distribution
2692system.membus.trans_dist::ReadResp 228474 # Transaction distribution
2693system.membus.trans_dist::WriteReq 31175 # Transaction distribution
2694system.membus.trans_dist::WriteResp 31175 # Transaction distribution
2695system.membus.trans_dist::Writeback 99922 # Transaction distribution
2696system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
2697system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
2698system.membus.trans_dist::UpgradeReq 85905 # Transaction distribution
2699system.membus.trans_dist::SCUpgradeReq 41202 # Transaction distribution
2700system.membus.trans_dist::UpgradeResp 15112 # Transaction distribution
2701system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution
2702system.membus.trans_dist::ReadExReq 28459 # Transaction distribution
2703system.membus.trans_dist::ReadExResp 11563 # Transaction distribution
2704system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes)
2705system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
2706system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14554 # Packet count per connected master and slave (bytes)
2707system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678409 # Packet count per connected master and slave (bytes)
2708system.membus.pkt_count_system.l2c.mem_side::total 800961 # Packet count per connected master and slave (bytes)
2709system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes)
2710system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes)
2711system.membus.pkt_count::total 873677 # Packet count per connected master and slave (bytes)
2712system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes)
2713system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
2714system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29108 # Cumulative packet size per connected master and slave (bytes)
2715system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962472 # Cumulative packet size per connected master and slave (bytes)
2716system.membus.pkt_size_system.l2c.mem_side::total 19154495 # Cumulative packet size per connected master and slave (bytes)
2717system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
2718system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
2719system.membus.pkt_size::total 21473791 # Cumulative packet size per connected master and slave (bytes)
2720system.membus.snoops 129134 # Total snoops (count)
2721system.membus.snoop_fanout::samples 475892 # Request fanout histogram
2722system.membus.snoop_fanout::mean 1 # Request fanout histogram
2723system.membus.snoop_fanout::stdev 0 # Request fanout histogram
2724system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2725system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2726system.membus.snoop_fanout::1 475892 100.00% 100.00% # Request fanout histogram
2727system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
2728system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2729system.membus.snoop_fanout::min_value 1 # Request fanout histogram
2730system.membus.snoop_fanout::max_value 1 # Request fanout histogram
2731system.membus.snoop_fanout::total 475892 # Request fanout histogram
2732system.membus.reqLayer0.occupancy 88166996 # Layer occupancy (ticks)
2733system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
2734system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks)
2735system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
2736system.membus.reqLayer2.occupancy 12082997 # Layer occupancy (ticks)
2737system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
2738system.membus.reqLayer5.occupancy 1515063497 # Layer occupancy (ticks)
2739system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
2740system.membus.respLayer2.occupancy 1971064197 # Layer occupancy (ticks)
2741system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
2742system.membus.respLayer3.occupancy 38584420 # Layer occupancy (ticks)
2743system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
2744system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
2745system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
2746system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
2747system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
2748system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
2749system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
2750system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
2751system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
2752system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
2753system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
2754system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
2755system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
2756system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
2757system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
2758system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
2759system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
2760system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
2761system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
2762system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
2763system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
2764system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
2765system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
2766system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
2767system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
2768system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
2769system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
2770system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
2771system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
2772system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
2773system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
2774system.realview.ethernet.droppedPackets 0 # number of packets dropped
2775system.toL2Bus.trans_dist::ReadReq 633379 # Transaction distribution
2776system.toL2Bus.trans_dist::ReadResp 633359 # Transaction distribution
2777system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution
2778system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution
2779system.toL2Bus.trans_dist::Writeback 240423 # Transaction distribution
2780system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
2781system.toL2Bus.trans_dist::UpgradeReq 96357 # Transaction distribution
2782system.toL2Bus.trans_dist::SCUpgradeReq 41586 # Transaction distribution
2783system.toL2Bus.trans_dist::UpgradeResp 137943 # Transaction distribution
2784system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
2785system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
2786system.toL2Bus.trans_dist::ReadExReq 39964 # Transaction distribution
2787system.toL2Bus.trans_dist::ReadExResp 39964 # Transaction distribution
2788system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256968 # Packet count per connected master and slave (bytes)
2789system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399943 # Packet count per connected master and slave (bytes)
2790system.toL2Bus.pkt_count::total 1656911 # Packet count per connected master and slave (bytes)
2791system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37604672 # Cumulative packet size per connected master and slave (bytes)
2792system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8289023 # Cumulative packet size per connected master and slave (bytes)
2793system.toL2Bus.pkt_size::total 45893695 # Cumulative packet size per connected master and slave (bytes)
2794system.toL2Bus.snoops 305031 # Total snoops (count)
2795system.toL2Bus.snoop_fanout::samples 1043713 # Request fanout histogram
2796system.toL2Bus.snoop_fanout::mean 1.034956 # Request fanout histogram
2797system.toL2Bus.snoop_fanout::stdev 0.183668 # Request fanout histogram
2798system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2799system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2800system.toL2Bus.snoop_fanout::1 1007229 96.50% 96.50% # Request fanout histogram
2801system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram
2802system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2803system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2804system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2805system.toL2Bus.snoop_fanout::total 1043713 # Request fanout histogram
2806system.toL2Bus.reqLayer0.occupancy 1520313197 # Layer occupancy (ticks)
2807system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2808system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks)
2809system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2810system.toL2Bus.respLayer0.occupancy 2134327544 # Layer occupancy (ticks)
2811system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
2812system.toL2Bus.respLayer1.occupancy 850356790 # Layer occupancy (ticks)
2813system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2814
2815---------- End Simulation Statistics ----------