40a41
> mmap_using_noreserve=false
175a177
> sys=system
193d194
< port=system.cpu0.toL2Bus.slave[5]
286a288
> sys=system
304d305
< port=system.cpu0.toL2Bus.slave[4]
388c389,391
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
389a393
> snoop_response_latency=1
394c398
< slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
475a480
> sys=system
493d497
< port=system.cpu1.toL2Bus.slave[5]
586a591
> sys=system
604d608
< port=system.cpu1.toL2Bus.slave[4]
688c692,694
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
689a696
> snoop_response_latency=1
694c701
< slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
725c732,734
< header_cycles=1
---
> forward_latency=1
> frontend_latency=2
> response_latency=2
727c736
< width=8
---
> width=16
809c818,820
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
810a822
> snoop_response_latency=4
813c825
< width=8
---
> width=16
863c875
< addr_mapping=RoRaBaChCo
---
> addr_mapping=RoRaBaCoCh
1574c1586,1588
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
1575a1590
> snoop_response_latency=1
1578c1593
< width=8
---
> width=32