1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=LinuxArmSystem
13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
14atags_addr=134217728
15boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17cache_line_size=64
18clk_domain=system.clk_domain
19default_p_state=UNDEFINED
20dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
21early_kernel_symbols=false
22enable_context_switch_stats_dump=false
23eventq_index=0
24exit_on_work_items=false
25flags_addr=469827632
26gic_cpu_addr=738205696
27have_large_asid_64=false
28have_lpae=true
29have_security=false
30have_virtualization=false
31highest_el_is_64=false
32init_param=0
33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM
38mem_mode=timing
39mem_ranges=2147483648:2415919103:0:0:0:0
40memories=system.physmem system.realview.nvmem system.realview.vram
41mmap_using_noreserve=false
42multi_proc=true
43multi_thread=false
44num_work_ids=16
45p_state_clk_gate_bins=20
46p_state_clk_gate_max=1000000000000
47p_state_clk_gate_min=1000
48panic_on_oops=true
49panic_on_panic=true
50phys_addr_range_64=40
51power_model=Null
52readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
53reset_addr_64=0
54symbolfile=
55thermal_components=
56thermal_model=Null
57work_begin_ckpt_count=0
58work_begin_cpu_id_exit=-1
59work_begin_exit_count=0
60work_cpus_ckpt_count=0
--- 33 unchanged lines hidden (view full) ---
94eventq_index=0
95image_file=
96read_only=false
97table_size=65536
98
99[system.cf0.image.child]
100type=RawDiskImage
101eventq_index=0
102image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
103read_only=true
104
105[system.clk_domain]
106type=SrcClockDomain
107clock=1000
108domain_id=-1
109eventq_index=0
110init_perf_level=0
--- 41 unchanged lines hidden (view full) ---
152
153[system.cpu0.dcache]
154type=Cache
155children=tags
156addr_ranges=0:18446744073709551615:0:0:0:0
157assoc=2
158clk_domain=system.cpu_clk_domain
159clusivity=mostly_incl
160default_p_state=UNDEFINED
161demand_mshr_reserve=1
162eventq_index=0
163hit_latency=2
164is_read_only=false
165max_miss_count=0
166mshrs=6
167p_state_clk_gate_bins=20
168p_state_clk_gate_max=1000000000000
169p_state_clk_gate_min=1000
170power_model=Null
171prefetch_on_access=false
172prefetcher=Null
173response_latency=2
174sequential_access=false
175size=32768
176system=system
177tags=system.cpu0.dcache.tags
178tgts_per_mshr=8
179write_buffers=16
180writeback_clean=true
181cpu_side=system.cpu0.dcache_port
182mem_side=system.cpu0.toL2Bus.slave[1]
183
184[system.cpu0.dcache.tags]
185type=LRU
186assoc=2
187block_size=64
188clk_domain=system.cpu_clk_domain
189default_p_state=UNDEFINED
190eventq_index=0
191hit_latency=2
192p_state_clk_gate_bins=20
193p_state_clk_gate_max=1000000000000
194p_state_clk_gate_min=1000
195power_model=Null
196sequential_access=false
197size=32768
198
199[system.cpu0.dstage2_mmu]
200type=ArmStage2MMU
201children=stage2_tlb
202eventq_index=0
203stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
204sys=system
205tlb=system.cpu0.dtb
--- 43 unchanged lines hidden (view full) ---
249
250[system.cpu0.icache]
251type=Cache
252children=tags
253addr_ranges=0:18446744073709551615:0:0:0:0
254assoc=2
255clk_domain=system.cpu_clk_domain
256clusivity=mostly_incl
257default_p_state=UNDEFINED
258demand_mshr_reserve=1
259eventq_index=0
260hit_latency=1
261is_read_only=true
262max_miss_count=0
263mshrs=2
264p_state_clk_gate_bins=20
265p_state_clk_gate_max=1000000000000
266p_state_clk_gate_min=1000
267power_model=Null
268prefetch_on_access=false
269prefetcher=Null
270response_latency=1
271sequential_access=false
272size=32768
273system=system
274tags=system.cpu0.icache.tags
275tgts_per_mshr=8
276write_buffers=8
277writeback_clean=true
278cpu_side=system.cpu0.icache_port
279mem_side=system.cpu0.toL2Bus.slave[0]
280
281[system.cpu0.icache.tags]
282type=LRU
283assoc=2
284block_size=64
285clk_domain=system.cpu_clk_domain
286default_p_state=UNDEFINED
287eventq_index=0
288hit_latency=1
289p_state_clk_gate_bins=20
290p_state_clk_gate_max=1000000000000
291p_state_clk_gate_min=1000
292power_model=Null
293sequential_access=false
294size=32768
295
296[system.cpu0.interrupts]
297type=ArmInterrupts
298eventq_index=0
299
300[system.cpu0.isa]
301type=ArmISA
302decoderFlavour=Generic
--- 78 unchanged lines hidden (view full) ---
381
382[system.cpu0.l2cache]
383type=Cache
384children=prefetcher tags
385addr_ranges=0:18446744073709551615:0:0:0:0
386assoc=16
387clk_domain=system.cpu_clk_domain
388clusivity=mostly_excl
389default_p_state=UNDEFINED
390demand_mshr_reserve=1
391eventq_index=0
392hit_latency=12
393is_read_only=false
394max_miss_count=0
395mshrs=16
396p_state_clk_gate_bins=20
397p_state_clk_gate_max=1000000000000
398p_state_clk_gate_min=1000
399power_model=Null
400prefetch_on_access=true
401prefetcher=system.cpu0.l2cache.prefetcher
402response_latency=12
403sequential_access=false
404size=1048576
405system=system
406tags=system.cpu0.l2cache.tags
407tgts_per_mshr=8
408write_buffers=8
409writeback_clean=false
410cpu_side=system.cpu0.toL2Bus.master[0]
411mem_side=system.toL2Bus.slave[0]
412
413[system.cpu0.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
440thresh_conf=4
441use_master_id=true
442
443[system.cpu0.l2cache.tags]
444type=RandomRepl
445assoc=16
446block_size=64
447clk_domain=system.cpu_clk_domain
448default_p_state=UNDEFINED
449eventq_index=0
450hit_latency=12
451p_state_clk_gate_bins=20
452p_state_clk_gate_max=1000000000000
453p_state_clk_gate_min=1000
454power_model=Null
455sequential_access=false
456size=1048576
457
458[system.cpu0.toL2Bus]
459type=CoherentXBar
460children=snoop_filter
461clk_domain=system.cpu_clk_domain
462default_p_state=UNDEFINED
463eventq_index=0
464forward_latency=0
--- 65 unchanged lines hidden (view full) ---
530
531[system.cpu1.dcache]
532type=Cache
533children=tags
534addr_ranges=0:18446744073709551615:0:0:0:0
535assoc=2
536clk_domain=system.cpu_clk_domain
537clusivity=mostly_incl
538default_p_state=UNDEFINED
539demand_mshr_reserve=1
540eventq_index=0
541hit_latency=2
542is_read_only=false
543max_miss_count=0
544mshrs=6
545p_state_clk_gate_bins=20
546p_state_clk_gate_max=1000000000000
547p_state_clk_gate_min=1000
548power_model=Null
549prefetch_on_access=false
550prefetcher=Null
551response_latency=2
552sequential_access=false
553size=32768
554system=system
555tags=system.cpu1.dcache.tags
556tgts_per_mshr=8
557write_buffers=16
558writeback_clean=true
559cpu_side=system.cpu1.dcache_port
560mem_side=system.cpu1.toL2Bus.slave[1]
561
562[system.cpu1.dcache.tags]
563type=LRU
564assoc=2
565block_size=64
566clk_domain=system.cpu_clk_domain
567default_p_state=UNDEFINED
568eventq_index=0
569hit_latency=2
570p_state_clk_gate_bins=20
571p_state_clk_gate_max=1000000000000
572p_state_clk_gate_min=1000
573power_model=Null
574sequential_access=false
575size=32768
576
577[system.cpu1.dstage2_mmu]
578type=ArmStage2MMU
579children=stage2_tlb
580eventq_index=0
581stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
582sys=system
583tlb=system.cpu1.dtb
--- 43 unchanged lines hidden (view full) ---
627
628[system.cpu1.icache]
629type=Cache
630children=tags
631addr_ranges=0:18446744073709551615:0:0:0:0
632assoc=2
633clk_domain=system.cpu_clk_domain
634clusivity=mostly_incl
635default_p_state=UNDEFINED
636demand_mshr_reserve=1
637eventq_index=0
638hit_latency=1
639is_read_only=true
640max_miss_count=0
641mshrs=2
642p_state_clk_gate_bins=20
643p_state_clk_gate_max=1000000000000
644p_state_clk_gate_min=1000
645power_model=Null
646prefetch_on_access=false
647prefetcher=Null
648response_latency=1
649sequential_access=false
650size=32768
651system=system
652tags=system.cpu1.icache.tags
653tgts_per_mshr=8
654write_buffers=8
655writeback_clean=true
656cpu_side=system.cpu1.icache_port
657mem_side=system.cpu1.toL2Bus.slave[0]
658
659[system.cpu1.icache.tags]
660type=LRU
661assoc=2
662block_size=64
663clk_domain=system.cpu_clk_domain
664default_p_state=UNDEFINED
665eventq_index=0
666hit_latency=1
667p_state_clk_gate_bins=20
668p_state_clk_gate_max=1000000000000
669p_state_clk_gate_min=1000
670power_model=Null
671sequential_access=false
672size=32768
673
674[system.cpu1.interrupts]
675type=ArmInterrupts
676eventq_index=0
677
678[system.cpu1.isa]
679type=ArmISA
680decoderFlavour=Generic
--- 78 unchanged lines hidden (view full) ---
759
760[system.cpu1.l2cache]
761type=Cache
762children=prefetcher tags
763addr_ranges=0:18446744073709551615:0:0:0:0
764assoc=16
765clk_domain=system.cpu_clk_domain
766clusivity=mostly_excl
767default_p_state=UNDEFINED
768demand_mshr_reserve=1
769eventq_index=0
770hit_latency=12
771is_read_only=false
772max_miss_count=0
773mshrs=16
774p_state_clk_gate_bins=20
775p_state_clk_gate_max=1000000000000
776p_state_clk_gate_min=1000
777power_model=Null
778prefetch_on_access=true
779prefetcher=system.cpu1.l2cache.prefetcher
780response_latency=12
781sequential_access=false
782size=1048576
783system=system
784tags=system.cpu1.l2cache.tags
785tgts_per_mshr=8
786write_buffers=8
787writeback_clean=false
788cpu_side=system.cpu1.toL2Bus.master[0]
789mem_side=system.toL2Bus.slave[1]
790
791[system.cpu1.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
818thresh_conf=4
819use_master_id=true
820
821[system.cpu1.l2cache.tags]
822type=RandomRepl
823assoc=16
824block_size=64
825clk_domain=system.cpu_clk_domain
826default_p_state=UNDEFINED
827eventq_index=0
828hit_latency=12
829p_state_clk_gate_bins=20
830p_state_clk_gate_max=1000000000000
831p_state_clk_gate_min=1000
832power_model=Null
833sequential_access=false
834size=1048576
835
836[system.cpu1.toL2Bus]
837type=CoherentXBar
838children=snoop_filter
839clk_domain=system.cpu_clk_domain
840default_p_state=UNDEFINED
841eventq_index=0
842forward_latency=0
--- 63 unchanged lines hidden (view full) ---
906
907[system.iocache]
908type=Cache
909children=tags
910addr_ranges=2147483648:2415919103:0:0:0:0
911assoc=8
912clk_domain=system.clk_domain
913clusivity=mostly_incl
914default_p_state=UNDEFINED
915demand_mshr_reserve=1
916eventq_index=0
917hit_latency=50
918is_read_only=false
919max_miss_count=0
920mshrs=20
921p_state_clk_gate_bins=20
922p_state_clk_gate_max=1000000000000
923p_state_clk_gate_min=1000
924power_model=Null
925prefetch_on_access=false
926prefetcher=Null
927response_latency=50
928sequential_access=false
929size=1024
930system=system
931tags=system.iocache.tags
932tgts_per_mshr=12
933write_buffers=8
934writeback_clean=false
935cpu_side=system.iobus.master[25]
936mem_side=system.membus.slave[3]
937
938[system.iocache.tags]
939type=LRU
940assoc=8
941block_size=64
942clk_domain=system.clk_domain
943default_p_state=UNDEFINED
944eventq_index=0
945hit_latency=50
946p_state_clk_gate_bins=20
947p_state_clk_gate_max=1000000000000
948p_state_clk_gate_min=1000
949power_model=Null
950sequential_access=false
951size=1024
952
953[system.l2c]
954type=Cache
955children=tags
956addr_ranges=0:18446744073709551615:0:0:0:0
957assoc=8
958clk_domain=system.cpu_clk_domain
959clusivity=mostly_incl
960default_p_state=UNDEFINED
961demand_mshr_reserve=1
962eventq_index=0
963hit_latency=20
964is_read_only=false
965max_miss_count=0
966mshrs=20
967p_state_clk_gate_bins=20
968p_state_clk_gate_max=1000000000000
969p_state_clk_gate_min=1000
970power_model=Null
971prefetch_on_access=false
972prefetcher=Null
973response_latency=20
974sequential_access=false
975size=4194304
976system=system
977tags=system.l2c.tags
978tgts_per_mshr=12
979write_buffers=8
980writeback_clean=false
981cpu_side=system.toL2Bus.master[0]
982mem_side=system.membus.slave[2]
983
984[system.l2c.tags]
985type=LRU
986assoc=8
987block_size=64
988clk_domain=system.cpu_clk_domain
989default_p_state=UNDEFINED
990eventq_index=0
991hit_latency=20
992p_state_clk_gate_bins=20
993p_state_clk_gate_max=1000000000000
994p_state_clk_gate_min=1000
995power_model=Null
996sequential_access=false
997size=4194304
998
999[system.membus]
1000type=CoherentXBar
1001children=badaddr_responder snoop_filter
1002clk_domain=system.clk_domain
1003default_p_state=UNDEFINED
1004eventq_index=0
1005forward_latency=4
--- 1107 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=LinuxArmSystem
13children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
14atags_addr=134217728
15boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm
16boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
17cache_line_size=64
18clk_domain=system.clk_domain
19default_p_state=UNDEFINED
20dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
21early_kernel_symbols=false
22enable_context_switch_stats_dump=false
23eventq_index=0
24exit_on_work_items=false
25flags_addr=469827632
26gic_cpu_addr=738205696
27have_large_asid_64=false
28have_lpae=true
29have_security=false
30have_virtualization=false
31highest_el_is_64=false
32init_param=0
33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM
38mem_mode=timing
39mem_ranges=2147483648:2415919103:0:0:0:0
40memories=system.physmem system.realview.nvmem system.realview.vram
41mmap_using_noreserve=false
42multi_proc=true
43multi_thread=false
44num_work_ids=16
45p_state_clk_gate_bins=20
46p_state_clk_gate_max=1000000000000
47p_state_clk_gate_min=1000
48panic_on_oops=true
49panic_on_panic=true
50phys_addr_range_64=40
51power_model=Null
52readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
53reset_addr_64=0
54symbolfile=
55thermal_components=
56thermal_model=Null
57work_begin_ckpt_count=0
58work_begin_cpu_id_exit=-1
59work_begin_exit_count=0
60work_cpus_ckpt_count=0
--- 33 unchanged lines hidden (view full) ---
94eventq_index=0
95image_file=
96read_only=false
97table_size=65536
98
99[system.cf0.image.child]
100type=RawDiskImage
101eventq_index=0
102image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img
103read_only=true
104
105[system.clk_domain]
106type=SrcClockDomain
107clock=1000
108domain_id=-1
109eventq_index=0
110init_perf_level=0
--- 41 unchanged lines hidden (view full) ---
152
153[system.cpu0.dcache]
154type=Cache
155children=tags
156addr_ranges=0:18446744073709551615:0:0:0:0
157assoc=2
158clk_domain=system.cpu_clk_domain
159clusivity=mostly_incl
160default_p_state=UNDEFINED
161demand_mshr_reserve=1
162eventq_index=0
163hit_latency=2
164is_read_only=false
165max_miss_count=0
166mshrs=6
167p_state_clk_gate_bins=20
168p_state_clk_gate_max=1000000000000
169p_state_clk_gate_min=1000
170power_model=Null
171prefetch_on_access=false
172prefetcher=Null
173response_latency=2
174sequential_access=false
175size=32768
176system=system
177tags=system.cpu0.dcache.tags
178tgts_per_mshr=8
179write_buffers=16
180writeback_clean=true
181cpu_side=system.cpu0.dcache_port
182mem_side=system.cpu0.toL2Bus.slave[1]
183
184[system.cpu0.dcache.tags]
185type=LRU
186assoc=2
187block_size=64
188clk_domain=system.cpu_clk_domain
189default_p_state=UNDEFINED
190eventq_index=0
191hit_latency=2
192p_state_clk_gate_bins=20
193p_state_clk_gate_max=1000000000000
194p_state_clk_gate_min=1000
195power_model=Null
196sequential_access=false
197size=32768
198
199[system.cpu0.dstage2_mmu]
200type=ArmStage2MMU
201children=stage2_tlb
202eventq_index=0
203stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
204sys=system
205tlb=system.cpu0.dtb
--- 43 unchanged lines hidden (view full) ---
249
250[system.cpu0.icache]
251type=Cache
252children=tags
253addr_ranges=0:18446744073709551615:0:0:0:0
254assoc=2
255clk_domain=system.cpu_clk_domain
256clusivity=mostly_incl
257default_p_state=UNDEFINED
258demand_mshr_reserve=1
259eventq_index=0
260hit_latency=1
261is_read_only=true
262max_miss_count=0
263mshrs=2
264p_state_clk_gate_bins=20
265p_state_clk_gate_max=1000000000000
266p_state_clk_gate_min=1000
267power_model=Null
268prefetch_on_access=false
269prefetcher=Null
270response_latency=1
271sequential_access=false
272size=32768
273system=system
274tags=system.cpu0.icache.tags
275tgts_per_mshr=8
276write_buffers=8
277writeback_clean=true
278cpu_side=system.cpu0.icache_port
279mem_side=system.cpu0.toL2Bus.slave[0]
280
281[system.cpu0.icache.tags]
282type=LRU
283assoc=2
284block_size=64
285clk_domain=system.cpu_clk_domain
286default_p_state=UNDEFINED
287eventq_index=0
288hit_latency=1
289p_state_clk_gate_bins=20
290p_state_clk_gate_max=1000000000000
291p_state_clk_gate_min=1000
292power_model=Null
293sequential_access=false
294size=32768
295
296[system.cpu0.interrupts]
297type=ArmInterrupts
298eventq_index=0
299
300[system.cpu0.isa]
301type=ArmISA
302decoderFlavour=Generic
--- 78 unchanged lines hidden (view full) ---
381
382[system.cpu0.l2cache]
383type=Cache
384children=prefetcher tags
385addr_ranges=0:18446744073709551615:0:0:0:0
386assoc=16
387clk_domain=system.cpu_clk_domain
388clusivity=mostly_excl
389default_p_state=UNDEFINED
390demand_mshr_reserve=1
391eventq_index=0
392hit_latency=12
393is_read_only=false
394max_miss_count=0
395mshrs=16
396p_state_clk_gate_bins=20
397p_state_clk_gate_max=1000000000000
398p_state_clk_gate_min=1000
399power_model=Null
400prefetch_on_access=true
401prefetcher=system.cpu0.l2cache.prefetcher
402response_latency=12
403sequential_access=false
404size=1048576
405system=system
406tags=system.cpu0.l2cache.tags
407tgts_per_mshr=8
408write_buffers=8
409writeback_clean=false
410cpu_side=system.cpu0.toL2Bus.master[0]
411mem_side=system.toL2Bus.slave[0]
412
413[system.cpu0.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
440thresh_conf=4
441use_master_id=true
442
443[system.cpu0.l2cache.tags]
444type=RandomRepl
445assoc=16
446block_size=64
447clk_domain=system.cpu_clk_domain
448default_p_state=UNDEFINED
449eventq_index=0
450hit_latency=12
451p_state_clk_gate_bins=20
452p_state_clk_gate_max=1000000000000
453p_state_clk_gate_min=1000
454power_model=Null
455sequential_access=false
456size=1048576
457
458[system.cpu0.toL2Bus]
459type=CoherentXBar
460children=snoop_filter
461clk_domain=system.cpu_clk_domain
462default_p_state=UNDEFINED
463eventq_index=0
464forward_latency=0
--- 65 unchanged lines hidden (view full) ---
530
531[system.cpu1.dcache]
532type=Cache
533children=tags
534addr_ranges=0:18446744073709551615:0:0:0:0
535assoc=2
536clk_domain=system.cpu_clk_domain
537clusivity=mostly_incl
538default_p_state=UNDEFINED
539demand_mshr_reserve=1
540eventq_index=0
541hit_latency=2
542is_read_only=false
543max_miss_count=0
544mshrs=6
545p_state_clk_gate_bins=20
546p_state_clk_gate_max=1000000000000
547p_state_clk_gate_min=1000
548power_model=Null
549prefetch_on_access=false
550prefetcher=Null
551response_latency=2
552sequential_access=false
553size=32768
554system=system
555tags=system.cpu1.dcache.tags
556tgts_per_mshr=8
557write_buffers=16
558writeback_clean=true
559cpu_side=system.cpu1.dcache_port
560mem_side=system.cpu1.toL2Bus.slave[1]
561
562[system.cpu1.dcache.tags]
563type=LRU
564assoc=2
565block_size=64
566clk_domain=system.cpu_clk_domain
567default_p_state=UNDEFINED
568eventq_index=0
569hit_latency=2
570p_state_clk_gate_bins=20
571p_state_clk_gate_max=1000000000000
572p_state_clk_gate_min=1000
573power_model=Null
574sequential_access=false
575size=32768
576
577[system.cpu1.dstage2_mmu]
578type=ArmStage2MMU
579children=stage2_tlb
580eventq_index=0
581stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
582sys=system
583tlb=system.cpu1.dtb
--- 43 unchanged lines hidden (view full) ---
627
628[system.cpu1.icache]
629type=Cache
630children=tags
631addr_ranges=0:18446744073709551615:0:0:0:0
632assoc=2
633clk_domain=system.cpu_clk_domain
634clusivity=mostly_incl
635default_p_state=UNDEFINED
636demand_mshr_reserve=1
637eventq_index=0
638hit_latency=1
639is_read_only=true
640max_miss_count=0
641mshrs=2
642p_state_clk_gate_bins=20
643p_state_clk_gate_max=1000000000000
644p_state_clk_gate_min=1000
645power_model=Null
646prefetch_on_access=false
647prefetcher=Null
648response_latency=1
649sequential_access=false
650size=32768
651system=system
652tags=system.cpu1.icache.tags
653tgts_per_mshr=8
654write_buffers=8
655writeback_clean=true
656cpu_side=system.cpu1.icache_port
657mem_side=system.cpu1.toL2Bus.slave[0]
658
659[system.cpu1.icache.tags]
660type=LRU
661assoc=2
662block_size=64
663clk_domain=system.cpu_clk_domain
664default_p_state=UNDEFINED
665eventq_index=0
666hit_latency=1
667p_state_clk_gate_bins=20
668p_state_clk_gate_max=1000000000000
669p_state_clk_gate_min=1000
670power_model=Null
671sequential_access=false
672size=32768
673
674[system.cpu1.interrupts]
675type=ArmInterrupts
676eventq_index=0
677
678[system.cpu1.isa]
679type=ArmISA
680decoderFlavour=Generic
--- 78 unchanged lines hidden (view full) ---
759
760[system.cpu1.l2cache]
761type=Cache
762children=prefetcher tags
763addr_ranges=0:18446744073709551615:0:0:0:0
764assoc=16
765clk_domain=system.cpu_clk_domain
766clusivity=mostly_excl
767default_p_state=UNDEFINED
768demand_mshr_reserve=1
769eventq_index=0
770hit_latency=12
771is_read_only=false
772max_miss_count=0
773mshrs=16
774p_state_clk_gate_bins=20
775p_state_clk_gate_max=1000000000000
776p_state_clk_gate_min=1000
777power_model=Null
778prefetch_on_access=true
779prefetcher=system.cpu1.l2cache.prefetcher
780response_latency=12
781sequential_access=false
782size=1048576
783system=system
784tags=system.cpu1.l2cache.tags
785tgts_per_mshr=8
786write_buffers=8
787writeback_clean=false
788cpu_side=system.cpu1.toL2Bus.master[0]
789mem_side=system.toL2Bus.slave[1]
790
791[system.cpu1.l2cache.prefetcher]
--- 26 unchanged lines hidden (view full) ---
818thresh_conf=4
819use_master_id=true
820
821[system.cpu1.l2cache.tags]
822type=RandomRepl
823assoc=16
824block_size=64
825clk_domain=system.cpu_clk_domain
826default_p_state=UNDEFINED
827eventq_index=0
828hit_latency=12
829p_state_clk_gate_bins=20
830p_state_clk_gate_max=1000000000000
831p_state_clk_gate_min=1000
832power_model=Null
833sequential_access=false
834size=1048576
835
836[system.cpu1.toL2Bus]
837type=CoherentXBar
838children=snoop_filter
839clk_domain=system.cpu_clk_domain
840default_p_state=UNDEFINED
841eventq_index=0
842forward_latency=0
--- 63 unchanged lines hidden (view full) ---
906
907[system.iocache]
908type=Cache
909children=tags
910addr_ranges=2147483648:2415919103:0:0:0:0
911assoc=8
912clk_domain=system.clk_domain
913clusivity=mostly_incl
914default_p_state=UNDEFINED
915demand_mshr_reserve=1
916eventq_index=0
917hit_latency=50
918is_read_only=false
919max_miss_count=0
920mshrs=20
921p_state_clk_gate_bins=20
922p_state_clk_gate_max=1000000000000
923p_state_clk_gate_min=1000
924power_model=Null
925prefetch_on_access=false
926prefetcher=Null
927response_latency=50
928sequential_access=false
929size=1024
930system=system
931tags=system.iocache.tags
932tgts_per_mshr=12
933write_buffers=8
934writeback_clean=false
935cpu_side=system.iobus.master[25]
936mem_side=system.membus.slave[3]
937
938[system.iocache.tags]
939type=LRU
940assoc=8
941block_size=64
942clk_domain=system.clk_domain
943default_p_state=UNDEFINED
944eventq_index=0
945hit_latency=50
946p_state_clk_gate_bins=20
947p_state_clk_gate_max=1000000000000
948p_state_clk_gate_min=1000
949power_model=Null
950sequential_access=false
951size=1024
952
953[system.l2c]
954type=Cache
955children=tags
956addr_ranges=0:18446744073709551615:0:0:0:0
957assoc=8
958clk_domain=system.cpu_clk_domain
959clusivity=mostly_incl
960default_p_state=UNDEFINED
961demand_mshr_reserve=1
962eventq_index=0
963hit_latency=20
964is_read_only=false
965max_miss_count=0
966mshrs=20
967p_state_clk_gate_bins=20
968p_state_clk_gate_max=1000000000000
969p_state_clk_gate_min=1000
970power_model=Null
971prefetch_on_access=false
972prefetcher=Null
973response_latency=20
974sequential_access=false
975size=4194304
976system=system
977tags=system.l2c.tags
978tgts_per_mshr=12
979write_buffers=8
980writeback_clean=false
981cpu_side=system.toL2Bus.master[0]
982mem_side=system.membus.slave[2]
983
984[system.l2c.tags]
985type=LRU
986assoc=8
987block_size=64
988clk_domain=system.cpu_clk_domain
989default_p_state=UNDEFINED
990eventq_index=0
991hit_latency=20
992p_state_clk_gate_bins=20
993p_state_clk_gate_max=1000000000000
994p_state_clk_gate_min=1000
995power_model=Null
996sequential_access=false
997size=4194304
998
999[system.membus]
1000type=CoherentXBar
1001children=badaddr_responder snoop_filter
1002clk_domain=system.clk_domain
1003default_p_state=UNDEFINED
1004eventq_index=0
1005forward_latency=4
--- 1107 unchanged lines hidden ---