1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 24 unchanged lines hidden (view full) ---
33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM
38mem_mode=timing
39mem_ranges=2147483648:2415919103
40memories=system.physmem system.realview.nvmem system.realview.vram
41mmap_using_noreserve=false
42multi_proc=true
43num_work_ids=16
44panic_on_oops=true
45panic_on_panic=true
46phys_addr_range_64=40
47readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
48reset_addr_64=0
49symbolfile=
--- 119 unchanged lines hidden (view full) ---
169sequential_access=false
170size=32768
171
172[system.cpu0.dstage2_mmu]
173type=ArmStage2MMU
174children=stage2_tlb
175eventq_index=0
176stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
177sys=system
178tlb=system.cpu0.dtb
179
180[system.cpu0.dstage2_mmu.stage2_tlb]
181type=ArmTLB
182children=walker
183eventq_index=0
184is_stage2=true
185size=32
186walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
187
188[system.cpu0.dstage2_mmu.stage2_tlb.walker]
189type=ArmTableWalker
190clk_domain=system.cpu_clk_domain
191eventq_index=0
192is_stage2=true
193num_squash_per_cycle=2
194sys=system
195
196[system.cpu0.dtb]
197type=ArmTLB
198children=walker
199eventq_index=0
200is_stage2=false
201size=64
202walker=system.cpu0.dtb.walker
--- 77 unchanged lines hidden (view full) ---
280pmu=Null
281system=system
282
283[system.cpu0.istage2_mmu]
284type=ArmStage2MMU
285children=stage2_tlb
286eventq_index=0
287stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
288sys=system
289tlb=system.cpu0.itb
290
291[system.cpu0.istage2_mmu.stage2_tlb]
292type=ArmTLB
293children=walker
294eventq_index=0
295is_stage2=true
296size=32
297walker=system.cpu0.istage2_mmu.stage2_tlb.walker
298
299[system.cpu0.istage2_mmu.stage2_tlb.walker]
300type=ArmTableWalker
301clk_domain=system.cpu_clk_domain
302eventq_index=0
303is_stage2=true
304num_squash_per_cycle=2
305sys=system
306
307[system.cpu0.itb]
308type=ArmTLB
309children=walker
310eventq_index=0
311is_stage2=false
312size=64
313walker=system.cpu0.itb.walker
--- 67 unchanged lines hidden (view full) ---
381hit_latency=12
382sequential_access=false
383size=1048576
384
385[system.cpu0.toL2Bus]
386type=CoherentXBar
387clk_domain=system.cpu_clk_domain
388eventq_index=0
389forward_latency=0
390frontend_latency=1
391response_latency=1
392snoop_filter=Null
393snoop_response_latency=1
394system=system
395use_default_range=false
396width=32
397master=system.cpu0.l2cache.cpu_side
398slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
399
400[system.cpu0.tracer]
401type=ExeTracer
402eventq_index=0
403
404[system.cpu1]
405type=TimingSimpleCPU
406children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
--- 65 unchanged lines hidden (view full) ---
472sequential_access=false
473size=32768
474
475[system.cpu1.dstage2_mmu]
476type=ArmStage2MMU
477children=stage2_tlb
478eventq_index=0
479stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
480sys=system
481tlb=system.cpu1.dtb
482
483[system.cpu1.dstage2_mmu.stage2_tlb]
484type=ArmTLB
485children=walker
486eventq_index=0
487is_stage2=true
488size=32
489walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
490
491[system.cpu1.dstage2_mmu.stage2_tlb.walker]
492type=ArmTableWalker
493clk_domain=system.cpu_clk_domain
494eventq_index=0
495is_stage2=true
496num_squash_per_cycle=2
497sys=system
498
499[system.cpu1.dtb]
500type=ArmTLB
501children=walker
502eventq_index=0
503is_stage2=false
504size=64
505walker=system.cpu1.dtb.walker
--- 77 unchanged lines hidden (view full) ---
583pmu=Null
584system=system
585
586[system.cpu1.istage2_mmu]
587type=ArmStage2MMU
588children=stage2_tlb
589eventq_index=0
590stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
591sys=system
592tlb=system.cpu1.itb
593
594[system.cpu1.istage2_mmu.stage2_tlb]
595type=ArmTLB
596children=walker
597eventq_index=0
598is_stage2=true
599size=32
600walker=system.cpu1.istage2_mmu.stage2_tlb.walker
601
602[system.cpu1.istage2_mmu.stage2_tlb.walker]
603type=ArmTableWalker
604clk_domain=system.cpu_clk_domain
605eventq_index=0
606is_stage2=true
607num_squash_per_cycle=2
608sys=system
609
610[system.cpu1.itb]
611type=ArmTLB
612children=walker
613eventq_index=0
614is_stage2=false
615size=64
616walker=system.cpu1.itb.walker
--- 67 unchanged lines hidden (view full) ---
684hit_latency=12
685sequential_access=false
686size=1048576
687
688[system.cpu1.toL2Bus]
689type=CoherentXBar
690clk_domain=system.cpu_clk_domain
691eventq_index=0
692forward_latency=0
693frontend_latency=1
694response_latency=1
695snoop_filter=Null
696snoop_response_latency=1
697system=system
698use_default_range=false
699width=32
700master=system.cpu1.l2cache.cpu_side
701slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
702
703[system.cpu1.tracer]
704type=ExeTracer
705eventq_index=0
706
707[system.cpu_clk_domain]
708type=SrcClockDomain
709clock=500
--- 14 unchanged lines hidden (view full) ---
724type=IntrControl
725eventq_index=0
726sys=system
727
728[system.iobus]
729type=NoncoherentXBar
730clk_domain=system.clk_domain
731eventq_index=0
732forward_latency=1
733frontend_latency=2
734response_latency=2
735use_default_range=true
736width=16
737default=system.realview.pciconfig.pio
738master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
739slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
740
741[system.iocache]
742type=BaseCache
743children=tags
744addr_ranges=2147483648:2415919103
--- 65 unchanged lines hidden (view full) ---
810sequential_access=false
811size=4194304
812
813[system.membus]
814type=CoherentXBar
815children=badaddr_responder
816clk_domain=system.clk_domain
817eventq_index=0
818forward_latency=4
819frontend_latency=3
820response_latency=2
821snoop_filter=Null
822snoop_response_latency=4
823system=system
824use_default_range=false
825width=16
826default=system.membus.badaddr_responder.pio
827master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
828slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
829
830[system.membus.badaddr_responder]
831type=IsaFake
832clk_domain=system.clk_domain
833eventq_index=0
--- 33 unchanged lines hidden (view full) ---
867IDD4W2=0.000000
868IDD5=0.220000
869IDD52=0.000000
870IDD6=0.000000
871IDD62=0.000000
872VDD=1.500000
873VDD2=0.000000
874activation_limit=4
875addr_mapping=RoRaBaCoCh
876bank_groups_per_rank=0
877banks_per_rank=8
878burst_length=8
879channels=1
880clk_domain=system.clk_domain
881conf_table_reported=true
882device_bus_width=8
883device_rowbuffer_size=1024
--- 694 unchanged lines hidden (view full) ---
1578number=0
1579output=true
1580port=3456
1581
1582[system.toL2Bus]
1583type=CoherentXBar
1584clk_domain=system.cpu_clk_domain
1585eventq_index=0
1586forward_latency=0
1587frontend_latency=1
1588response_latency=1
1589snoop_filter=Null
1590snoop_response_latency=1
1591system=system
1592use_default_range=false
1593width=32
1594master=system.l2c.cpu_side
1595slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
1596
1597[system.vncserver]
1598type=VncServer
1599eventq_index=0
1600frame_capture=false
1601number=0
1602port=5900
1603
1604[system.voltage_domain]
1605type=VoltageDomain
1606eventq_index=0
1607voltage=1.000000
1608
2type=Root
3children=system
4eventq_index=0
5full_system=true
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 24 unchanged lines hidden (view full) ---
33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
34kernel_addr_check=true
35load_addr_mask=268435455
36load_offset=2147483648
37machine_type=VExpress_EMM
38mem_mode=timing
39mem_ranges=2147483648:2415919103
40memories=system.physmem system.realview.nvmem system.realview.vram
41mmap_using_noreserve=false
42multi_proc=true
43num_work_ids=16
44panic_on_oops=true
45panic_on_panic=true
46phys_addr_range_64=40
47readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
48reset_addr_64=0
49symbolfile=
--- 119 unchanged lines hidden (view full) ---
169sequential_access=false
170size=32768
171
172[system.cpu0.dstage2_mmu]
173type=ArmStage2MMU
174children=stage2_tlb
175eventq_index=0
176stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
177sys=system
178tlb=system.cpu0.dtb
179
180[system.cpu0.dstage2_mmu.stage2_tlb]
181type=ArmTLB
182children=walker
183eventq_index=0
184is_stage2=true
185size=32
186walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
187
188[system.cpu0.dstage2_mmu.stage2_tlb.walker]
189type=ArmTableWalker
190clk_domain=system.cpu_clk_domain
191eventq_index=0
192is_stage2=true
193num_squash_per_cycle=2
194sys=system
195
196[system.cpu0.dtb]
197type=ArmTLB
198children=walker
199eventq_index=0
200is_stage2=false
201size=64
202walker=system.cpu0.dtb.walker
--- 77 unchanged lines hidden (view full) ---
280pmu=Null
281system=system
282
283[system.cpu0.istage2_mmu]
284type=ArmStage2MMU
285children=stage2_tlb
286eventq_index=0
287stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
288sys=system
289tlb=system.cpu0.itb
290
291[system.cpu0.istage2_mmu.stage2_tlb]
292type=ArmTLB
293children=walker
294eventq_index=0
295is_stage2=true
296size=32
297walker=system.cpu0.istage2_mmu.stage2_tlb.walker
298
299[system.cpu0.istage2_mmu.stage2_tlb.walker]
300type=ArmTableWalker
301clk_domain=system.cpu_clk_domain
302eventq_index=0
303is_stage2=true
304num_squash_per_cycle=2
305sys=system
306
307[system.cpu0.itb]
308type=ArmTLB
309children=walker
310eventq_index=0
311is_stage2=false
312size=64
313walker=system.cpu0.itb.walker
--- 67 unchanged lines hidden (view full) ---
381hit_latency=12
382sequential_access=false
383size=1048576
384
385[system.cpu0.toL2Bus]
386type=CoherentXBar
387clk_domain=system.cpu_clk_domain
388eventq_index=0
389forward_latency=0
390frontend_latency=1
391response_latency=1
392snoop_filter=Null
393snoop_response_latency=1
394system=system
395use_default_range=false
396width=32
397master=system.cpu0.l2cache.cpu_side
398slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
399
400[system.cpu0.tracer]
401type=ExeTracer
402eventq_index=0
403
404[system.cpu1]
405type=TimingSimpleCPU
406children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer
--- 65 unchanged lines hidden (view full) ---
472sequential_access=false
473size=32768
474
475[system.cpu1.dstage2_mmu]
476type=ArmStage2MMU
477children=stage2_tlb
478eventq_index=0
479stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
480sys=system
481tlb=system.cpu1.dtb
482
483[system.cpu1.dstage2_mmu.stage2_tlb]
484type=ArmTLB
485children=walker
486eventq_index=0
487is_stage2=true
488size=32
489walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
490
491[system.cpu1.dstage2_mmu.stage2_tlb.walker]
492type=ArmTableWalker
493clk_domain=system.cpu_clk_domain
494eventq_index=0
495is_stage2=true
496num_squash_per_cycle=2
497sys=system
498
499[system.cpu1.dtb]
500type=ArmTLB
501children=walker
502eventq_index=0
503is_stage2=false
504size=64
505walker=system.cpu1.dtb.walker
--- 77 unchanged lines hidden (view full) ---
583pmu=Null
584system=system
585
586[system.cpu1.istage2_mmu]
587type=ArmStage2MMU
588children=stage2_tlb
589eventq_index=0
590stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
591sys=system
592tlb=system.cpu1.itb
593
594[system.cpu1.istage2_mmu.stage2_tlb]
595type=ArmTLB
596children=walker
597eventq_index=0
598is_stage2=true
599size=32
600walker=system.cpu1.istage2_mmu.stage2_tlb.walker
601
602[system.cpu1.istage2_mmu.stage2_tlb.walker]
603type=ArmTableWalker
604clk_domain=system.cpu_clk_domain
605eventq_index=0
606is_stage2=true
607num_squash_per_cycle=2
608sys=system
609
610[system.cpu1.itb]
611type=ArmTLB
612children=walker
613eventq_index=0
614is_stage2=false
615size=64
616walker=system.cpu1.itb.walker
--- 67 unchanged lines hidden (view full) ---
684hit_latency=12
685sequential_access=false
686size=1048576
687
688[system.cpu1.toL2Bus]
689type=CoherentXBar
690clk_domain=system.cpu_clk_domain
691eventq_index=0
692forward_latency=0
693frontend_latency=1
694response_latency=1
695snoop_filter=Null
696snoop_response_latency=1
697system=system
698use_default_range=false
699width=32
700master=system.cpu1.l2cache.cpu_side
701slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
702
703[system.cpu1.tracer]
704type=ExeTracer
705eventq_index=0
706
707[system.cpu_clk_domain]
708type=SrcClockDomain
709clock=500
--- 14 unchanged lines hidden (view full) ---
724type=IntrControl
725eventq_index=0
726sys=system
727
728[system.iobus]
729type=NoncoherentXBar
730clk_domain=system.clk_domain
731eventq_index=0
732forward_latency=1
733frontend_latency=2
734response_latency=2
735use_default_range=true
736width=16
737default=system.realview.pciconfig.pio
738master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
739slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
740
741[system.iocache]
742type=BaseCache
743children=tags
744addr_ranges=2147483648:2415919103
--- 65 unchanged lines hidden (view full) ---
810sequential_access=false
811size=4194304
812
813[system.membus]
814type=CoherentXBar
815children=badaddr_responder
816clk_domain=system.clk_domain
817eventq_index=0
818forward_latency=4
819frontend_latency=3
820response_latency=2
821snoop_filter=Null
822snoop_response_latency=4
823system=system
824use_default_range=false
825width=16
826default=system.membus.badaddr_responder.pio
827master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
828slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
829
830[system.membus.badaddr_responder]
831type=IsaFake
832clk_domain=system.clk_domain
833eventq_index=0
--- 33 unchanged lines hidden (view full) ---
867IDD4W2=0.000000
868IDD5=0.220000
869IDD52=0.000000
870IDD6=0.000000
871IDD62=0.000000
872VDD=1.500000
873VDD2=0.000000
874activation_limit=4
875addr_mapping=RoRaBaCoCh
876bank_groups_per_rank=0
877banks_per_rank=8
878burst_length=8
879channels=1
880clk_domain=system.clk_domain
881conf_table_reported=true
882device_bus_width=8
883device_rowbuffer_size=1024
--- 694 unchanged lines hidden (view full) ---
1578number=0
1579output=true
1580port=3456
1581
1582[system.toL2Bus]
1583type=CoherentXBar
1584clk_domain=system.cpu_clk_domain
1585eventq_index=0
1586forward_latency=0
1587frontend_latency=1
1588response_latency=1
1589snoop_filter=Null
1590snoop_response_latency=1
1591system=system
1592use_default_range=false
1593width=32
1594master=system.l2c.cpu_side
1595slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
1596
1597[system.vncserver]
1598type=VncServer
1599eventq_index=0
1600frame_capture=false
1601number=0
1602port=5900
1603
1604[system.voltage_domain]
1605type=VoltageDomain
1606eventq_index=0
1607voltage=1.000000
1608