| stats.txt (9265:8fe936e937bd) | stats.txt (9283:490958b032d6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332810 # Number of seconds simulated 4sim_ticks 2332810264000 # Number of ticks simulated 5final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1681370 # Simulator instruction rate (inst/s) 8host_op_rate 2162138 # Simulator op (including micro ops) rate (op/s) --- 47 unchanged lines hidden (view full) --- 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332810 # Number of seconds simulated 4sim_ticks 2332810264000 # Number of ticks simulated 5final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1681370 # Simulator instruction rate (inst/s) 8host_op_rate 2162138 # Simulator op (including micro ops) rate (op/s) --- 47 unchanged lines hidden (view full) --- 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) |
| 64system.l2c.replacements 62243 # number of replacements 65system.l2c.tagsinuse 50007.272909 # Cycle average of tags in use 66system.l2c.total_refs 1669922 # Total number of references to valid blocks. 67system.l2c.sampled_refs 127628 # Sample count of references to valid blocks. 68system.l2c.avg_refs 13.084292 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor 72system.l2c.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor 73system.l2c.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor 74system.l2c.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor 75system.l2c.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy 76system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 77system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy 78system.l2c.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy 79system.l2c.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy 80system.l2c.occ_percent::total 0.763050 # Average percentage of cache occupancy 81system.l2c.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits 82system.l2c.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits 83system.l2c.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits 84system.l2c.ReadReq_hits::cpu.data 366771 # number of ReadReq hits 85system.l2c.ReadReq_hits::total 1216278 # number of ReadReq hits 86system.l2c.Writeback_hits::writebacks 592643 # number of Writeback hits 87system.l2c.Writeback_hits::total 592643 # number of Writeback hits 88system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 89system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits 90system.l2c.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits 91system.l2c.ReadExReq_hits::total 113739 # number of ReadExReq hits 92system.l2c.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits 93system.l2c.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits 94system.l2c.demand_hits::cpu.inst 838871 # number of demand (read+write) hits 95system.l2c.demand_hits::cpu.data 480510 # number of demand (read+write) hits 96system.l2c.demand_hits::total 1330017 # number of demand (read+write) hits 97system.l2c.overall_hits::cpu.dtb.walker 7507 # number of overall hits 98system.l2c.overall_hits::cpu.itb.walker 3129 # number of overall hits 99system.l2c.overall_hits::cpu.inst 838871 # number of overall hits 100system.l2c.overall_hits::cpu.data 480510 # number of overall hits 101system.l2c.overall_hits::total 1330017 # number of overall hits 102system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 103system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 104system.l2c.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses 105system.l2c.ReadReq_misses::cpu.data 9871 # number of ReadReq misses 106system.l2c.ReadReq_misses::total 20483 # number of ReadReq misses 107system.l2c.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses 108system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses 109system.l2c.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses 110system.l2c.ReadExReq_misses::total 133468 # number of ReadExReq misses 111system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 112system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 113system.l2c.demand_misses::cpu.inst 10604 # number of demand (read+write) misses 114system.l2c.demand_misses::cpu.data 143339 # number of demand (read+write) misses 115system.l2c.demand_misses::total 153951 # number of demand (read+write) misses 116system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses 117system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses 118system.l2c.overall_misses::cpu.inst 10604 # number of overall misses 119system.l2c.overall_misses::cpu.data 143339 # number of overall misses 120system.l2c.overall_misses::total 153951 # number of overall misses 121system.l2c.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) 122system.l2c.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) 123system.l2c.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) 124system.l2c.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) 125system.l2c.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) 126system.l2c.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) 127system.l2c.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) 128system.l2c.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) 129system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) 130system.l2c.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) 131system.l2c.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) 132system.l2c.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses 133system.l2c.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses 134system.l2c.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses 135system.l2c.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses 136system.l2c.demand_accesses::total 1483968 # number of demand (read+write) accesses 137system.l2c.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses 138system.l2c.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses 139system.l2c.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses 140system.l2c.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses 141system.l2c.overall_accesses::total 1483968 # number of overall (read+write) accesses 142system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses 143system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses 144system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses 145system.l2c.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses 146system.l2c.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses 147system.l2c.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses 148system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses 149system.l2c.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses 150system.l2c.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses 151system.l2c.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses 152system.l2c.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses 153system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses 154system.l2c.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses 155system.l2c.demand_miss_rate::total 0.103743 # miss rate for demand accesses 156system.l2c.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses 157system.l2c.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses 158system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses 159system.l2c.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses 160system.l2c.overall_miss_rate::total 0.103743 # miss rate for overall accesses 161system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 162system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 163system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 164system.l2c.blocked::no_targets 0 # number of cycles access was blocked 165system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 167system.l2c.fast_writes 0 # number of fast writes performed 168system.l2c.cache_copies 0 # number of cache copies performed 169system.l2c.writebacks::writebacks 57863 # number of writebacks 170system.l2c.writebacks::total 57863 # number of writebacks 171system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 64system.cpu.l2cache.replacements 62243 # number of replacements 65system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use 66system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks. 67system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks. 68system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks. 69system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. 70system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor 71system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor 72system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor 73system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor 74system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor 75system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy 76system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 77system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy 78system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy 79system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy 80system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy 81system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits 82system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits 83system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits 84system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits 85system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits 86system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits 87system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits 88system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 89system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 90system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits 91system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits 92system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits 93system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits 94system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits 95system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits 96system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits 97system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits 98system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits 99system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits 100system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits 101system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits 102system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 103system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 104system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses 105system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses 106system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses 107system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses 108system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses 109system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses 110system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses 111system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 112system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 113system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses 114system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses 115system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses 116system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 117system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 118system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses 119system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses 120system.cpu.l2cache.overall_misses::total 153951 # number of overall misses 121system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) 122system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) 123system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) 124system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) 125system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) 126system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) 127system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) 128system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) 129system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) 130system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) 131system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) 132system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses 133system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses 134system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses 135system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses 136system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses 137system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses 138system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses 139system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses 140system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses 141system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses 142system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses 143system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses 144system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses 145system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses 146system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses 147system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses 148system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses 149system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses 150system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses 151system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses 152system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses 153system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses 154system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses 155system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses 156system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses 157system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses 158system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses 159system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses 160system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses 161system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 162system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 163system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 164system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 165system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 167system.cpu.l2cache.fast_writes 0 # number of fast writes performed 168system.cpu.l2cache.cache_copies 0 # number of cache copies performed 169system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks 170system.cpu.l2cache.writebacks::total 57863 # number of writebacks 171system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 172system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 173system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 174system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 175system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 176system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 177system.cf0.dma_write_txs 0 # Number of DMA write transactions. 178system.cpu.dtb.inst_hits 0 # ITB inst hits 179system.cpu.dtb.inst_misses 0 # ITB inst misses --- 187 unchanged lines hidden --- | 172system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 173system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 174system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 175system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 176system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 177system.cf0.dma_write_txs 0 # Number of DMA write transactions. 178system.cpu.dtb.inst_hits 0 # ITB inst hits 179system.cpu.dtb.inst_misses 0 # ITB inst misses --- 187 unchanged lines hidden --- |