Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 2.332330 # Number of seconds simulated
4sim_ticks 2332330037000 # Number of ticks simulated
5final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 2.332810 # Number of seconds simulated
4sim_ticks 2332810264000 # Number of ticks simulated
5final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1988795 # Simulator instruction rate (inst/s)
8host_op_rate 2567201 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 78099767101 # Simulator tick rate (ticks/s)
10host_mem_usage 382744 # Number of bytes of host memory used
11host_seconds 29.86 # Real time elapsed on the host
12sim_insts 59392246 # Number of instructions simulated
13sim_ops 76665494 # Number of ops (including micro ops) simulated

7host_inst_rate 1498673 # Simulator instruction rate (inst/s)
8host_op_rate 1927201 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 57874436068 # Simulator tick rate (ticks/s)
10host_mem_usage 388524 # Number of bytes of host memory used
11host_seconds 40.31 # Real time elapsed on the host
12sim_insts 60408639 # Number of instructions simulated
13sim_ops 77681819 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory

17system.physmem.bytes_read::cpu.inst 704992 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9071568 # Number of bytes read from this memory
19system.physmem.bytes_read::total 121450416 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 704992 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 704992 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory

17system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory
19system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory

23system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory

24system.physmem.bytes_written::total 6718856 # Number of bytes written to this memory

24system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory

25system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory

28system.physmem.num_reads::cpu.inst 17218 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 141777 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 14118171 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory

28system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory

32system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory

33system.physmem.num_writes::total 811814 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s)

33system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)

35system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s)

37system.physmem.bw_read::cpu.inst 302269 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3889487 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 52072569 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 302269 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 302269 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1587700 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_write::total 2880748 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1587700 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s)

37system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)

47system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.bw_total::cpu.inst 302269 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 5182536 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 54953317 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)

52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
58system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
59system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
60system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
61system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
62system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
63system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)

64system.l2c.replacements 62240 # number of replacements
65system.l2c.tagsinuse 50004.786190 # Cycle average of tags in use
66system.l2c.total_refs 1717775 # Total number of references to valid blocks.
67system.l2c.sampled_refs 127625 # Sample count of references to valid blocks.
68system.l2c.avg_refs 13.459549 # Average number of references to valid blocks.
69system.l2c.warmup_cycle 2316513323500 # Cycle when the warmup percentage was hit.
70system.l2c.occ_blocks::writebacks 36897.037256 # Average occupied blocks per requestor
71system.l2c.occ_blocks::cpu.dtb.walker 2.960071 # Average occupied blocks per requestor
72system.l2c.occ_blocks::cpu.itb.walker 0.993930 # Average occupied blocks per requestor
73system.l2c.occ_blocks::cpu.inst 7014.608709 # Average occupied blocks per requestor
74system.l2c.occ_blocks::cpu.data 6089.186223 # Average occupied blocks per requestor
75system.l2c.occ_percent::writebacks 0.563004 # Average percentage of cache occupancy

64system.l2c.replacements 62243 # number of replacements
65system.l2c.tagsinuse 50007.272909 # Cycle average of tags in use
66system.l2c.total_refs 1669922 # Total number of references to valid blocks.
67system.l2c.sampled_refs 127628 # Sample count of references to valid blocks.
68system.l2c.avg_refs 13.084292 # Average number of references to valid blocks.
69system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
70system.l2c.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
71system.l2c.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
72system.l2c.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
73system.l2c.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
74system.l2c.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
75system.l2c.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy

76system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
77system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy

78system.l2c.occ_percent::cpu.inst 0.107034 # Average percentage of cache occupancy
79system.l2c.occ_percent::cpu.data 0.092914 # Average percentage of cache occupancy
80system.l2c.occ_percent::total 0.763012 # Average percentage of cache occupancy
81system.l2c.ReadReq_hits::cpu.dtb.walker 7534 # number of ReadReq hits
82system.l2c.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits
83system.l2c.ReadReq_hits::cpu.inst 838895 # number of ReadReq hits
84system.l2c.ReadReq_hits::cpu.data 364444 # number of ReadReq hits
85system.l2c.ReadReq_hits::total 1214024 # number of ReadReq hits
86system.l2c.Writeback_hits::writebacks 642748 # number of Writeback hits
87system.l2c.Writeback_hits::total 642748 # number of Writeback hits

78system.l2c.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
79system.l2c.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
80system.l2c.occ_percent::total 0.763050 # Average percentage of cache occupancy
81system.l2c.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
82system.l2c.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
83system.l2c.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
84system.l2c.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
85system.l2c.ReadReq_hits::total 1216278 # number of ReadReq hits
86system.l2c.Writeback_hits::writebacks 592643 # number of Writeback hits
87system.l2c.Writeback_hits::total 592643 # number of Writeback hits

88system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
89system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits

90system.l2c.ReadExReq_hits::cpu.data 113737 # number of ReadExReq hits
91system.l2c.ReadExReq_hits::total 113737 # number of ReadExReq hits
92system.l2c.demand_hits::cpu.dtb.walker 7534 # number of demand (read+write) hits
93system.l2c.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits
94system.l2c.demand_hits::cpu.inst 838895 # number of demand (read+write) hits
95system.l2c.demand_hits::cpu.data 478181 # number of demand (read+write) hits
96system.l2c.demand_hits::total 1327761 # number of demand (read+write) hits
97system.l2c.overall_hits::cpu.dtb.walker 7534 # number of overall hits
98system.l2c.overall_hits::cpu.itb.walker 3151 # number of overall hits
99system.l2c.overall_hits::cpu.inst 838895 # number of overall hits
100system.l2c.overall_hits::cpu.data 478181 # number of overall hits
101system.l2c.overall_hits::total 1327761 # number of overall hits

90system.l2c.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
91system.l2c.ReadExReq_hits::total 113739 # number of ReadExReq hits
92system.l2c.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
93system.l2c.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
94system.l2c.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
95system.l2c.demand_hits::cpu.data 480510 # number of demand (read+write) hits
96system.l2c.demand_hits::total 1330017 # number of demand (read+write) hits
97system.l2c.overall_hits::cpu.dtb.walker 7507 # number of overall hits
98system.l2c.overall_hits::cpu.itb.walker 3129 # number of overall hits
99system.l2c.overall_hits::cpu.inst 838871 # number of overall hits
100system.l2c.overall_hits::cpu.data 480510 # number of overall hits
101system.l2c.overall_hits::total 1330017 # number of overall hits

102system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
103system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses

104system.l2c.ReadReq_misses::cpu.inst 10602 # number of ReadReq misses
105system.l2c.ReadReq_misses::cpu.data 9870 # number of ReadReq misses
106system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses
107system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
108system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
109system.l2c.ReadExReq_misses::cpu.data 133469 # number of ReadExReq misses
110system.l2c.ReadExReq_misses::total 133469 # number of ReadExReq misses

104system.l2c.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
105system.l2c.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
106system.l2c.ReadReq_misses::total 20483 # number of ReadReq misses
107system.l2c.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
108system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
109system.l2c.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
110system.l2c.ReadExReq_misses::total 133468 # number of ReadExReq misses

111system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
112system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses

113system.l2c.demand_misses::cpu.inst 10602 # number of demand (read+write) misses

113system.l2c.demand_misses::cpu.inst 10604 # number of demand (read+write) misses

114system.l2c.demand_misses::cpu.data 143339 # number of demand (read+write) misses

115system.l2c.demand_misses::total 153949 # number of demand (read+write) misses

115system.l2c.demand_misses::total 153951 # number of demand (read+write) misses

116system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses
117system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses

118system.l2c.overall_misses::cpu.inst 10602 # number of overall misses

118system.l2c.overall_misses::cpu.inst 10604 # number of overall misses

119system.l2c.overall_misses::cpu.data 143339 # number of overall misses

120system.l2c.overall_misses::total 153949 # number of overall misses
121system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses)
122system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
123system.l2c.ReadReq_accesses::cpu.inst 849497 # number of ReadReq accesses(hits+misses)
124system.l2c.ReadReq_accesses::cpu.data 374314 # number of ReadReq accesses(hits+misses)
125system.l2c.ReadReq_accesses::total 1234504 # number of ReadReq accesses(hits+misses)
126system.l2c.Writeback_accesses::writebacks 642748 # number of Writeback accesses(hits+misses)
127system.l2c.Writeback_accesses::total 642748 # number of Writeback accesses(hits+misses)
128system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses)
129system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses)
130system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses)
131system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses)
132system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses
133system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
134system.l2c.demand_accesses::cpu.inst 849497 # number of demand (read+write) accesses
135system.l2c.demand_accesses::cpu.data 621520 # number of demand (read+write) accesses
136system.l2c.demand_accesses::total 1481710 # number of demand (read+write) accesses
137system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses
138system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
139system.l2c.overall_accesses::cpu.inst 849497 # number of overall (read+write) accesses
140system.l2c.overall_accesses::cpu.data 621520 # number of overall (read+write) accesses
141system.l2c.overall_accesses::total 1481710 # number of overall (read+write) accesses
142system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses
143system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses
144system.l2c.ReadReq_miss_rate::cpu.inst 0.012480 # miss rate for ReadReq accesses
145system.l2c.ReadReq_miss_rate::cpu.data 0.026368 # miss rate for ReadReq accesses
146system.l2c.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses
147system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses
148system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses
149system.l2c.ReadExReq_miss_rate::cpu.data 0.539910 # miss rate for ReadExReq accesses
150system.l2c.ReadExReq_miss_rate::total 0.539910 # miss rate for ReadExReq accesses
151system.l2c.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses
152system.l2c.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses
153system.l2c.demand_miss_rate::cpu.inst 0.012480 # miss rate for demand accesses
154system.l2c.demand_miss_rate::cpu.data 0.230627 # miss rate for demand accesses
155system.l2c.demand_miss_rate::total 0.103900 # miss rate for demand accesses
156system.l2c.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses
157system.l2c.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses
158system.l2c.overall_miss_rate::cpu.inst 0.012480 # miss rate for overall accesses
159system.l2c.overall_miss_rate::cpu.data 0.230627 # miss rate for overall accesses
160system.l2c.overall_miss_rate::total 0.103900 # miss rate for overall accesses

120system.l2c.overall_misses::total 153951 # number of overall misses
121system.l2c.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
122system.l2c.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
123system.l2c.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
124system.l2c.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
125system.l2c.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
126system.l2c.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
127system.l2c.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
128system.l2c.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
129system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
130system.l2c.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
131system.l2c.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
132system.l2c.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
133system.l2c.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
134system.l2c.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
135system.l2c.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
136system.l2c.demand_accesses::total 1483968 # number of demand (read+write) accesses
137system.l2c.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
138system.l2c.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
139system.l2c.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
140system.l2c.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
141system.l2c.overall_accesses::total 1483968 # number of overall (read+write) accesses
142system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
143system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
144system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
145system.l2c.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
146system.l2c.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
147system.l2c.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
148system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
149system.l2c.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
150system.l2c.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
151system.l2c.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
152system.l2c.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
153system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
154system.l2c.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
155system.l2c.demand_miss_rate::total 0.103743 # miss rate for demand accesses
156system.l2c.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
157system.l2c.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
158system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
159system.l2c.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
160system.l2c.overall_miss_rate::total 0.103743 # miss rate for overall accesses

161system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
162system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
163system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
164system.l2c.blocked::no_targets 0 # number of cycles access was blocked
165system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
166system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
167system.l2c.fast_writes 0 # number of fast writes performed
168system.l2c.cache_copies 0 # number of cache copies performed

169system.l2c.writebacks::writebacks 57860 # number of writebacks
170system.l2c.writebacks::total 57860 # number of writebacks

169system.l2c.writebacks::writebacks 57863 # number of writebacks
170system.l2c.writebacks::total 57863 # number of writebacks

171system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
172system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
173system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
174system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
175system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
176system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
177system.cf0.dma_write_txs 0 # Number of DMA write transactions.
178system.cpu.dtb.inst_hits 0 # ITB inst hits
179system.cpu.dtb.inst_misses 0 # ITB inst misses

180system.cpu.dtb.read_hits 14971229 # DTB read hits
181system.cpu.dtb.read_misses 7293 # DTB read misses
182system.cpu.dtb.write_hits 11217018 # DTB write hits

180system.cpu.dtb.read_hits 14971214 # DTB read hits
181system.cpu.dtb.read_misses 7294 # DTB read misses
182system.cpu.dtb.write_hits 11217004 # DTB write hits

183system.cpu.dtb.write_misses 2181 # DTB write misses
184system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
185system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
186system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
187system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID

188system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB

188system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB

189system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
190system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
191system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
192system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions

193system.cpu.dtb.read_accesses 14978522 # DTB read accesses
194system.cpu.dtb.write_accesses 11219199 # DTB write accesses

193system.cpu.dtb.read_accesses 14978508 # DTB read accesses
194system.cpu.dtb.write_accesses 11219185 # DTB write accesses

195system.cpu.dtb.inst_accesses 0 # ITB inst accesses

196system.cpu.dtb.hits 26188247 # DTB hits
197system.cpu.dtb.misses 9474 # DTB misses
198system.cpu.dtb.accesses 26197721 # DTB accesses
199system.cpu.itb.inst_hits 60403303 # ITB inst hits

196system.cpu.dtb.hits 26188218 # DTB hits
197system.cpu.dtb.misses 9475 # DTB misses
198system.cpu.dtb.accesses 26197693 # DTB accesses
199system.cpu.itb.inst_hits 61431840 # ITB inst hits

200system.cpu.itb.inst_misses 4471 # ITB inst misses
201system.cpu.itb.read_hits 0 # DTB read hits
202system.cpu.itb.read_misses 0 # DTB read misses
203system.cpu.itb.write_hits 0 # DTB write hits
204system.cpu.itb.write_misses 0 # DTB write misses
205system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
206system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
207system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
208system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
209system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
210system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
211system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
212system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
213system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
214system.cpu.itb.read_accesses 0 # DTB read accesses
215system.cpu.itb.write_accesses 0 # DTB write accesses

216system.cpu.itb.inst_accesses 60407774 # ITB inst accesses
217system.cpu.itb.hits 60403303 # DTB hits

216system.cpu.itb.inst_accesses 61436311 # ITB inst accesses
217system.cpu.itb.hits 61431840 # DTB hits

218system.cpu.itb.misses 4471 # DTB misses

219system.cpu.itb.accesses 60407774 # DTB accesses
220system.cpu.numCycles 4664583062 # number of cpu cycles simulated

219system.cpu.itb.accesses 61436311 # DTB accesses
220system.cpu.numCycles 4665543516 # number of cpu cycles simulated

221system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
222system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

223system.cpu.committedInsts 59392246 # Number of instructions committed
224system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed
225system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses

223system.cpu.committedInsts 60408639 # Number of instructions committed
224system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed
225system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses

226system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses

227system.cpu.num_func_calls 2136013 # number of times a function call or return occured
228system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls
229system.cpu.num_int_insts 68281415 # number of integer instructions

227system.cpu.num_func_calls 2136008 # number of times a function call or return occured
228system.cpu.num_conditional_control_insts 7904929 # number of instructions that are conditional controls
229system.cpu.num_int_insts 68795605 # number of integer instructions

230system.cpu.num_fp_insts 10269 # number of float instructions

231system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read
232system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written

231system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read
232system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written

233system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
234system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written

235system.cpu.num_mem_refs 27361692 # number of memory refs
236system.cpu.num_load_insts 15639569 # Number of load instructions
237system.cpu.num_store_insts 11722123 # Number of store instructions
238system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles
239system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles
240system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles
241system.cpu.idle_fraction 0.983328 # Percentage of idle cycles

235system.cpu.num_mem_refs 27361637 # number of memory refs
236system.cpu.num_load_insts 15639527 # Number of load instructions
237system.cpu.num_store_insts 11722110 # Number of store instructions
238system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles
239system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles
240system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles
241system.cpu.idle_fraction 0.983111 # Percentage of idle cycles

242system.cpu.kern.inst.arm 0 # number of arm instructions executed
243system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed

244system.cpu.icache.replacements 850612 # number of replacements
245system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use
246system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks.
247system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks.
248system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks.
249system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit.
250system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor

244system.cpu.icache.replacements 850590 # number of replacements
245system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use
246system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks.
247system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks.
248system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks.
249system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
250system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor

251system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
252system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy

253system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits
254system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits
255system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits
256system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits
257system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits
258system.cpu.icache.overall_hits::total 59554939 # number of overall hits
259system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses
260system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses
261system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses
262system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses
263system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses
264system.cpu.icache.overall_misses::total 851124 # number of overall misses
265system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses)
266system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses)
267system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses
268system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses
269system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses
270system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses
271system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses
272system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses
273system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses
274system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses
275system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses
276system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses

253system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits
254system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
255system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits
256system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits
257system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits
258system.cpu.icache.overall_hits::total 60583498 # number of overall hits
259system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses
260system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses
261system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses
262system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses
263system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses
264system.cpu.icache.overall_misses::total 851102 # number of overall misses
265system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses)
266system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses)
267system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses
268system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
269system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses
270system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
271system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses
272system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses
273system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses
274system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses
275system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses
276system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses

277system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
278system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
279system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
280system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
281system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
282system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
283system.cpu.icache.fast_writes 0 # number of fast writes performed
284system.cpu.icache.cache_copies 0 # number of cache copies performed

285system.cpu.icache.writebacks::writebacks 50093 # number of writebacks
286system.cpu.icache.writebacks::total 50093 # number of writebacks

287system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

285system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

288system.cpu.dcache.replacements 623347 # number of replacements
289system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use
290system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks.
291system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks.
292system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks.

286system.cpu.dcache.replacements 623337 # number of replacements
287system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use
288system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks.
289system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks.
290system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks.

293system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.

291system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.

294system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor

292system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor

295system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
296system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy

293system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
294system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy

297system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits
298system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits
299system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits
300system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits
301system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits
302system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits
303system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits
304system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits
305system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits
306system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits
307system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits
308system.cpu.dcache.overall_hits::total 23142161 # number of overall hits
309system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses
310system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses
311system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses
312system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses
313system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses
314system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses
315system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses
316system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses
317system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses
318system.cpu.dcache.overall_misses::total 615615 # number of overall misses
319system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses)
320system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses)
321system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses)
322system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses)
323system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses)
324system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses)
325system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses)
326system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses)
327system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses
328system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses
329system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses
330system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses

295system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
296system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
297system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
298system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
299system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
300system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
301system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
302system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
303system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
304system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
305system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
306system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
307system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
308system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
309system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
310system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
311system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
312system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
313system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
314system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
315system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
316system.cpu.dcache.overall_misses::total 615611 # number of overall misses
317system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
318system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
319system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
320system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
321system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
322system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
323system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
324system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
325system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
326system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
327system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
328system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses

331system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
332system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
333system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
334system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses

329system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
330system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
331system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
332system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses

335system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses
336system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses

333system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
334system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses

337system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
338system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
339system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
340system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
341system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
342system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
343system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
344system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
345system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
346system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
347system.cpu.dcache.fast_writes 0 # number of fast writes performed
348system.cpu.dcache.cache_copies 0 # number of cache copies performed

335system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
336system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
337system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
338system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
339system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
340system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
341system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
342system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
343system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
344system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
345system.cpu.dcache.fast_writes 0 # number of fast writes performed
346system.cpu.dcache.cache_copies 0 # number of cache copies performed

349system.cpu.dcache.writebacks::writebacks 592655 # number of writebacks
350system.cpu.dcache.writebacks::total 592655 # number of writebacks

347system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
348system.cpu.dcache.writebacks::total 592643 # number of writebacks