| stats.txt (9005:f681719e2e99) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332330 # Number of seconds simulated 4sim_ticks 2332330037000 # Number of ticks simulated 5final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332330 # Number of seconds simulated 4sim_ticks 2332330037000 # Number of ticks simulated 5final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1538399 # Simulator instruction rate (inst/s) 8host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 60412799239 # Simulator tick rate (ticks/s) 10host_mem_usage 379756 # Number of bytes of host memory used 11host_seconds 38.61 # Real time elapsed on the host | 7host_inst_rate 1412842 # Simulator instruction rate (inst/s) 8host_op_rate 1823742 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 55482154888 # Simulator tick rate (ticks/s) 10host_mem_usage 382804 # Number of bytes of host memory used 11host_seconds 42.04 # Real time elapsed on the host |
| 12sim_insts 59392246 # Number of instructions simulated 13sim_ops 76665494 # Number of ops (including micro ops) simulated | 12sim_insts 59392246 # Number of instructions simulated 13sim_ops 76665494 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 122661296 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 9590216 # Number of bytes written to this memory 17system.physmem.num_reads 14137091 # Number of read requests responded to by this memory 18system.physmem.num_writes 856679 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s) 24system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 1536 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 960 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 941920 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10043536 # Number of bytes read from this memory 19system.physmem.bytes_read::total 122661296 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 941920 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 941920 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6574400 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory 24system.physmem.bytes_written::total 9590216 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 24 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 15 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 20920 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 156964 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 14137091 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 102725 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 856679 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 659 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 412 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 403854 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 4306224 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 52591740 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 403854 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 403854 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 2818812 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 4111861 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 2818812 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 659 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 412 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 403854 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 5599273 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 56703601 # Total bandwidth to/from this memory (bytes/s) 52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 58system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) 59system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) 60system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) 63system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) |
| 33system.l2c.replacements 117012 # number of replacements 34system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use 35system.l2c.total_refs 1527554 # Total number of references to valid blocks. 36system.l2c.sampled_refs 146810 # Sample count of references to valid blocks. 37system.l2c.avg_refs 10.404972 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 39system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor --- 66 unchanged lines hidden (view full) --- 107system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses 109system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses 110system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses 111system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses 113system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses 114system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses | 64system.l2c.replacements 117012 # number of replacements 65system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use 66system.l2c.total_refs 1527554 # Total number of references to valid blocks. 67system.l2c.sampled_refs 146810 # Sample count of references to valid blocks. 68system.l2c.avg_refs 10.404972 # Average number of references to valid blocks. 69system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor 71system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor --- 66 unchanged lines hidden (view full) --- 138system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses 139system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses 140system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses 141system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses 142system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses 143system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses 144system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses 145system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses |
| 146system.l2c.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses |
|
| 115system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses | 147system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses |
| 148system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses |
|
| 116system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses | 149system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses |
| 150system.l2c.ReadExReq_miss_rate::total 0.570577 # miss rate for ReadExReq accesses |
|
| 117system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses 118system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses 119system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses 120system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses | 151system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses 152system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses 153system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses 154system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses |
| 155system.l2c.demand_miss_rate::total 0.116613 # miss rate for demand accesses |
|
| 121system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses 122system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses 123system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses 124system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses | 156system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses 157system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses 158system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses 159system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses |
| 160system.l2c.overall_miss_rate::total 0.116613 # miss rate for overall accesses |
|
| 125system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 126system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 127system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 128system.l2c.blocked::no_targets 0 # number of cycles access was blocked 129system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 130system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 131system.l2c.fast_writes 0 # number of fast writes performed 132system.l2c.cache_copies 0 # number of cache copies performed --- 95 unchanged lines hidden (view full) --- 228system.cpu.icache.overall_misses::total 851124 # number of overall misses 229system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses) 230system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses) 231system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses 232system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses 233system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses 234system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses 235system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses | 161system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 162system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 163system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 164system.l2c.blocked::no_targets 0 # number of cycles access was blocked 165system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 166system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 167system.l2c.fast_writes 0 # number of fast writes performed 168system.l2c.cache_copies 0 # number of cache copies performed --- 95 unchanged lines hidden (view full) --- 264system.cpu.icache.overall_misses::total 851124 # number of overall misses 265system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses) 266system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses) 267system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses 268system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses 269system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses 270system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses 271system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses |
| 272system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses |
|
| 236system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses | 273system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses |
| 274system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses |
|
| 237system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses | 275system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses |
| 276system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses |
|
| 238system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 239system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 240system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 241system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 242system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 243system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 244system.cpu.icache.fast_writes 0 # number of fast writes performed 245system.cpu.icache.cache_copies 0 # number of cache copies performed --- 39 unchanged lines hidden (view full) --- 285system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses) 286system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses) 287system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses) 288system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses 289system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses 290system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses 291system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses 292system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses | 277system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 278system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 279system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 280system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 281system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 282system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 283system.cpu.icache.fast_writes 0 # number of fast writes performed 284system.cpu.icache.cache_copies 0 # number of cache copies performed --- 39 unchanged lines hidden (view full) --- 324system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses) 325system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses) 326system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses) 327system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses 328system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses 329system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses 330system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses 331system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses |
| 332system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses |
|
| 293system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses | 333system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses |
| 334system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses |
|
| 294system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses | 335system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses |
| 336system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses |
|
| 295system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses | 337system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses |
| 338system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses |
|
| 296system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses | 339system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses |
| 340system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses |
|
| 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 303system.cpu.dcache.fast_writes 0 # number of fast writes performed 304system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 20 unchanged lines hidden --- | 341system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 342system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 344system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 345system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 346system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.cpu.dcache.fast_writes 0 # number of fast writes performed 348system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 20 unchanged lines hidden --- |