Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

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sdiff udiff text old ( 8983:8800b05e1cb3 ) new ( 9005:f681719e2e99 )

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stats.txt (8983:8800b05e1cb3)	stats.txt (9005:f681719e2e99)
1 2---------- Begin Simulation Statistics ----------	1 2---------- Begin Simulation Statistics ----------
3sim_seconds 2.332317 # Number of seconds simulated 4sim_ticks 2332316587000 # Number of ticks simulated 5final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)	3sim_seconds 2.332330 # Number of seconds simulated 4sim_ticks 2332330037000 # Number of ticks simulated 5final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks	6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 864582 # Simulator instruction rate (inst/s) 8host_op_rate 1116533 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34025972839 # Simulator tick rate (ticks/s) 10host_mem_usage 383900 # Number of bytes of host memory used 11host_seconds 68.55 # Real time elapsed on the host 12sim_insts 59262896 # Number of instructions simulated 13sim_ops 76532951 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 122663536 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 941280 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 9577800 # Number of bytes written to this memory 17system.physmem.num_reads 14137126 # Number of read requests responded to by this memory 18system.physmem.num_writes 856485 # Number of write requests responded to by this memory	7host_inst_rate 1538399 # Simulator instruction rate (inst/s) 8host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 60412799239 # Simulator tick rate (ticks/s) 10host_mem_usage 379756 # Number of bytes of host memory used 11host_seconds 38.61 # Real time elapsed on the host 12sim_insts 59392246 # Number of instructions simulated 13sim_ops 76665494 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 122661296 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 9590216 # Number of bytes written to this memory 17system.physmem.num_reads 14137091 # Number of read requests responded to by this memory 18system.physmem.num_writes 856679 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory	19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s)	20system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s)
24system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s)	24system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory 25system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 26system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 27system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory 28system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 29system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 30system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) 32system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s)
33system.l2c.replacements 116822 # number of replacements 34system.l2c.tagsinuse 24240.388395 # Cycle average of tags in use 35system.l2c.total_refs 1520830 # Total number of references to valid blocks. 36system.l2c.sampled_refs 146847 # Sample count of references to valid blocks. 37system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.	33system.l2c.replacements 117012 # number of replacements 34system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use 35system.l2c.total_refs 1527554 # Total number of references to valid blocks. 36system.l2c.sampled_refs 146810 # Sample count of references to valid blocks. 37system.l2c.avg_refs 10.404972 # Average number of references to valid blocks.
38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.	38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
39system.l2c.occ_blocks::writebacks 13639.466229 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor 41system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor 42system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor 43system.l2c.occ_blocks::cpu.data 5344.680068 # Average occupied blocks per requestor 44system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy	39system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor 40system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor 41system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor 42system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor 43system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor 44system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy
45system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy 46system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy	45system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy 46system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy
47system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy 48system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy 49system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy 50system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits 51system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits 52system.l2c.ReadReq_hits::cpu.inst 831710 # number of ReadReq hits 53system.l2c.ReadReq_hits::cpu.data 356506 # number of ReadReq hits 54system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits 55system.l2c.Writeback_hits::writebacks 604613 # number of Writeback hits 56system.l2c.Writeback_hits::total 604613 # number of Writeback hits	47system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy 48system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy 49system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy 50system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits 51system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits 52system.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits 53system.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits 54system.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits 55system.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits 56system.l2c.Writeback_hits::total 605735 # number of Writeback hits
57system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 58system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits	57system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 58system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits
59system.l2c.ReadExReq_hits::cpu.data 105791 # number of ReadExReq hits 60system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits 61system.l2c.demand_hits::cpu.dtb.walker 7522 # number of demand (read+write) hits 62system.l2c.demand_hits::cpu.itb.walker 3147 # number of demand (read+write) hits 63system.l2c.demand_hits::cpu.inst 831710 # number of demand (read+write) hits 64system.l2c.demand_hits::cpu.data 462297 # number of demand (read+write) hits 65system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits 66system.l2c.overall_hits::cpu.dtb.walker 7522 # number of overall hits 67system.l2c.overall_hits::cpu.itb.walker 3147 # number of overall hits 68system.l2c.overall_hits::cpu.inst 831710 # number of overall hits 69system.l2c.overall_hits::cpu.data 462297 # number of overall hits 70system.l2c.overall_hits::total 1304676 # number of overall hits 71system.l2c.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses 72system.l2c.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses 73system.l2c.ReadReq_misses::cpu.inst 14294 # number of ReadReq misses 74system.l2c.ReadReq_misses::cpu.data 17422 # number of ReadReq misses 75system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses 76system.l2c.UpgradeReq_misses::cpu.data 2911 # number of UpgradeReq misses 77system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses 78system.l2c.ReadExReq_misses::cpu.data 141169 # number of ReadExReq misses 79system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses 80system.l2c.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses 81system.l2c.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses 82system.l2c.demand_misses::cpu.inst 14294 # number of demand (read+write) misses 83system.l2c.demand_misses::cpu.data 158591 # number of demand (read+write) misses 84system.l2c.demand_misses::total 172912 # number of demand (read+write) misses 85system.l2c.overall_misses::cpu.dtb.walker 19 # number of overall misses 86system.l2c.overall_misses::cpu.itb.walker 8 # number of overall misses 87system.l2c.overall_misses::cpu.inst 14294 # number of overall misses 88system.l2c.overall_misses::cpu.data 158591 # number of overall misses 89system.l2c.overall_misses::total 172912 # number of overall misses 90system.l2c.ReadReq_accesses::cpu.dtb.walker 7541 # number of ReadReq accesses(hits+misses) 91system.l2c.ReadReq_accesses::cpu.itb.walker 3155 # number of ReadReq accesses(hits+misses) 92system.l2c.ReadReq_accesses::cpu.inst 846004 # number of ReadReq accesses(hits+misses) 93system.l2c.ReadReq_accesses::cpu.data 373928 # number of ReadReq accesses(hits+misses) 94system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses) 95system.l2c.Writeback_accesses::writebacks 604613 # number of Writeback accesses(hits+misses) 96system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses) 97system.l2c.UpgradeReq_accesses::cpu.data 2937 # number of UpgradeReq accesses(hits+misses) 98system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) 99system.l2c.ReadExReq_accesses::cpu.data 246960 # number of ReadExReq accesses(hits+misses) 100system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses) 101system.l2c.demand_accesses::cpu.dtb.walker 7541 # number of demand (read+write) accesses 102system.l2c.demand_accesses::cpu.itb.walker 3155 # number of demand (read+write) accesses 103system.l2c.demand_accesses::cpu.inst 846004 # number of demand (read+write) accesses 104system.l2c.demand_accesses::cpu.data 620888 # number of demand (read+write) accesses 105system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses 106system.l2c.overall_accesses::cpu.dtb.walker 7541 # number of overall (read+write) accesses 107system.l2c.overall_accesses::cpu.itb.walker 3155 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.inst 846004 # number of overall (read+write) accesses 109system.l2c.overall_accesses::cpu.data 620888 # number of overall (read+write) accesses 110system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses 111system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002520 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.002536 # miss rate for ReadReq accesses 113system.l2c.ReadReq_miss_rate::cpu.inst 0.016896 # miss rate for ReadReq accesses	59system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits 60system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits 61system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits 62system.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits 63system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits 64system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits 65system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits 66system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits 67system.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits 68system.l2c.overall_hits::cpu.inst 835264 # number of overall hits 69system.l2c.overall_hits::cpu.data 463541 # number of overall hits 70system.l2c.overall_hits::total 1309459 # number of overall hits 71system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses 72system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses 73system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses 74system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses 75system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses 76system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses 77system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses 78system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses 79system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses 80system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses 81system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses 82system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses 83system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses 84system.l2c.demand_misses::total 172858 # number of demand (read+write) misses 85system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses 86system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses 87system.l2c.overall_misses::cpu.inst 14304 # number of overall misses 88system.l2c.overall_misses::cpu.data 158515 # number of overall misses 89system.l2c.overall_misses::total 172858 # number of overall misses 90system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses) 91system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) 92system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses) 93system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses) 94system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses) 95system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses) 96system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses) 97system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses) 98system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) 99system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses) 100system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses) 101system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses 102system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses 103system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses 104system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses 105system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses 106system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses 107system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses 109system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses 110system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses 111system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses 113system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses
114system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses	114system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses
115system.l2c.UpgradeReq_miss_rate::cpu.data 0.991147 # miss rate for UpgradeReq accesses 116system.l2c.ReadExReq_miss_rate::cpu.data 0.571627 # miss rate for ReadExReq accesses 117system.l2c.demand_miss_rate::cpu.dtb.walker 0.002520 # miss rate for demand accesses 118system.l2c.demand_miss_rate::cpu.itb.walker 0.002536 # miss rate for demand accesses 119system.l2c.demand_miss_rate::cpu.inst 0.016896 # miss rate for demand accesses 120system.l2c.demand_miss_rate::cpu.data 0.255426 # miss rate for demand accesses 121system.l2c.overall_miss_rate::cpu.dtb.walker 0.002520 # miss rate for overall accesses 122system.l2c.overall_miss_rate::cpu.itb.walker 0.002536 # miss rate for overall accesses 123system.l2c.overall_miss_rate::cpu.inst 0.016896 # miss rate for overall accesses 124system.l2c.overall_miss_rate::cpu.data 0.255426 # miss rate for overall accesses	115system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses 116system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses 117system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses 118system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses 119system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses 120system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses 121system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses 122system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses 123system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses 124system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses
125system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 126system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 127system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 128system.l2c.blocked::no_targets 0 # number of cycles access was blocked 129system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 130system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 131system.l2c.fast_writes 0 # number of fast writes performed 132system.l2c.cache_copies 0 # number of cache copies performed	125system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 126system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 127system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 128system.l2c.blocked::no_targets 0 # number of cycles access was blocked 129system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 130system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 131system.l2c.fast_writes 0 # number of fast writes performed 132system.l2c.cache_copies 0 # number of cache copies performed
133system.l2c.writebacks::writebacks 102531 # number of writebacks 134system.l2c.writebacks::total 102531 # number of writebacks	133system.l2c.writebacks::writebacks 102725 # number of writebacks 134system.l2c.writebacks::total 102725 # number of writebacks
135system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 136system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 137system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 138system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 139system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 140system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 141system.cf0.dma_write_txs 0 # Number of DMA write transactions. 142system.cpu.dtb.inst_hits 0 # ITB inst hits 143system.cpu.dtb.inst_misses 0 # ITB inst misses	135system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 136system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 137system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 138system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 139system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 140system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 141system.cf0.dma_write_txs 0 # Number of DMA write transactions. 142system.cpu.dtb.inst_hits 0 # ITB inst hits 143system.cpu.dtb.inst_misses 0 # ITB inst misses
144system.cpu.dtb.read_hits 14940568 # DTB read hits 145system.cpu.dtb.read_misses 7288 # DTB read misses 146system.cpu.dtb.write_hits 11198206 # DTB write hits 147system.cpu.dtb.write_misses 2199 # DTB write misses	144system.cpu.dtb.read_hits 14971229 # DTB read hits 145system.cpu.dtb.read_misses 7293 # DTB read misses 146system.cpu.dtb.write_hits 11217018 # DTB write hits 147system.cpu.dtb.write_misses 2181 # DTB write misses
148system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 149system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 151system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID	148system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 149system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 151system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
152system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB	152system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB
153system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions	153system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
154system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch	154system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
155system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 156system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions	155system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 156system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
157system.cpu.dtb.read_accesses 14947856 # DTB read accesses 158system.cpu.dtb.write_accesses 11200405 # DTB write accesses	157system.cpu.dtb.read_accesses 14978522 # DTB read accesses 158system.cpu.dtb.write_accesses 11219199 # DTB write accesses
159system.cpu.dtb.inst_accesses 0 # ITB inst accesses	159system.cpu.dtb.inst_accesses 0 # ITB inst accesses
160system.cpu.dtb.hits 26138774 # DTB hits 161system.cpu.dtb.misses 9487 # DTB misses 162system.cpu.dtb.accesses 26148261 # DTB accesses 163system.cpu.itb.inst_hits 60273909 # ITB inst hits	160system.cpu.dtb.hits 26188247 # DTB hits 161system.cpu.dtb.misses 9474 # DTB misses 162system.cpu.dtb.accesses 26197721 # DTB accesses 163system.cpu.itb.inst_hits 60403303 # ITB inst hits
164system.cpu.itb.inst_misses 4471 # ITB inst misses 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.write_hits 0 # DTB write hits 168system.cpu.itb.write_misses 0 # DTB write misses 169system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 170system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 171system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 172system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 173system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 174system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 175system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 176system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 177system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 178system.cpu.itb.read_accesses 0 # DTB read accesses 179system.cpu.itb.write_accesses 0 # DTB write accesses	164system.cpu.itb.inst_misses 4471 # ITB inst misses 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.write_hits 0 # DTB write hits 168system.cpu.itb.write_misses 0 # DTB write misses 169system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 170system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 171system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 172system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 173system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 174system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 175system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 176system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 177system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 178system.cpu.itb.read_accesses 0 # DTB read accesses 179system.cpu.itb.write_accesses 0 # DTB write accesses
180system.cpu.itb.inst_accesses 60278380 # ITB inst accesses 181system.cpu.itb.hits 60273909 # DTB hits	180system.cpu.itb.inst_accesses 60407774 # ITB inst accesses 181system.cpu.itb.hits 60403303 # DTB hits
182system.cpu.itb.misses 4471 # DTB misses	182system.cpu.itb.misses 4471 # DTB misses
183system.cpu.itb.accesses 60278380 # DTB accesses 184system.cpu.numCycles 4664556206 # number of cpu cycles simulated	183system.cpu.itb.accesses 60407774 # DTB accesses 184system.cpu.numCycles 4664583062 # number of cpu cycles simulated
185system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 186system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed	185system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 186system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
187system.cpu.committedInsts 59262896 # Number of instructions committed 188system.cpu.committedOps 76532951 # Number of ops (including micro ops) committed 189system.cpu.num_int_alu_accesses 68161195 # Number of integer alu accesses	187system.cpu.committedInsts 59392246 # Number of instructions committed 188system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed 189system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses
190system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses	190system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
191system.cpu.num_func_calls 1971944 # number of times a function call or return occured 192system.cpu.num_conditional_control_insts 7636089 # number of instructions that are conditional controls 193system.cpu.num_int_insts 68161195 # number of integer instructions	191system.cpu.num_func_calls 1972385 # number of times a function call or return occured 192system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls 193system.cpu.num_int_insts 68281415 # number of integer instructions
194system.cpu.num_fp_insts 10269 # number of float instructions	194system.cpu.num_fp_insts 10269 # number of float instructions
195system.cpu.num_int_register_reads 345365700 # number of times the integer registers were read 196system.cpu.num_int_register_writes 72877714 # number of times the integer registers were written	195system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read 196system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written
197system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 198system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written	197system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 198system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
199system.cpu.num_mem_refs 27310787 # number of memory refs 200system.cpu.num_load_insts 15607076 # Number of load instructions 201system.cpu.num_store_insts 11703711 # Number of store instructions 202system.cpu.num_idle_cycles 4586920130.978250 # Number of idle cycles 203system.cpu.num_busy_cycles 77636075.021750 # Number of busy cycles 204system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles 205system.cpu.idle_fraction 0.983356 # Percentage of idle cycles	199system.cpu.num_mem_refs 27361692 # number of memory refs 200system.cpu.num_load_insts 15639569 # Number of load instructions 201system.cpu.num_store_insts 11722123 # Number of store instructions 202system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles 203system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles 204system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles 205system.cpu.idle_fraction 0.983328 # Percentage of idle cycles