| stats.txt (8893:e29c604a2582) | stats.txt (8911:4da2ea94319f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332317 # Number of seconds simulated 4sim_ticks 2332316587000 # Number of ticks simulated 5final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332317 # Number of seconds simulated 4sim_ticks 2332316587000 # Number of ticks simulated 5final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1979884 # Simulator instruction rate (inst/s) 8host_op_rate 2556849 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 77919104565 # Simulator tick rate (ticks/s) 10host_mem_usage 379864 # Number of bytes of host memory used 11host_seconds 29.93 # Real time elapsed on the host 12sim_insts 59262876 # Number of instructions simulated 13sim_ops 76532931 # Number of ops (including micro ops) simulated | 7host_inst_rate 1994377 # Simulator instruction rate (inst/s) 8host_op_rate 2575566 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 78489486028 # Simulator tick rate (ticks/s) 10host_mem_usage 377288 # Number of bytes of host memory used 11host_seconds 29.72 # Real time elapsed on the host 12sim_insts 59262896 # Number of instructions simulated 13sim_ops 76532951 # Number of ops (including micro ops) simulated |
| 14system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 17system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory 18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 20system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) 21system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) --- 4 unchanged lines hidden (view full) --- 26system.physmem.num_reads 14137126 # Number of read requests responded to by this memory 27system.physmem.num_writes 856485 # Number of write requests responded to by this memory 28system.physmem.num_other 0 # Number of other requests responded to by this memory 29system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s) 33system.l2c.replacements 116822 # number of replacements | 14system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 16system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 17system.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory 18system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 19system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 20system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) 21system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) --- 4 unchanged lines hidden (view full) --- 26system.physmem.num_reads 14137126 # Number of read requests responded to by this memory 27system.physmem.num_writes 856485 # Number of write requests responded to by this memory 28system.physmem.num_other 0 # Number of other requests responded to by this memory 29system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s) 33system.l2c.replacements 116822 # number of replacements |
| 34system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use | 34system.l2c.tagsinuse 24240.388395 # Cycle average of tags in use |
| 35system.l2c.total_refs 1520830 # Total number of references to valid blocks. 36system.l2c.sampled_refs 146847 # Sample count of references to valid blocks. 37system.l2c.avg_refs 10.356562 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 35system.l2c.total_refs 1520830 # Total number of references to valid blocks. 36system.l2c.sampled_refs 146847 # Sample count of references to valid blocks. 37system.l2c.avg_refs 10.356562 # Average number of references to valid blocks. 38system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 39system.l2c.occ_blocks::writebacks 13639.466210 # Average occupied blocks per requestor | 39system.l2c.occ_blocks::writebacks 13639.466229 # Average occupied blocks per requestor |
| 40system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor 41system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor 42system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor | 40system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor 41system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor 42system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor |
| 43system.l2c.occ_blocks::cpu.data 5344.680069 # Average occupied blocks per requestor | 43system.l2c.occ_blocks::cpu.data 5344.680068 # Average occupied blocks per requestor |
| 44system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy 45system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy 46system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy 47system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy 48system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy 49system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy 50system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits 51system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits --- 84 unchanged lines hidden (view full) --- 136system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 137system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 138system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 139system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 140system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 141system.cf0.dma_write_txs 0 # Number of DMA write transactions. 142system.cpu.dtb.inst_hits 0 # ITB inst hits 143system.cpu.dtb.inst_misses 0 # ITB inst misses | 44system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy 45system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy 46system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy 47system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy 48system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy 49system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy 50system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits 51system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits --- 84 unchanged lines hidden (view full) --- 136system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 137system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 138system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 139system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 140system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 141system.cf0.dma_write_txs 0 # Number of DMA write transactions. 142system.cpu.dtb.inst_hits 0 # ITB inst hits 143system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 144system.cpu.dtb.read_hits 14940566 # DTB read hits | 144system.cpu.dtb.read_hits 14940568 # DTB read hits |
| 145system.cpu.dtb.read_misses 7288 # DTB read misses | 145system.cpu.dtb.read_misses 7288 # DTB read misses |
| 146system.cpu.dtb.write_hits 11198205 # DTB write hits | 146system.cpu.dtb.write_hits 11198206 # DTB write hits |
| 147system.cpu.dtb.write_misses 2199 # DTB write misses 148system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 149system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 151system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 152system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB 153system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 154system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch 155system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 156system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions | 147system.cpu.dtb.write_misses 2199 # DTB write misses 148system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 149system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 151system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 152system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB 153system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 154system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch 155system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 156system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions |
| 157system.cpu.dtb.read_accesses 14947854 # DTB read accesses 158system.cpu.dtb.write_accesses 11200404 # DTB write accesses | 157system.cpu.dtb.read_accesses 14947856 # DTB read accesses 158system.cpu.dtb.write_accesses 11200405 # DTB write accesses |
| 159system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 159system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 160system.cpu.dtb.hits 26138771 # DTB hits | 160system.cpu.dtb.hits 26138774 # DTB hits |
| 161system.cpu.dtb.misses 9487 # DTB misses | 161system.cpu.dtb.misses 9487 # DTB misses |
| 162system.cpu.dtb.accesses 26148258 # DTB accesses 163system.cpu.itb.inst_hits 60273889 # ITB inst hits | 162system.cpu.dtb.accesses 26148261 # DTB accesses 163system.cpu.itb.inst_hits 60273909 # ITB inst hits |
| 164system.cpu.itb.inst_misses 4471 # ITB inst misses 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.write_hits 0 # DTB write hits 168system.cpu.itb.write_misses 0 # DTB write misses 169system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 170system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 171system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 172system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 173system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 174system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 175system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 176system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 177system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 178system.cpu.itb.read_accesses 0 # DTB read accesses 179system.cpu.itb.write_accesses 0 # DTB write accesses | 164system.cpu.itb.inst_misses 4471 # ITB inst misses 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.write_hits 0 # DTB write hits 168system.cpu.itb.write_misses 0 # DTB write misses 169system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 170system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 171system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 172system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 173system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 174system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 175system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 176system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 177system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 178system.cpu.itb.read_accesses 0 # DTB read accesses 179system.cpu.itb.write_accesses 0 # DTB write accesses |
| 180system.cpu.itb.inst_accesses 60278360 # ITB inst accesses 181system.cpu.itb.hits 60273889 # DTB hits | 180system.cpu.itb.inst_accesses 60278380 # ITB inst accesses 181system.cpu.itb.hits 60273909 # DTB hits |
| 182system.cpu.itb.misses 4471 # DTB misses | 182system.cpu.itb.misses 4471 # DTB misses |
| 183system.cpu.itb.accesses 60278360 # DTB accesses | 183system.cpu.itb.accesses 60278380 # DTB accesses |
| 184system.cpu.numCycles 4664556206 # number of cpu cycles simulated 185system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 186system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 184system.cpu.numCycles 4664556206 # number of cpu cycles simulated 185system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 186system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 187system.cpu.committedInsts 59262876 # Number of instructions committed 188system.cpu.committedOps 76532931 # Number of ops (including micro ops) committed 189system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses | 187system.cpu.committedInsts 59262896 # Number of instructions committed 188system.cpu.committedOps 76532951 # Number of ops (including micro ops) committed 189system.cpu.num_int_alu_accesses 68161195 # Number of integer alu accesses |
| 190system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 191system.cpu.num_func_calls 1971944 # number of times a function call or return occured | 190system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 191system.cpu.num_func_calls 1971944 # number of times a function call or return occured |
| 192system.cpu.num_conditional_control_insts 7793824 # number of instructions that are conditional controls 193system.cpu.num_int_insts 68161177 # number of integer instructions | 192system.cpu.num_conditional_control_insts 7636089 # number of instructions that are conditional controls 193system.cpu.num_int_insts 68161195 # number of integer instructions |
| 194system.cpu.num_fp_insts 10269 # number of float instructions | 194system.cpu.num_fp_insts 10269 # number of float instructions |
| 195system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read 196system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written | 195system.cpu.num_int_register_reads 345365700 # number of times the integer registers were read 196system.cpu.num_int_register_writes 72877714 # number of times the integer registers were written |
| 197system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 198system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written | 197system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 198system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written |
| 199system.cpu.num_mem_refs 27310784 # number of memory refs 200system.cpu.num_load_insts 15607074 # Number of load instructions 201system.cpu.num_store_insts 11703710 # Number of store instructions 202system.cpu.num_idle_cycles 4586920150.977920 # Number of idle cycles 203system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles | 199system.cpu.num_mem_refs 27310787 # number of memory refs 200system.cpu.num_load_insts 15607076 # Number of load instructions 201system.cpu.num_store_insts 11703711 # Number of store instructions 202system.cpu.num_idle_cycles 4586920130.978250 # Number of idle cycles 203system.cpu.num_busy_cycles 77636075.021750 # Number of busy cycles |
| 204system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles 205system.cpu.idle_fraction 0.983356 # Percentage of idle cycles 206system.cpu.kern.inst.arm 0 # number of arm instructions executed 207system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed 208system.cpu.icache.replacements 847054 # number of replacements 209system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use | 204system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles 205system.cpu.idle_fraction 0.983356 # Percentage of idle cycles 206system.cpu.kern.inst.arm 0 # number of arm instructions executed 207system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed 208system.cpu.icache.replacements 847054 # number of replacements 209system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use |
| 210system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks. | 210system.cpu.icache.total_refs 59429103 # Total number of references to valid blocks. |
| 211system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks. | 211system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks. |
| 212system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks. 213system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit. | 212system.cpu.icache.avg_refs 70.117375 # Average number of references to valid blocks. 213system.cpu.icache.warmup_cycle 5705462000 # Cycle when the warmup percentage was hit. |
| 214system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor 215system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy 216system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy | 214system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor 215system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy 216system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy |
| 217system.cpu.icache.ReadReq_hits::cpu.inst 59429083 # number of ReadReq hits 218system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits 219system.cpu.icache.demand_hits::cpu.inst 59429083 # number of demand (read+write) hits 220system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits 221system.cpu.icache.overall_hits::cpu.inst 59429083 # number of overall hits 222system.cpu.icache.overall_hits::total 59429083 # number of overall hits | 217system.cpu.icache.ReadReq_hits::cpu.inst 59429103 # number of ReadReq hits 218system.cpu.icache.ReadReq_hits::total 59429103 # number of ReadReq hits 219system.cpu.icache.demand_hits::cpu.inst 59429103 # number of demand (read+write) hits 220system.cpu.icache.demand_hits::total 59429103 # number of demand (read+write) hits 221system.cpu.icache.overall_hits::cpu.inst 59429103 # number of overall hits 222system.cpu.icache.overall_hits::total 59429103 # number of overall hits |
| 223system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses 224system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses 225system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses 226system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses 227system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses 228system.cpu.icache.overall_misses::total 847566 # number of overall misses | 223system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses 224system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses 225system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses 226system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses 227system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses 228system.cpu.icache.overall_misses::total 847566 # number of overall misses |
| 229system.cpu.icache.ReadReq_accesses::cpu.inst 60276649 # number of ReadReq accesses(hits+misses) 230system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses) 231system.cpu.icache.demand_accesses::cpu.inst 60276649 # number of demand (read+write) accesses 232system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses 233system.cpu.icache.overall_accesses::cpu.inst 60276649 # number of overall (read+write) accesses 234system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses | 229system.cpu.icache.ReadReq_accesses::cpu.inst 60276669 # number of ReadReq accesses(hits+misses) 230system.cpu.icache.ReadReq_accesses::total 60276669 # number of ReadReq accesses(hits+misses) 231system.cpu.icache.demand_accesses::cpu.inst 60276669 # number of demand (read+write) accesses 232system.cpu.icache.demand_accesses::total 60276669 # number of demand (read+write) accesses 233system.cpu.icache.overall_accesses::cpu.inst 60276669 # number of overall (read+write) accesses 234system.cpu.icache.overall_accesses::total 60276669 # number of overall (read+write) accesses |
| 235system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses 236system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses 237system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses 238system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 239system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 240system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 241system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 242system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 243system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 244system.cpu.icache.fast_writes 0 # number of fast writes performed 245system.cpu.icache.cache_copies 0 # number of cache copies performed 246system.cpu.icache.writebacks::writebacks 44721 # number of writebacks 247system.cpu.icache.writebacks::total 44721 # number of writebacks 248system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 249system.cpu.dcache.replacements 622134 # number of replacements 250system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use | 235system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses 236system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses 237system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses 238system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 239system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 240system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 241system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 242system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 243system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 244system.cpu.icache.fast_writes 0 # number of fast writes performed 245system.cpu.icache.cache_copies 0 # number of cache copies performed 246system.cpu.icache.writebacks::writebacks 44721 # number of writebacks 247system.cpu.icache.writebacks::total 44721 # number of writebacks 248system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 249system.cpu.dcache.replacements 622134 # number of replacements 250system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use |
| 251system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks. | 251system.cpu.dcache.total_refs 23580072 # Total number of references to valid blocks. |
| 252system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks. | 252system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks. |
| 253system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks. | 253system.cpu.dcache.avg_refs 37.870752 # Average number of references to valid blocks. |
| 254system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. 255system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor 256system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 257system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy | 254system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. 255system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor 256system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 257system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy |
| 258system.cpu.dcache.ReadReq_hits::cpu.data 13150366 # number of ReadReq hits 259system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits 260system.cpu.dcache.WriteReq_hits::cpu.data 9943631 # number of WriteReq hits 261system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits | 258system.cpu.dcache.ReadReq_hits::cpu.data 13150368 # number of ReadReq hits 259system.cpu.dcache.ReadReq_hits::total 13150368 # number of ReadReq hits 260system.cpu.dcache.WriteReq_hits::cpu.data 9943632 # number of WriteReq hits 261system.cpu.dcache.WriteReq_hits::total 9943632 # number of WriteReq hits |
| 262system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits 263system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits 264system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits 265system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits | 262system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits 263system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits 264system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits 265system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits |
| 266system.cpu.dcache.demand_hits::cpu.data 23093997 # number of demand (read+write) hits 267system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits 268system.cpu.dcache.overall_hits::cpu.data 23093997 # number of overall hits 269system.cpu.dcache.overall_hits::total 23093997 # number of overall hits | 266system.cpu.dcache.demand_hits::cpu.data 23094000 # number of demand (read+write) hits 267system.cpu.dcache.demand_hits::total 23094000 # number of demand (read+write) hits 268system.cpu.dcache.overall_hits::cpu.data 23094000 # number of overall hits 269system.cpu.dcache.overall_hits::total 23094000 # number of overall hits |
| 270system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses 271system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses 272system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses 273system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses 274system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses 275system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses 276system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses 277system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses 278system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses 279system.cpu.dcache.overall_misses::total 614445 # number of overall misses | 270system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses 271system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses 272system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses 273system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses 274system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses 275system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses 276system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses 277system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses 278system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses 279system.cpu.dcache.overall_misses::total 614445 # number of overall misses |
| 280system.cpu.dcache.ReadReq_accesses::cpu.data 13514914 # number of ReadReq accesses(hits+misses) 281system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses) 282system.cpu.dcache.WriteReq_accesses::cpu.data 10193528 # number of WriteReq accesses(hits+misses) 283system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses) | 280system.cpu.dcache.ReadReq_accesses::cpu.data 13514916 # number of ReadReq accesses(hits+misses) 281system.cpu.dcache.ReadReq_accesses::total 13514916 # number of ReadReq accesses(hits+misses) 282system.cpu.dcache.WriteReq_accesses::cpu.data 10193529 # number of WriteReq accesses(hits+misses) 283system.cpu.dcache.WriteReq_accesses::total 10193529 # number of WriteReq accesses(hits+misses) |
| 284system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses) 285system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses) 286system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses) 287system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses) | 284system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses) 285system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses) 286system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses) 287system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses) |
| 288system.cpu.dcache.demand_accesses::cpu.data 23708442 # number of demand (read+write) accesses 289system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses 290system.cpu.dcache.overall_accesses::cpu.data 23708442 # number of overall (read+write) accesses 291system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses | 288system.cpu.dcache.demand_accesses::cpu.data 23708445 # number of demand (read+write) accesses 289system.cpu.dcache.demand_accesses::total 23708445 # number of demand (read+write) accesses 290system.cpu.dcache.overall_accesses::cpu.data 23708445 # number of overall (read+write) accesses 291system.cpu.dcache.overall_accesses::total 23708445 # number of overall (read+write) accesses |
| 292system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses 293system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses 294system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses 295system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses 296system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked --- 25 unchanged lines hidden --- | 292system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses 293system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses 294system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses 295system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses 296system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked --- 25 unchanged lines hidden --- |