Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 2.783855 # Number of seconds simulated
4sim_ticks 2783854715000 # Number of ticks simulated
5final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 2.783856 # Number of seconds simulated
4sim_ticks 2783855588000 # Number of ticks simulated
5final_tick 2783855588000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1570014 # Simulator instruction rate (inst/s)
8host_op_rate 1911240 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 30613244357 # Simulator tick rate (ticks/s)
10host_mem_usage 581428 # Number of bytes of host memory used
11host_seconds 90.94 # Real time elapsed on the host
12sim_insts 142771202 # Number of instructions simulated
13sim_ops 173801044 # Number of ops (including micro ops) simulated

7host_inst_rate 1539062 # Simulator instruction rate (inst/s)
8host_op_rate 1873561 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 30009675812 # Simulator tick rate (ticks/s)
10host_mem_usage 581968 # Number of bytes of host memory used
11host_seconds 92.77 # Real time elapsed on the host
12sim_insts 142771499 # Number of instructions simulated
13sim_ops 173801409 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory

20system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory

20system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory

21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory

22system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory

22system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory

23system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory
24system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory
25system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory
26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
27system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory
28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory

31system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory

31system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory

32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory

33system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory

33system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory

34system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory
35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
36system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory
37system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s)

40system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s)

40system.physmem.bw_read::cpu.data 3708849 # Total read bandwidth from this memory (bytes/s)

41system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)

42system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s)

42system.physmem.bw_read::total 4142976 # Total read bandwidth from this memory (bytes/s)

43system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s)

45system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s)

45system.physmem.bw_write::writebacks 3175774 # Write bandwidth from this memory (bytes/s)

46system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)

47system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s)
48system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s)

47system.physmem.bw_write::total 3182069 # Write bandwidth from this memory (bytes/s)
48system.physmem.bw_total::writebacks 3175774 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s)

52system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s)

52system.physmem.bw_total::cpu.data 3715144 # Total bandwidth to/from this memory (bytes/s)

53system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)

54system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s)
55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

54system.physmem.bw_total::total 7325045 # Total bandwidth to/from this memory (bytes/s)
55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

56system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
57system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
58system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
59system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
60system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
61system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
62system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
63system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
64system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
65system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
66system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
67system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)

68system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
69system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
70system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

68system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
69system.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
70system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

71system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
72system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
73system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
74system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
75system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
76system.cf0.dma_write_txs 631 # Number of DMA write transactions.
77system.cpu_clk_domain.clock 500 # Clock period in ticks

78system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

78system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

79system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
81system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
82system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
83system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

100system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
101system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
102system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
103system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
104system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
105system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
106system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
107system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

108system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

108system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

109system.cpu.dtb.walker.walks 10028 # Table walker walks requested
110system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors
111system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency
112system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency
113system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency
114system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
115system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
116system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution

--- 4 unchanged lines hidden (view full) ---

121system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
122system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst
123system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst
124system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
125system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst
126system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst
127system.cpu.dtb.inst_hits 0 # ITB inst hits
128system.cpu.dtb.inst_misses 0 # ITB inst misses

129system.cpu.dtb.read_hits 31525882 # DTB read hits

129system.cpu.dtb.read_hits 31525952 # DTB read hits

130system.cpu.dtb.read_misses 8580 # DTB read misses

131system.cpu.dtb.write_hits 23124079 # DTB write hits

131system.cpu.dtb.write_hits 23124113 # DTB write hits

132system.cpu.dtb.write_misses 1448 # DTB write misses
133system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
134system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
135system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
136system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
137system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB
138system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
139system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
140system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
141system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions

142system.cpu.dtb.read_accesses 31534462 # DTB read accesses
143system.cpu.dtb.write_accesses 23125527 # DTB write accesses

142system.cpu.dtb.read_accesses 31534532 # DTB read accesses
143system.cpu.dtb.write_accesses 23125561 # DTB write accesses

144system.cpu.dtb.inst_accesses 0 # ITB inst accesses

145system.cpu.dtb.hits 54649961 # DTB hits

145system.cpu.dtb.hits 54650065 # DTB hits

146system.cpu.dtb.misses 10028 # DTB misses

147system.cpu.dtb.accesses 54659989 # DTB accesses
148system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

147system.cpu.dtb.accesses 54660093 # DTB accesses
148system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

149system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
150system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
151system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
152system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
153system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

170system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
171system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
172system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
173system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
174system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
175system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
176system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
177system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

178system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

178system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

179system.cpu.itb.walker.walks 4762 # Table walker walks requested
180system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
181system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
182system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
183system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
184system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
185system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
186system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
187system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
188system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
189system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
190system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
191system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
192system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
193system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
194system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
195system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
196system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst

197system.cpu.itb.inst_hits 147037694 # ITB inst hits

197system.cpu.itb.inst_hits 147038008 # ITB inst hits

198system.cpu.itb.inst_misses 4762 # ITB inst misses
199system.cpu.itb.read_hits 0 # DTB read hits
200system.cpu.itb.read_misses 0 # DTB read misses
201system.cpu.itb.write_hits 0 # DTB write hits
202system.cpu.itb.write_misses 0 # DTB write misses
203system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
204system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
205system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
206system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
207system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
208system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
209system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
210system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
211system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
212system.cpu.itb.read_accesses 0 # DTB read accesses
213system.cpu.itb.write_accesses 0 # DTB write accesses

214system.cpu.itb.inst_accesses 147042456 # ITB inst accesses
215system.cpu.itb.hits 147037694 # DTB hits

214system.cpu.itb.inst_accesses 147042770 # ITB inst accesses
215system.cpu.itb.hits 147038008 # DTB hits

216system.cpu.itb.misses 4762 # DTB misses

217system.cpu.itb.accesses 147042456 # DTB accesses

217system.cpu.itb.accesses 147042770 # DTB accesses

218system.cpu.numPwrStateTransitions 6160 # Number of power state transitions
219system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state

220system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state
221system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state

220system.cpu.pwrStateClkGateDist::mean 874939855.098377 # Distribution of time spent in the clock gated state
221system.cpu.pwrStateClkGateDist::stdev 17329944394.226795 # Distribution of time spent in the clock gated state

222system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state
223system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state
224system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state
225system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state
226system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state
227system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state
228system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
229system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state
230system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state

231system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states
232system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states
233system.cpu.numCycles 5567712511 # number of cpu cycles simulated

231system.cpu.pwrStateResidencyTicks::ON 89040834297 # Cumulative time (in ticks) in various power states
232system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814753703 # Cumulative time (in ticks) in various power states
233system.cpu.numCycles 5567714257 # number of cpu cycles simulated

234system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
235system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
236system.cpu.kern.inst.arm 0 # number of arm instructions executed
237system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed

238system.cpu.committedInsts 142771202 # Number of instructions committed
239system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed
240system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses

238system.cpu.committedInsts 142771499 # Number of instructions committed
239system.cpu.committedOps 173801409 # Number of ops (including micro ops) committed
240system.cpu.num_int_alu_accesses 153161120 # Number of integer alu accesses

241system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses

242system.cpu.num_func_calls 16873864 # number of times a function call or return occured
243system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls
244system.cpu.num_int_insts 153160791 # number of integer instructions

242system.cpu.num_func_calls 16873932 # number of times a function call or return occured
243system.cpu.num_conditional_control_insts 18730256 # number of instructions that are conditional controls
244system.cpu.num_int_insts 153161120 # number of integer instructions

245system.cpu.num_fp_insts 11484 # number of float instructions

246system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read
247system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written

246system.cpu.num_int_register_reads 285043874 # number of times the integer registers were read
247system.cpu.num_int_register_writes 107178310 # number of times the integer registers were written

248system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
249system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written

250system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read
251system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written
252system.cpu.num_mem_refs 55938510 # number of memory refs
253system.cpu.num_load_insts 31855508 # Number of load instructions
254system.cpu.num_store_insts 24083002 # Number of store instructions
255system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles
256system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles

250system.cpu.num_cc_register_reads 530848973 # number of times the CC registers were read
251system.cpu.num_cc_register_writes 62363815 # number of times the CC registers were written
252system.cpu.num_mem_refs 55938612 # number of memory refs
253system.cpu.num_load_insts 31855576 # Number of load instructions
254system.cpu.num_store_insts 24083036 # Number of store instructions
255system.cpu.num_idle_cycles 5389632489.859149 # Number of idle cycles
256system.cpu.num_busy_cycles 178081767.140850 # Number of busy cycles

257system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
258system.cpu.idle_fraction 0.968015 # Percentage of idle cycles

259system.cpu.Branches 36396820 # Number of branches fetched

259system.cpu.Branches 36396926 # Number of branches fetched

260system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction

261system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction

261system.cpu.op_class::IntAlu 121151851 68.36% 68.36% # Class of executed instruction

262system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
263system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
264system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
265system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
266system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction
267system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction
268system.cpu.op_class::FloatMultAcc 0 0.00% 68.43% # Class of executed instruction
269system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction

--- 14 unchanged lines hidden (view full) ---

284system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction
285system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction
286system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction
287system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction
288system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction
289system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
290system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
291system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction

292system.cpu.op_class::MemRead 31852800 17.97% 86.41% # Class of executed instruction
293system.cpu.op_class::MemWrite 24074230 13.58% 99.99% # Class of executed instruction

292system.cpu.op_class::MemRead 31852868 17.97% 86.41% # Class of executed instruction
293system.cpu.op_class::MemWrite 24074264 13.58% 99.99% # Class of executed instruction

294system.cpu.op_class::FloatMemRead 2708 0.00% 100.00% # Class of executed instruction
295system.cpu.op_class::FloatMemWrite 8772 0.00% 100.00% # Class of executed instruction
296system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
297system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction

298system.cpu.op_class::total 177217860 # Class of executed instruction
299system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
300system.cpu.dcache.tags.replacements 819387 # number of replacements

298system.cpu.op_class::total 177218242 # Class of executed instruction
299system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
300system.cpu.dcache.tags.replacements 819384 # number of replacements

301system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use

302system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks.
303system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks.
304system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks.

302system.cpu.dcache.tags.total_refs 53783890 # Total number of references to valid blocks.
303system.cpu.dcache.tags.sampled_refs 819896 # Sample count of references to valid blocks.
304system.cpu.dcache.tags.avg_refs 65.598430 # Average number of references to valid blocks.

305system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
306system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
307system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
308system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
309system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
310system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
311system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
312system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
313system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

314system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses
315system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses
316system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
317system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits
318system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits
319system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits
320system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits

314system.cpu.dcache.tags.tag_accesses 219235120 # Number of tag accesses
315system.cpu.dcache.tags.data_accesses 219235120 # Number of data accesses
316system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
317system.cpu.dcache.ReadReq_hits::cpu.data 30128814 # number of ReadReq hits
318system.cpu.dcache.ReadReq_hits::total 30128814 # number of ReadReq hits
319system.cpu.dcache.WriteReq_hits::cpu.data 22339797 # number of WriteReq hits
320system.cpu.dcache.WriteReq_hits::total 22339797 # number of WriteReq hits

321system.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits
322system.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits
323system.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits
324system.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits
325system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
326system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits

327system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits
328system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits
329system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits
330system.cpu.dcache.overall_hits::total 52863571 # number of overall hits
331system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
332system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
333system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
334system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses

327system.cpu.dcache.demand_hits::cpu.data 52468611 # number of demand (read+write) hits
328system.cpu.dcache.demand_hits::total 52468611 # number of demand (read+write) hits
329system.cpu.dcache.overall_hits::cpu.data 52863678 # number of overall hits
330system.cpu.dcache.overall_hits::total 52863678 # number of overall hits
331system.cpu.dcache.ReadReq_misses::cpu.data 396270 # number of ReadReq misses
332system.cpu.dcache.ReadReq_misses::total 396270 # number of ReadReq misses
333system.cpu.dcache.WriteReq_misses::cpu.data 301666 # number of WriteReq misses
334system.cpu.dcache.WriteReq_misses::total 301666 # number of WriteReq misses

335system.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses
336system.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses
337system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
338system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
339system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
340system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses

341system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses
342system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses
343system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses
344system.cpu.dcache.overall_misses::total 814058 # number of overall misses
345system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses)
346system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses)
347system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses)
348system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses)

341system.cpu.dcache.demand_misses::cpu.data 697936 # number of demand (read+write) misses
342system.cpu.dcache.demand_misses::total 697936 # number of demand (read+write) misses
343system.cpu.dcache.overall_misses::cpu.data 814055 # number of overall misses
344system.cpu.dcache.overall_misses::total 814055 # number of overall misses
345system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses)
346system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses)
347system.cpu.dcache.WriteReq_accesses::cpu.data 22641463 # number of WriteReq accesses(hits+misses)
348system.cpu.dcache.WriteReq_accesses::total 22641463 # number of WriteReq accesses(hits+misses)

349system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
350system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
351system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
352system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
353system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
354system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)

355system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses
356system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses
357system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses
358system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses

355system.cpu.dcache.demand_accesses::cpu.data 53166547 # number of demand (read+write) accesses
356system.cpu.dcache.demand_accesses::total 53166547 # number of demand (read+write) accesses
357system.cpu.dcache.overall_accesses::cpu.data 53677733 # number of overall (read+write) accesses
358system.cpu.dcache.overall_accesses::total 53677733 # number of overall (read+write) accesses

359system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
360system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses

361system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
362system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses

361system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
362system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses

363system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227156 # miss rate for SoftPFReq accesses
364system.cpu.dcache.SoftPFReq_miss_rate::total 0.227156 # miss rate for SoftPFReq accesses
365system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018483 # miss rate for LoadLockedReq accesses
366system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018483 # miss rate for LoadLockedReq accesses
367system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
368system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
369system.cpu.dcache.demand_miss_rate::cpu.data 0.013127 # miss rate for demand accesses
370system.cpu.dcache.demand_miss_rate::total 0.013127 # miss rate for demand accesses
371system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
372system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
373system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
374system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
375system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
376system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
377system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
378system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

379system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks
380system.cpu.dcache.writebacks::total 682138 # number of writebacks
381system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
382system.cpu.icache.tags.replacements 1698988 # number of replacements

379system.cpu.dcache.writebacks::writebacks 682141 # number of writebacks
380system.cpu.dcache.writebacks::total 682141 # number of writebacks
381system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
382system.cpu.icache.tags.replacements 1698986 # number of replacements

383system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use

384system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks.
385system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks.
386system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks.

384system.cpu.icache.tags.total_refs 145341611 # Total number of references to valid blocks.
385system.cpu.icache.tags.sampled_refs 1699498 # Sample count of references to valid blocks.
386system.cpu.icache.tags.avg_refs 85.520319 # Average number of references to valid blocks.

387system.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit.
388system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
389system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
390system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
391system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
392system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
393system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
394system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
395system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
396system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

397system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses
398system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses
399system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
400system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits
401system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits
402system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits
403system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits
404system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits
405system.cpu.icache.overall_hits::total 145341295 # number of overall hits
406system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses
407system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses
408system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses
409system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses
410system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses
411system.cpu.icache.overall_misses::total 1699506 # number of overall misses
412system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses)
413system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses)
414system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses
415system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses
416system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses
417system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses

397system.cpu.icache.tags.tag_accesses 148740619 # Number of tag accesses
398system.cpu.icache.tags.data_accesses 148740619 # Number of data accesses
399system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
400system.cpu.icache.ReadReq_hits::cpu.inst 145341611 # number of ReadReq hits
401system.cpu.icache.ReadReq_hits::total 145341611 # number of ReadReq hits
402system.cpu.icache.demand_hits::cpu.inst 145341611 # number of demand (read+write) hits
403system.cpu.icache.demand_hits::total 145341611 # number of demand (read+write) hits
404system.cpu.icache.overall_hits::cpu.inst 145341611 # number of overall hits
405system.cpu.icache.overall_hits::total 145341611 # number of overall hits
406system.cpu.icache.ReadReq_misses::cpu.inst 1699504 # number of ReadReq misses
407system.cpu.icache.ReadReq_misses::total 1699504 # number of ReadReq misses
408system.cpu.icache.demand_misses::cpu.inst 1699504 # number of demand (read+write) misses
409system.cpu.icache.demand_misses::total 1699504 # number of demand (read+write) misses
410system.cpu.icache.overall_misses::cpu.inst 1699504 # number of overall misses
411system.cpu.icache.overall_misses::total 1699504 # number of overall misses
412system.cpu.icache.ReadReq_accesses::cpu.inst 147041115 # number of ReadReq accesses(hits+misses)
413system.cpu.icache.ReadReq_accesses::total 147041115 # number of ReadReq accesses(hits+misses)
414system.cpu.icache.demand_accesses::cpu.inst 147041115 # number of demand (read+write) accesses
415system.cpu.icache.demand_accesses::total 147041115 # number of demand (read+write) accesses
416system.cpu.icache.overall_accesses::cpu.inst 147041115 # number of overall (read+write) accesses
417system.cpu.icache.overall_accesses::total 147041115 # number of overall (read+write) accesses

418system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
419system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
420system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
421system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
422system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses
423system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
424system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
425system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
426system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
427system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
428system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
429system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

430system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks
431system.cpu.icache.writebacks::total 1698988 # number of writebacks
432system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
433system.cpu.l2cache.tags.replacements 109912 # number of replacements
434system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use
435system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks.
436system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks.
437system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks.

430system.cpu.icache.writebacks::writebacks 1698986 # number of writebacks
431system.cpu.icache.writebacks::total 1698986 # number of writebacks
432system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
433system.cpu.l2cache.tags.replacements 109914 # number of replacements
434system.cpu.l2cache.tags.tagsinuse 65246.862425 # Cycle average of tags in use
435system.cpu.l2cache.tags.total_refs 4827677 # Total number of references to valid blocks.
436system.cpu.l2cache.tags.sampled_refs 175340 # Sample count of references to valid blocks.
437system.cpu.l2cache.tags.avg_refs 27.533233 # Average number of references to valid blocks.

438system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit.
439system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor
440system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor

441system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor
442system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor

441system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.133245 # Average occupied blocks per requestor
442system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734054 # Average occupied blocks per requestor

443system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
444system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
445system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy
446system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy
447system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy
448system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
449system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id
450system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
451system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id
454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id
455system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
456system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id

457system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses
458system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses
459system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

457system.cpu.l2cache.tags.tag_accesses 40257153 # Number of tag accesses
458system.cpu.l2cache.tags.data_accesses 40257153 # Number of data accesses
459system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

460system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits
461system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits
462system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits

463system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits
464system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits
465system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits
466system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits

463system.cpu.l2cache.WritebackDirty_hits::writebacks 682141 # number of WritebackDirty hits
464system.cpu.l2cache.WritebackDirty_hits::total 682141 # number of WritebackDirty hits
465system.cpu.l2cache.WritebackClean_hits::writebacks 1666986 # number of WritebackClean hits
466system.cpu.l2cache.WritebackClean_hits::total 1666986 # number of WritebackClean hits

467system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits
468system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits

469system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits
470system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits
471system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits
472system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits
473system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits
474system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits

469system.cpu.l2cache.ReadExReq_hits::cpu.data 152792 # number of ReadExReq hits
470system.cpu.l2cache.ReadExReq_hits::total 152792 # number of ReadExReq hits
471system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681189 # number of ReadCleanReq hits
472system.cpu.l2cache.ReadCleanReq_hits::total 1681189 # number of ReadCleanReq hits
473system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505433 # number of ReadSharedReq hits
474system.cpu.l2cache.ReadSharedReq_hits::total 505433 # number of ReadSharedReq hits

475system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits
476system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits

477system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits
478system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits
479system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits

477system.cpu.l2cache.demand_hits::cpu.inst 1681189 # number of demand (read+write) hits
478system.cpu.l2cache.demand_hits::cpu.data 658225 # number of demand (read+write) hits
479system.cpu.l2cache.demand_hits::total 2347799 # number of demand (read+write) hits

480system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits
481system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits

482system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits
483system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits
484system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits

482system.cpu.l2cache.overall_hits::cpu.inst 1681189 # number of overall hits
483system.cpu.l2cache.overall_hits::cpu.data 658225 # number of overall hits
484system.cpu.l2cache.overall_hits::total 2347799 # number of overall hits

485system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
486system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
487system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses
488system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
489system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
490system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
491system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses

492system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses
493system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses

492system.cpu.l2cache.ReadExReq_misses::cpu.data 146119 # number of ReadExReq misses
493system.cpu.l2cache.ReadExReq_misses::total 146119 # number of ReadExReq misses

494system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses
495system.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses
496system.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses
497system.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses
498system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
499system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
500system.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses

501system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses
502system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses

501system.cpu.l2cache.demand_misses::cpu.data 161687 # number of demand (read+write) misses
502system.cpu.l2cache.demand_misses::total 179994 # number of demand (read+write) misses

503system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
504system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
505system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses

506system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses
507system.cpu.l2cache.overall_misses::total 179992 # number of overall misses

506system.cpu.l2cache.overall_misses::cpu.data 161687 # number of overall misses
507system.cpu.l2cache.overall_misses::total 179994 # number of overall misses

508system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses)
509system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses)
510system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses)

511system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses)
512system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses)
513system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses)
514system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses)

511system.cpu.l2cache.WritebackDirty_accesses::writebacks 682141 # number of WritebackDirty accesses(hits+misses)
512system.cpu.l2cache.WritebackDirty_accesses::total 682141 # number of WritebackDirty accesses(hits+misses)
513system.cpu.l2cache.WritebackClean_accesses::writebacks 1666986 # number of WritebackClean accesses(hits+misses)
514system.cpu.l2cache.WritebackClean_accesses::total 1666986 # number of WritebackClean accesses(hits+misses)

515system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses)
516system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses)
517system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
518system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)

519system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
520system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
521system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses)
522system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses)
523system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses)
524system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses)

519system.cpu.l2cache.ReadExReq_accesses::cpu.data 298911 # number of ReadExReq accesses(hits+misses)
520system.cpu.l2cache.ReadExReq_accesses::total 298911 # number of ReadExReq accesses(hits+misses)
521system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699487 # number of ReadCleanReq accesses(hits+misses)
522system.cpu.l2cache.ReadCleanReq_accesses::total 1699487 # number of ReadCleanReq accesses(hits+misses)
523system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521001 # number of ReadSharedReq accesses(hits+misses)
524system.cpu.l2cache.ReadSharedReq_accesses::total 521001 # number of ReadSharedReq accesses(hits+misses)

525system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses
526system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses

527system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses
528system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses
529system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses

527system.cpu.l2cache.demand_accesses::cpu.inst 1699487 # number of demand (read+write) accesses
528system.cpu.l2cache.demand_accesses::cpu.data 819912 # number of demand (read+write) accesses
529system.cpu.l2cache.demand_accesses::total 2527793 # number of demand (read+write) accesses

530system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses
531system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses

532system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses
533system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses
534system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses

532system.cpu.l2cache.overall_accesses::cpu.inst 1699487 # number of overall (read+write) accesses
533system.cpu.l2cache.overall_accesses::cpu.data 819912 # number of overall (read+write) accesses
534system.cpu.l2cache.overall_accesses::total 2527793 # number of overall (read+write) accesses

535system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses
536system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses
537system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses
538system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses
539system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses
540system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
541system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
542system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses
543system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses
544system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses
545system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses
546system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses
547system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses
548system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses
549system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses
550system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses

551system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses
552system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses

551system.cpu.l2cache.demand_miss_rate::cpu.data 0.197200 # miss rate for demand accesses
552system.cpu.l2cache.demand_miss_rate::total 0.071206 # miss rate for demand accesses

553system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses
554system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses
555system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses

556system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses
557system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses

556system.cpu.l2cache.overall_miss_rate::cpu.data 0.197200 # miss rate for overall accesses
557system.cpu.l2cache.overall_miss_rate::total 0.071206 # miss rate for overall accesses

558system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
559system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
560system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
561system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
562system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
563system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
564system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
565system.cpu.l2cache.writebacks::total 101949 # number of writebacks

566system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter.
567system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data.
568system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
569system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter.
570system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

566system.cpu.toL2Bus.snoop_filter.tot_requests 5059862 # Total number of requests made to the snoop filter.
567system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540459 # Number of requests hitting in the snoop filter with a single holder of the requested data.
568system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39267 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
569system.cpu.toL2Bus.snoop_filter.tot_snoops 427 # Total number of snoops made to the snoop filter.
570system.cpu.toL2Bus.snoop_filter.hit_single_snoops 427 # Number of snoops hitting in the snoop filter with a single holder of the requested data.

571system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

572system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

572system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

573system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution

574system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution

574system.cpu.toL2Bus.trans_dist::ReadResp 2288305 # Transaction distribution

575system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
576system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution

577system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution
578system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution
579system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution

577system.cpu.toL2Bus.trans_dist::WritebackDirty 682141 # Transaction distribution
578system.cpu.toL2Bus.trans_dist::WritebackClean 1698986 # Transaction distribution
579system.cpu.toL2Bus.trans_dist::CleanEvict 137243 # Transaction distribution

580system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
581system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
582system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution

583system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
584system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
585system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution
586system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
587system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes)
588system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes)

583system.cpu.toL2Bus.trans_dist::ReadExReq 298911 # Transaction distribution
584system.cpu.toL2Bus.trans_dist::ReadExResp 298911 # Transaction distribution
585system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699504 # Transaction distribution
586system.cpu.toL2Bus.trans_dist::ReadSharedReq 521001 # Transaction distribution
587system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116038 # Packet count per connected master and slave (bytes)
588system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581944 # Packet count per connected master and slave (bytes)

589system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
590system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)

591system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes)
592system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes)

591system.cpu.toL2Bus.pkt_count::total 7753408 # Packet count per connected master and slave (bytes)
592system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539448 # Cumulative packet size per connected master and slave (bytes)

593system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes)
594system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
595system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)

596system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes)
597system.cpu.toL2Bus.snoops 115326 # Total snoops (count)
598system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes)
599system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram
600system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram
601system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram

596system.cpu.toL2Bus.pkt_size::total 313964445 # Cumulative packet size per connected master and slave (bytes)
597system.cpu.toL2Bus.snoops 115353 # Total snoops (count)
598system.cpu.toL2Bus.snoopTraffic 6542464 # Total snoop traffic (bytes)
599system.cpu.toL2Bus.snoop_fanout::samples 5251071 # Request fanout histogram
600system.cpu.toL2Bus.snoop_fanout::mean 0.018719 # Request fanout histogram
601system.cpu.toL2Bus.snoop_fanout::stdev 0.135530 # Request fanout histogram

602system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

603system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram
604system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram

603system.cpu.toL2Bus.snoop_fanout::0 5152778 98.13% 98.13% # Request fanout histogram
604system.cpu.toL2Bus.snoop_fanout::1 98293 1.87% 100.00% # Request fanout histogram

605system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
606system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
607system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
608system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram

609system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram
610system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

609system.cpu.toL2Bus.snoop_fanout::total 5251071 # Request fanout histogram
610system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

611system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
612system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
613system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
614system.iobus.trans_dist::WriteResp 59002 # Transaction distribution
615system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
616system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
617system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
618system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)

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653system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
654system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
655system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
656system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
657system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
658system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
659system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
660system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)

661system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

661system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

662system.iocache.tags.replacements 36430 # number of replacements

663system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use

663system.iocache.tags.tagsinuse 0.909895 # Cycle average of tags in use

664system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
665system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
666system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
667system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit.

668system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor

668system.iocache.tags.occ_blocks::realview.ide 0.909895 # Average occupied blocks per requestor

669system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
670system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
671system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
672system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
673system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
674system.iocache.tags.tag_accesses 328176 # Number of tag accesses
675system.iocache.tags.data_accesses 328176 # Number of data accesses

676system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

676system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

677system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
678system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
679system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
680system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
681system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses
682system.iocache.demand_misses::total 36464 # number of demand (read+write) misses
683system.iocache.overall_misses::realview.ide 36464 # number of overall misses
684system.iocache.overall_misses::total 36464 # number of overall misses

--- 16 unchanged lines hidden (view full) ---

701system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
702system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
703system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
704system.iocache.blocked::no_targets 0 # number of cycles access was blocked
705system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
706system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
707system.iocache.writebacks::writebacks 36190 # number of writebacks
708system.iocache.writebacks::total 36190 # number of writebacks

709system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter.
710system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data.
711system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

709system.membus.snoop_filter.tot_requests 362813 # Total number of requests made to the snoop filter.
710system.membus.snoop_filter.hit_single_requests 151005 # Number of requests hitting in the snoop filter with a single holder of the requested data.
711system.membus.snoop_filter.hit_multi_requests 526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.

712system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
713system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
714system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

715system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

715system.membus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

716system.membus.trans_dist::ReadReq 40087 # Transaction distribution
717system.membus.trans_dist::ReadResp 74202 # Transaction distribution
718system.membus.trans_dist::WriteReq 27546 # Transaction distribution
719system.membus.trans_dist::WriteResp 27546 # Transaction distribution
720system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution

721system.membus.trans_dist::CleanEvict 8203 # Transaction distribution

721system.membus.trans_dist::CleanEvict 8205 # Transaction distribution

722system.membus.trans_dist::UpgradeReq 130 # Transaction distribution
723system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
724system.membus.trans_dist::UpgradeResp 132 # Transaction distribution

725system.membus.trans_dist::ReadExReq 145996 # Transaction distribution
726system.membus.trans_dist::ReadExResp 145996 # Transaction distribution

725system.membus.trans_dist::ReadExReq 145998 # Transaction distribution
726system.membus.trans_dist::ReadExResp 145998 # Transaction distribution

727system.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution
728system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
729system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
730system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
731system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
732system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)

733system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes)
734system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes)

733system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497830 # Packet count per connected master and slave (bytes)
734system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605190 # Packet count per connected master and slave (bytes)

735system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes)
736system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes)

737system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes)

737system.membus.pkt_count::total 714548 # Packet count per connected master and slave (bytes)

738system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
739system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
740system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)

741system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes)
742system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes)

741system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes)
742system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes)

743system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes)
744system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes)

745system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes)

745system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes)

746system.membus.snoops 0 # Total snoops (count)
747system.membus.snoopTraffic 0 # Total snoop traffic (bytes)

748system.membus.snoop_fanout::samples 430442 # Request fanout histogram
749system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram
750system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram

748system.membus.snoop_fanout::samples 430446 # Request fanout histogram
749system.membus.snoop_fanout::mean 0.012887 # Request fanout histogram
750system.membus.snoop_fanout::stdev 0.112786 # Request fanout histogram

751system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

752system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram
753system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram

752system.membus.snoop_fanout::0 424899 98.71% 98.71% # Request fanout histogram
753system.membus.snoop_fanout::1 5547 1.29% 100.00% # Request fanout histogram

754system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
755system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
756system.membus.snoop_fanout::min_value 0 # Request fanout histogram
757system.membus.snoop_fanout::max_value 1 # Request fanout histogram

758system.membus.snoop_fanout::total 430442 # Request fanout histogram
759system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
760system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
761system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
762system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
763system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
764system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
765system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

758system.membus.snoop_fanout::total 430446 # Request fanout histogram
759system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
760system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
761system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
762system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
763system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
764system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
765system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

766system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
767system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
768system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
769system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
770system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
771system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks

772system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
773system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

772system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
773system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

774system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
775system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
776system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
777system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
778system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
779system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
780system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
781system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU

--- 15 unchanged lines hidden (view full) ---

797system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
798system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
799system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
800system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
801system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
802system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
803system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
804system.realview.ethernet.droppedPackets 0 # number of packets dropped

805system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
806system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
807system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
808system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
809system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
810system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
811system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

805system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
806system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
807system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
808system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
809system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
810system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
811system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states

812system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
813system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
814system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
815system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks

816system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
817system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
818system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
819system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
820system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
821system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
822system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
823system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
824system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
825system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
826system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
827system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states

816system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
817system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
818system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
819system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
820system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
821system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
822system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
823system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
824system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
825system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
826system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states
827system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states