Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

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stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783855 # Number of seconds simulated 4sim_ticks 2783854535000 # Number of ticks simulated 5final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783855 # Number of seconds simulated 4sim_ticks 2783854535000 # Number of ticks simulated 5final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1429089 # Simulator instruction rate (inst/s) 8host_op_rate 1739687 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27865307050 # Simulator tick rate (ticks/s) 10host_mem_usage 619548 # Number of bytes of host memory used 11host_seconds 99.90 # Real time elapsed on the host	7host_inst_rate 972221 # Simulator instruction rate (inst/s) 8host_op_rate 1183523 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18956985191 # Simulator tick rate (ticks/s) 10host_mem_usage 578524 # Number of bytes of host memory used 11host_seconds 146.85 # Real time elapsed on the host
12sim_insts 142771651 # Number of instructions simulated 13sim_ops 173801592 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory --- 109 unchanged lines hidden (view full) --- 129system.cpu.dtb.read_hits 31525950 # DTB read hits 130system.cpu.dtb.read_misses 8580 # DTB read misses 131system.cpu.dtb.write_hits 23124105 # DTB write hits 132system.cpu.dtb.write_misses 1448 # DTB write misses 133system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 134system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 135system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 136system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	12sim_insts 142771651 # Number of instructions simulated 13sim_ops 173801592 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory --- 109 unchanged lines hidden (view full) --- 129system.cpu.dtb.read_hits 31525950 # DTB read hits 130system.cpu.dtb.read_misses 8580 # DTB read misses 131system.cpu.dtb.write_hits 23124105 # DTB write hits 132system.cpu.dtb.write_misses 1448 # DTB write misses 133system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 134system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 135system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 136system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
137system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB	137system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB
138system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 139system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 140system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 141system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 142system.cpu.dtb.read_accesses 31534530 # DTB read accesses 143system.cpu.dtb.write_accesses 23125553 # DTB write accesses 144system.cpu.dtb.inst_accesses 0 # ITB inst accesses 145system.cpu.dtb.hits 54650055 # DTB hits --- 53 unchanged lines hidden (view full) --- 199system.cpu.itb.read_hits 0 # DTB read hits 200system.cpu.itb.read_misses 0 # DTB read misses 201system.cpu.itb.write_hits 0 # DTB write hits 202system.cpu.itb.write_misses 0 # DTB write misses 203system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 204system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 205system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 206system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID	138system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 139system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 140system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 141system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 142system.cpu.dtb.read_accesses 31534530 # DTB read accesses 143system.cpu.dtb.write_accesses 23125553 # DTB write accesses 144system.cpu.dtb.inst_accesses 0 # ITB inst accesses 145system.cpu.dtb.hits 54650055 # DTB hits --- 53 unchanged lines hidden (view full) --- 199system.cpu.itb.read_hits 0 # DTB read hits 200system.cpu.itb.read_misses 0 # DTB read misses 201system.cpu.itb.write_hits 0 # DTB write hits 202system.cpu.itb.write_misses 0 # DTB write misses 203system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 204system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 205system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 206system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
207system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB	207system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB
208system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 209system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 210system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 211system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 212system.cpu.itb.read_accesses 0 # DTB read accesses 213system.cpu.itb.write_accesses 0 # DTB write accesses 214system.cpu.itb.inst_accesses 147042928 # ITB inst accesses 215system.cpu.itb.hits 147038166 # DTB hits --- 605 unchanged lines hidden ---	208system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 209system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 210system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 211system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 212system.cpu.itb.read_accesses 0 # DTB read accesses 213system.cpu.itb.write_accesses 0 # DTB write accesses 214system.cpu.itb.inst_accesses 147042928 # ITB inst accesses 215system.cpu.itb.hits 147038166 # DTB hits --- 605 unchanged lines hidden ---