| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783855 # Number of seconds simulated 4sim_ticks 2783854535000 # Number of ticks simulated 5final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783855 # Number of seconds simulated 4sim_ticks 2783854535000 # Number of ticks simulated 5final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1638061 # Simulator instruction rate (inst/s) 8host_op_rate 1994077 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 31939974807 # Simulator tick rate (ticks/s) 10host_mem_usage 619068 # Number of bytes of host memory used 11host_seconds 87.16 # Real time elapsed on the host | 7host_inst_rate 1429089 # Simulator instruction rate (inst/s) 8host_op_rate 1739687 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27865307050 # Simulator tick rate (ticks/s) 10host_mem_usage 619548 # Number of bytes of host memory used 11host_seconds 99.90 # Real time elapsed on the host |
| 12sim_insts 142771651 # Number of instructions simulated 13sim_ops 173801592 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 142771651 # Number of instructions simulated 13sim_ops 173801592 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10324836 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory --- 22 unchanged lines hidden (view full) --- 46system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10324836 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory --- 22 unchanged lines hidden (view full) --- 47system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s) |
| 55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 54system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 55system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 56system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 57system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 58system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 59system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 60system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 65system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) | 56system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 57system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 58system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 59system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 60system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 61system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 62system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 67system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) |
| 68system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 69system.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 70system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 66system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 67system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 68system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 69system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 70system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 71system.cf0.dma_write_txs 631 # Number of DMA write transactions. 72system.cpu_clk_domain.clock 500 # Clock period in ticks | 71system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 72system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 73system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 74system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 75system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 76system.cf0.dma_write_txs 631 # Number of DMA write transactions. 77system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 78system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 73system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 74system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 94system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 97system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 98system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 99system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 100system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 101system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 79system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 81system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 82system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 83system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 100system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 101system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 102system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 103system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 104system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 105system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 106system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 107system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 108system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 102system.cpu.dtb.walker.walks 10028 # Table walker walks requested 103system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors 104system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency 105system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency 106system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency 107system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 108system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 109system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 133system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 134system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 135system.cpu.dtb.read_accesses 31534530 # DTB read accesses 136system.cpu.dtb.write_accesses 23125553 # DTB write accesses 137system.cpu.dtb.inst_accesses 0 # ITB inst accesses 138system.cpu.dtb.hits 54650055 # DTB hits 139system.cpu.dtb.misses 10028 # DTB misses 140system.cpu.dtb.accesses 54660083 # DTB accesses | 109system.cpu.dtb.walker.walks 10028 # Table walker walks requested 110system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors 111system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency 112system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency 113system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency 114system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 115system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 116system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 140system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 141system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 142system.cpu.dtb.read_accesses 31534530 # DTB read accesses 143system.cpu.dtb.write_accesses 23125553 # DTB write accesses 144system.cpu.dtb.inst_accesses 0 # ITB inst accesses 145system.cpu.dtb.hits 54650055 # DTB hits 146system.cpu.dtb.misses 10028 # DTB misses 147system.cpu.dtb.accesses 54660083 # DTB accesses |
| 148system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 141system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 142system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 143system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 145system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 162system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 163system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 164system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 165system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 166system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 167system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 168system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 169system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 149system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 150system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 151system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 152system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 153system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 170system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 171system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 172system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 173system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 174system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 175system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 176system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 177system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 178system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 170system.cpu.itb.walker.walks 4762 # Table walker walks requested 171system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 172system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 173system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 174system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 175system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 176system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 177system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 201system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 202system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 203system.cpu.itb.read_accesses 0 # DTB read accesses 204system.cpu.itb.write_accesses 0 # DTB write accesses 205system.cpu.itb.inst_accesses 147042928 # ITB inst accesses 206system.cpu.itb.hits 147038166 # DTB hits 207system.cpu.itb.misses 4762 # DTB misses 208system.cpu.itb.accesses 147042928 # DTB accesses | 179system.cpu.itb.walker.walks 4762 # Table walker walks requested 180system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 181system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 182system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 183system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 184system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 185system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 186system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 210system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 211system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 212system.cpu.itb.read_accesses 0 # DTB read accesses 213system.cpu.itb.write_accesses 0 # DTB write accesses 214system.cpu.itb.inst_accesses 147042928 # ITB inst accesses 215system.cpu.itb.hits 147038166 # DTB hits 216system.cpu.itb.misses 4762 # DTB misses 217system.cpu.itb.accesses 147042928 # DTB accesses |
| 218system.cpu.numPwrStateTransitions 6160 # Number of power state transitions 219system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state 220system.cpu.pwrStateClkGateDist::mean 874939482.384091 # Distribution of time spent in the clock gated state 221system.cpu.pwrStateClkGateDist::stdev 17329944773.080986 # Distribution of time spent in the clock gated state 222system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state 223system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state 224system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 225system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 226system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 227system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 228system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 229system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state 230system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state 231system.cpu.pwrStateResidencyTicks::ON 89040929257 # Cumulative time (in ticks) in various power states 232system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813605743 # Cumulative time (in ticks) in various power states |
|
| 209system.cpu.numCycles 5567712151 # number of cpu cycles simulated 210system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 211system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 212system.cpu.kern.inst.arm 0 # number of arm instructions executed 213system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 214system.cpu.committedInsts 142771651 # Number of instructions committed 215system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed 216system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 263system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 264system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 265system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 266system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction 267system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction 268system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 269system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 270system.cpu.op_class::total 177218432 # Class of executed instruction | 233system.cpu.numCycles 5567712151 # number of cpu cycles simulated 234system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 235system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 236system.cpu.kern.inst.arm 0 # number of arm instructions executed 237system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 238system.cpu.committedInsts 142771651 # Number of instructions committed 239system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed 240system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 287system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 288system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 289system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 290system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction 291system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction 292system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 293system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 294system.cpu.op_class::total 177218432 # Class of executed instruction |
| 295system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 271system.cpu.dcache.tags.replacements 819392 # number of replacements 272system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 273system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks. 274system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. 275system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks. 276system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 277system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 278system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 279system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 280system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 281system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 282system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 283system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 284system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 285system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses 286system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses | 296system.cpu.dcache.tags.replacements 819392 # number of replacements 297system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 298system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks. 299system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. 300system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks. 301system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 302system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 303system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 304system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 305system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 306system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 307system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 308system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 309system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 310system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses 311system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses |
| 312system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 287system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits 288system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits 289system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits 290system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits 291system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits 292system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits 293system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits 294system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits --- 48 unchanged lines hidden (view full) --- 343system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 344system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 345system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 346system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 347system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 348system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 349system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks 350system.cpu.dcache.writebacks::total 682017 # number of writebacks | 313system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits 314system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits 315system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits 316system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits 317system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits 318system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits 319system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits 320system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits --- 48 unchanged lines hidden (view full) --- 369system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 370system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 371system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 372system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 373system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 374system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 375system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks 376system.cpu.dcache.writebacks::total 682017 # number of writebacks |
| 377system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 351system.cpu.icache.tags.replacements 1698998 # number of replacements 352system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use 353system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. 354system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. 355system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. 356system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. 357system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor 358system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 359system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 360system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 362system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 365system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 366system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses 367system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses | 378system.cpu.icache.tags.replacements 1698998 # number of replacements 379system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use 380system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. 381system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. 382system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. 383system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. 384system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor 385system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 386system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 387system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 388system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 389system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 390system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 391system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 392system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 393system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses 394system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses |
| 395system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 368system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits 369system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits 370system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits 371system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits 372system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits 373system.cpu.icache.overall_hits::total 145341757 # number of overall hits 374system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses 375system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 392system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 393system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 394system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 397system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 398system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks 399system.cpu.icache.writebacks::total 1698998 # number of writebacks | 396system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits 397system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits 398system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits 399system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits 400system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits 401system.cpu.icache.overall_hits::total 145341757 # number of overall hits 402system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses 403system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 420system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 421system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 422system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 423system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 424system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 425system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 426system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks 427system.cpu.icache.writebacks::total 1698998 # number of writebacks |
| 428system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 400system.cpu.l2cache.tags.replacements 109913 # number of replacements 401system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use 402system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. 403system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. 404system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks. 405system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 406system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor 407system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 421system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 422system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id 423system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id 424system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id 425system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 426system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id 427system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses 428system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses | 429system.cpu.l2cache.tags.replacements 109913 # number of replacements 430system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use 431system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. 432system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. 433system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks. 434system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 435system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor 436system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor --- 13 unchanged lines hidden (view full) --- 450system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 451system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id 452system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id 454system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id 456system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses 457system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses |
| 458system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 429system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits 430system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits 431system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits 432system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits 433system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits 434system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits 435system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits 436system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits --- 96 unchanged lines hidden (view full) --- 533system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks 534system.cpu.l2cache.writebacks::total 101950 # number of writebacks 535system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. 536system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. 537system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 538system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. 539system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 540system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 459system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits 460system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits 461system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits 462system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits 463system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits 464system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits 465system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits 466system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits --- 96 unchanged lines hidden (view full) --- 563system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks 564system.cpu.l2cache.writebacks::total 101950 # number of writebacks 565system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. 566system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. 567system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 568system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. 569system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 570system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 571system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 541system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution 542system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution 543system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution 544system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution 545system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution 546system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution 547system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution 548system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution --- 20 unchanged lines hidden (view full) --- 569system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 570system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram 571system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram 572system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 573system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 574system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 575system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 576system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram | 572system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution 573system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution 578system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution 579system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution --- 20 unchanged lines hidden (view full) --- 600system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 601system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram 602system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram 603system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 604system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 605system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 606system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 607system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram |
| 608system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 577system.iobus.trans_dist::ReadReq 30164 # Transaction distribution 578system.iobus.trans_dist::ReadResp 30164 # Transaction distribution 579system.iobus.trans_dist::WriteReq 59002 # Transaction distribution 580system.iobus.trans_dist::WriteResp 59002 # Transaction distribution 581system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) 582system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 583system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 584system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 619system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 620system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 621system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 622system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 623system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) | 609system.iobus.trans_dist::ReadReq 30164 # Transaction distribution 610system.iobus.trans_dist::ReadResp 30164 # Transaction distribution 611system.iobus.trans_dist::WriteReq 59002 # Transaction distribution 612system.iobus.trans_dist::WriteResp 59002 # Transaction distribution 613system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) 614system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 615system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 616system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 651system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 652system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 653system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 654system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 655system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) 656system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 657system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 658system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) |
| 659system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 627system.iocache.tags.replacements 36430 # number of replacements 628system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use 629system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 630system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 631system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 632system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. 633system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor 634system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy 635system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy 636system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 637system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 638system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 639system.iocache.tags.tag_accesses 328176 # Number of tag accesses 640system.iocache.tags.data_accesses 328176 # Number of data accesses | 660system.iocache.tags.replacements 36430 # number of replacements 661system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use 662system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 663system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 664system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 665system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. 666system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor 667system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy 668system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy 669system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 670system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 671system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 672system.iocache.tags.tag_accesses 328176 # Number of tag accesses 673system.iocache.tags.data_accesses 328176 # Number of data accesses |
| 674system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 641system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 642system.iocache.ReadReq_misses::total 240 # number of ReadReq misses 643system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 644system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 645system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses 646system.iocache.demand_misses::total 36464 # number of demand (read+write) misses 647system.iocache.overall_misses::realview.ide 36464 # number of overall misses 648system.iocache.overall_misses::total 36464 # number of overall misses --- 16 unchanged lines hidden (view full) --- 665system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 666system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 667system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 668system.iocache.blocked::no_targets 0 # number of cycles access was blocked 669system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 670system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 671system.iocache.writebacks::writebacks 36190 # number of writebacks 672system.iocache.writebacks::total 36190 # number of writebacks | 675system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 676system.iocache.ReadReq_misses::total 240 # number of ReadReq misses 677system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 678system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 679system.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses 680system.iocache.demand_misses::total 36464 # number of demand (read+write) misses 681system.iocache.overall_misses::realview.ide 36464 # number of overall misses 682system.iocache.overall_misses::total 36464 # number of overall misses --- 16 unchanged lines hidden (view full) --- 699system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 700system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 701system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 702system.iocache.blocked::no_targets 0 # number of cycles access was blocked 703system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 704system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 705system.iocache.writebacks::writebacks 36190 # number of writebacks 706system.iocache.writebacks::total 36190 # number of writebacks |
| 707system.membus.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 673system.membus.trans_dist::ReadReq 40087 # Transaction distribution 674system.membus.trans_dist::ReadResp 74202 # Transaction distribution 675system.membus.trans_dist::WriteReq 27546 # Transaction distribution 676system.membus.trans_dist::WriteResp 27546 # Transaction distribution 677system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution 678system.membus.trans_dist::CleanEvict 8203 # Transaction distribution 679system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 680system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 26 unchanged lines hidden (view full) --- 707system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 708system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 709system.membus.snoop_fanout::1 434821 100.00% 100.00% # Request fanout histogram 710system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 711system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 712system.membus.snoop_fanout::min_value 1 # Request fanout histogram 713system.membus.snoop_fanout::max_value 1 # Request fanout histogram 714system.membus.snoop_fanout::total 434821 # Request fanout histogram | 708system.membus.trans_dist::ReadReq 40087 # Transaction distribution 709system.membus.trans_dist::ReadResp 74202 # Transaction distribution 710system.membus.trans_dist::WriteReq 27546 # Transaction distribution 711system.membus.trans_dist::WriteResp 27546 # Transaction distribution 712system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution 713system.membus.trans_dist::CleanEvict 8203 # Transaction distribution 714system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 715system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution --- 26 unchanged lines hidden (view full) --- 742system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 743system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 744system.membus.snoop_fanout::1 434821 100.00% 100.00% # Request fanout histogram 745system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 746system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 747system.membus.snoop_fanout::min_value 1 # Request fanout histogram 748system.membus.snoop_fanout::max_value 1 # Request fanout histogram 749system.membus.snoop_fanout::total 434821 # Request fanout histogram |
| 750system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 751system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 752system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 753system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 754system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 755system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 756system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 715system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 716system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 717system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 718system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 719system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 720system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 757system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 758system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 759system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 760system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 761system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 762system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 763system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 764system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 721system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 722system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 723system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 724system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 725system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 726system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 727system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 728system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 744system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 745system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 746system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 747system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 748system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 749system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 750system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 751system.realview.ethernet.droppedPackets 0 # number of packets dropped | 765system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 766system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 767system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 768system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 769system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 770system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 771system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 772system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 788system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 789system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 790system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 791system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 792system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 793system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 794system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 795system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 796system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 797system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 798system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 799system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 800system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 801system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 802system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 752system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 753system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 754system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 755system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 803system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 804system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 805system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 806system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 807system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 808system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 809system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 810system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 811system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 812system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 813system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 814system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 815system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 816system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 817system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states 818system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854535000 # Cumulative time (in ticks) in various power states |
|
| 756 757---------- End Simulation Statistics ---------- | 819 820---------- End Simulation Statistics ---------- |