| stats.txt (11502:e273e86a873d) | stats.txt (11507:be6065c1d8d2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783855 # Number of seconds simulated 4sim_ticks 2783854535000 # Number of ticks simulated 5final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783855 # Number of seconds simulated 4sim_ticks 2783854535000 # Number of ticks simulated 5final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 888036 # Simulator instruction rate (inst/s) 8host_op_rate 1081042 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 17315504636 # Simulator tick rate (ticks/s) 10host_mem_usage 573724 # Number of bytes of host memory used 11host_seconds 160.77 # Real time elapsed on the host | 7host_inst_rate 766060 # Simulator instruction rate (inst/s) 8host_op_rate 932555 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14937129777 # Simulator tick rate (ticks/s) 10host_mem_usage 573732 # Number of bytes of host memory used 11host_seconds 186.37 # Real time elapsed on the host |
| 12sim_insts 142771651 # Number of instructions simulated 13sim_ops 173801592 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10324836 # Number of bytes read from this memory --- 94 unchanged lines hidden (view full) --- 114system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 115system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst 116system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst 117system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 118system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst 119system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst 120system.cpu.dtb.inst_hits 0 # ITB inst hits 121system.cpu.dtb.inst_misses 0 # ITB inst misses | 12sim_insts 142771651 # Number of instructions simulated 13sim_ops 173801592 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10324836 # Number of bytes read from this memory --- 94 unchanged lines hidden (view full) --- 114system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 115system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst 116system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst 117system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 118system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst 119system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst 120system.cpu.dtb.inst_hits 0 # ITB inst hits 121system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 122system.cpu.dtb.read_hits 31525949 # DTB read hits | 122system.cpu.dtb.read_hits 31525950 # DTB read hits |
| 123system.cpu.dtb.read_misses 8580 # DTB read misses | 123system.cpu.dtb.read_misses 8580 # DTB read misses |
| 124system.cpu.dtb.write_hits 23124104 # DTB write hits | 124system.cpu.dtb.write_hits 23124105 # DTB write hits |
| 125system.cpu.dtb.write_misses 1448 # DTB write misses 126system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 127system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 128system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 129system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 130system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 131system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 132system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 133system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 134system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions | 125system.cpu.dtb.write_misses 1448 # DTB write misses 126system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 127system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 128system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 129system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 130system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 131system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 132system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 133system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 134system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions |
| 135system.cpu.dtb.read_accesses 31534529 # DTB read accesses 136system.cpu.dtb.write_accesses 23125552 # DTB write accesses | 135system.cpu.dtb.read_accesses 31534530 # DTB read accesses 136system.cpu.dtb.write_accesses 23125553 # DTB write accesses |
| 137system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 137system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 138system.cpu.dtb.hits 54650053 # DTB hits | 138system.cpu.dtb.hits 54650055 # DTB hits |
| 139system.cpu.dtb.misses 10028 # DTB misses | 139system.cpu.dtb.misses 10028 # DTB misses |
| 140system.cpu.dtb.accesses 54660081 # DTB accesses | 140system.cpu.dtb.accesses 54660083 # DTB accesses |
| 141system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 142system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 143system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 145system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 66 unchanged lines hidden (view full) --- 215system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed 216system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses 217system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 218system.cpu.num_func_calls 16873962 # number of times a function call or return occured 219system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls 220system.cpu.num_int_insts 153161279 # number of integer instructions 221system.cpu.num_fp_insts 11484 # number of float instructions 222system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read | 141system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 142system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 143system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 145system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 66 unchanged lines hidden (view full) --- 215system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed 216system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses 217system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 218system.cpu.num_func_calls 16873962 # number of times a function call or return occured 219system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls 220system.cpu.num_int_insts 153161279 # number of integer instructions 221system.cpu.num_fp_insts 11484 # number of float instructions 222system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read |
| 223system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written | 223system.cpu.num_int_register_writes 107178468 # number of times the integer registers were written |
| 224system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 225system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 226system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read 227system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written 228system.cpu.num_mem_refs 55938616 # number of memory refs 229system.cpu.num_load_insts 31855585 # Number of load instructions 230system.cpu.num_store_insts 24083031 # Number of store instructions 231system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles --- 33 unchanged lines hidden (view full) --- 265system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 266system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction 267system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction 268system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 269system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 270system.cpu.op_class::total 177218432 # Class of executed instruction 271system.cpu.dcache.tags.replacements 819392 # number of replacements 272system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use | 224system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 225system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 226system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read 227system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written 228system.cpu.num_mem_refs 55938616 # number of memory refs 229system.cpu.num_load_insts 31855585 # Number of load instructions 230system.cpu.num_store_insts 24083031 # Number of store instructions 231system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles --- 33 unchanged lines hidden (view full) --- 265system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 266system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction 267system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction 268system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 269system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 270system.cpu.op_class::total 177218432 # Class of executed instruction 271system.cpu.dcache.tags.replacements 819392 # number of replacements 272system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use |
| 273system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. | 273system.cpu.dcache.tags.total_refs 53783872 # Total number of references to valid blocks. |
| 274system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. | 274system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. |
| 275system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. | 275system.cpu.dcache.tags.avg_refs 65.597768 # Average number of references to valid blocks. |
| 276system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 277system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 278system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 279system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 280system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 281system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 282system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 283system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 284system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 276system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 277system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 278system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 279system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 280system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 281system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 282system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 283system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 284system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 285system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses 286system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses 287system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits 288system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits 289system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits 290system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits | 285system.cpu.dcache.tags.tag_accesses 219235088 # Number of tag accesses 286system.cpu.dcache.tags.data_accesses 219235088 # Number of data accesses 287system.cpu.dcache.ReadReq_hits::cpu.data 30128801 # number of ReadReq hits 288system.cpu.dcache.ReadReq_hits::total 30128801 # number of ReadReq hits 289system.cpu.dcache.WriteReq_hits::cpu.data 22339792 # number of WriteReq hits 290system.cpu.dcache.WriteReq_hits::total 22339792 # number of WriteReq hits |
| 291system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits 292system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits 293system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits 294system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits 295system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits 296system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits | 291system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits 292system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits 293system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits 294system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits 295system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits 296system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits |
| 297system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits 298system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits 299system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits 300system.cpu.dcache.overall_hits::total 52863656 # number of overall hits | 297system.cpu.dcache.demand_hits::cpu.data 52468593 # number of demand (read+write) hits 298system.cpu.dcache.demand_hits::total 52468593 # number of demand (read+write) hits 299system.cpu.dcache.overall_hits::cpu.data 52863658 # number of overall hits 300system.cpu.dcache.overall_hits::total 52863658 # number of overall hits |
| 301system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses 302system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses 303system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses 304system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses 305system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses 306system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses 307system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses 308system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses 309system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 310system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 311system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses 312system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses 313system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses 314system.cpu.dcache.overall_misses::total 814065 # number of overall misses | 301system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses 302system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses 303system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses 304system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses 305system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses 306system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses 307system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses 308system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses 309system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 310system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 311system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses 312system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses 313system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses 314system.cpu.dcache.overall_misses::total 814065 # number of overall misses |
| 315system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) 316system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) 317system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) 318system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) | 315system.cpu.dcache.ReadReq_accesses::cpu.data 30525082 # number of ReadReq accesses(hits+misses) 316system.cpu.dcache.ReadReq_accesses::total 30525082 # number of ReadReq accesses(hits+misses) 317system.cpu.dcache.WriteReq_accesses::cpu.data 22641455 # number of WriteReq accesses(hits+misses) 318system.cpu.dcache.WriteReq_accesses::total 22641455 # number of WriteReq accesses(hits+misses) |
| 319system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) 320system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) 321system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) 322system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) 323system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) 324system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) | 319system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) 320system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) 321system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) 322system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) 323system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) 324system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) |
| 325system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses 326system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses 327system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses 328system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses | 325system.cpu.dcache.demand_accesses::cpu.data 53166537 # number of demand (read+write) accesses 326system.cpu.dcache.demand_accesses::total 53166537 # number of demand (read+write) accesses 327system.cpu.dcache.overall_accesses::cpu.data 53677723 # number of overall (read+write) accesses 328system.cpu.dcache.overall_accesses::total 53677723 # number of overall (read+write) accesses |
| 329system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 330system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 331system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses 332system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses 333system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses 334system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses 335system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses 336system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses --- 421 unchanged lines hidden --- | 329system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 330system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 331system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses 332system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses 333system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses 334system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses 335system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses 336system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses --- 421 unchanged lines hidden --- |