| stats.txt (10585:1c9d5d9417b3) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783867 # Number of seconds simulated 4sim_ticks 2783867165000 # Number of ticks simulated 5final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783867 # Number of seconds simulated 4sim_ticks 2783867165000 # Number of ticks simulated 5final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1064003 # Simulator instruction rate (inst/s) 8host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20746494205 # Simulator tick rate (ticks/s) 10host_mem_usage 558936 # Number of bytes of host memory used 11host_seconds 134.19 # Real time elapsed on the host | 7host_inst_rate 1374338 # Simulator instruction rate (inst/s) 8host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26797569978 # Simulator tick rate (ticks/s) 10host_mem_usage 615488 # Number of bytes of host memory used 11host_seconds 103.89 # Real time elapsed on the host |
| 12sim_insts 142773109 # Number of instructions simulated 13sim_ops 173803334 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory --- 45 unchanged lines hidden (view full) --- 65system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 66system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 67system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 68system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 69system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 70system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 71system.cf0.dma_write_txs 631 # Number of DMA write transactions. 72system.cpu_clk_domain.clock 500 # Clock period in ticks | 12sim_insts 142773109 # Number of instructions simulated 13sim_ops 173803334 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory --- 45 unchanged lines hidden (view full) --- 65system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 66system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 67system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 68system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 69system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 70system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 71system.cf0.dma_write_txs 631 # Number of DMA write transactions. 72system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 73system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 74system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 75system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 76system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 78system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 79system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 73system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 74system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 75system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 76system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 77system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 78system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 79system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 80system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 86system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 87system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 88system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 89system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 90system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 91system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 92system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 93system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 81system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 82system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 83system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 84system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 85system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 86system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 87system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 88system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 94system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 95system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 96system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 97system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 98system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 99system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 100system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 101system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 102system.cpu.dtb.walker.walks 10029 # Table walker walks requested 103system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors 104system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency 105system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency 106system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency 107system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 108system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 109system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 110system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated 111system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated 112system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated 113system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst 114system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 115system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst 116system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst 117system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 118system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst 119system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst |
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| 94system.cpu.dtb.inst_hits 0 # ITB inst hits 95system.cpu.dtb.inst_misses 0 # ITB inst misses 96system.cpu.dtb.read_hits 31526301 # DTB read hits 97system.cpu.dtb.read_misses 8581 # DTB read misses 98system.cpu.dtb.write_hits 23124463 # DTB write hits 99system.cpu.dtb.write_misses 1448 # DTB write misses 100system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 101system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 107system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 108system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 109system.cpu.dtb.read_accesses 31534882 # DTB read accesses 110system.cpu.dtb.write_accesses 23125911 # DTB write accesses 111system.cpu.dtb.inst_accesses 0 # ITB inst accesses 112system.cpu.dtb.hits 54650764 # DTB hits 113system.cpu.dtb.misses 10029 # DTB misses 114system.cpu.dtb.accesses 54660793 # DTB accesses | 120system.cpu.dtb.inst_hits 0 # ITB inst hits 121system.cpu.dtb.inst_misses 0 # ITB inst misses 122system.cpu.dtb.read_hits 31526301 # DTB read hits 123system.cpu.dtb.read_misses 8581 # DTB read misses 124system.cpu.dtb.write_hits 23124463 # DTB write hits 125system.cpu.dtb.write_misses 1448 # DTB write misses 126system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 127system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 133system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 134system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 135system.cpu.dtb.read_accesses 31534882 # DTB read accesses 136system.cpu.dtb.write_accesses 23125911 # DTB write accesses 137system.cpu.dtb.inst_accesses 0 # ITB inst accesses 138system.cpu.dtb.hits 54650764 # DTB hits 139system.cpu.dtb.misses 10029 # DTB misses 140system.cpu.dtb.accesses 54660793 # DTB accesses |
| 141system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 142system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 143system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 144system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 145system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 146system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 148system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
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| 115system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 116system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 117system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 118system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 119system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 120system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 121system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 122system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 128system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 129system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 130system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 131system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 132system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 133system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 134system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 135system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 149system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 150system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 151system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 152system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 153system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 154system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 155system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 156system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 162system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 163system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 164system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 165system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 166system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 167system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 168system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 169system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 170system.cpu.itb.walker.walks 4762 # Table walker walks requested 171system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 172system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 173system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 174system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 175system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 176system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 177system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 178system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 179system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 180system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated 181system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 182system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 183system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst 184system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 185system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 186system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 187system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst |
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| 136system.cpu.itb.inst_hits 147039592 # ITB inst hits 137system.cpu.itb.inst_misses 4762 # ITB inst misses 138system.cpu.itb.read_hits 0 # DTB read hits 139system.cpu.itb.read_misses 0 # DTB read misses 140system.cpu.itb.write_hits 0 # DTB write hits 141system.cpu.itb.write_misses 0 # DTB write misses 142system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 143system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 547 unchanged lines hidden --- | 188system.cpu.itb.inst_hits 147039592 # ITB inst hits 189system.cpu.itb.inst_misses 4762 # ITB inst misses 190system.cpu.itb.read_hits 0 # DTB read hits 191system.cpu.itb.read_misses 0 # DTB read misses 192system.cpu.itb.write_hits 0 # DTB write hits 193system.cpu.itb.write_misses 0 # DTB write misses 194system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 195system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 547 unchanged lines hidden --- |