Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 2.332810 # Number of seconds simulated
4sim_ticks 2332810269000 # Number of ticks simulated
5final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 2.332812 # Number of seconds simulated
4sim_ticks 2332811899500 # Number of ticks simulated
5final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 702757 # Simulator instruction rate (inst/s)
8host_op_rate 903702 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 27138460197 # Simulator tick rate (ticks/s)
10host_mem_usage 475940 # Number of bytes of host memory used
11host_seconds 85.96 # Real time elapsed on the host
12sim_insts 60408649 # Number of instructions simulated
13sim_ops 77681829 # Number of ops (including micro ops) simulated

7host_inst_rate 1065837 # Simulator instruction rate (inst/s)
8host_op_rate 1370594 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 41157671581 # Simulator tick rate (ticks/s)
10host_mem_usage 420236 # Number of bytes of host memory used
11host_seconds 56.68 # Real time elapsed on the host
12sim_insts 60411489 # Number of instructions simulated
13sim_ops 77685090 # Number of ops (including micro ops) simulated

14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
17system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
18system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
19system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
20system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
21system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
22system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
23system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
24system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
25system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
26system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
27system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
29system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
30system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
31system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory

32system.physmem.bytes_read::cpu.data 9071640 # Number of bytes read from this memory
33system.physmem.bytes_read::total 121450656 # Number of bytes read from this memory

32system.physmem.bytes_read::cpu.data 9071768 # Number of bytes read from this memory
33system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory

34system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory
35system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory

36system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory

36system.physmem.bytes_written::writebacks 3703424 # Number of bytes written to this memory

37system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory

38system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory

38system.physmem.bytes_written::total 6719240 # Number of bytes written to this memory

39system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory

43system.physmem.num_reads::cpu.data 141780 # Number of read requests responded to by this memory
44system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory
45system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory

43system.physmem.num_reads::cpu.data 141782 # Number of read requests responded to by this memory
44system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory
45system.physmem.num_writes::writebacks 57866 # Number of write requests responded to by this memory

46system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory

47system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory
48system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)

47system.physmem.num_writes::total 811820 # Number of write requests responded to by this memory
48system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s)

49system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s)

52system.physmem.bw_read::cpu.data 3888717 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::total 52061952 # Total read bandwidth from this memory (bytes/s)

52system.physmem.bw_read::cpu.data 3888770 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s)

54system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s)
55system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s)

56system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s)
57system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s)
58system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)

56system.physmem.bw_write::writebacks 1587536 # Write bandwidth from this memory (bytes/s)
57system.physmem.bw_write::cpu.data 1292781 # Write bandwidth from this memory (bytes/s)
58system.physmem.bw_write::total 2880318 # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_total::writebacks 1587536 # Total bandwidth to/from this memory (bytes/s)
60system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s)

61system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s)

64system.physmem.bw_total::cpu.data 5181500 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::total 54942190 # Total bandwidth to/from this memory (bytes/s)
66system.membus.throughput 55969605 # Throughput (bytes/s)
67system.membus.data_through_bus 130566470 # Total data (bytes)

64system.physmem.bw_total::cpu.data 5181551 # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::total 54942288 # Total bandwidth to/from this memory (bytes/s)
66system.membus.throughput 55969769 # Throughput (bytes/s)
67system.membus.data_through_bus 130566943 # Total data (bytes)

68system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
69system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
70system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
71system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
72system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
73system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
74system.cf0.dma_write_txs 0 # Number of DMA write transactions.

75system.iobus.throughput 48895252 # Throughput (bytes/s)
76system.iobus.data_through_bus 114063346 # Total data (bytes)

75system.iobus.throughput 48895283 # Throughput (bytes/s)
76system.iobus.data_through_bus 114063499 # Total data (bytes)

77system.cpu_clk_domain.clock 500 # Clock period in ticks
78system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
79system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
80system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
81system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
82system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
83system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
84system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed

--- 8 unchanged lines hidden (view full) ---

93system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
94system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
95system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
96system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
97system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
98system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
99system.cpu.dtb.inst_hits 0 # ITB inst hits
100system.cpu.dtb.inst_misses 0 # ITB inst misses

101system.cpu.dtb.read_hits 14971217 # DTB read hits

101system.cpu.dtb.read_hits 14971763 # DTB read hits

102system.cpu.dtb.read_misses 7294 # DTB read misses

103system.cpu.dtb.write_hits 11217004 # DTB write hits

103system.cpu.dtb.write_hits 11217184 # DTB write hits

104system.cpu.dtb.write_misses 2181 # DTB write misses
105system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
106system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
107system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
108system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
109system.cpu.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB
110system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
111system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
112system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
113system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions

114system.cpu.dtb.read_accesses 14978511 # DTB read accesses
115system.cpu.dtb.write_accesses 11219185 # DTB write accesses

114system.cpu.dtb.read_accesses 14979057 # DTB read accesses
115system.cpu.dtb.write_accesses 11219365 # DTB write accesses

116system.cpu.dtb.inst_accesses 0 # ITB inst accesses

117system.cpu.dtb.hits 26188221 # DTB hits

117system.cpu.dtb.hits 26188947 # DTB hits

118system.cpu.dtb.misses 9475 # DTB misses

119system.cpu.dtb.accesses 26197696 # DTB accesses

119system.cpu.dtb.accesses 26198422 # DTB accesses

120system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
121system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
122system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
123system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
124system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
125system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
126system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
127system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

133system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
134system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
135system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
136system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
137system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
138system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
139system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
140system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

141system.cpu.itb.inst_hits 61431840 # ITB inst hits

141system.cpu.itb.inst_hits 61434680 # ITB inst hits

142system.cpu.itb.inst_misses 4471 # ITB inst misses
143system.cpu.itb.read_hits 0 # DTB read hits
144system.cpu.itb.read_misses 0 # DTB read misses
145system.cpu.itb.write_hits 0 # DTB write hits
146system.cpu.itb.write_misses 0 # DTB write misses
147system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
148system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
149system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
150system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
151system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB
152system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
153system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
154system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
156system.cpu.itb.read_accesses 0 # DTB read accesses
157system.cpu.itb.write_accesses 0 # DTB write accesses

158system.cpu.itb.inst_accesses 61436311 # ITB inst accesses
159system.cpu.itb.hits 61431840 # DTB hits

158system.cpu.itb.inst_accesses 61439151 # ITB inst accesses
159system.cpu.itb.hits 61434680 # DTB hits

160system.cpu.itb.misses 4471 # DTB misses

161system.cpu.itb.accesses 61436311 # DTB accesses
162system.cpu.numCycles 4665620539 # number of cpu cycles simulated

161system.cpu.itb.accesses 61439151 # DTB accesses
162system.cpu.numCycles 4665623800 # number of cpu cycles simulated

163system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
164system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

165system.cpu.committedInsts 60408649 # Number of instructions committed
166system.cpu.committedOps 77681829 # Number of ops (including micro ops) committed
167system.cpu.num_int_alu_accesses 69130761 # Number of integer alu accesses

165system.cpu.committedInsts 60411489 # Number of instructions committed
166system.cpu.committedOps 77685090 # Number of ops (including micro ops) committed
167system.cpu.num_int_alu_accesses 69133554 # Number of integer alu accesses

168system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses

169system.cpu.num_func_calls 2136008 # number of times a function call or return occured
170system.cpu.num_conditional_control_insts 7942115 # number of instructions that are conditional controls
171system.cpu.num_int_insts 69130761 # number of integer instructions

169system.cpu.num_func_calls 2136078 # number of times a function call or return occured
170system.cpu.num_conditional_control_insts 7942566 # number of instructions that are conditional controls
171system.cpu.num_int_insts 69133554 # number of integer instructions

172system.cpu.num_fp_insts 10269 # number of float instructions

173system.cpu.num_int_register_reads 355896757 # number of times the integer registers were read
174system.cpu.num_int_register_writes 74438766 # number of times the integer registers were written

173system.cpu.num_int_register_reads 355910547 # number of times the integer registers were read
174system.cpu.num_int_register_writes 74442273 # number of times the integer registers were written

175system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
176system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written

177system.cpu.num_mem_refs 27361639 # number of memory refs
178system.cpu.num_load_insts 15639529 # Number of load instructions
179system.cpu.num_store_insts 11722110 # Number of store instructions
180system.cpu.num_idle_cycles 4586822073.007145 # Number of idle cycles
181system.cpu.num_busy_cycles 78798465.992855 # Number of busy cycles
182system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles
183system.cpu.idle_fraction 0.983111 # Percentage of idle cycles
184system.cpu.Branches 10298723 # Number of branches fetched

177system.cpu.num_mem_refs 27362421 # number of memory refs
178system.cpu.num_load_insts 15640088 # Number of load instructions
179system.cpu.num_store_insts 11722333 # Number of store instructions
180system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles
181system.cpu.num_busy_cycles 78801726.992856 # Number of busy cycles
182system.cpu.not_idle_fraction 0.016890 # Percentage of non-idle cycles
183system.cpu.idle_fraction 0.983110 # Percentage of idle cycles
184system.cpu.Branches 10299261 # Number of branches fetched

185system.cpu.kern.inst.arm 0 # number of arm instructions executed
186system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
187system.cpu.icache.tags.replacements 850590 # number of replacements

188system.cpu.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use
189system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks.

188system.cpu.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use
189system.cpu.icache.tags.total_refs 60586338 # Total number of references to valid blocks.

190system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.

191system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
192system.cpu.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit.
193system.cpu.icache.tags.occ_blocks::cpu.inst 511.678592 # Average occupied blocks per requestor

191system.cpu.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks.
192system.cpu.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit.
193system.cpu.icache.tags.occ_blocks::cpu.inst 511.678462 # Average occupied blocks per requestor

194system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
195system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
196system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
197system.cpu.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
198system.cpu.icache.tags.age_task_id_blocks_1024::1 78 # Occupied blocks per task id
199system.cpu.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id
200system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
201system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

202system.cpu.icache.tags.tag_accesses 62285702 # Number of tag accesses
203system.cpu.icache.tags.data_accesses 62285702 # Number of data accesses
204system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits
205system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
206system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits
207system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits
208system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits
209system.cpu.icache.overall_hits::total 60583498 # number of overall hits

202system.cpu.icache.tags.tag_accesses 62288542 # Number of tag accesses
203system.cpu.icache.tags.data_accesses 62288542 # Number of data accesses
204system.cpu.icache.ReadReq_hits::cpu.inst 60586338 # number of ReadReq hits
205system.cpu.icache.ReadReq_hits::total 60586338 # number of ReadReq hits
206system.cpu.icache.demand_hits::cpu.inst 60586338 # number of demand (read+write) hits
207system.cpu.icache.demand_hits::total 60586338 # number of demand (read+write) hits
208system.cpu.icache.overall_hits::cpu.inst 60586338 # number of overall hits
209system.cpu.icache.overall_hits::total 60586338 # number of overall hits

210system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses
211system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses
212system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses
213system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses
214system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses
215system.cpu.icache.overall_misses::total 851102 # number of overall misses

216system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses)
217system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses)
218system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses
219system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
220system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses
221system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
222system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses
223system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses
224system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses
225system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses
226system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses
227system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses

216system.cpu.icache.ReadReq_accesses::cpu.inst 61437440 # number of ReadReq accesses(hits+misses)
217system.cpu.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses)
218system.cpu.icache.demand_accesses::cpu.inst 61437440 # number of demand (read+write) accesses
219system.cpu.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses
220system.cpu.icache.overall_accesses::cpu.inst 61437440 # number of overall (read+write) accesses
221system.cpu.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses
222system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013853 # miss rate for ReadReq accesses
223system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses
224system.cpu.icache.demand_miss_rate::cpu.inst 0.013853 # miss rate for demand accesses
225system.cpu.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses
226system.cpu.icache.overall_miss_rate::cpu.inst 0.013853 # miss rate for overall accesses
227system.cpu.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses

228system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
229system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
230system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
231system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
232system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
233system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
234system.cpu.icache.fast_writes 0 # number of fast writes performed
235system.cpu.icache.cache_copies 0 # number of cache copies performed
236system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

237system.cpu.l2cache.tags.replacements 62243 # number of replacements
238system.cpu.l2cache.tags.tagsinuse 50007.272801 # Cycle average of tags in use
239system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks.
240system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks.
241system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks.
242system.cpu.l2cache.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit.
243system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582911 # Average occupied blocks per requestor
244system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor

237system.cpu.l2cache.tags.replacements 62245 # number of replacements
238system.cpu.l2cache.tags.tagsinuse 50007.460447 # Cycle average of tags in use
239system.cpu.l2cache.tags.total_refs 1669929 # Total number of references to valid blocks.
240system.cpu.l2cache.tags.sampled_refs 127630 # Sample count of references to valid blocks.
241system.cpu.l2cache.tags.avg_refs 13.084142 # Average number of references to valid blocks.
242system.cpu.l2cache.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit.
243system.cpu.l2cache.tags.occ_blocks::writebacks 36899.777920 # Average occupied blocks per requestor
244system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960146 # Average occupied blocks per requestor

245system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor

246system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720467 # Average occupied blocks per requestor
247system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015344 # Average occupied blocks per requestor
248system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy

246system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.716487 # Average occupied blocks per requestor
247system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.011961 # Average occupied blocks per requestor
248system.cpu.l2cache.tags.occ_percent::writebacks 0.563046 # Average percentage of cache occupancy

249system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
250system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
251system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
252system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy

253system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy

253system.cpu.l2cache.tags.occ_percent::total 0.763053 # Average percentage of cache occupancy

254system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
255system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id
256system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
257system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
258system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
259system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3589 # Occupied blocks per task id
260system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9187 # Occupied blocks per task id
261system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52388 # Occupied blocks per task id
262system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
263system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id

264system.cpu.l2cache.tags.tag_accesses 17035899 # Number of tag accesses
265system.cpu.l2cache.tags.data_accesses 17035899 # Number of data accesses

264system.cpu.l2cache.tags.tag_accesses 17035991 # Number of tag accesses
265system.cpu.l2cache.tags.data_accesses 17035991 # Number of data accesses

266system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
267system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
268system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits

269system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
270system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits
271system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits
272system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits

269system.cpu.l2cache.ReadReq_hits::cpu.data 366775 # number of ReadReq hits
270system.cpu.l2cache.ReadReq_hits::total 1216282 # number of ReadReq hits
271system.cpu.l2cache.Writeback_hits::writebacks 592648 # number of Writeback hits
272system.cpu.l2cache.Writeback_hits::total 592648 # number of Writeback hits

273system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
274system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
275system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
276system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits
277system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
278system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
279system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits

280system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits
281system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits

280system.cpu.l2cache.demand_hits::cpu.data 480514 # number of demand (read+write) hits
281system.cpu.l2cache.demand_hits::total 1330021 # number of demand (read+write) hits

282system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits
283system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits
284system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits

285system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits
286system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits

285system.cpu.l2cache.overall_hits::cpu.data 480514 # number of overall hits
286system.cpu.l2cache.overall_hits::total 1330021 # number of overall hits

287system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
288system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
289system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
290system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
291system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses
292system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
293system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses

294system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
295system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses

294system.cpu.l2cache.ReadExReq_misses::cpu.data 133470 # number of ReadExReq misses
295system.cpu.l2cache.ReadExReq_misses::total 133470 # number of ReadExReq misses

296system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
297system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
298system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses

299system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses
300system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses

299system.cpu.l2cache.demand_misses::cpu.data 143341 # number of demand (read+write) misses
300system.cpu.l2cache.demand_misses::total 153953 # number of demand (read+write) misses

301system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
302system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
303system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses

304system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses
305system.cpu.l2cache.overall_misses::total 153951 # number of overall misses

304system.cpu.l2cache.overall_misses::cpu.data 143341 # number of overall misses
305system.cpu.l2cache.overall_misses::total 153953 # number of overall misses

306system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
307system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
308system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)

309system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
310system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
311system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
312system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)

309system.cpu.l2cache.ReadReq_accesses::cpu.data 376646 # number of ReadReq accesses(hits+misses)
310system.cpu.l2cache.ReadReq_accesses::total 1236765 # number of ReadReq accesses(hits+misses)
311system.cpu.l2cache.Writeback_accesses::writebacks 592648 # number of Writeback accesses(hits+misses)
312system.cpu.l2cache.Writeback_accesses::total 592648 # number of Writeback accesses(hits+misses)

313system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
314system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)

315system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
316system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)

315system.cpu.l2cache.ReadExReq_accesses::cpu.data 247209 # number of ReadExReq accesses(hits+misses)
316system.cpu.l2cache.ReadExReq_accesses::total 247209 # number of ReadExReq accesses(hits+misses)

317system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
318system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
319system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses

320system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
321system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses

320system.cpu.l2cache.demand_accesses::cpu.data 623855 # number of demand (read+write) accesses
321system.cpu.l2cache.demand_accesses::total 1483974 # number of demand (read+write) accesses

322system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
323system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
324system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses

325system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
326system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses

325system.cpu.l2cache.overall_accesses::cpu.data 623855 # number of overall (read+write) accesses
326system.cpu.l2cache.overall_accesses::total 1483974 # number of overall (read+write) accesses

327system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
328system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
329system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
330system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
331system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
332system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
333system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses

334system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
335system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses

334system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539908 # miss rate for ReadExReq accesses
335system.cpu.l2cache.ReadExReq_miss_rate::total 0.539908 # miss rate for ReadExReq accesses

336system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
337system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
338system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses

339system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
340system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses

339system.cpu.l2cache.demand_miss_rate::cpu.data 0.229767 # miss rate for demand accesses
340system.cpu.l2cache.demand_miss_rate::total 0.103744 # miss rate for demand accesses

341system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
342system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
343system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses

344system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
345system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses

344system.cpu.l2cache.overall_miss_rate::cpu.data 0.229767 # miss rate for overall accesses
345system.cpu.l2cache.overall_miss_rate::total 0.103744 # miss rate for overall accesses

346system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
347system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
348system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
349system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
350system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
351system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
352system.cpu.l2cache.fast_writes 0 # number of fast writes performed
353system.cpu.l2cache.cache_copies 0 # number of cache copies performed

354system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
355system.cpu.l2cache.writebacks::total 57863 # number of writebacks

354system.cpu.l2cache.writebacks::writebacks 57866 # number of writebacks
355system.cpu.l2cache.writebacks::total 57866 # number of writebacks

356system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

357system.cpu.dcache.tags.replacements 623337 # number of replacements

357system.cpu.dcache.tags.replacements 623343 # number of replacements

358system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use

359system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks.
360system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks.
361system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks.

359system.cpu.dcache.tags.total_refs 23629012 # Total number of references to valid blocks.
360system.cpu.dcache.tags.sampled_refs 623855 # Sample count of references to valid blocks.
361system.cpu.dcache.tags.avg_refs 37.875808 # Average number of references to valid blocks.

362system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit.
363system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
364system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
365system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
366system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
367system.cpu.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id
368system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
369system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
370system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id

371system.cpu.dcache.tags.tag_accesses 97632617 # Number of tag accesses
372system.cpu.dcache.tags.data_accesses 97632617 # Number of data accesses
373system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
374system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
375system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
376system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits

371system.cpu.dcache.tags.tag_accesses 97635323 # Number of tag accesses
372system.cpu.dcache.tags.data_accesses 97635323 # Number of data accesses
373system.cpu.dcache.ReadReq_hits::cpu.data 13180574 # number of ReadReq hits
374system.cpu.dcache.ReadReq_hits::total 13180574 # number of ReadReq hits
375system.cpu.dcache.WriteReq_hits::cpu.data 9962233 # number of WriteReq hits
376system.cpu.dcache.WriteReq_hits::total 9962233 # number of WriteReq hits

377system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
378system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
379system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
380system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits

381system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
382system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
383system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
384system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
385system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
386system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
387system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
388system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses

381system.cpu.dcache.demand_hits::cpu.data 23142807 # number of demand (read+write) hits
382system.cpu.dcache.demand_hits::total 23142807 # number of demand (read+write) hits
383system.cpu.dcache.overall_hits::cpu.data 23142807 # number of overall hits
384system.cpu.dcache.overall_hits::total 23142807 # number of overall hits
385system.cpu.dcache.ReadReq_misses::cpu.data 365463 # number of ReadReq misses
386system.cpu.dcache.ReadReq_misses::total 365463 # number of ReadReq misses
387system.cpu.dcache.WriteReq_misses::cpu.data 250154 # number of WriteReq misses
388system.cpu.dcache.WriteReq_misses::total 250154 # number of WriteReq misses

389system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
390system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses

391system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
392system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
393system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
394system.cpu.dcache.overall_misses::total 615611 # number of overall misses
395system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
396system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
397system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
398system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)

391system.cpu.dcache.demand_misses::cpu.data 615617 # number of demand (read+write) misses
392system.cpu.dcache.demand_misses::total 615617 # number of demand (read+write) misses
393system.cpu.dcache.overall_misses::cpu.data 615617 # number of overall misses
394system.cpu.dcache.overall_misses::total 615617 # number of overall misses
395system.cpu.dcache.ReadReq_accesses::cpu.data 13546037 # number of ReadReq accesses(hits+misses)
396system.cpu.dcache.ReadReq_accesses::total 13546037 # number of ReadReq accesses(hits+misses)
397system.cpu.dcache.WriteReq_accesses::cpu.data 10212387 # number of WriteReq accesses(hits+misses)
398system.cpu.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses)

399system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
400system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
401system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
402system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)

403system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
404system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
405system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
406system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
408system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses

403system.cpu.dcache.demand_accesses::cpu.data 23758424 # number of demand (read+write) accesses
404system.cpu.dcache.demand_accesses::total 23758424 # number of demand (read+write) accesses
405system.cpu.dcache.overall_accesses::cpu.data 23758424 # number of overall (read+write) accesses
406system.cpu.dcache.overall_accesses::total 23758424 # number of overall (read+write) accesses
407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses
408system.cpu.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses

409system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
410system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
411system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
412system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
413system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
414system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
415system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
416system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
417system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
418system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
419system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
420system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
421system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
422system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
423system.cpu.dcache.fast_writes 0 # number of fast writes performed
424system.cpu.dcache.cache_copies 0 # number of cache copies performed

425system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
426system.cpu.dcache.writebacks::total 592643 # number of writebacks

425system.cpu.dcache.writebacks::writebacks 592648 # number of writebacks
426system.cpu.dcache.writebacks::total 592648 # number of writebacks

427system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

428system.cpu.toL2Bus.throughput 59102669 # Throughput (bytes/s)
429system.cpu.toL2Bus.data_through_bus 137875314 # Total data (bytes)

428system.cpu.toL2Bus.throughput 59102995 # Throughput (bytes/s)
429system.cpu.toL2Bus.data_through_bus 137876171 # Total data (bytes)