3,5c3,5
< sim_seconds 2.332317 # Number of seconds simulated
< sim_ticks 2332316587000 # Number of ticks simulated
< final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.332330 # Number of seconds simulated
> sim_ticks 2332330037000 # Number of ticks simulated
> final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,18c7,18
< host_inst_rate 864582 # Simulator instruction rate (inst/s)
< host_op_rate 1116533 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 34025972839 # Simulator tick rate (ticks/s)
< host_mem_usage 383900 # Number of bytes of host memory used
< host_seconds 68.55 # Real time elapsed on the host
< sim_insts 59262896 # Number of instructions simulated
< sim_ops 76532951 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read 122663536 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 941280 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 9577800 # Number of bytes written to this memory
< system.physmem.num_reads 14137126 # Number of read requests responded to by this memory
< system.physmem.num_writes 856485 # Number of write requests responded to by this memory
---
> host_inst_rate 1538399 # Simulator instruction rate (inst/s)
> host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 60412799239 # Simulator tick rate (ticks/s)
> host_mem_usage 379756 # Number of bytes of host memory used
> host_seconds 38.61 # Real time elapsed on the host
> sim_insts 59392246 # Number of instructions simulated
> sim_ops 76665494 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read 122661296 # Number of bytes read from this memory
> system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory
> system.physmem.bytes_written 9590216 # Number of bytes written to this memory
> system.physmem.num_reads 14137091 # Number of read requests responded to by this memory
> system.physmem.num_writes 856679 # Number of write requests responded to by this memory
20,23c20,23
< system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s)
33,37c33,37
< system.l2c.replacements 116822 # number of replacements
< system.l2c.tagsinuse 24240.388395 # Cycle average of tags in use
< system.l2c.total_refs 1520830 # Total number of references to valid blocks.
< system.l2c.sampled_refs 146847 # Sample count of references to valid blocks.
< system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
---
> system.l2c.replacements 117012 # number of replacements
> system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use
> system.l2c.total_refs 1527554 # Total number of references to valid blocks.
> system.l2c.sampled_refs 146810 # Sample count of references to valid blocks.
> system.l2c.avg_refs 10.404972 # Average number of references to valid blocks.
39,44c39,44
< system.l2c.occ_blocks::writebacks 13639.466229 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 5344.680068 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy
---
> system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy
47,56c47,56
< system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.inst 831710 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.data 356506 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 604613 # number of Writeback hits
< system.l2c.Writeback_hits::total 604613 # number of Writeback hits
---
> system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy
> system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits
> system.l2c.Writeback_hits::total 605735 # number of Writeback hits
59,113c59,113
< system.l2c.ReadExReq_hits::cpu.data 105791 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits
< system.l2c.demand_hits::cpu.dtb.walker 7522 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.itb.walker 3147 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.inst 831710 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.data 462297 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu.dtb.walker 7522 # number of overall hits
< system.l2c.overall_hits::cpu.itb.walker 3147 # number of overall hits
< system.l2c.overall_hits::cpu.inst 831710 # number of overall hits
< system.l2c.overall_hits::cpu.data 462297 # number of overall hits
< system.l2c.overall_hits::total 1304676 # number of overall hits
< system.l2c.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.inst 14294 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.data 17422 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu.data 2911 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses
< system.l2c.ReadExReq_misses::cpu.data 141169 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses
< system.l2c.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.inst 14294 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.data 158591 # number of demand (read+write) misses
< system.l2c.demand_misses::total 172912 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu.dtb.walker 19 # number of overall misses
< system.l2c.overall_misses::cpu.itb.walker 8 # number of overall misses
< system.l2c.overall_misses::cpu.inst 14294 # number of overall misses
< system.l2c.overall_misses::cpu.data 158591 # number of overall misses
< system.l2c.overall_misses::total 172912 # number of overall misses
< system.l2c.ReadReq_accesses::cpu.dtb.walker 7541 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.itb.walker 3155 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.inst 846004 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.data 373928 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 604613 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu.data 2937 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu.data 246960 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu.dtb.walker 7541 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.itb.walker 3155 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.inst 846004 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.data 620888 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu.dtb.walker 7541 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.itb.walker 3155 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.inst 846004 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.data 620888 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002520 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.002536 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.inst 0.016896 # miss rate for ReadReq accesses
---
> system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits
> system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits
> system.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits
> system.l2c.overall_hits::cpu.inst 835264 # number of overall hits
> system.l2c.overall_hits::cpu.data 463541 # number of overall hits
> system.l2c.overall_hits::total 1309459 # number of overall hits
> system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
> system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses
> system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses
> system.l2c.demand_misses::total 172858 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses
> system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses
> system.l2c.overall_misses::cpu.inst 14304 # number of overall misses
> system.l2c.overall_misses::cpu.data 158515 # number of overall misses
> system.l2c.overall_misses::total 172858 # number of overall misses
> system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses
115,124c115,124
< system.l2c.UpgradeReq_miss_rate::cpu.data 0.991147 # miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu.data 0.571627 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu.dtb.walker 0.002520 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.itb.walker 0.002536 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.inst 0.016896 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.data 0.255426 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu.dtb.walker 0.002520 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.itb.walker 0.002536 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.inst 0.016896 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.data 0.255426 # miss rate for overall accesses
---
> system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses
133,134c133,134
< system.l2c.writebacks::writebacks 102531 # number of writebacks
< system.l2c.writebacks::total 102531 # number of writebacks
---
> system.l2c.writebacks::writebacks 102725 # number of writebacks
> system.l2c.writebacks::total 102725 # number of writebacks
144,147c144,147
< system.cpu.dtb.read_hits 14940568 # DTB read hits
< system.cpu.dtb.read_misses 7288 # DTB read misses
< system.cpu.dtb.write_hits 11198206 # DTB write hits
< system.cpu.dtb.write_misses 2199 # DTB write misses
---
> system.cpu.dtb.read_hits 14971229 # DTB read hits
> system.cpu.dtb.read_misses 7293 # DTB read misses
> system.cpu.dtb.write_hits 11217018 # DTB write hits
> system.cpu.dtb.write_misses 2181 # DTB write misses
152c152
< system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
---
> system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB
154c154
< system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
157,158c157,158
< system.cpu.dtb.read_accesses 14947856 # DTB read accesses
< system.cpu.dtb.write_accesses 11200405 # DTB write accesses
---
> system.cpu.dtb.read_accesses 14978522 # DTB read accesses
> system.cpu.dtb.write_accesses 11219199 # DTB write accesses
160,163c160,163
< system.cpu.dtb.hits 26138774 # DTB hits
< system.cpu.dtb.misses 9487 # DTB misses
< system.cpu.dtb.accesses 26148261 # DTB accesses
< system.cpu.itb.inst_hits 60273909 # ITB inst hits
---
> system.cpu.dtb.hits 26188247 # DTB hits
> system.cpu.dtb.misses 9474 # DTB misses
> system.cpu.dtb.accesses 26197721 # DTB accesses
> system.cpu.itb.inst_hits 60403303 # ITB inst hits
180,181c180,181
< system.cpu.itb.inst_accesses 60278380 # ITB inst accesses
< system.cpu.itb.hits 60273909 # DTB hits
---
> system.cpu.itb.inst_accesses 60407774 # ITB inst accesses
> system.cpu.itb.hits 60403303 # DTB hits
183,184c183,184
< system.cpu.itb.accesses 60278380 # DTB accesses
< system.cpu.numCycles 4664556206 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 60407774 # DTB accesses
> system.cpu.numCycles 4664583062 # number of cpu cycles simulated
187,189c187,189
< system.cpu.committedInsts 59262896 # Number of instructions committed
< system.cpu.committedOps 76532951 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 68161195 # Number of integer alu accesses
---
> system.cpu.committedInsts 59392246 # Number of instructions committed
> system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses
191,193c191,193
< system.cpu.num_func_calls 1971944 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 7636089 # number of instructions that are conditional controls
< system.cpu.num_int_insts 68161195 # number of integer instructions
---
> system.cpu.num_func_calls 1972385 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls
> system.cpu.num_int_insts 68281415 # number of integer instructions
195,196c195,196
< system.cpu.num_int_register_reads 345365700 # number of times the integer registers were read
< system.cpu.num_int_register_writes 72877714 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read
> system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written
199,205c199,205
< system.cpu.num_mem_refs 27310787 # number of memory refs
< system.cpu.num_load_insts 15607076 # Number of load instructions
< system.cpu.num_store_insts 11703711 # Number of store instructions
< system.cpu.num_idle_cycles 4586920130.978250 # Number of idle cycles
< system.cpu.num_busy_cycles 77636075.021750 # Number of busy cycles
< system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 27361692 # number of memory refs
> system.cpu.num_load_insts 15639569 # Number of load instructions
> system.cpu.num_store_insts 11722123 # Number of store instructions
> system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles
> system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles
> system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.983328 # Percentage of idle cycles
207,214c207,214
< system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
< system.cpu.icache.replacements 847054 # number of replacements
< system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use
< system.cpu.icache.total_refs 59429103 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 70.117375 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 5705462000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor
---
> system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
> system.cpu.icache.replacements 850612 # number of replacements
> system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use
> system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor
217,237c217,237
< system.cpu.icache.ReadReq_hits::cpu.inst 59429103 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 59429103 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 59429103 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 59429103 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 59429103 # number of overall hits
< system.cpu.icache.overall_hits::total 59429103 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses
< system.cpu.icache.overall_misses::total 847566 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 60276669 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 60276669 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 60276669 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 60276669 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 60276669 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 60276669 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses
---
> system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits
> system.cpu.icache.overall_hits::total 59554939 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses
> system.cpu.icache.overall_misses::total 851124 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses
246,247c246,247
< system.cpu.icache.writebacks::writebacks 44721 # number of writebacks
< system.cpu.icache.writebacks::total 44721 # number of writebacks
---
> system.cpu.icache.writebacks::writebacks 44595 # number of writebacks
> system.cpu.icache.writebacks::total 44595 # number of writebacks
249c249
< system.cpu.dcache.replacements 622134 # number of replacements
---
> system.cpu.dcache.replacements 623347 # number of replacements
251,253c251,253
< system.cpu.dcache.total_refs 23580072 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 37.870752 # Average number of references to valid blocks.
---
> system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks.
258,296c258,296
< system.cpu.dcache.ReadReq_hits::cpu.data 13150368 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13150368 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 9943632 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 9943632 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 23094000 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 23094000 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 23094000 # number of overall hits
< system.cpu.dcache.overall_hits::total 23094000 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses
< system.cpu.dcache.overall_misses::total 614445 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 13514916 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13514916 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 10193529 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10193529 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 23708445 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 23708445 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 23708445 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 23708445 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses
---
> system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits
> system.cpu.dcache.overall_hits::total 23142161 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses
> system.cpu.dcache.overall_misses::total 615615 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
305,306c305,306
< system.cpu.dcache.writebacks::writebacks 559892 # number of writebacks
< system.cpu.dcache.writebacks::total 559892 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks
> system.cpu.dcache.writebacks::total 561140 # number of writebacks
< sim_seconds 2.332317 # Number of seconds simulated
< sim_ticks 2332316587000 # Number of ticks simulated
< final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.332330 # Number of seconds simulated
> sim_ticks 2332330037000 # Number of ticks simulated
> final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,18c7,18
< host_inst_rate 864582 # Simulator instruction rate (inst/s)
< host_op_rate 1116533 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 34025972839 # Simulator tick rate (ticks/s)
< host_mem_usage 383900 # Number of bytes of host memory used
< host_seconds 68.55 # Real time elapsed on the host
< sim_insts 59262896 # Number of instructions simulated
< sim_ops 76532951 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read 122663536 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 941280 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 9577800 # Number of bytes written to this memory
< system.physmem.num_reads 14137126 # Number of read requests responded to by this memory
< system.physmem.num_writes 856485 # Number of write requests responded to by this memory
---
> host_inst_rate 1538399 # Simulator instruction rate (inst/s)
> host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 60412799239 # Simulator tick rate (ticks/s)
> host_mem_usage 379756 # Number of bytes of host memory used
> host_seconds 38.61 # Real time elapsed on the host
> sim_insts 59392246 # Number of instructions simulated
> sim_ops 76665494 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read 122661296 # Number of bytes read from this memory
> system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory
> system.physmem.bytes_written 9590216 # Number of bytes written to this memory
> system.physmem.num_reads 14137091 # Number of read requests responded to by this memory
> system.physmem.num_writes 856679 # Number of write requests responded to by this memory
20,23c20,23
< system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s)
33,37c33,37
< system.l2c.replacements 116822 # number of replacements
< system.l2c.tagsinuse 24240.388395 # Cycle average of tags in use
< system.l2c.total_refs 1520830 # Total number of references to valid blocks.
< system.l2c.sampled_refs 146847 # Sample count of references to valid blocks.
< system.l2c.avg_refs 10.356562 # Average number of references to valid blocks.
---
> system.l2c.replacements 117012 # number of replacements
> system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use
> system.l2c.total_refs 1527554 # Total number of references to valid blocks.
> system.l2c.sampled_refs 146810 # Sample count of references to valid blocks.
> system.l2c.avg_refs 10.404972 # Average number of references to valid blocks.
39,44c39,44
< system.l2c.occ_blocks::writebacks 13639.466229 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 5344.680068 # Average occupied blocks per requestor
< system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy
---
> system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor
> system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy
47,56c47,56
< system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy
< system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy
< system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy
< system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.inst 831710 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu.data 356506 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 604613 # number of Writeback hits
< system.l2c.Writeback_hits::total 604613 # number of Writeback hits
---
> system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy
> system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy
> system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy
> system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits
> system.l2c.Writeback_hits::total 605735 # number of Writeback hits
59,113c59,113
< system.l2c.ReadExReq_hits::cpu.data 105791 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits
< system.l2c.demand_hits::cpu.dtb.walker 7522 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.itb.walker 3147 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.inst 831710 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu.data 462297 # number of demand (read+write) hits
< system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu.dtb.walker 7522 # number of overall hits
< system.l2c.overall_hits::cpu.itb.walker 3147 # number of overall hits
< system.l2c.overall_hits::cpu.inst 831710 # number of overall hits
< system.l2c.overall_hits::cpu.data 462297 # number of overall hits
< system.l2c.overall_hits::total 1304676 # number of overall hits
< system.l2c.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.inst 14294 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu.data 17422 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu.data 2911 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses
< system.l2c.ReadExReq_misses::cpu.data 141169 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses
< system.l2c.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.inst 14294 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu.data 158591 # number of demand (read+write) misses
< system.l2c.demand_misses::total 172912 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu.dtb.walker 19 # number of overall misses
< system.l2c.overall_misses::cpu.itb.walker 8 # number of overall misses
< system.l2c.overall_misses::cpu.inst 14294 # number of overall misses
< system.l2c.overall_misses::cpu.data 158591 # number of overall misses
< system.l2c.overall_misses::total 172912 # number of overall misses
< system.l2c.ReadReq_accesses::cpu.dtb.walker 7541 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.itb.walker 3155 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.inst 846004 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu.data 373928 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 604613 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu.data 2937 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu.data 246960 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu.dtb.walker 7541 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.itb.walker 3155 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.inst 846004 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu.data 620888 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu.dtb.walker 7541 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.itb.walker 3155 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.inst 846004 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu.data 620888 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002520 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.002536 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu.inst 0.016896 # miss rate for ReadReq accesses
---
> system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits
> system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits
> system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits
> system.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits
> system.l2c.overall_hits::cpu.inst 835264 # number of overall hits
> system.l2c.overall_hits::cpu.data 463541 # number of overall hits
> system.l2c.overall_hits::total 1309459 # number of overall hits
> system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
> system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses
> system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses
> system.l2c.demand_misses::total 172858 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses
> system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses
> system.l2c.overall_misses::cpu.inst 14304 # number of overall misses
> system.l2c.overall_misses::cpu.data 158515 # number of overall misses
> system.l2c.overall_misses::total 172858 # number of overall misses
> system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses
115,124c115,124
< system.l2c.UpgradeReq_miss_rate::cpu.data 0.991147 # miss rate for UpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu.data 0.571627 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu.dtb.walker 0.002520 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.itb.walker 0.002536 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.inst 0.016896 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu.data 0.255426 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu.dtb.walker 0.002520 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.itb.walker 0.002536 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.inst 0.016896 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu.data 0.255426 # miss rate for overall accesses
---
> system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses
133,134c133,134
< system.l2c.writebacks::writebacks 102531 # number of writebacks
< system.l2c.writebacks::total 102531 # number of writebacks
---
> system.l2c.writebacks::writebacks 102725 # number of writebacks
> system.l2c.writebacks::total 102725 # number of writebacks
144,147c144,147
< system.cpu.dtb.read_hits 14940568 # DTB read hits
< system.cpu.dtb.read_misses 7288 # DTB read misses
< system.cpu.dtb.write_hits 11198206 # DTB write hits
< system.cpu.dtb.write_misses 2199 # DTB write misses
---
> system.cpu.dtb.read_hits 14971229 # DTB read hits
> system.cpu.dtb.read_misses 7293 # DTB read misses
> system.cpu.dtb.write_hits 11217018 # DTB write hits
> system.cpu.dtb.write_misses 2181 # DTB write misses
152c152
< system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
---
> system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB
154c154
< system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch
---
> system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
157,158c157,158
< system.cpu.dtb.read_accesses 14947856 # DTB read accesses
< system.cpu.dtb.write_accesses 11200405 # DTB write accesses
---
> system.cpu.dtb.read_accesses 14978522 # DTB read accesses
> system.cpu.dtb.write_accesses 11219199 # DTB write accesses
160,163c160,163
< system.cpu.dtb.hits 26138774 # DTB hits
< system.cpu.dtb.misses 9487 # DTB misses
< system.cpu.dtb.accesses 26148261 # DTB accesses
< system.cpu.itb.inst_hits 60273909 # ITB inst hits
---
> system.cpu.dtb.hits 26188247 # DTB hits
> system.cpu.dtb.misses 9474 # DTB misses
> system.cpu.dtb.accesses 26197721 # DTB accesses
> system.cpu.itb.inst_hits 60403303 # ITB inst hits
180,181c180,181
< system.cpu.itb.inst_accesses 60278380 # ITB inst accesses
< system.cpu.itb.hits 60273909 # DTB hits
---
> system.cpu.itb.inst_accesses 60407774 # ITB inst accesses
> system.cpu.itb.hits 60403303 # DTB hits
183,184c183,184
< system.cpu.itb.accesses 60278380 # DTB accesses
< system.cpu.numCycles 4664556206 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 60407774 # DTB accesses
> system.cpu.numCycles 4664583062 # number of cpu cycles simulated
187,189c187,189
< system.cpu.committedInsts 59262896 # Number of instructions committed
< system.cpu.committedOps 76532951 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 68161195 # Number of integer alu accesses
---
> system.cpu.committedInsts 59392246 # Number of instructions committed
> system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses
191,193c191,193
< system.cpu.num_func_calls 1971944 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 7636089 # number of instructions that are conditional controls
< system.cpu.num_int_insts 68161195 # number of integer instructions
---
> system.cpu.num_func_calls 1972385 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls
> system.cpu.num_int_insts 68281415 # number of integer instructions
195,196c195,196
< system.cpu.num_int_register_reads 345365700 # number of times the integer registers were read
< system.cpu.num_int_register_writes 72877714 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read
> system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written
199,205c199,205
< system.cpu.num_mem_refs 27310787 # number of memory refs
< system.cpu.num_load_insts 15607076 # Number of load instructions
< system.cpu.num_store_insts 11703711 # Number of store instructions
< system.cpu.num_idle_cycles 4586920130.978250 # Number of idle cycles
< system.cpu.num_busy_cycles 77636075.021750 # Number of busy cycles
< system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.983356 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 27361692 # number of memory refs
> system.cpu.num_load_insts 15639569 # Number of load instructions
> system.cpu.num_store_insts 11722123 # Number of store instructions
> system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles
> system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles
> system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.983328 # Percentage of idle cycles
207,214c207,214
< system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed
< system.cpu.icache.replacements 847054 # number of replacements
< system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use
< system.cpu.icache.total_refs 59429103 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 70.117375 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 5705462000 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor
---
> system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
> system.cpu.icache.replacements 850612 # number of replacements
> system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use
> system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor
217,237c217,237
< system.cpu.icache.ReadReq_hits::cpu.inst 59429103 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 59429103 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 59429103 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 59429103 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 59429103 # number of overall hits
< system.cpu.icache.overall_hits::total 59429103 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses
< system.cpu.icache.overall_misses::total 847566 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 60276669 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 60276669 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 60276669 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 60276669 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 60276669 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 60276669 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses
---
> system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits
> system.cpu.icache.overall_hits::total 59554939 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses
> system.cpu.icache.overall_misses::total 851124 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses
246,247c246,247
< system.cpu.icache.writebacks::writebacks 44721 # number of writebacks
< system.cpu.icache.writebacks::total 44721 # number of writebacks
---
> system.cpu.icache.writebacks::writebacks 44595 # number of writebacks
> system.cpu.icache.writebacks::total 44595 # number of writebacks
249c249
< system.cpu.dcache.replacements 622134 # number of replacements
---
> system.cpu.dcache.replacements 623347 # number of replacements
251,253c251,253
< system.cpu.dcache.total_refs 23580072 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 37.870752 # Average number of references to valid blocks.
---
> system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks.
258,296c258,296
< system.cpu.dcache.ReadReq_hits::cpu.data 13150368 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 13150368 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 9943632 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 9943632 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 23094000 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 23094000 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 23094000 # number of overall hits
< system.cpu.dcache.overall_hits::total 23094000 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses
< system.cpu.dcache.overall_misses::total 614445 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 13514916 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13514916 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 10193529 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 10193529 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 23708445 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 23708445 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 23708445 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 23708445 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses
---
> system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits
> system.cpu.dcache.overall_hits::total 23142161 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses
> system.cpu.dcache.overall_misses::total 615615 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
305,306c305,306
< system.cpu.dcache.writebacks::writebacks 559892 # number of writebacks
< system.cpu.dcache.writebacks::total 559892 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks
> system.cpu.dcache.writebacks::total 561140 # number of writebacks