4,5c4,5
< sim_ticks 2783855034000 # Number of ticks simulated
< final_tick 2783855034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 2783854715000 # Number of ticks simulated
> final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 704767 # Simulator instruction rate (inst/s)
< host_op_rate 857940 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 13741971204 # Simulator tick rate (ticks/s)
< host_mem_usage 573692 # Number of bytes of host memory used
< host_seconds 202.58 # Real time elapsed on the host
< sim_insts 142771937 # Number of instructions simulated
< sim_ops 173801895 # Number of ops (including micro ops) simulated
---
> host_inst_rate 812904 # Simulator instruction rate (inst/s)
> host_op_rate 989581 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 15850589349 # Simulator tick rate (ticks/s)
> host_mem_usage 583016 # Number of bytes of host memory used
> host_seconds 175.63 # Real time elapsed on the host
> sim_insts 142771202 # Number of instructions simulated
> sim_ops 173801044 # Number of ops (including micro ops) simulated
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
20c20
< system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory
22c22
< system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory
25c25
< system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory
27c27
< system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory
31c31
< system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory
33,34c33,34
< system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory
36c36
< system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory
40c40
< system.physmem.bw_read::cpu.data 3708850 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s)
42c42
< system.physmem.bw_read::total 4142977 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s)
45c45
< system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s)
47,48c47,48
< system.physmem.bw_write::total 3182092 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s)
52c52
< system.physmem.bw_total::cpu.data 3715145 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s)
54,55c54,55
< system.physmem.bw_total::total 7325070 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
68,70c68,70
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
78c78
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
108c108
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
129c129
< system.cpu.dtb.read_hits 31526014 # DTB read hits
---
> system.cpu.dtb.read_hits 31525882 # DTB read hits
131c131
< system.cpu.dtb.write_hits 23124171 # DTB write hits
---
> system.cpu.dtb.write_hits 23124079 # DTB write hits
142,143c142,143
< system.cpu.dtb.read_accesses 31534594 # DTB read accesses
< system.cpu.dtb.write_accesses 23125619 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534462 # DTB read accesses
> system.cpu.dtb.write_accesses 23125527 # DTB write accesses
145c145
< system.cpu.dtb.hits 54650185 # DTB hits
---
> system.cpu.dtb.hits 54649961 # DTB hits
147,148c147,148
< system.cpu.dtb.accesses 54660213 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.accesses 54659989 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
178c178
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
197c197
< system.cpu.itb.inst_hits 147038452 # ITB inst hits
---
> system.cpu.itb.inst_hits 147037694 # ITB inst hits
214,215c214,215
< system.cpu.itb.inst_accesses 147043214 # ITB inst accesses
< system.cpu.itb.hits 147038452 # DTB hits
---
> system.cpu.itb.inst_accesses 147042456 # ITB inst accesses
> system.cpu.itb.hits 147037694 # DTB hits
217c217
< system.cpu.itb.accesses 147043214 # DTB accesses
---
> system.cpu.itb.accesses 147042456 # DTB accesses
220,221c220,221
< system.cpu.pwrStateClkGateDist::mean 874939595.358117 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 17329944407.298908 # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state
231,233c231,233
< system.cpu.pwrStateResidencyTicks::ON 89041080297 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813953703 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 5567713149 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 5567712511 # number of cpu cycles simulated
238,240c238,240
< system.cpu.committedInsts 142771937 # Number of instructions committed
< system.cpu.committedOps 173801895 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153161571 # Number of integer alu accesses
---
> system.cpu.committedInsts 142771202 # Number of instructions committed
> system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses
242,244c242,244
< system.cpu.num_func_calls 16873976 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730294 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153161571 # number of integer instructions
---
> system.cpu.num_func_calls 16873864 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153160791 # number of integer instructions
246,247c246,247
< system.cpu.num_int_register_reads 285044694 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107178579 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written
250,256c250,256
< system.cpu.num_cc_register_reads 530850452 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62364047 # number of times the CC registers were written
< system.cpu.num_mem_refs 55938751 # number of memory refs
< system.cpu.num_load_insts 31855653 # Number of load instructions
< system.cpu.num_store_insts 24083098 # Number of store instructions
< system.cpu.num_idle_cycles 5389630889.858858 # Number of idle cycles
< system.cpu.num_busy_cycles 178082259.141142 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written
> system.cpu.num_mem_refs 55938510 # number of memory refs
> system.cpu.num_load_insts 31855508 # Number of load instructions
> system.cpu.num_store_insts 24083002 # Number of store instructions
> system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles
> system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles
259c259
< system.cpu.Branches 36397005 # Number of branches fetched
---
> system.cpu.Branches 36396820 # Number of branches fetched
261,262c261,262
< system.cpu.op_class::IntAlu 121152199 68.36% 68.36% # Class of executed instruction
< system.cpu.op_class::IntMult 116879 0.07% 68.43% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction
> system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
290,291c290,291
< system.cpu.op_class::MemRead 31855653 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24083098 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction
294,296c294,296
< system.cpu.op_class::total 177218735 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 819389 # number of replacements
---
> system.cpu.op_class::total 177217860 # Class of executed instruction
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 819387 # number of replacements
298,300c298,300
< system.cpu.dcache.tags.total_refs 53784005 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819901 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.598170 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks.
310,316c310,316
< system.cpu.dcache.tags.tag_accesses 219235605 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219235605 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 30128867 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30128867 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22339858 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22339858 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits
323,330c323,330
< system.cpu.dcache.demand_hits::cpu.data 52468725 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52468725 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52863792 # number of overall hits
< system.cpu.dcache.overall_hits::total 52863792 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396279 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396279 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits
> system.cpu.dcache.overall_hits::total 52863571 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
337,344c337,344
< system.cpu.dcache.demand_misses::cpu.data 697942 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697942 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814061 # number of overall misses
< system.cpu.dcache.overall_misses::total 814061 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30525146 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30525146 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641521 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641521 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses
> system.cpu.dcache.overall_misses::total 814058 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses)
351,354c351,354
< system.cpu.dcache.demand_accesses::cpu.data 53166667 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53166667 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53677853 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53677853 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses
375,378c375,378
< system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
< system.cpu.dcache.writebacks::total 682017 # number of writebacks
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1698989 # number of replacements
---
> system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks
> system.cpu.dcache.writebacks::total 682138 # number of writebacks
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1698988 # number of replacements
380,382c380,382
< system.cpu.icache.tags.total_refs 145342052 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1699501 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 85.520427 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks.
393,413c393,413
< system.cpu.icache.tags.tag_accesses 148741066 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148741066 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 145342052 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145342052 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145342052 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145342052 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145342052 # number of overall hits
< system.cpu.icache.overall_hits::total 145342052 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1699507 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1699507 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1699507 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1699507 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1699507 # number of overall misses
< system.cpu.icache.overall_misses::total 1699507 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 147041559 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147041559 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147041559 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147041559 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147041559 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147041559 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits
> system.cpu.icache.overall_hits::total 145341295 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses
> system.cpu.icache.overall_misses::total 1699506 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses
426,440c426,438
< system.cpu.icache.writebacks::writebacks 1698989 # number of writebacks
< system.cpu.icache.writebacks::total 1698989 # number of writebacks
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 109914 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65155.312641 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4524828 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 175195 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 25.827381 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 48764.064013 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931994 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.693007 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.619283 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy
---
> system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks
> system.cpu.icache.writebacks::total 1698988 # number of writebacks
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 109912 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor
443,445c441,443
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy
447c445
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id
449,453c447,450
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id
455,483c452,480
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 40578737 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 40578737 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1666988 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1666988 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 151130 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 151130 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681192 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1681192 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505442 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 505442 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1681192 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 656572 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2348982 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1681192 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 656572 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2348982 # number of overall hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits
487,488c484,485
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
---
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
491,492c488,489
< system.cpu.l2cache.ReadExReq_misses::cpu.data 147777 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 147777 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses
500,501c497,498
< system.cpu.l2cache.demand_misses::cpu.data 163345 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 181652 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses
505,515c502,512
< system.cpu.l2cache.overall_misses::cpu.data 163345 # number of overall misses
< system.cpu.l2cache.overall_misses::total 181652 # number of overall misses
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1666988 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1666988 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses
> system.cpu.l2cache.overall_misses::total 179992 # number of overall misses
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses)
520,538c517,535
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699490 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1699490 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521010 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 521010 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1699490 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 819917 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530634 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1699490 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 819917 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530634 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses
541,542c538,539
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494391 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.494391 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses
545,548c542,545
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses
550,553c547,550
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.199221 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.071781 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses
555,556c552,553
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.199221 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.071781 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses
563,567c560,564
< system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
< system.cpu.l2cache.writebacks::total 101950 # number of writebacks
< system.cpu.toL2Bus.snoop_filter.tot_requests 5059879 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540474 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39263 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
> system.cpu.l2cache.writebacks::total 101949 # number of writebacks
> system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
571c568
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
573c570
< system.cpu.toL2Bus.trans_dist::ReadResp 2288317 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution
576,579c573,576
< system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1698989 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 137372 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
581c578
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution
584,587c581,584
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699507 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 521010 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116047 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581961 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes)
590,592c587,589
< system.cpu.toL2Bus.pkt_count::total 7753434 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539832 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306529 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes)
595,600c592,597
< system.cpu.toL2Bus.pkt_size::total 313957213 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 182976 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 8840960 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 5318714 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.018479 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.134677 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 115326 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram
602,603c599,600
< system.cpu.toL2Bus.snoop_fanout::0 5220428 98.15% 98.15% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 98286 1.85% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram
608,609c605,606
< system.cpu.toL2Bus.snoop_fanout::total 5318714 # Request fanout histogram
< system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram
> system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
660c657
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
662c659
< system.iocache.tags.tagsinuse 0.909892 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use
666,667c663,664
< system.iocache.tags.warmup_cycle 227410175509 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 0.909892 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor
675c672
< system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
708c705,711
< system.membus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
713,715c716,718
< system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution
< system.membus.trans_dist::CleanEvict 8204 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
> system.membus.trans_dist::CleanEvict 8203 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 130 # Transaction distribution
717,719c720,722
< system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
< system.membus.trans_dist::ReadExReq 145998 # Transaction distribution
< system.membus.trans_dist::ReadExResp 145998 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
> system.membus.trans_dist::ReadExReq 145996 # Transaction distribution
> system.membus.trans_dist::ReadExResp 145996 # Transaction distribution
726,727c729,730
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506584 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613944 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes)
730c733
< system.membus.pkt_count::total 723302 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes)
734,735c737,738
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092540 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255513 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes)
738c741
< system.membus.pkt_size::total 20587033 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes)
741,743c744,746
< system.membus.snoop_fanout::samples 434823 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 430442 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram
745,746c748,749
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 434823 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram
> system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram
749c752
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
751,758c754,761
< system.membus.snoop_fanout::total 434823 # Request fanout histogram
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_fanout::total 430442 # Request fanout histogram
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
765,766c768,769
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
798,804c801,807
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
809,820c812,823
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
< sim_ticks 2783855034000 # Number of ticks simulated
< final_tick 2783855034000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 2783854715000 # Number of ticks simulated
> final_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 704767 # Simulator instruction rate (inst/s)
< host_op_rate 857940 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 13741971204 # Simulator tick rate (ticks/s)
< host_mem_usage 573692 # Number of bytes of host memory used
< host_seconds 202.58 # Real time elapsed on the host
< sim_insts 142771937 # Number of instructions simulated
< sim_ops 173801895 # Number of ops (including micro ops) simulated
---
> host_inst_rate 812904 # Simulator instruction rate (inst/s)
> host_op_rate 989581 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 15850589349 # Simulator tick rate (ticks/s)
> host_mem_usage 583016 # Number of bytes of host memory used
> host_seconds 175.63 # Real time elapsed on the host
> sim_insts 142771202 # Number of instructions simulated
> sim_ops 173801044 # Number of ops (including micro ops) simulated
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
20c20
< system.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory
22c22
< system.physmem.bytes_read::total 11533448 # Number of bytes read from this memory
---
> system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory
25c25
< system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory
27c27
< system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory
31c31
< system.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory
33,34c33,34
< system.physmem.num_reads::total 189183 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory
36c36
< system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory
40c40
< system.physmem.bw_read::cpu.data 3708850 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s)
42c42
< system.physmem.bw_read::total 4142977 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s)
45c45
< system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s)
47,48c47,48
< system.physmem.bw_write::total 3182092 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s)
52c52
< system.physmem.bw_total::cpu.data 3715145 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s)
54,55c54,55
< system.physmem.bw_total::total 7325070 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
68,70c68,70
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
78c78
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
108c108
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
129c129
< system.cpu.dtb.read_hits 31526014 # DTB read hits
---
> system.cpu.dtb.read_hits 31525882 # DTB read hits
131c131
< system.cpu.dtb.write_hits 23124171 # DTB write hits
---
> system.cpu.dtb.write_hits 23124079 # DTB write hits
142,143c142,143
< system.cpu.dtb.read_accesses 31534594 # DTB read accesses
< system.cpu.dtb.write_accesses 23125619 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534462 # DTB read accesses
> system.cpu.dtb.write_accesses 23125527 # DTB write accesses
145c145
< system.cpu.dtb.hits 54650185 # DTB hits
---
> system.cpu.dtb.hits 54649961 # DTB hits
147,148c147,148
< system.cpu.dtb.accesses 54660213 # DTB accesses
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.accesses 54659989 # DTB accesses
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
178c178
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
197c197
< system.cpu.itb.inst_hits 147038452 # ITB inst hits
---
> system.cpu.itb.inst_hits 147037694 # ITB inst hits
214,215c214,215
< system.cpu.itb.inst_accesses 147043214 # ITB inst accesses
< system.cpu.itb.hits 147038452 # DTB hits
---
> system.cpu.itb.inst_accesses 147042456 # ITB inst accesses
> system.cpu.itb.hits 147037694 # DTB hits
217c217
< system.cpu.itb.accesses 147043214 # DTB accesses
---
> system.cpu.itb.accesses 147042456 # DTB accesses
220,221c220,221
< system.cpu.pwrStateClkGateDist::mean 874939595.358117 # Distribution of time spent in the clock gated state
< system.cpu.pwrStateClkGateDist::stdev 17329944407.298908 # Distribution of time spent in the clock gated state
---
> system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state
> system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state
231,233c231,233
< system.cpu.pwrStateResidencyTicks::ON 89041080297 # Cumulative time (in ticks) in various power states
< system.cpu.pwrStateResidencyTicks::CLK_GATED 2694813953703 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 5567713149 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states
> system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 5567712511 # number of cpu cycles simulated
238,240c238,240
< system.cpu.committedInsts 142771937 # Number of instructions committed
< system.cpu.committedOps 173801895 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153161571 # Number of integer alu accesses
---
> system.cpu.committedInsts 142771202 # Number of instructions committed
> system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses
242,244c242,244
< system.cpu.num_func_calls 16873976 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730294 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153161571 # number of integer instructions
---
> system.cpu.num_func_calls 16873864 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153160791 # number of integer instructions
246,247c246,247
< system.cpu.num_int_register_reads 285044694 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107178579 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written
250,256c250,256
< system.cpu.num_cc_register_reads 530850452 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62364047 # number of times the CC registers were written
< system.cpu.num_mem_refs 55938751 # number of memory refs
< system.cpu.num_load_insts 31855653 # Number of load instructions
< system.cpu.num_store_insts 24083098 # Number of store instructions
< system.cpu.num_idle_cycles 5389630889.858858 # Number of idle cycles
< system.cpu.num_busy_cycles 178082259.141142 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written
> system.cpu.num_mem_refs 55938510 # number of memory refs
> system.cpu.num_load_insts 31855508 # Number of load instructions
> system.cpu.num_store_insts 24083002 # Number of store instructions
> system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles
> system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles
259c259
< system.cpu.Branches 36397005 # Number of branches fetched
---
> system.cpu.Branches 36396820 # Number of branches fetched
261,262c261,262
< system.cpu.op_class::IntAlu 121152199 68.36% 68.36% # Class of executed instruction
< system.cpu.op_class::IntMult 116879 0.07% 68.43% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction
> system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
290,291c290,291
< system.cpu.op_class::MemRead 31855653 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24083098 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction
294,296c294,296
< system.cpu.op_class::total 177218735 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 819389 # number of replacements
---
> system.cpu.op_class::total 177217860 # Class of executed instruction
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 819387 # number of replacements
298,300c298,300
< system.cpu.dcache.tags.total_refs 53784005 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819901 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.598170 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks.
310,316c310,316
< system.cpu.dcache.tags.tag_accesses 219235605 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219235605 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 30128867 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30128867 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22339858 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22339858 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits
323,330c323,330
< system.cpu.dcache.demand_hits::cpu.data 52468725 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52468725 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52863792 # number of overall hits
< system.cpu.dcache.overall_hits::total 52863792 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396279 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396279 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits
> system.cpu.dcache.overall_hits::total 52863571 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
337,344c337,344
< system.cpu.dcache.demand_misses::cpu.data 697942 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697942 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814061 # number of overall misses
< system.cpu.dcache.overall_misses::total 814061 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30525146 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30525146 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641521 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641521 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses
> system.cpu.dcache.overall_misses::total 814058 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses)
351,354c351,354
< system.cpu.dcache.demand_accesses::cpu.data 53166667 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53166667 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53677853 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53677853 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses
375,378c375,378
< system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks
< system.cpu.dcache.writebacks::total 682017 # number of writebacks
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 1698989 # number of replacements
---
> system.cpu.dcache.writebacks::writebacks 682138 # number of writebacks
> system.cpu.dcache.writebacks::total 682138 # number of writebacks
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 1698988 # number of replacements
380,382c380,382
< system.cpu.icache.tags.total_refs 145342052 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1699501 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 85.520427 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks.
393,413c393,413
< system.cpu.icache.tags.tag_accesses 148741066 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148741066 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 145342052 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145342052 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145342052 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145342052 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145342052 # number of overall hits
< system.cpu.icache.overall_hits::total 145342052 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1699507 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1699507 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1699507 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1699507 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1699507 # number of overall misses
< system.cpu.icache.overall_misses::total 1699507 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 147041559 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147041559 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147041559 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147041559 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147041559 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147041559 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148740307 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits
> system.cpu.icache.overall_hits::total 145341295 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses
> system.cpu.icache.overall_misses::total 1699506 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses
426,440c426,438
< system.cpu.icache.writebacks::writebacks 1698989 # number of writebacks
< system.cpu.icache.writebacks::total 1698989 # number of writebacks
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 109914 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65155.312641 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 4524828 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 175195 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 25.827381 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 48764.064013 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931994 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.693007 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.619283 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy
---
> system.cpu.icache.writebacks::writebacks 1698988 # number of writebacks
> system.cpu.icache.writebacks::total 1698988 # number of writebacks
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 109912 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor
443,445c441,443
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139903 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.110163 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy
447c445
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id
449,453c447,450
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id
455,483c452,480
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 40578737 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 40578737 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits
< system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 1666988 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 1666988 # number of WritebackClean hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 151130 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 151130 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681192 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 1681192 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505442 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 505442 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 1681192 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 656572 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2348982 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 1681192 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 656572 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2348982 # number of overall hits
---
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits
> system.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2347806 # number of overall hits
487,488c484,485
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
---
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
491,492c488,489
< system.cpu.l2cache.ReadExReq_misses::cpu.data 147777 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 147777 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses
500,501c497,498
< system.cpu.l2cache.demand_misses::cpu.data 163345 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 181652 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses
505,515c502,512
< system.cpu.l2cache.overall_misses::cpu.data 163345 # number of overall misses
< system.cpu.l2cache.overall_misses::total 181652 # number of overall misses
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 1666988 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 1666988 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses
> system.cpu.l2cache.overall_misses::total 179992 # number of overall misses
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses)
520,538c517,535
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699490 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1699490 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521010 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 521010 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 1699490 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 819917 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530634 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1699490 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 819917 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530634 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses
541,542c538,539
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494391 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.494391 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses
545,548c542,545
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses
550,553c547,550
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.199221 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.071781 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses
555,556c552,553
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.199221 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.071781 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses
563,567c560,564
< system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks
< system.cpu.l2cache.writebacks::total 101950 # number of writebacks
< system.cpu.toL2Bus.snoop_filter.tot_requests 5059879 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540474 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39263 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks
> system.cpu.l2cache.writebacks::total 101949 # number of writebacks
> system.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
571c568
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
573c570
< system.cpu.toL2Bus.trans_dist::ReadResp 2288317 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution
576,579c573,576
< system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 1698989 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 137372 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution
581c578
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution
584,587c581,584
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699507 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 521010 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116047 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581961 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes)
590,592c587,589
< system.cpu.toL2Bus.pkt_count::total 7753434 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539832 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306529 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes)
595,600c592,597
< system.cpu.toL2Bus.pkt_size::total 313957213 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 182976 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 8840960 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 5318714 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.018479 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.134677 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 115326 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram
602,603c599,600
< system.cpu.toL2Bus.snoop_fanout::0 5220428 98.15% 98.15% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 98286 1.85% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram
608,609c605,606
< system.cpu.toL2Bus.snoop_fanout::total 5318714 # Request fanout histogram
< system.iobus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram
> system.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
660c657
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
662c659
< system.iocache.tags.tagsinuse 0.909892 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use
666,667c663,664
< system.iocache.tags.warmup_cycle 227410175509 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 0.909892 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor
675c672
< system.iocache.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
708c705,711
< system.membus.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
713,715c716,718
< system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution
< system.membus.trans_dist::CleanEvict 8204 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
---
> system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution
> system.membus.trans_dist::CleanEvict 8203 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 130 # Transaction distribution
717,719c720,722
< system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
< system.membus.trans_dist::ReadExReq 145998 # Transaction distribution
< system.membus.trans_dist::ReadExResp 145998 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
> system.membus.trans_dist::ReadExReq 145996 # Transaction distribution
> system.membus.trans_dist::ReadExResp 145996 # Transaction distribution
726,727c729,730
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506584 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613944 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes)
730c733
< system.membus.pkt_count::total 723302 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes)
734,735c737,738
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092540 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255513 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes)
738c741
< system.membus.pkt_size::total 20587033 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes)
741,743c744,746
< system.membus.snoop_fanout::samples 434823 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 430442 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.012836 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram
745,746c748,749
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 434823 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram
> system.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram
749c752
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
751,758c754,761
< system.membus.snoop_fanout::total 434823 # Request fanout histogram
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_fanout::total 430442 # Request fanout histogram
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
765,766c768,769
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
798,804c801,807
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
809,820c812,823
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855034000 # Cumulative time (in ticks) in various power states
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states