4,5c4,5
< sim_ticks 2783867165000 # Number of ticks simulated
< final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 2783867052000 # Number of ticks simulated
> final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1374338 # Simulator instruction rate (inst/s)
< host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 26797569978 # Simulator tick rate (ticks/s)
< host_mem_usage 615488 # Number of bytes of host memory used
< host_seconds 103.89 # Real time elapsed on the host
< sim_insts 142773109 # Number of instructions simulated
< sim_ops 173803334 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1378466 # Simulator instruction rate (inst/s)
> host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26878113924 # Simulator tick rate (ticks/s)
> host_mem_usage 614624 # Number of bytes of host memory used
> host_seconds 103.57 # Real time elapsed on the host
> sim_insts 142772879 # Number of instructions simulated
> sim_ops 173803124 # Number of ops (including micro ops) simulated
18c18
< system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory
26c26
< system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory
29c29
< system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory
35c35
< system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory
38c38
< system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s)
41,44c41,44
< system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s)
46,47c46,47
< system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s)
50c50
< system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s)
53c53
< system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s)
122c122
< system.cpu.dtb.read_hits 31526301 # DTB read hits
---
> system.cpu.dtb.read_hits 31526223 # DTB read hits
124c124
< system.cpu.dtb.write_hits 23124463 # DTB write hits
---
> system.cpu.dtb.write_hits 23124452 # DTB write hits
135,136c135,136
< system.cpu.dtb.read_accesses 31534882 # DTB read accesses
< system.cpu.dtb.write_accesses 23125911 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534804 # DTB read accesses
> system.cpu.dtb.write_accesses 23125900 # DTB write accesses
138c138
< system.cpu.dtb.hits 54650764 # DTB hits
---
> system.cpu.dtb.hits 54650675 # DTB hits
140c140
< system.cpu.dtb.accesses 54660793 # DTB accesses
---
> system.cpu.dtb.accesses 54660704 # DTB accesses
188c188
< system.cpu.itb.inst_hits 147039592 # ITB inst hits
---
> system.cpu.itb.inst_hits 147039346 # ITB inst hits
205,206c205,206
< system.cpu.itb.inst_accesses 147044354 # ITB inst accesses
< system.cpu.itb.hits 147039592 # DTB hits
---
> system.cpu.itb.inst_accesses 147044108 # ITB inst accesses
> system.cpu.itb.hits 147039346 # DTB hits
208,209c208,209
< system.cpu.itb.accesses 147044354 # DTB accesses
< system.cpu.numCycles 5567737414 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 147044108 # DTB accesses
> system.cpu.numCycles 5567737188 # number of cpu cycles simulated
212,214c212,214
< system.cpu.committedInsts 142773109 # Number of instructions committed
< system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses
---
> system.cpu.committedInsts 142772879 # Number of instructions committed
> system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
216,218c216,218
< system.cpu.num_func_calls 16873879 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153162826 # number of integer instructions
---
> system.cpu.num_func_calls 16873899 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153162683 # number of integer instructions
220,221c220,221
< system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written
224,230c224,230
< system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written
< system.cpu.num_mem_refs 55939365 # number of memory refs
< system.cpu.num_load_insts 31855962 # Number of load instructions
< system.cpu.num_store_insts 24083403 # Number of store instructions
< system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles
< system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written
> system.cpu.num_mem_refs 55939276 # number of memory refs
> system.cpu.num_load_insts 31855884 # Number of load instructions
> system.cpu.num_store_insts 24083392 # Number of store instructions
> system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles
> system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles
233c233
< system.cpu.Branches 36397028 # Number of branches fetched
---
> system.cpu.Branches 36396981 # Number of branches fetched
235c235
< system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction
264,265c264,265
< system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction
268c268
< system.cpu.op_class::total 177220138 # Class of executed instruction
---
> system.cpu.op_class::total 177219912 # Class of executed instruction
271c271
< system.cpu.dcache.tags.replacements 819403 # number of replacements
---
> system.cpu.dcache.tags.replacements 819402 # number of replacements
273,275c273,275
< system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks.
285,290c285,290
< system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits
297,302c297,302
< system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits
< system.cpu.dcache.overall_hits::total 52864309 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits
> system.cpu.dcache.overall_hits::total 52864242 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses
311,318c311,318
< system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
< system.cpu.dcache.overall_misses::total 814075 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses
> system.cpu.dcache.overall_misses::total 814074 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses)
325,328c325,328
< system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses
351,352c351,352
< system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks
< system.cpu.dcache.writebacks::total 682060 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks
> system.cpu.dcache.writebacks::total 682059 # number of writebacks
354c354
< system.cpu.icache.tags.replacements 1699220 # number of replacements
---
> system.cpu.icache.tags.replacements 1699214 # number of replacements
356,358c356,358
< system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
369,388c369,388
< system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits
< system.cpu.icache.overall_hits::total 145342961 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses
< system.cpu.icache.overall_misses::total 1699738 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits
> system.cpu.icache.overall_hits::total 145342721 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses
> system.cpu.icache.overall_misses::total 1699732 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
404,408c404,408
< system.cpu.l2cache.tags.replacements 110027 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 110026 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks.
410c410
< system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor
413,414c413,414
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor
431,432c431,432
< system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses
435,439c435,439
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits
446,448c446,448
< system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits
451,453c451,453
< system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits
456c456
< system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses
458c458
< system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses
467c467
< system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses
469c469
< system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses
472c472
< system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses
474c474
< system.cpu.l2cache.overall_misses::total 181765 # number of overall misses
---
> system.cpu.l2cache.overall_misses::total 181764 # number of overall misses
477,481c477,481
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses)
490,492c490,492
< system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses
495,497c495,497
< system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses
500c500
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses
502c502
< system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses
511c511
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses
516c516
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses
527,528c527,528
< system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
< system.cpu.l2cache.writebacks::total 101898 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks
> system.cpu.l2cache.writebacks::total 101897 # number of writebacks
530,534c530,534
< system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution
540,541c540,541
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes)
544,546c544,546
< system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes)
549c549
< system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
551,553c551,553
< system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
558,561c558,559
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
563,569c561,567
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram
< system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
< system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
> system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
> system.iobus.trans_dist::WriteResp 22778 # Transaction distribution
571c569
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
592c590
< system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
595,596c593,594
< system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
617c615
< system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
620c618
< system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
622c620
< system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use
627c625
< system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor
---
> system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor
670,674c668,672
< system.membus.trans_dist::ReadReq 74235 # Transaction distribution
< system.membus.trans_dist::ReadResp 74235 # Transaction distribution
< system.membus.trans_dist::WriteReq 27560 # Transaction distribution
< system.membus.trans_dist::WriteResp 27560 # Transaction distribution
< system.membus.trans_dist::Writeback 138088 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 74227 # Transaction distribution
> system.membus.trans_dist::ReadResp 74227 # Transaction distribution
> system.membus.trans_dist::WriteReq 27546 # Transaction distribution
> system.membus.trans_dist::WriteResp 27546 # Transaction distribution
> system.membus.trans_dist::Writeback 138087 # Transaction distribution
682c680
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
685,686c683,684
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes)
689,690c687,688
< system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
693,694c691,692
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes)
697c695
< system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
699c697
< system.membus.snoop_fanout::samples 359047 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 359045 # Request fanout histogram
704c702
< system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
709c707
< system.membus.snoop_fanout::total 359047 # Request fanout histogram
---
> system.membus.snoop_fanout::total 359045 # Request fanout histogram
< sim_ticks 2783867165000 # Number of ticks simulated
< final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 2783867052000 # Number of ticks simulated
> final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1374338 # Simulator instruction rate (inst/s)
< host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 26797569978 # Simulator tick rate (ticks/s)
< host_mem_usage 615488 # Number of bytes of host memory used
< host_seconds 103.89 # Real time elapsed on the host
< sim_insts 142773109 # Number of instructions simulated
< sim_ops 173803334 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1378466 # Simulator instruction rate (inst/s)
> host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26878113924 # Simulator tick rate (ticks/s)
> host_mem_usage 614624 # Number of bytes of host memory used
> host_seconds 103.57 # Real time elapsed on the host
> sim_insts 142772879 # Number of instructions simulated
> sim_ops 173803124 # Number of ops (including micro ops) simulated
18c18
< system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory
26c26
< system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory
29c29
< system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory
32,33c32,33
< system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory
35c35
< system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory
38c38
< system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s)
41,44c41,44
< system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s)
46,47c46,47
< system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s)
50c50
< system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s)
53c53
< system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s)
122c122
< system.cpu.dtb.read_hits 31526301 # DTB read hits
---
> system.cpu.dtb.read_hits 31526223 # DTB read hits
124c124
< system.cpu.dtb.write_hits 23124463 # DTB write hits
---
> system.cpu.dtb.write_hits 23124452 # DTB write hits
135,136c135,136
< system.cpu.dtb.read_accesses 31534882 # DTB read accesses
< system.cpu.dtb.write_accesses 23125911 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534804 # DTB read accesses
> system.cpu.dtb.write_accesses 23125900 # DTB write accesses
138c138
< system.cpu.dtb.hits 54650764 # DTB hits
---
> system.cpu.dtb.hits 54650675 # DTB hits
140c140
< system.cpu.dtb.accesses 54660793 # DTB accesses
---
> system.cpu.dtb.accesses 54660704 # DTB accesses
188c188
< system.cpu.itb.inst_hits 147039592 # ITB inst hits
---
> system.cpu.itb.inst_hits 147039346 # ITB inst hits
205,206c205,206
< system.cpu.itb.inst_accesses 147044354 # ITB inst accesses
< system.cpu.itb.hits 147039592 # DTB hits
---
> system.cpu.itb.inst_accesses 147044108 # ITB inst accesses
> system.cpu.itb.hits 147039346 # DTB hits
208,209c208,209
< system.cpu.itb.accesses 147044354 # DTB accesses
< system.cpu.numCycles 5567737414 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 147044108 # DTB accesses
> system.cpu.numCycles 5567737188 # number of cpu cycles simulated
212,214c212,214
< system.cpu.committedInsts 142773109 # Number of instructions committed
< system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses
---
> system.cpu.committedInsts 142772879 # Number of instructions committed
> system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
216,218c216,218
< system.cpu.num_func_calls 16873879 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153162826 # number of integer instructions
---
> system.cpu.num_func_calls 16873899 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153162683 # number of integer instructions
220,221c220,221
< system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written
224,230c224,230
< system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written
< system.cpu.num_mem_refs 55939365 # number of memory refs
< system.cpu.num_load_insts 31855962 # Number of load instructions
< system.cpu.num_store_insts 24083403 # Number of store instructions
< system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles
< system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written
> system.cpu.num_mem_refs 55939276 # number of memory refs
> system.cpu.num_load_insts 31855884 # Number of load instructions
> system.cpu.num_store_insts 24083392 # Number of store instructions
> system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles
> system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles
233c233
< system.cpu.Branches 36397028 # Number of branches fetched
---
> system.cpu.Branches 36396981 # Number of branches fetched
235c235
< system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction
264,265c264,265
< system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction
268c268
< system.cpu.op_class::total 177220138 # Class of executed instruction
---
> system.cpu.op_class::total 177219912 # Class of executed instruction
271c271
< system.cpu.dcache.tags.replacements 819403 # number of replacements
---
> system.cpu.dcache.tags.replacements 819402 # number of replacements
273,275c273,275
< system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks.
285,290c285,290
< system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits
297,302c297,302
< system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits
< system.cpu.dcache.overall_hits::total 52864309 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits
> system.cpu.dcache.overall_hits::total 52864242 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses
311,318c311,318
< system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
< system.cpu.dcache.overall_misses::total 814075 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses
> system.cpu.dcache.overall_misses::total 814074 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses)
325,328c325,328
< system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses
351,352c351,352
< system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks
< system.cpu.dcache.writebacks::total 682060 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks
> system.cpu.dcache.writebacks::total 682059 # number of writebacks
354c354
< system.cpu.icache.tags.replacements 1699220 # number of replacements
---
> system.cpu.icache.tags.replacements 1699214 # number of replacements
356,358c356,358
< system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
369,388c369,388
< system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits
< system.cpu.icache.overall_hits::total 145342961 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses
< system.cpu.icache.overall_misses::total 1699738 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits
> system.cpu.icache.overall_hits::total 145342721 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses
> system.cpu.icache.overall_misses::total 1699732 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
404,408c404,408
< system.cpu.l2cache.tags.replacements 110027 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 110026 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks.
410c410
< system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor
413,414c413,414
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor
431,432c431,432
< system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses
435,439c435,439
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits
446,448c446,448
< system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits
451,453c451,453
< system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits
456c456
< system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses
458c458
< system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses
---
> system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses
467c467
< system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses
469c469
< system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses
472c472
< system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses
474c474
< system.cpu.l2cache.overall_misses::total 181765 # number of overall misses
---
> system.cpu.l2cache.overall_misses::total 181764 # number of overall misses
477,481c477,481
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses)
490,492c490,492
< system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses
495,497c495,497
< system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses
500c500
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses
502c502
< system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses
511c511
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses
516c516
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses
527,528c527,528
< system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
< system.cpu.l2cache.writebacks::total 101898 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks
> system.cpu.l2cache.writebacks::total 101897 # number of writebacks
530,534c530,534
< system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution
540,541c540,541
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes)
544,546c544,546
< system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes)
549c549
< system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
551,553c551,553
< system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
558,561c558,559
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
563,569c561,567
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram
< system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
< system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
> system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
> system.iobus.trans_dist::WriteResp 22778 # Transaction distribution
571c569
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
592c590
< system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
595,596c593,594
< system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
617c615
< system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
620c618
< system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
622c620
< system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use
627c625
< system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor
---
> system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor
670,674c668,672
< system.membus.trans_dist::ReadReq 74235 # Transaction distribution
< system.membus.trans_dist::ReadResp 74235 # Transaction distribution
< system.membus.trans_dist::WriteReq 27560 # Transaction distribution
< system.membus.trans_dist::WriteResp 27560 # Transaction distribution
< system.membus.trans_dist::Writeback 138088 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 74227 # Transaction distribution
> system.membus.trans_dist::ReadResp 74227 # Transaction distribution
> system.membus.trans_dist::WriteReq 27546 # Transaction distribution
> system.membus.trans_dist::WriteResp 27546 # Transaction distribution
> system.membus.trans_dist::Writeback 138087 # Transaction distribution
682c680
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
685,686c683,684
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes)
689,690c687,688
< system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
693,694c691,692
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes)
697c695
< system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
699c697
< system.membus.snoop_fanout::samples 359047 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 359045 # Request fanout histogram
704c702
< system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
709c707
< system.membus.snoop_fanout::total 359047 # Request fanout histogram
---
> system.membus.snoop_fanout::total 359045 # Request fanout histogram