3,5c3,5
< sim_seconds 2.783854 # Number of seconds simulated
< sim_ticks 2783854461500 # Number of ticks simulated
< final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.783867 # Number of seconds simulated
> sim_ticks 2783867165000 # Number of ticks simulated
> final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1414038 # Simulator instruction rate (inst/s)
< host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 27571822204 # Simulator tick rate (ticks/s)
< host_mem_usage 560116 # Number of bytes of host memory used
< host_seconds 100.97 # Real time elapsed on the host
< sim_insts 142771592 # Number of instructions simulated
< sim_ops 173801445 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1064003 # Simulator instruction rate (inst/s)
> host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 20746494205 # Simulator tick rate (ticks/s)
> host_mem_usage 558936 # Number of bytes of host memory used
> host_seconds 134.19 # Real time elapsed on the host
> sim_insts 142773109 # Number of instructions simulated
> sim_ops 173803334 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory
26,27c26
< system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
< system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory
30,31c29,30
< system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory
33,34c32,33
< system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory
36,37c35
< system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory
40,41c38,39
< system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s)
43,46c41,44
< system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s)
48,50c46,47
< system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s)
53,56c50,53
< system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s)
99,101c96,98
< system.cpu.dtb.read_hits 31525959 # DTB read hits
< system.cpu.dtb.read_misses 8580 # DTB read misses
< system.cpu.dtb.write_hits 23124081 # DTB write hits
---
> system.cpu.dtb.read_hits 31526301 # DTB read hits
> system.cpu.dtb.read_misses 8581 # DTB read misses
> system.cpu.dtb.write_hits 23124463 # DTB write hits
112,113c109,110
< system.cpu.dtb.read_accesses 31534539 # DTB read accesses
< system.cpu.dtb.write_accesses 23125529 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534882 # DTB read accesses
> system.cpu.dtb.write_accesses 23125911 # DTB write accesses
115,117c112,114
< system.cpu.dtb.hits 54650040 # DTB hits
< system.cpu.dtb.misses 10028 # DTB misses
< system.cpu.dtb.accesses 54660068 # DTB accesses
---
> system.cpu.dtb.hits 54650764 # DTB hits
> system.cpu.dtb.misses 10029 # DTB misses
> system.cpu.dtb.accesses 54660793 # DTB accesses
139c136
< system.cpu.itb.inst_hits 147038107 # ITB inst hits
---
> system.cpu.itb.inst_hits 147039592 # ITB inst hits
156,157c153,154
< system.cpu.itb.inst_accesses 147042869 # ITB inst accesses
< system.cpu.itb.hits 147038107 # DTB hits
---
> system.cpu.itb.inst_accesses 147044354 # ITB inst accesses
> system.cpu.itb.hits 147039592 # DTB hits
159,160c156,157
< system.cpu.itb.accesses 147042869 # DTB accesses
< system.cpu.numCycles 5567712004 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 147044354 # DTB accesses
> system.cpu.numCycles 5567737414 # number of cpu cycles simulated
163,165c160,162
< system.cpu.committedInsts 142771592 # Number of instructions committed
< system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses
---
> system.cpu.committedInsts 142773109 # Number of instructions committed
> system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses
167,169c164,166
< system.cpu.num_func_calls 16873874 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153161099 # number of integer instructions
---
> system.cpu.num_func_calls 16873879 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153162826 # number of integer instructions
171,172c168,169
< system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written
175,181c172,178
< system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written
< system.cpu.num_mem_refs 55938603 # number of memory refs
< system.cpu.num_load_insts 31855595 # Number of load instructions
< system.cpu.num_store_insts 24083008 # Number of store instructions
< system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles
< system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written
> system.cpu.num_mem_refs 55939365 # number of memory refs
> system.cpu.num_load_insts 31855962 # Number of load instructions
> system.cpu.num_store_insts 24083403 # Number of store instructions
> system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles
> system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles
184c181
< system.cpu.Branches 36396923 # Number of branches fetched
---
> system.cpu.Branches 36397028 # Number of branches fetched
186,187c183,184
< system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction
< system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction
> system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
215,216c212,213
< system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction
219c216
< system.cpu.op_class::total 177218284 # Class of executed instruction
---
> system.cpu.op_class::total 177220138 # Class of executed instruction
221,222c218,219
< system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
< system.cpu.dcache.tags.replacements 819396 # number of replacements
---
> system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
> system.cpu.dcache.tags.replacements 819403 # number of replacements
224,226c221,223
< system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks.
236,259c233,256
< system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits
< system.cpu.dcache.overall_hits::total 52863618 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits
> system.cpu.dcache.overall_hits::total 52864309 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
262,279c259,276
< system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses
< system.cpu.dcache.overall_misses::total 814069 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
> system.cpu.dcache.overall_misses::total 814075 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses
284,287c281,284
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses
302,303c299,300
< system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks
< system.cpu.dcache.writebacks::total 682037 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks
> system.cpu.dcache.writebacks::total 682060 # number of writebacks
305,309c302,306
< system.cpu.icache.tags.replacements 1699006 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 1699220 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks.
311c308
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
320,345c317,342
< system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits
< system.cpu.icache.overall_hits::total 145341690 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses
< system.cpu.icache.overall_misses::total 1699524 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
---
> system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits
> system.cpu.icache.overall_hits::total 145342961 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses
> system.cpu.icache.overall_misses::total 1699738 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses
356,357c353,354
< system.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks.
359c356
< system.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks.
361,365c358,362
< system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor
370c367
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy
382,384c379,381
< system.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
---
> system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
386,390c383,387
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits
393,395c390,392
< system.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits
397,400c394,397
< system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits
402,404c399,401
< system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2348893 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits
426c423
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
428,432c425,429
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses)
437,439c434,436
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses
441,444c438,441
< system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses
446,449c443,446
< system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
451c448
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses
453c450
< system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses
458,460c455,457
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses
462,465c459,462
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses
467,469c464,466
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses
478,479c475,476
< system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks
< system.cpu.l2cache.writebacks::total 101899 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
> system.cpu.l2cache.writebacks::total 101898 # number of writebacks
481,482c478,479
< system.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution
485c482
< system.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution
489,492c486,489
< system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes)
494,497c491,494
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes)
499,502c496,499
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 36632 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram
504c501
< system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram
511c508
< system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram
516c513
< system.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram
573c570
< system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use
578,580c575,577
< system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
---
> system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy
586,587d582
< system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
< system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
589a585,586
> system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
603a601,602
> system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
614c613
< system.iocache.fast_writes 36224 # number of fast writes performed
---
> system.iocache.fast_writes 0 # number of fast writes performed
615a615,616
> system.iocache.writebacks::writebacks 36190 # number of writebacks
> system.iocache.writebacks::total 36190 # number of writebacks
621c622
< system.membus.trans_dist::Writeback 101899 # Transaction distribution
---
> system.membus.trans_dist::Writeback 138088 # Transaction distribution
632,636c633,637
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes)
640,644c641,645
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes)
646c647
< system.membus.snoop_fanout::samples 322858 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 359047 # Request fanout histogram
651c652
< system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram
656c657
< system.membus.snoop_fanout::total 322858 # Request fanout histogram
---
> system.membus.snoop_fanout::total 359047 # Request fanout histogram
< sim_seconds 2.783854 # Number of seconds simulated
< sim_ticks 2783854461500 # Number of ticks simulated
< final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.783867 # Number of seconds simulated
> sim_ticks 2783867165000 # Number of ticks simulated
> final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1414038 # Simulator instruction rate (inst/s)
< host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 27571822204 # Simulator tick rate (ticks/s)
< host_mem_usage 560116 # Number of bytes of host memory used
< host_seconds 100.97 # Real time elapsed on the host
< sim_insts 142771592 # Number of instructions simulated
< sim_ops 173801445 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1064003 # Simulator instruction rate (inst/s)
> host_op_rate 1295252 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 20746494205 # Simulator tick rate (ticks/s)
> host_mem_usage 558936 # Number of bytes of host memory used
> host_seconds 134.19 # Real time elapsed on the host
> sim_insts 142773109 # Number of instructions simulated
> sim_ops 173803334 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory
21,24c21,24
< system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory
26,27c26
< system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
< system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory
30,31c29,30
< system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory
33,34c32,33
< system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory
36,37c35
< system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory
40,41c38,39
< system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s)
43,46c41,44
< system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s)
48,50c46,47
< system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s)
53,56c50,53
< system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s)
99,101c96,98
< system.cpu.dtb.read_hits 31525959 # DTB read hits
< system.cpu.dtb.read_misses 8580 # DTB read misses
< system.cpu.dtb.write_hits 23124081 # DTB write hits
---
> system.cpu.dtb.read_hits 31526301 # DTB read hits
> system.cpu.dtb.read_misses 8581 # DTB read misses
> system.cpu.dtb.write_hits 23124463 # DTB write hits
112,113c109,110
< system.cpu.dtb.read_accesses 31534539 # DTB read accesses
< system.cpu.dtb.write_accesses 23125529 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534882 # DTB read accesses
> system.cpu.dtb.write_accesses 23125911 # DTB write accesses
115,117c112,114
< system.cpu.dtb.hits 54650040 # DTB hits
< system.cpu.dtb.misses 10028 # DTB misses
< system.cpu.dtb.accesses 54660068 # DTB accesses
---
> system.cpu.dtb.hits 54650764 # DTB hits
> system.cpu.dtb.misses 10029 # DTB misses
> system.cpu.dtb.accesses 54660793 # DTB accesses
139c136
< system.cpu.itb.inst_hits 147038107 # ITB inst hits
---
> system.cpu.itb.inst_hits 147039592 # ITB inst hits
156,157c153,154
< system.cpu.itb.inst_accesses 147042869 # ITB inst accesses
< system.cpu.itb.hits 147038107 # DTB hits
---
> system.cpu.itb.inst_accesses 147044354 # ITB inst accesses
> system.cpu.itb.hits 147039592 # DTB hits
159,160c156,157
< system.cpu.itb.accesses 147042869 # DTB accesses
< system.cpu.numCycles 5567712004 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 147044354 # DTB accesses
> system.cpu.numCycles 5567737414 # number of cpu cycles simulated
163,165c160,162
< system.cpu.committedInsts 142771592 # Number of instructions committed
< system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses
---
> system.cpu.committedInsts 142773109 # Number of instructions committed
> system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses
167,169c164,166
< system.cpu.num_func_calls 16873874 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153161099 # number of integer instructions
---
> system.cpu.num_func_calls 16873879 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153162826 # number of integer instructions
171,172c168,169
< system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written
175,181c172,178
< system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written
< system.cpu.num_mem_refs 55938603 # number of memory refs
< system.cpu.num_load_insts 31855595 # Number of load instructions
< system.cpu.num_store_insts 24083008 # Number of store instructions
< system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles
< system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written
> system.cpu.num_mem_refs 55939365 # number of memory refs
> system.cpu.num_load_insts 31855962 # Number of load instructions
> system.cpu.num_store_insts 24083403 # Number of store instructions
> system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles
> system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles
184c181
< system.cpu.Branches 36396923 # Number of branches fetched
---
> system.cpu.Branches 36397028 # Number of branches fetched
186,187c183,184
< system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction
< system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction
> system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
215,216c212,213
< system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction
219c216
< system.cpu.op_class::total 177218284 # Class of executed instruction
---
> system.cpu.op_class::total 177220138 # Class of executed instruction
221,222c218,219
< system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
< system.cpu.dcache.tags.replacements 819396 # number of replacements
---
> system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
> system.cpu.dcache.tags.replacements 819403 # number of replacements
224,226c221,223
< system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks.
236,259c233,256
< system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits
< system.cpu.dcache.overall_hits::total 52863618 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
---
> system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits
> system.cpu.dcache.overall_hits::total 52864309 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
262,279c259,276
< system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses
< system.cpu.dcache.overall_misses::total 814069 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
> system.cpu.dcache.overall_misses::total 814075 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses
284,287c281,284
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses
302,303c299,300
< system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks
< system.cpu.dcache.writebacks::total 682037 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks
> system.cpu.dcache.writebacks::total 682060 # number of writebacks
305,309c302,306
< system.cpu.icache.tags.replacements 1699006 # number of replacements
< system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 1699220 # number of replacements
> system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks.
311c308
< system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
320,345c317,342
< system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits
< system.cpu.icache.overall_hits::total 145341690 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses
< system.cpu.icache.overall_misses::total 1699524 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
---
> system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits
> system.cpu.icache.overall_hits::total 145342961 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses
> system.cpu.icache.overall_misses::total 1699738 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses
356,357c353,354
< system.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks.
359c356
< system.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks.
361,365c358,362
< system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor
370c367
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy
382,384c379,381
< system.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits
---
> system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
386,390c383,387
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits
393,395c390,392
< system.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits
397,400c394,397
< system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits
402,404c399,401
< system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2348893 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits
426c423
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
428,432c425,429
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses)
437,439c434,436
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses
441,444c438,441
< system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses
446,449c443,446
< system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
451c448
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses
453c450
< system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses
458,460c455,457
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses
462,465c459,462
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses
467,469c464,466
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses
478,479c475,476
< system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks
< system.cpu.l2cache.writebacks::total 101899 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
> system.cpu.l2cache.writebacks::total 101898 # number of writebacks
481,482c478,479
< system.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution
485c482
< system.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution
489,492c486,489
< system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes)
494,497c491,494
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes)
499,502c496,499
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 36632 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram
504c501
< system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram
511c508
< system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram
516c513
< system.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram
573c570
< system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use
578,580c575,577
< system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
---
> system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy
586,587d582
< system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
< system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
589a585,586
> system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
603a601,602
> system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
614c613
< system.iocache.fast_writes 36224 # number of fast writes performed
---
> system.iocache.fast_writes 0 # number of fast writes performed
615a615,616
> system.iocache.writebacks::writebacks 36190 # number of writebacks
> system.iocache.writebacks::total 36190 # number of writebacks
621c622
< system.membus.trans_dist::Writeback 101899 # Transaction distribution
---
> system.membus.trans_dist::Writeback 138088 # Transaction distribution
632,636c633,637
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes)
640,644c641,645
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes)
646c647
< system.membus.snoop_fanout::samples 322858 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 359047 # Request fanout histogram
651c652
< system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram
656c657
< system.membus.snoop_fanout::total 322858 # Request fanout histogram
---
> system.membus.snoop_fanout::total 359047 # Request fanout histogram