4,5c4,5
< sim_ticks 2783854177000 # Number of ticks simulated
< final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 2783854461500 # Number of ticks simulated
> final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1378246 # Simulator instruction rate (inst/s)
< host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 26874016957 # Simulator tick rate (ticks/s)
< host_mem_usage 553624 # Number of bytes of host memory used
< host_seconds 103.59 # Real time elapsed on the host
< sim_insts 142771179 # Number of instructions simulated
< sim_ops 173800939 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1414038 # Simulator instruction rate (inst/s)
> host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 27571822204 # Simulator tick rate (ticks/s)
> host_mem_usage 560116 # Number of bytes of host memory used
> host_seconds 100.97 # Real time elapsed on the host
> sim_insts 142771592 # Number of instructions simulated
> sim_ops 173801445 # Number of ops (including micro ops) simulated
16d15
< system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
20a20
> system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
25d24
< system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
26a26
> system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
28d27
< system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32a32
> system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
35d34
< system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
36a36
> system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
38d37
< system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
42a42
> system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
47d46
< system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
49c48,49
< system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s)
51d50
< system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
56c55,56
< system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s)
69,139d68
< system.membus.trans_dist::ReadReq 74235 # Transaction distribution
< system.membus.trans_dist::ReadResp 74235 # Transaction distribution
< system.membus.trans_dist::WriteReq 27560 # Transaction distribution
< system.membus.trans_dist::WriteResp 27560 # Transaction distribution
< system.membus.trans_dist::Writeback 101899 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
< system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
< system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 322858 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 322858 # Request fanout histogram
< system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
< system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
< system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
< system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
< system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
< system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
< system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
< system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
< system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
< system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
< system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
< system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
< system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
< system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
< system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
< system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
< system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
< system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
< system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
< system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
< system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
< system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
< system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
< system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
< system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
< system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
< system.realview.ethernet.droppedPackets 0 # number of packets dropped
146,200d74
< system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
< system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
< system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
225c99
< system.cpu.dtb.read_hits 31525864 # DTB read hits
---
> system.cpu.dtb.read_hits 31525959 # DTB read hits
227c101
< system.cpu.dtb.write_hits 23124034 # DTB write hits
---
> system.cpu.dtb.write_hits 23124081 # DTB write hits
238,239c112,113
< system.cpu.dtb.read_accesses 31534444 # DTB read accesses
< system.cpu.dtb.write_accesses 23125482 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534539 # DTB read accesses
> system.cpu.dtb.write_accesses 23125529 # DTB write accesses
241c115
< system.cpu.dtb.hits 54649898 # DTB hits
---
> system.cpu.dtb.hits 54650040 # DTB hits
243c117
< system.cpu.dtb.accesses 54659926 # DTB accesses
---
> system.cpu.dtb.accesses 54660068 # DTB accesses
265c139
< system.cpu.itb.inst_hits 147037671 # ITB inst hits
---
> system.cpu.itb.inst_hits 147038107 # ITB inst hits
282,283c156,157
< system.cpu.itb.inst_accesses 147042433 # ITB inst accesses
< system.cpu.itb.hits 147037671 # DTB hits
---
> system.cpu.itb.inst_accesses 147042869 # ITB inst accesses
> system.cpu.itb.hits 147038107 # DTB hits
285,286c159,160
< system.cpu.itb.accesses 147042433 # DTB accesses
< system.cpu.numCycles 5567711435 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 147042869 # DTB accesses
> system.cpu.numCycles 5567712004 # number of cpu cycles simulated
289,291c163,165
< system.cpu.committedInsts 142771179 # Number of instructions committed
< system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses
---
> system.cpu.committedInsts 142771592 # Number of instructions committed
> system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses
293,295c167,169
< system.cpu.num_func_calls 16873782 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153160639 # number of integer instructions
---
> system.cpu.num_func_calls 16873874 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153161099 # number of integer instructions
297,298c171,172
< system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written
301,307c175,181
< system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written
< system.cpu.num_mem_refs 55938446 # number of memory refs
< system.cpu.num_load_insts 31855497 # Number of load instructions
< system.cpu.num_store_insts 24082949 # Number of store instructions
< system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles
< system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written
> system.cpu.num_mem_refs 55938603 # number of memory refs
> system.cpu.num_load_insts 31855595 # Number of load instructions
> system.cpu.num_store_insts 24083008 # Number of store instructions
> system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles
> system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles
310c184
< system.cpu.Branches 36396779 # Number of branches fetched
---
> system.cpu.Branches 36396923 # Number of branches fetched
312,313c186,187
< system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction
< system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction
> system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
341,342c215,216
< system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction
345c219
< system.cpu.op_class::total 177217756 # Class of executed instruction
---
> system.cpu.op_class::total 177218284 # Class of executed instruction
347a222,304
> system.cpu.dcache.tags.replacements 819396 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits
> system.cpu.dcache.overall_hits::total 52863618 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses
> system.cpu.dcache.overall_misses::total 814069 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks
> system.cpu.dcache.writebacks::total 682037 # number of writebacks
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
350c307
< system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks.
352c309
< system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks.
363,370c320,327
< system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits
< system.cpu.icache.overall_hits::total 145341254 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits
> system.cpu.icache.overall_hits::total 145341690 # number of overall hits
377,382c334,339
< system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses
399,400c356,357
< system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks.
402c359
< system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks.
404c361
< system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor
407,408c364,365
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor
425,426c382,383
< system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses
430,433c387,390
< system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits
436,437c393,394
< system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits
441,442c398,399
< system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits
446,447c403,404
< system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2348893 # number of overall hits
472,475c429,432
< system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses)
480,481c437,438
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
485,486c442,443
< system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses
490,491c447,448
< system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses
501,502c458,459
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses
506c463
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses
511c468
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses
524,608c481,482
< system.cpu.dcache.tags.replacements 819392 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits
< system.cpu.dcache.overall_hits::total 52863480 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
< system.cpu.dcache.overall_misses::total 814065 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks
< system.cpu.dcache.writebacks::total 682036 # number of writebacks
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution
611c485
< system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution
615,616c489,490
< system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
618c492
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes)
621c495
< system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes)
623c497
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes)
626c500
< system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes)
628c502
< system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram
637c511
< system.cpu.toL2Bus.snoop_fanout::5 3231951 98.88% 98.88% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram
642c516,571
< system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram
> system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
> system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
> system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
644c573
< system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
649c578
< system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor
---
> system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor
687a617,687
> system.membus.trans_dist::ReadReq 74235 # Transaction distribution
> system.membus.trans_dist::ReadResp 74235 # Transaction distribution
> system.membus.trans_dist::WriteReq 27560 # Transaction distribution
> system.membus.trans_dist::WriteResp 27560 # Transaction distribution
> system.membus.trans_dist::Writeback 101899 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
> system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
> system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 322858 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 322858 # Request fanout histogram
> system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
> system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
> system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
> system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
> system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
> system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
> system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
> system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
> system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
> system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
> system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
> system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
> system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
> system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
> system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
> system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
> system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
> system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
> system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
> system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
> system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
> system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
> system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
> system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
> system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
> system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
> system.realview.ethernet.droppedPackets 0 # number of packets dropped
< sim_ticks 2783854177000 # Number of ticks simulated
< final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 2783854461500 # Number of ticks simulated
> final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1378246 # Simulator instruction rate (inst/s)
< host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 26874016957 # Simulator tick rate (ticks/s)
< host_mem_usage 553624 # Number of bytes of host memory used
< host_seconds 103.59 # Real time elapsed on the host
< sim_insts 142771179 # Number of instructions simulated
< sim_ops 173800939 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1414038 # Simulator instruction rate (inst/s)
> host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 27571822204 # Simulator tick rate (ticks/s)
> host_mem_usage 560116 # Number of bytes of host memory used
> host_seconds 100.97 # Real time elapsed on the host
> sim_insts 142771592 # Number of instructions simulated
> sim_ops 173801445 # Number of ops (including micro ops) simulated
16d15
< system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
20a20
> system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
25d24
< system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
26a26
> system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
28d27
< system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
32a32
> system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
35d34
< system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
36a36
> system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
38d37
< system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
42a42
> system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
47d46
< system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
49c48,49
< system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s)
51d50
< system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
56c55,56
< system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s)
69,139d68
< system.membus.trans_dist::ReadReq 74235 # Transaction distribution
< system.membus.trans_dist::ReadResp 74235 # Transaction distribution
< system.membus.trans_dist::WriteReq 27560 # Transaction distribution
< system.membus.trans_dist::WriteResp 27560 # Transaction distribution
< system.membus.trans_dist::Writeback 101899 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
< system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
< system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
< system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 322858 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 1 # Request fanout histogram
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 322858 # Request fanout histogram
< system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
< system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
< system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
< system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
< system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
< system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
< system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
< system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
< system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
< system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
< system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
< system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
< system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
< system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
< system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
< system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
< system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
< system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
< system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
< system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
< system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
< system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
< system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
< system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
< system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
< system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
< system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
< system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
< system.realview.ethernet.droppedPackets 0 # number of packets dropped
146,200d74
< system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
< system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
< system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
< system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
225c99
< system.cpu.dtb.read_hits 31525864 # DTB read hits
---
> system.cpu.dtb.read_hits 31525959 # DTB read hits
227c101
< system.cpu.dtb.write_hits 23124034 # DTB write hits
---
> system.cpu.dtb.write_hits 23124081 # DTB write hits
238,239c112,113
< system.cpu.dtb.read_accesses 31534444 # DTB read accesses
< system.cpu.dtb.write_accesses 23125482 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534539 # DTB read accesses
> system.cpu.dtb.write_accesses 23125529 # DTB write accesses
241c115
< system.cpu.dtb.hits 54649898 # DTB hits
---
> system.cpu.dtb.hits 54650040 # DTB hits
243c117
< system.cpu.dtb.accesses 54659926 # DTB accesses
---
> system.cpu.dtb.accesses 54660068 # DTB accesses
265c139
< system.cpu.itb.inst_hits 147037671 # ITB inst hits
---
> system.cpu.itb.inst_hits 147038107 # ITB inst hits
282,283c156,157
< system.cpu.itb.inst_accesses 147042433 # ITB inst accesses
< system.cpu.itb.hits 147037671 # DTB hits
---
> system.cpu.itb.inst_accesses 147042869 # ITB inst accesses
> system.cpu.itb.hits 147038107 # DTB hits
285,286c159,160
< system.cpu.itb.accesses 147042433 # DTB accesses
< system.cpu.numCycles 5567711435 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 147042869 # DTB accesses
> system.cpu.numCycles 5567712004 # number of cpu cycles simulated
289,291c163,165
< system.cpu.committedInsts 142771179 # Number of instructions committed
< system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses
---
> system.cpu.committedInsts 142771592 # Number of instructions committed
> system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses
293,295c167,169
< system.cpu.num_func_calls 16873782 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153160639 # number of integer instructions
---
> system.cpu.num_func_calls 16873874 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153161099 # number of integer instructions
297,298c171,172
< system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written
301,307c175,181
< system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written
< system.cpu.num_mem_refs 55938446 # number of memory refs
< system.cpu.num_load_insts 31855497 # Number of load instructions
< system.cpu.num_store_insts 24082949 # Number of store instructions
< system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles
< system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written
> system.cpu.num_mem_refs 55938603 # number of memory refs
> system.cpu.num_load_insts 31855595 # Number of load instructions
> system.cpu.num_store_insts 24083008 # Number of store instructions
> system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles
> system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles
310c184
< system.cpu.Branches 36396779 # Number of branches fetched
---
> system.cpu.Branches 36396923 # Number of branches fetched
312,313c186,187
< system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction
< system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction
> system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
341,342c215,216
< system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction
345c219
< system.cpu.op_class::total 177217756 # Class of executed instruction
---
> system.cpu.op_class::total 177218284 # Class of executed instruction
347a222,304
> system.cpu.dcache.tags.replacements 819396 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits
> system.cpu.dcache.overall_hits::total 52863618 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
> system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
> system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
> system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses
> system.cpu.dcache.overall_misses::total 814069 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
> system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks
> system.cpu.dcache.writebacks::total 682037 # number of writebacks
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
350c307
< system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks.
352c309
< system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks.
363,370c320,327
< system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits
< system.cpu.icache.overall_hits::total 145341254 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits
> system.cpu.icache.overall_hits::total 145341690 # number of overall hits
377,382c334,339
< system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses
399,400c356,357
< system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks.
402c359
< system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks.
404c361
< system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor
407,408c364,365
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor
425,426c382,383
< system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses
430,433c387,390
< system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits
436,437c393,394
< system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits
441,442c398,399
< system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits
446,447c403,404
< system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2348893 # number of overall hits
472,475c429,432
< system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses)
480,481c437,438
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
485,486c442,443
< system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses
490,491c447,448
< system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses
501,502c458,459
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses
506c463
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses
511c468
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses
524,608c481,482
< system.cpu.dcache.tags.replacements 819392 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits
< system.cpu.dcache.overall_hits::total 52863480 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
< system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
< system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
< system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
< system.cpu.dcache.overall_misses::total 814065 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
< system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks
< system.cpu.dcache.writebacks::total 682036 # number of writebacks
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
< system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution
611c485
< system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution
615,616c489,490
< system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
618c492
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes)
621c495
< system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes)
623c497
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes)
626c500
< system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes)
628c502
< system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram
637c511
< system.cpu.toL2Bus.snoop_fanout::5 3231951 98.88% 98.88% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram
642c516,571
< system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram
> system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
> system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
> system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
644c573
< system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
649c578
< system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor
---
> system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor
687a617,687
> system.membus.trans_dist::ReadReq 74235 # Transaction distribution
> system.membus.trans_dist::ReadResp 74235 # Transaction distribution
> system.membus.trans_dist::WriteReq 27560 # Transaction distribution
> system.membus.trans_dist::WriteResp 27560 # Transaction distribution
> system.membus.trans_dist::Writeback 101899 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
> system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
> system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 322858 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 322858 # Request fanout histogram
> system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
> system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
> system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
> system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
> system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
> system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
> system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
> system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
> system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
> system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
> system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
> system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
> system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
> system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
> system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
> system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
> system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
> system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
> system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
> system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
> system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
> system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
> system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
> system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
> system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
> system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
> system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
> system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
> system.realview.ethernet.droppedPackets 0 # number of packets dropped