3,5c3,5
< sim_seconds 2.783853 # Number of seconds simulated
< sim_ticks 2783853461500 # Number of ticks simulated
< final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.783854 # Number of seconds simulated
> sim_ticks 2783854177000 # Number of ticks simulated
> final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1369296 # Simulator instruction rate (inst/s)
< host_op_rate 1666897 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 26699855189 # Simulator tick rate (ticks/s)
< host_mem_usage 553552 # Number of bytes of host memory used
< host_seconds 104.26 # Real time elapsed on the host
< sim_insts 142769281 # Number of instructions simulated
< sim_ops 173798567 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1378246 # Simulator instruction rate (inst/s)
> host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26874016957 # Simulator tick rate (ticks/s)
> host_mem_usage 553624 # Number of bytes of host memory used
> host_seconds 103.59 # Real time elapsed on the host
> sim_insts 142771179 # Number of instructions simulated
> sim_ops 173800939 # Number of ops (including micro ops) simulated
24c24
< system.physmem.bytes_written::writebacks 6521472 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory
27c27
< system.physmem.bytes_written::total 8857332 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory
34c34
< system.physmem.num_writes::writebacks 101898 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory
37c37
< system.physmem.num_writes::total 142503 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory
42,43c42,43
< system.physmem.bw_read::cpu.data 3716392 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4151946 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s)
46c46
< system.physmem.bw_write::writebacks 2342606 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s)
49,50c49,50
< system.physmem.bw_write::total 3181680 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2342606 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s)
55,70c55,70
< system.physmem.bw_total::cpu.data 3722687 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 7333626 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 74236 # Transaction distribution
< system.membus.trans_dist::ReadResp 74236 # Transaction distribution
---
> system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
> system.membus.trans_dist::ReadReq 74235 # Transaction distribution
> system.membus.trans_dist::ReadResp 74235 # Transaction distribution
73c73
< system.membus.trans_dist::Writeback 101898 # Transaction distribution
---
> system.membus.trans_dist::Writeback 101899 # Transaction distribution
82c82
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
84,85c84,85
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606198 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
88c88
< system.membus.pkt_count::total 679126 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
90c90
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
92,93c92,93
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259463 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
96c96
< system.membus.pkt_size::total 20593159 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
98c98
< system.membus.snoop_fanout::samples 322857 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 322858 # Request fanout histogram
103c103
< system.membus.snoop_fanout::1 322857 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
108c108
< system.membus.snoop_fanout::total 322857 # Request fanout histogram
---
> system.membus.snoop_fanout::total 322858 # Request fanout histogram
225c225
< system.cpu.dtb.read_hits 31525428 # DTB read hits
---
> system.cpu.dtb.read_hits 31525864 # DTB read hits
227c227
< system.cpu.dtb.write_hits 23123837 # DTB write hits
---
> system.cpu.dtb.write_hits 23124034 # DTB write hits
238,239c238,239
< system.cpu.dtb.read_accesses 31534008 # DTB read accesses
< system.cpu.dtb.write_accesses 23125285 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534444 # DTB read accesses
> system.cpu.dtb.write_accesses 23125482 # DTB write accesses
241c241
< system.cpu.dtb.hits 54649265 # DTB hits
---
> system.cpu.dtb.hits 54649898 # DTB hits
243c243
< system.cpu.dtb.accesses 54659293 # DTB accesses
---
> system.cpu.dtb.accesses 54659926 # DTB accesses
265c265
< system.cpu.itb.inst_hits 147035651 # ITB inst hits
---
> system.cpu.itb.inst_hits 147037671 # ITB inst hits
282,283c282,283
< system.cpu.itb.inst_accesses 147040413 # ITB inst accesses
< system.cpu.itb.hits 147035651 # DTB hits
---
> system.cpu.itb.inst_accesses 147042433 # ITB inst accesses
> system.cpu.itb.hits 147037671 # DTB hits
285,286c285,286
< system.cpu.itb.accesses 147040413 # DTB accesses
< system.cpu.numCycles 5567710004 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 147042433 # DTB accesses
> system.cpu.numCycles 5567711435 # number of cpu cycles simulated
289,291c289,291
< system.cpu.committedInsts 142769281 # Number of instructions committed
< system.cpu.committedOps 173798567 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153158502 # Number of integer alu accesses
---
> system.cpu.committedInsts 142771179 # Number of instructions committed
> system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses
293,295c293,295
< system.cpu.num_func_calls 16873305 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730015 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153158502 # number of integer instructions
---
> system.cpu.num_func_calls 16873782 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153160639 # number of integer instructions
297,298c297,298
< system.cpu.num_int_register_reads 285052059 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107176408 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written
301,310c301,310
< system.cpu.num_cc_register_reads 530840054 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62363143 # number of times the CC registers were written
< system.cpu.num_mem_refs 55937812 # number of memory refs
< system.cpu.num_load_insts 31855061 # Number of load instructions
< system.cpu.num_store_insts 24082751 # Number of store instructions
< system.cpu.num_idle_cycles 5389631214.604722 # Number of idle cycles
< system.cpu.num_busy_cycles 178078789.395278 # Number of busy cycles
< system.cpu.not_idle_fraction 0.031984 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.968016 # Percentage of idle cycles
< system.cpu.Branches 36396067 # Number of branches fetched
---
> system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written
> system.cpu.num_mem_refs 55938446 # number of memory refs
> system.cpu.num_load_insts 31855497 # Number of load instructions
> system.cpu.num_store_insts 24082949 # Number of store instructions
> system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles
> system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles
> system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
> system.cpu.Branches 36396779 # Number of branches fetched
312,313c312,313
< system.cpu.op_class::IntAlu 121149664 68.36% 68.36% # Class of executed instruction
< system.cpu.op_class::IntMult 116881 0.07% 68.43% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction
> system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction
341,342c341,342
< system.cpu.op_class::MemRead 31855061 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24082751 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction
345c345
< system.cpu.op_class::total 177215263 # Class of executed instruction
---
> system.cpu.op_class::total 177217756 # Class of executed instruction
348c348
< system.cpu.icache.tags.replacements 1698994 # number of replacements
---
> system.cpu.icache.tags.replacements 1699006 # number of replacements
350,353c350,353
< system.cpu.icache.tags.total_refs 145339246 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit.
---
> system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
363,382c363,382
< system.cpu.icache.tags.tag_accesses 148738270 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148738270 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 145339246 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145339246 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145339246 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145339246 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145339246 # number of overall hits
< system.cpu.icache.overall_hits::total 145339246 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1699512 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1699512 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1699512 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1699512 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1699512 # number of overall misses
< system.cpu.icache.overall_misses::total 1699512 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 147038758 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147038758 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147038758 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits
> system.cpu.icache.overall_hits::total 145341254 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses
> system.cpu.icache.overall_misses::total 1699524 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses
399,400c399,400
< system.cpu.l2cache.tags.tagsinuse 65155.315266 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2727659 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks.
402c402
< system.cpu.l2cache.tags.avg_refs 15.559239 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks.
404c404
< system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414938 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor
407,408c407,408
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.653997 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309992 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor
425,426c425,426
< system.cpu.l2cache.tags.tag_accesses 26202376 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26202376 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses
429,433c429,433
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1681137 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 505491 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2197846 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 682038 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 682038 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits
436,437c436,437
< system.cpu.l2cache.ReadExReq_hits::cpu.data 151041 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 151041 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits
440,442c440,442
< system.cpu.l2cache.demand_hits::cpu.inst 1681137 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2348887 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits
445,447c445,447
< system.cpu.l2cache.overall_hits::cpu.inst 1681137 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2348887 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits
471,475c471,475
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699495 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 521025 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2231747 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 682038 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 682038 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses)
480,481c480,481
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 298905 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses)
484,486c484,486
< system.cpu.l2cache.demand_accesses::cpu.inst 1699495 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530652 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses
489,491c489,491
< system.cpu.l2cache.overall_accesses::cpu.inst 1699495 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530652 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses
495c495
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029814 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
501,502c501,502
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494686 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses
506c506
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses
511c511
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses
521,522c521,522
< system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
< system.cpu.l2cache.writebacks::total 101898 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks
> system.cpu.l2cache.writebacks::total 101899 # number of writebacks
524c524
< system.cpu.dcache.tags.replacements 819402 # number of replacements
---
> system.cpu.dcache.tags.replacements 819392 # number of replacements
526,529c526,529
< system.cpu.dcache.tags.total_refs 53783051 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.595966 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit.
---
> system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
538,545c538,545
< system.cpu.dcache.tags.tag_accesses 219231854 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219231854 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 30128262 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30128262 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22339512 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 395063 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 395063 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
550,559c550,559
< system.cpu.dcache.demand_hits::cpu.data 52467774 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52467774 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52862837 # number of overall hits
< system.cpu.dcache.overall_hits::total 52862837 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396291 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396291 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 301661 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 301661 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 116123 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 116123 # number of SoftPFReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits
> system.cpu.dcache.overall_hits::total 52863480 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
564,571c564,571
< system.cpu.dcache.demand_misses::cpu.data 697952 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697952 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
< system.cpu.dcache.overall_misses::total 814075 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30524553 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641173 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
> system.cpu.dcache.overall_misses::total 814065 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses)
578,587c578,587
< system.cpu.dcache.demand_accesses::cpu.data 53165726 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53676912 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53676912 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012983 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227164 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.227164 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
604,605c604,605
< system.cpu.dcache.writebacks::writebacks 682038 # number of writebacks
< system.cpu.dcache.writebacks::total 682038 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks
> system.cpu.dcache.writebacks::total 682036 # number of writebacks
611c611
< system.cpu.toL2Bus.trans_dist::Writeback 682038 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution
615,618c615,618
< system.cpu.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417070 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444678 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes)
622,623c622,623
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308747 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes)
626c626
< system.cpu.toL2Bus.pkt_size::total 205224459 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes)
644c644
< system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use
648,649c648,649
< system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor
< sim_seconds 2.783853 # Number of seconds simulated
< sim_ticks 2783853461500 # Number of ticks simulated
< final_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 2.783854 # Number of seconds simulated
> sim_ticks 2783854177000 # Number of ticks simulated
> final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1369296 # Simulator instruction rate (inst/s)
< host_op_rate 1666897 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 26699855189 # Simulator tick rate (ticks/s)
< host_mem_usage 553552 # Number of bytes of host memory used
< host_seconds 104.26 # Real time elapsed on the host
< sim_insts 142769281 # Number of instructions simulated
< sim_ops 173798567 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1378246 # Simulator instruction rate (inst/s)
> host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26874016957 # Simulator tick rate (ticks/s)
> host_mem_usage 553624 # Number of bytes of host memory used
> host_seconds 103.59 # Real time elapsed on the host
> sim_insts 142771179 # Number of instructions simulated
> sim_ops 173800939 # Number of ops (including micro ops) simulated
24c24
< system.physmem.bytes_written::writebacks 6521472 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory
27c27
< system.physmem.bytes_written::total 8857332 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory
34c34
< system.physmem.num_writes::writebacks 101898 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory
37c37
< system.physmem.num_writes::total 142503 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory
42,43c42,43
< system.physmem.bw_read::cpu.data 3716392 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 4151946 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s)
46c46
< system.physmem.bw_write::writebacks 2342606 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s)
49,50c49,50
< system.physmem.bw_write::total 3181680 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2342606 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s)
55,70c55,70
< system.physmem.bw_total::cpu.data 3722687 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 7333626 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory
< system.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory
< system.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory
< system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory
< system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
< system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
< system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 74236 # Transaction distribution
< system.membus.trans_dist::ReadResp 74236 # Transaction distribution
---
> system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
> system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
> system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
> system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
> system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
> system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
> system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
> system.membus.trans_dist::ReadReq 74235 # Transaction distribution
> system.membus.trans_dist::ReadResp 74235 # Transaction distribution
73c73
< system.membus.trans_dist::Writeback 101898 # Transaction distribution
---
> system.membus.trans_dist::Writeback 101899 # Transaction distribution
82c82
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
84,85c84,85
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606198 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
88c88
< system.membus.pkt_count::total 679126 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
90c90
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
92,93c92,93
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259463 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
96c96
< system.membus.pkt_size::total 20593159 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
98c98
< system.membus.snoop_fanout::samples 322857 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 322858 # Request fanout histogram
103c103
< system.membus.snoop_fanout::1 322857 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
108c108
< system.membus.snoop_fanout::total 322857 # Request fanout histogram
---
> system.membus.snoop_fanout::total 322858 # Request fanout histogram
225c225
< system.cpu.dtb.read_hits 31525428 # DTB read hits
---
> system.cpu.dtb.read_hits 31525864 # DTB read hits
227c227
< system.cpu.dtb.write_hits 23123837 # DTB write hits
---
> system.cpu.dtb.write_hits 23124034 # DTB write hits
238,239c238,239
< system.cpu.dtb.read_accesses 31534008 # DTB read accesses
< system.cpu.dtb.write_accesses 23125285 # DTB write accesses
---
> system.cpu.dtb.read_accesses 31534444 # DTB read accesses
> system.cpu.dtb.write_accesses 23125482 # DTB write accesses
241c241
< system.cpu.dtb.hits 54649265 # DTB hits
---
> system.cpu.dtb.hits 54649898 # DTB hits
243c243
< system.cpu.dtb.accesses 54659293 # DTB accesses
---
> system.cpu.dtb.accesses 54659926 # DTB accesses
265c265
< system.cpu.itb.inst_hits 147035651 # ITB inst hits
---
> system.cpu.itb.inst_hits 147037671 # ITB inst hits
282,283c282,283
< system.cpu.itb.inst_accesses 147040413 # ITB inst accesses
< system.cpu.itb.hits 147035651 # DTB hits
---
> system.cpu.itb.inst_accesses 147042433 # ITB inst accesses
> system.cpu.itb.hits 147037671 # DTB hits
285,286c285,286
< system.cpu.itb.accesses 147040413 # DTB accesses
< system.cpu.numCycles 5567710004 # number of cpu cycles simulated
---
> system.cpu.itb.accesses 147042433 # DTB accesses
> system.cpu.numCycles 5567711435 # number of cpu cycles simulated
289,291c289,291
< system.cpu.committedInsts 142769281 # Number of instructions committed
< system.cpu.committedOps 173798567 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 153158502 # Number of integer alu accesses
---
> system.cpu.committedInsts 142771179 # Number of instructions committed
> system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses
293,295c293,295
< system.cpu.num_func_calls 16873305 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 18730015 # number of instructions that are conditional controls
< system.cpu.num_int_insts 153158502 # number of integer instructions
---
> system.cpu.num_func_calls 16873782 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls
> system.cpu.num_int_insts 153160639 # number of integer instructions
297,298c297,298
< system.cpu.num_int_register_reads 285052059 # number of times the integer registers were read
< system.cpu.num_int_register_writes 107176408 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read
> system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written
301,310c301,310
< system.cpu.num_cc_register_reads 530840054 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 62363143 # number of times the CC registers were written
< system.cpu.num_mem_refs 55937812 # number of memory refs
< system.cpu.num_load_insts 31855061 # Number of load instructions
< system.cpu.num_store_insts 24082751 # Number of store instructions
< system.cpu.num_idle_cycles 5389631214.604722 # Number of idle cycles
< system.cpu.num_busy_cycles 178078789.395278 # Number of busy cycles
< system.cpu.not_idle_fraction 0.031984 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.968016 # Percentage of idle cycles
< system.cpu.Branches 36396067 # Number of branches fetched
---
> system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written
> system.cpu.num_mem_refs 55938446 # number of memory refs
> system.cpu.num_load_insts 31855497 # Number of load instructions
> system.cpu.num_store_insts 24082949 # Number of store instructions
> system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles
> system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles
> system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
> system.cpu.Branches 36396779 # Number of branches fetched
312,313c312,313
< system.cpu.op_class::IntAlu 121149664 68.36% 68.36% # Class of executed instruction
< system.cpu.op_class::IntMult 116881 0.07% 68.43% # Class of executed instruction
---
> system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction
> system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction
341,342c341,342
< system.cpu.op_class::MemRead 31855061 17.98% 86.41% # Class of executed instruction
< system.cpu.op_class::MemWrite 24082751 13.59% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction
> system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction
345c345
< system.cpu.op_class::total 177215263 # Class of executed instruction
---
> system.cpu.op_class::total 177217756 # Class of executed instruction
348c348
< system.cpu.icache.tags.replacements 1698994 # number of replacements
---
> system.cpu.icache.tags.replacements 1699006 # number of replacements
350,353c350,353
< system.cpu.icache.tags.total_refs 145339246 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit.
---
> system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
363,382c363,382
< system.cpu.icache.tags.tag_accesses 148738270 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 148738270 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 145339246 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 145339246 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 145339246 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 145339246 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 145339246 # number of overall hits
< system.cpu.icache.overall_hits::total 145339246 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1699512 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1699512 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1699512 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1699512 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1699512 # number of overall misses
< system.cpu.icache.overall_misses::total 1699512 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 147038758 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 147038758 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 147038758 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits
> system.cpu.icache.overall_hits::total 145341254 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses
> system.cpu.icache.overall_misses::total 1699524 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses
399,400c399,400
< system.cpu.l2cache.tags.tagsinuse 65155.315266 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2727659 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks.
402c402
< system.cpu.l2cache.tags.avg_refs 15.559239 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks.
404c404
< system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414938 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor
407,408c407,408
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.653997 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309992 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor
425,426c425,426
< system.cpu.l2cache.tags.tag_accesses 26202376 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 26202376 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses
429,433c429,433
< system.cpu.l2cache.ReadReq_hits::cpu.inst 1681137 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 505491 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2197846 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 682038 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 682038 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits
436,437c436,437
< system.cpu.l2cache.ReadExReq_hits::cpu.data 151041 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 151041 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits
440,442c440,442
< system.cpu.l2cache.demand_hits::cpu.inst 1681137 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2348887 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits
445,447c445,447
< system.cpu.l2cache.overall_hits::cpu.inst 1681137 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2348887 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits
471,475c471,475
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699495 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 521025 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2231747 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 682038 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 682038 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses)
480,481c480,481
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 298905 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses)
484,486c484,486
< system.cpu.l2cache.demand_accesses::cpu.inst 1699495 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2530652 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses
489,491c489,491
< system.cpu.l2cache.overall_accesses::cpu.inst 1699495 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2530652 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses
495c495
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029814 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
501,502c501,502
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494686 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses
506c506
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses
511c511
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses
521,522c521,522
< system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks
< system.cpu.l2cache.writebacks::total 101898 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks
> system.cpu.l2cache.writebacks::total 101899 # number of writebacks
524c524
< system.cpu.dcache.tags.replacements 819402 # number of replacements
---
> system.cpu.dcache.tags.replacements 819392 # number of replacements
526,529c526,529
< system.cpu.dcache.tags.total_refs 53783051 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 65.595966 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit.
---
> system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
538,545c538,545
< system.cpu.dcache.tags.tag_accesses 219231854 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 219231854 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 30128262 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 30128262 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 22339512 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 395063 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 395063 # number of SoftPFReq hits
---
> system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
550,559c550,559
< system.cpu.dcache.demand_hits::cpu.data 52467774 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 52467774 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 52862837 # number of overall hits
< system.cpu.dcache.overall_hits::total 52862837 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 396291 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 396291 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 301661 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 301661 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 116123 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 116123 # number of SoftPFReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits
> system.cpu.dcache.overall_hits::total 52863480 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
564,571c564,571
< system.cpu.dcache.demand_misses::cpu.data 697952 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 697952 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses
< system.cpu.dcache.overall_misses::total 814075 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 30524553 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 22641173 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses
> system.cpu.dcache.overall_misses::total 814065 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses)
578,587c578,587
< system.cpu.dcache.demand_accesses::cpu.data 53165726 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 53676912 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 53676912 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012983 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227164 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.227164 # miss rate for SoftPFReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
604,605c604,605
< system.cpu.dcache.writebacks::writebacks 682038 # number of writebacks
< system.cpu.dcache.writebacks::total 682038 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks
> system.cpu.dcache.writebacks::total 682036 # number of writebacks
611c611
< system.cpu.toL2Bus.trans_dist::Writeback 682038 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution
615,618c615,618
< system.cpu.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417070 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444678 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes)
622,623c622,623
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308747 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes)
626c626
< system.cpu.toL2Bus.pkt_size::total 205224459 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes)
644c644
< system.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use
648,649c648,649
< system.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor