1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.332810 # Number of seconds simulated
4sim_ticks 2332810264000 # Number of ticks simulated
5final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.332810 # Number of seconds simulated
4sim_ticks 2332810264000 # Number of ticks simulated
5final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1754227 # Simulator instruction rate (inst/s)
8host_op_rate 2255827 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 67743178392 # Simulator tick rate (ticks/s)
10host_mem_usage 394608 # Number of bytes of host memory used
11host_seconds 34.44 # Real time elapsed on the host
| 7host_inst_rate 993135 # Simulator instruction rate (inst/s)
8host_op_rate 1277110 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 38352024586 # Simulator tick rate (ticks/s)
10host_mem_usage 443324 # Number of bytes of host memory used
11host_seconds 60.83 # Real time elapsed on the host
|
12sim_insts 60408639 # Number of instructions simulated
13sim_ops 77681819 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory
19system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory
23system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
24system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory
25system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory
32system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
58system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
59system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
60system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
61system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
62system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
63system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
64system.membus.throughput 55969585 # Throughput (bytes/s)
65system.membus.data_through_bus 130566422 # Total data (bytes)
66system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
67system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
68system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
69system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
70system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
71system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
72system.cf0.dma_write_txs 0 # Number of DMA write transactions.
73system.iobus.throughput 48895252 # Throughput (bytes/s)
74system.iobus.data_through_bus 114063346 # Total data (bytes)
75system.cpu.dtb.inst_hits 0 # ITB inst hits
76system.cpu.dtb.inst_misses 0 # ITB inst misses
77system.cpu.dtb.read_hits 14971214 # DTB read hits
78system.cpu.dtb.read_misses 7294 # DTB read misses
79system.cpu.dtb.write_hits 11217004 # DTB write hits
80system.cpu.dtb.write_misses 2181 # DTB write misses
81system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
82system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
83system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
84system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
85system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB
86system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
87system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
88system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
89system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
90system.cpu.dtb.read_accesses 14978508 # DTB read accesses
91system.cpu.dtb.write_accesses 11219185 # DTB write accesses
92system.cpu.dtb.inst_accesses 0 # ITB inst accesses
93system.cpu.dtb.hits 26188218 # DTB hits
94system.cpu.dtb.misses 9475 # DTB misses
95system.cpu.dtb.accesses 26197693 # DTB accesses
96system.cpu.itb.inst_hits 61431840 # ITB inst hits
97system.cpu.itb.inst_misses 4471 # ITB inst misses
98system.cpu.itb.read_hits 0 # DTB read hits
99system.cpu.itb.read_misses 0 # DTB read misses
100system.cpu.itb.write_hits 0 # DTB write hits
101system.cpu.itb.write_misses 0 # DTB write misses
102system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
103system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
104system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
105system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
106system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
107system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
108system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
109system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
110system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
111system.cpu.itb.read_accesses 0 # DTB read accesses
112system.cpu.itb.write_accesses 0 # DTB write accesses
113system.cpu.itb.inst_accesses 61436311 # ITB inst accesses
114system.cpu.itb.hits 61431840 # DTB hits
115system.cpu.itb.misses 4471 # DTB misses
116system.cpu.itb.accesses 61436311 # DTB accesses
| 12sim_insts 60408639 # Number of instructions simulated
13sim_ops 77681819 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory
19system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory
23system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
24system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory
25system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory
30system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory
31system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory
32system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory
34system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s)
52system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
53system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
54system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
55system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
56system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
57system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
58system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
59system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
60system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
61system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
62system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
63system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
64system.membus.throughput 55969585 # Throughput (bytes/s)
65system.membus.data_through_bus 130566422 # Total data (bytes)
66system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
67system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
68system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
69system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
70system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
71system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
72system.cf0.dma_write_txs 0 # Number of DMA write transactions.
73system.iobus.throughput 48895252 # Throughput (bytes/s)
74system.iobus.data_through_bus 114063346 # Total data (bytes)
75system.cpu.dtb.inst_hits 0 # ITB inst hits
76system.cpu.dtb.inst_misses 0 # ITB inst misses
77system.cpu.dtb.read_hits 14971214 # DTB read hits
78system.cpu.dtb.read_misses 7294 # DTB read misses
79system.cpu.dtb.write_hits 11217004 # DTB write hits
80system.cpu.dtb.write_misses 2181 # DTB write misses
81system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
82system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
83system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
84system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
85system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB
86system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
87system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
88system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
89system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
90system.cpu.dtb.read_accesses 14978508 # DTB read accesses
91system.cpu.dtb.write_accesses 11219185 # DTB write accesses
92system.cpu.dtb.inst_accesses 0 # ITB inst accesses
93system.cpu.dtb.hits 26188218 # DTB hits
94system.cpu.dtb.misses 9475 # DTB misses
95system.cpu.dtb.accesses 26197693 # DTB accesses
96system.cpu.itb.inst_hits 61431840 # ITB inst hits
97system.cpu.itb.inst_misses 4471 # ITB inst misses
98system.cpu.itb.read_hits 0 # DTB read hits
99system.cpu.itb.read_misses 0 # DTB read misses
100system.cpu.itb.write_hits 0 # DTB write hits
101system.cpu.itb.write_misses 0 # DTB write misses
102system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
103system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
104system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
105system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
106system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
107system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
108system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
109system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
110system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
111system.cpu.itb.read_accesses 0 # DTB read accesses
112system.cpu.itb.write_accesses 0 # DTB write accesses
113system.cpu.itb.inst_accesses 61436311 # ITB inst accesses
114system.cpu.itb.hits 61431840 # DTB hits
115system.cpu.itb.misses 4471 # DTB misses
116system.cpu.itb.accesses 61436311 # DTB accesses
|
117system.cpu.numCycles 4665543516 # number of cpu cycles simulated
| 117system.cpu.numCycles 4665620529 # number of cpu cycles simulated
|
118system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
119system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
120system.cpu.committedInsts 60408639 # Number of instructions committed
121system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed
122system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses
123system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
124system.cpu.num_func_calls 2136008 # number of times a function call or return occured
125system.cpu.num_conditional_control_insts 7942113 # number of instructions that are conditional controls
126system.cpu.num_int_insts 68795605 # number of integer instructions
127system.cpu.num_fp_insts 10269 # number of float instructions
128system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read
129system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written
130system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
131system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
132system.cpu.num_mem_refs 27361637 # number of memory refs
133system.cpu.num_load_insts 15639527 # Number of load instructions
134system.cpu.num_store_insts 11722110 # Number of store instructions
| 118system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
119system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
120system.cpu.committedInsts 60408639 # Number of instructions committed
121system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed
122system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses
123system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
124system.cpu.num_func_calls 2136008 # number of times a function call or return occured
125system.cpu.num_conditional_control_insts 7942113 # number of instructions that are conditional controls
126system.cpu.num_int_insts 68795605 # number of integer instructions
127system.cpu.num_fp_insts 10269 # number of float instructions
128system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read
129system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written
130system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
131system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
132system.cpu.num_mem_refs 27361637 # number of memory refs
133system.cpu.num_load_insts 15639527 # Number of load instructions
134system.cpu.num_store_insts 11722110 # Number of store instructions
|
135system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles
136system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles
| 135system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles
136system.cpu.num_busy_cycles 78798455.992855 # Number of busy cycles
|
137system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles
138system.cpu.idle_fraction 0.983111 # Percentage of idle cycles
139system.cpu.kern.inst.arm 0 # number of arm instructions executed
140system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
141system.cpu.icache.tags.replacements 850590 # number of replacements
142system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use
143system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
144system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
145system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
146system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
147system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor
148system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
149system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
150system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits
151system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
152system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits
153system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits
154system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits
155system.cpu.icache.overall_hits::total 60583498 # number of overall hits
156system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses
157system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses
158system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses
159system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses
160system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses
161system.cpu.icache.overall_misses::total 851102 # number of overall misses
162system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses)
163system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses)
164system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses
165system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
166system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses
167system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
168system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses
169system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses
170system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses
171system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses
172system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses
173system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses
174system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
175system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
176system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
177system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
178system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
179system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
180system.cpu.icache.fast_writes 0 # number of fast writes performed
181system.cpu.icache.cache_copies 0 # number of cache copies performed
182system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
183system.cpu.l2cache.tags.replacements 62243 # number of replacements
184system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use
185system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks.
186system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks.
187system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks.
188system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
189system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
190system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
191system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
192system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
193system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
194system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
195system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
196system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
197system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
198system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
199system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy
200system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
201system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
202system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
203system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
204system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits
205system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits
206system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits
207system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
208system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
209system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
210system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits
211system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
212system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
213system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
214system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits
215system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits
216system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits
217system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits
218system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits
219system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits
220system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits
221system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
222system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
223system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
224system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
225system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses
226system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
227system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
228system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
229system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses
230system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
231system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
232system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
233system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses
234system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses
235system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
236system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
237system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
238system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses
239system.cpu.l2cache.overall_misses::total 153951 # number of overall misses
240system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
241system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
242system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
243system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
244system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
245system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
246system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
247system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
248system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
249system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
250system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
251system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
252system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
253system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
254system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
255system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses
256system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
257system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
258system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
259system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
260system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses
261system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
262system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
263system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
264system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
265system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
266system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
267system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
268system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
269system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
270system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
271system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
272system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
273system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
274system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses
275system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
276system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
277system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
278system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
279system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses
280system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
281system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
282system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
283system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
284system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
285system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
286system.cpu.l2cache.fast_writes 0 # number of fast writes performed
287system.cpu.l2cache.cache_copies 0 # number of cache copies performed
288system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
289system.cpu.l2cache.writebacks::total 57863 # number of writebacks
290system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
291system.cpu.dcache.tags.replacements 623337 # number of replacements
292system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use
293system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks.
294system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks.
295system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks.
296system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
297system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
298system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
299system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
300system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
301system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
302system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
303system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
304system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
305system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
306system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
307system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
308system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
309system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
310system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
311system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
312system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
313system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
314system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
315system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
316system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
317system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
318system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
319system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
320system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
321system.cpu.dcache.overall_misses::total 615611 # number of overall misses
322system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
323system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
324system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
325system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
326system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
327system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
328system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
329system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
330system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
331system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
332system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
333system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
334system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
335system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
336system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
337system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
338system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
339system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
340system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
341system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
342system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
343system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
344system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
345system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
346system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
347system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
348system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
349system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
350system.cpu.dcache.fast_writes 0 # number of fast writes performed
351system.cpu.dcache.cache_copies 0 # number of cache copies performed
352system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
353system.cpu.dcache.writebacks::total 592643 # number of writebacks
354system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
355system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s)
356system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes)
357system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
358system.iocache.tags.replacements 0 # number of replacements
359system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
360system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
361system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
362system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
363system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
364system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
365system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
366system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
367system.iocache.blocked::no_targets 0 # number of cycles access was blocked
368system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
369system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
370system.iocache.fast_writes 0 # number of fast writes performed
371system.iocache.cache_copies 0 # number of cache copies performed
372system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
373
374---------- End Simulation Statistics ----------
| 137system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles
138system.cpu.idle_fraction 0.983111 # Percentage of idle cycles
139system.cpu.kern.inst.arm 0 # number of arm instructions executed
140system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
141system.cpu.icache.tags.replacements 850590 # number of replacements
142system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use
143system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks.
144system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
145system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks.
146system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit.
147system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor
148system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
149system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
150system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits
151system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits
152system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits
153system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits
154system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits
155system.cpu.icache.overall_hits::total 60583498 # number of overall hits
156system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses
157system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses
158system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses
159system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses
160system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses
161system.cpu.icache.overall_misses::total 851102 # number of overall misses
162system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses)
163system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses)
164system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses
165system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses
166system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses
167system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses
168system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses
169system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses
170system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses
171system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses
172system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses
173system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses
174system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
175system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
176system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
177system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
178system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
179system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
180system.cpu.icache.fast_writes 0 # number of fast writes performed
181system.cpu.icache.cache_copies 0 # number of cache copies performed
182system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
183system.cpu.l2cache.tags.replacements 62243 # number of replacements
184system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use
185system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks.
186system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks.
187system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks.
188system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit.
189system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor
190system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor
191system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
192system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor
193system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor
194system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy
195system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
196system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
197system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy
198system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy
199system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy
200system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits
201system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits
202system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits
203system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits
204system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits
205system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits
206system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits
207system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
208system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
209system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits
210system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits
211system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits
212system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits
213system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits
214system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits
215system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits
216system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits
217system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits
218system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits
219system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits
220system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits
221system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
222system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
223system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses
224system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
225system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses
226system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses
227system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses
228system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses
229system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses
230system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
231system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
232system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses
233system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses
234system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses
235system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
236system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
237system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses
238system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses
239system.cpu.l2cache.overall_misses::total 153951 # number of overall misses
240system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses)
241system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses)
242system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses)
243system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses)
244system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses)
245system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses)
246system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses)
247system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses)
248system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses)
249system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses)
250system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses)
251system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses
252system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses
253system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses
254system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses
255system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses
256system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses
257system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses
258system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses
259system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses
260system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses
261system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
262system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
263system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
264system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses
265system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses
266system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
267system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses
268system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses
269system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses
270system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
271system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
272system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
273system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses
274system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses
275system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
276system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
277system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
278system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses
279system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses
280system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
281system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
282system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
283system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
284system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
285system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
286system.cpu.l2cache.fast_writes 0 # number of fast writes performed
287system.cpu.l2cache.cache_copies 0 # number of cache copies performed
288system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
289system.cpu.l2cache.writebacks::total 57863 # number of writebacks
290system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
291system.cpu.dcache.tags.replacements 623337 # number of replacements
292system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use
293system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks.
294system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks.
295system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks.
296system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
297system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
298system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
299system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
300system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
301system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
302system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
303system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
304system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
305system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
306system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
307system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
308system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
309system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
310system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
311system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
312system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
313system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
314system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
315system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
316system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
317system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
318system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
319system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
320system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
321system.cpu.dcache.overall_misses::total 615611 # number of overall misses
322system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
323system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
324system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
325system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
326system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
327system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
328system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
329system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
330system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
331system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
332system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
333system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
334system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
335system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
336system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
337system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
338system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
339system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
340system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
341system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
342system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
343system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
344system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
345system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
346system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
347system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
348system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
349system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
350system.cpu.dcache.fast_writes 0 # number of fast writes performed
351system.cpu.dcache.cache_copies 0 # number of cache copies performed
352system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
353system.cpu.dcache.writebacks::total 592643 # number of writebacks
354system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
355system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s)
356system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes)
357system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
358system.iocache.tags.replacements 0 # number of replacements
359system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
360system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
361system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
362system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
363system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
364system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
365system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
366system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
367system.iocache.blocked::no_targets 0 # number of cycles access was blocked
368system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
369system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
370system.iocache.fast_writes 0 # number of fast writes performed
371system.iocache.cache_copies 0 # number of cache copies performed
372system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
373
374---------- End Simulation Statistics ----------
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