12sim_insts 142771202 # Number of instructions simulated 13sim_ops 173801044 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 27system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s) 55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 56system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 57system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 58system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 59system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 60system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 61system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 62system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 67system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 68system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 69system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 70system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 71system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 72system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 73system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 74system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 75system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 76system.cf0.dma_write_txs 631 # Number of DMA write transactions. 77system.cpu_clk_domain.clock 500 # Clock period in ticks 78system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 79system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 81system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 82system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 83system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 87system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 88system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 89system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 90system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 91system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 92system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 93system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 94system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 95system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 96system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 97system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 98system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 99system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 100system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 101system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 102system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 103system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 104system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 105system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 106system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 107system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 108system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 109system.cpu.dtb.walker.walks 10028 # Table walker walks requested 110system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors 111system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency 112system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency 113system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency 114system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 115system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 116system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 117system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated 118system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated 119system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated 120system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst 121system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 122system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst 123system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst 124system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 125system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst 126system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst 127system.cpu.dtb.inst_hits 0 # ITB inst hits 128system.cpu.dtb.inst_misses 0 # ITB inst misses 129system.cpu.dtb.read_hits 31525882 # DTB read hits 130system.cpu.dtb.read_misses 8580 # DTB read misses 131system.cpu.dtb.write_hits 23124079 # DTB write hits 132system.cpu.dtb.write_misses 1448 # DTB write misses 133system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 134system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 135system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 136system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 137system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB 138system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 139system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 140system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 141system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 142system.cpu.dtb.read_accesses 31534462 # DTB read accesses 143system.cpu.dtb.write_accesses 23125527 # DTB write accesses 144system.cpu.dtb.inst_accesses 0 # ITB inst accesses 145system.cpu.dtb.hits 54649961 # DTB hits 146system.cpu.dtb.misses 10028 # DTB misses 147system.cpu.dtb.accesses 54659989 # DTB accesses 148system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 149system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 150system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 151system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 152system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 153system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 157system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 158system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 159system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 160system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 161system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 162system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 163system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 164system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 165system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 166system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 167system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 168system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 169system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 170system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 171system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 172system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 173system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 174system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 175system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 176system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 177system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 178system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 179system.cpu.itb.walker.walks 4762 # Table walker walks requested 180system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 181system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 182system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 183system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 184system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 185system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 186system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 187system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 188system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 189system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated 190system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 191system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 192system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst 193system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 194system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 195system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 196system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst 197system.cpu.itb.inst_hits 147037694 # ITB inst hits 198system.cpu.itb.inst_misses 4762 # ITB inst misses 199system.cpu.itb.read_hits 0 # DTB read hits 200system.cpu.itb.read_misses 0 # DTB read misses 201system.cpu.itb.write_hits 0 # DTB write hits 202system.cpu.itb.write_misses 0 # DTB write misses 203system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 204system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 205system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 206system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 207system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB 208system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 209system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 210system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 211system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 212system.cpu.itb.read_accesses 0 # DTB read accesses 213system.cpu.itb.write_accesses 0 # DTB write accesses 214system.cpu.itb.inst_accesses 147042456 # ITB inst accesses 215system.cpu.itb.hits 147037694 # DTB hits 216system.cpu.itb.misses 4762 # DTB misses 217system.cpu.itb.accesses 147042456 # DTB accesses 218system.cpu.numPwrStateTransitions 6160 # Number of power state transitions 219system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state 220system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state 221system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state 222system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state 223system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state 224system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 225system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 226system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 227system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 228system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 229system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state 230system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state 231system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states 232system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states 233system.cpu.numCycles 5567712511 # number of cpu cycles simulated 234system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 235system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 236system.cpu.kern.inst.arm 0 # number of arm instructions executed 237system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 238system.cpu.committedInsts 142771202 # Number of instructions committed 239system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed 240system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses 241system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 242system.cpu.num_func_calls 16873864 # number of times a function call or return occured 243system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls 244system.cpu.num_int_insts 153160791 # number of integer instructions 245system.cpu.num_fp_insts 11484 # number of float instructions 246system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read 247system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written 248system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 249system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 250system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read 251system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written 252system.cpu.num_mem_refs 55938510 # number of memory refs 253system.cpu.num_load_insts 31855508 # Number of load instructions 254system.cpu.num_store_insts 24083002 # Number of store instructions 255system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles 256system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles 257system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 258system.cpu.idle_fraction 0.968015 # Percentage of idle cycles 259system.cpu.Branches 36396820 # Number of branches fetched 260system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 261system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction 262system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction 263system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 264system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 265system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 266system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 267system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction
| 12sim_insts 142771202 # Number of instructions simulated 13sim_ops 173801044 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 22system.physmem.bytes_read::total 11533320 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 27system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 189181 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s) 55system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 56system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 57system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 58system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 59system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 60system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 61system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 62system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 67system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 68system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 69system.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 70system.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 71system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 72system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 73system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 74system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 75system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 76system.cf0.dma_write_txs 631 # Number of DMA write transactions. 77system.cpu_clk_domain.clock 500 # Clock period in ticks 78system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 79system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 80system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 81system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 82system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 83system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 84system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 85system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 86system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 87system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 88system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 89system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 90system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 91system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 92system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 93system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 94system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 95system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 96system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 97system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 98system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 99system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 100system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 101system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 102system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 103system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 104system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 105system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 106system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 107system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 108system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 109system.cpu.dtb.walker.walks 10028 # Table walker walks requested 110system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors 111system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency 112system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency 113system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency 114system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 115system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 116system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 117system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated 118system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated 119system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated 120system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst 121system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 122system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst 123system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst 124system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 125system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst 126system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst 127system.cpu.dtb.inst_hits 0 # ITB inst hits 128system.cpu.dtb.inst_misses 0 # ITB inst misses 129system.cpu.dtb.read_hits 31525882 # DTB read hits 130system.cpu.dtb.read_misses 8580 # DTB read misses 131system.cpu.dtb.write_hits 23124079 # DTB write hits 132system.cpu.dtb.write_misses 1448 # DTB write misses 133system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 134system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 135system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 136system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 137system.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB 138system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 139system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 140system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 141system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 142system.cpu.dtb.read_accesses 31534462 # DTB read accesses 143system.cpu.dtb.write_accesses 23125527 # DTB write accesses 144system.cpu.dtb.inst_accesses 0 # ITB inst accesses 145system.cpu.dtb.hits 54649961 # DTB hits 146system.cpu.dtb.misses 10028 # DTB misses 147system.cpu.dtb.accesses 54659989 # DTB accesses 148system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 149system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 150system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 151system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 152system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 153system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 154system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 155system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 156system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 157system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 158system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 159system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 160system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 161system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 162system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 163system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 164system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 165system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 166system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 167system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 168system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 169system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 170system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 171system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 172system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 173system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 174system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 175system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 176system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 177system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 178system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 179system.cpu.itb.walker.walks 4762 # Table walker walks requested 180system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 181system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 182system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 183system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 184system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 185system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 186system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 187system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 188system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 189system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated 190system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 191system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 192system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst 193system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 194system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 195system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 196system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst 197system.cpu.itb.inst_hits 147037694 # ITB inst hits 198system.cpu.itb.inst_misses 4762 # ITB inst misses 199system.cpu.itb.read_hits 0 # DTB read hits 200system.cpu.itb.read_misses 0 # DTB read misses 201system.cpu.itb.write_hits 0 # DTB write hits 202system.cpu.itb.write_misses 0 # DTB write misses 203system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 204system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 205system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 206system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 207system.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB 208system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 209system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 210system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 211system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 212system.cpu.itb.read_accesses 0 # DTB read accesses 213system.cpu.itb.write_accesses 0 # DTB write accesses 214system.cpu.itb.inst_accesses 147042456 # ITB inst accesses 215system.cpu.itb.hits 147037694 # DTB hits 216system.cpu.itb.misses 4762 # DTB misses 217system.cpu.itb.accesses 147042456 # DTB accesses 218system.cpu.numPwrStateTransitions 6160 # Number of power state transitions 219system.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state 220system.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state 221system.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state 222system.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state 223system.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state 224system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 225system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 226system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 227system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 228system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 229system.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state 230system.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state 231system.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states 232system.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states 233system.cpu.numCycles 5567712511 # number of cpu cycles simulated 234system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 235system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 236system.cpu.kern.inst.arm 0 # number of arm instructions executed 237system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 238system.cpu.committedInsts 142771202 # Number of instructions committed 239system.cpu.committedOps 173801044 # Number of ops (including micro ops) committed 240system.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses 241system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 242system.cpu.num_func_calls 16873864 # number of times a function call or return occured 243system.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls 244system.cpu.num_int_insts 153160791 # number of integer instructions 245system.cpu.num_fp_insts 11484 # number of float instructions 246system.cpu.num_int_register_reads 285043206 # number of times the integer registers were read 247system.cpu.num_int_register_writes 107178068 # number of times the integer registers were written 248system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 249system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 250system.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read 251system.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written 252system.cpu.num_mem_refs 55938510 # number of memory refs 253system.cpu.num_load_insts 31855508 # Number of load instructions 254system.cpu.num_store_insts 24083002 # Number of store instructions 255system.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles 256system.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles 257system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 258system.cpu.idle_fraction 0.968015 # Percentage of idle cycles 259system.cpu.Branches 36396820 # Number of branches fetched 260system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 261system.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction 262system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction 263system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 264system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 265system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 266system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 267system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction
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