1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.321351 # Number of seconds simulated
4sim_ticks 2321351025500 # Number of ticks simulated
5final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 818788 # Simulator instruction rate (inst/s)
8host_op_rate 985991 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 31464875718 # Simulator tick rate (ticks/s)
10host_mem_usage 430844 # Number of bytes of host memory used
11host_seconds 73.78 # Real time elapsed on the host
12sim_insts 60406834 # Number of instructions simulated
13sim_ops 72742429 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 705416 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 9071832 # Number of bytes read from this memory
21system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 705416 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory
--- 4 unchanged lines hidden (view full) ---
28system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 17234 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 141773 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory
36system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s)
54system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
55system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
56system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
57system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
58system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
59system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
60system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
61system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
62system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
63system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
64system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
65system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
66system.membus.throughput 55568847 # Throughput (bytes/s)
67system.membus.data_through_bus 128994799 # Total data (bytes)
68system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
69system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
70system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
71system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
72system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
73system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
74system.cf0.dma_write_txs 0 # Number of DMA write transactions.
75system.iobus.throughput 48459111 # Throughput (bytes/s)
76system.iobus.data_through_bus 112490607 # Total data (bytes)
77system.cpu_clk_domain.clock 500 # Clock period in ticks
78system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
79system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
80system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
81system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
82system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
83system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
84system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
--- 8 unchanged lines hidden (view full) ---
93system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
94system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
95system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
96system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
97system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
98system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
99system.cpu.dtb.inst_hits 0 # ITB inst hits
100system.cpu.dtb.inst_misses 0 # ITB inst misses
101system.cpu.dtb.read_hits 13142244 # DTB read hits
102system.cpu.dtb.read_misses 7297 # DTB read misses
103system.cpu.dtb.write_hits 11216207 # DTB write hits
104system.cpu.dtb.write_misses 2181 # DTB write misses
105system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
106system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
107system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
108system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
109system.cpu.dtb.flush_entries 3399 # Number of entries that have been flushed from TLB
110system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
111system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
112system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
113system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
114system.cpu.dtb.read_accesses 13149541 # DTB read accesses
115system.cpu.dtb.write_accesses 11218388 # DTB write accesses
116system.cpu.dtb.inst_accesses 0 # ITB inst accesses
117system.cpu.dtb.hits 24358451 # DTB hits
118system.cpu.dtb.misses 9478 # DTB misses
119system.cpu.dtb.accesses 24367929 # DTB accesses
120system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
121system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
122system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
123system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
124system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
125system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
126system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
127system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 26 unchanged lines hidden (view full) ---
154system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
156system.cpu.itb.read_accesses 0 # DTB read accesses
157system.cpu.itb.write_accesses 0 # DTB write accesses
158system.cpu.itb.inst_accesses 61434478 # ITB inst accesses
159system.cpu.itb.hits 61430007 # DTB hits
160system.cpu.itb.misses 4471 # DTB misses
161system.cpu.itb.accesses 61434478 # DTB accesses
162system.cpu.numCycles 4642702052 # number of cpu cycles simulated
163system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
164system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
165system.cpu.committedInsts 60406834 # Number of instructions committed
166system.cpu.committedOps 72742429 # Number of ops (including micro ops) committed
167system.cpu.num_int_alu_accesses 64191430 # Number of integer alu accesses
168system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
169system.cpu.num_func_calls 2135762 # number of times a function call or return occured
170system.cpu.num_conditional_control_insts 7544984 # number of instructions that are conditional controls
171system.cpu.num_int_insts 64191430 # number of integer instructions
172system.cpu.num_fp_insts 10269 # number of float instructions
173system.cpu.num_int_register_reads 116427347 # number of times the integer registers were read
174system.cpu.num_int_register_writes 42818107 # number of times the integer registers were written
175system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
176system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
177system.cpu.num_cc_register_reads 217570004 # number of times the CC registers were read
178system.cpu.num_cc_register_writes 28977741 # number of times the CC registers were written
179system.cpu.num_mem_refs 25221274 # number of memory refs
180system.cpu.num_load_insts 13499937 # Number of load instructions
181system.cpu.num_store_insts 11721337 # Number of store instructions
182system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles
183system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles
184system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles
185system.cpu.idle_fraction 0.984091 # Percentage of idle cycles
186system.cpu.Branches 10298517 # Number of branches fetched
187system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
188system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction
189system.cpu.op_class::IntMult 87771 0.12% 65.39% # Class of executed instruction
190system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction
191system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction
192system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction
193system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction
--- 22 unchanged lines hidden (view full) ---
216system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction
217system.cpu.op_class::MemRead 13499937 18.52% 83.92% # Class of executed instruction
218system.cpu.op_class::MemWrite 11721337 16.08% 100.00% # Class of executed instruction
219system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
220system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
221system.cpu.op_class::total 72875708 # Class of executed instruction
222system.cpu.kern.inst.arm 0 # number of arm instructions executed
223system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed
224system.cpu.icache.tags.replacements 850515 # number of replacements
225system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use
226system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks.
227system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks.
228system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks.
229system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit.
230system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor
231system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy
232system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy
233system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
234system.cpu.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
235system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
236system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id
237system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
238system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
239system.cpu.icache.tags.tag_accesses 62283794 # Number of tag accesses
240system.cpu.icache.tags.data_accesses 62283794 # Number of data accesses
241system.cpu.icache.ReadReq_hits::cpu.inst 60581740 # number of ReadReq hits
242system.cpu.icache.ReadReq_hits::total 60581740 # number of ReadReq hits
243system.cpu.icache.demand_hits::cpu.inst 60581740 # number of demand (read+write) hits
244system.cpu.icache.demand_hits::total 60581740 # number of demand (read+write) hits
245system.cpu.icache.overall_hits::cpu.inst 60581740 # number of overall hits
246system.cpu.icache.overall_hits::total 60581740 # number of overall hits
247system.cpu.icache.ReadReq_misses::cpu.inst 851027 # number of ReadReq misses
248system.cpu.icache.ReadReq_misses::total 851027 # number of ReadReq misses
249system.cpu.icache.demand_misses::cpu.inst 851027 # number of demand (read+write) misses
250system.cpu.icache.demand_misses::total 851027 # number of demand (read+write) misses
251system.cpu.icache.overall_misses::cpu.inst 851027 # number of overall misses
252system.cpu.icache.overall_misses::total 851027 # number of overall misses
253system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses)
254system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses)
255system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses
256system.cpu.icache.demand_accesses::total 61432767 # number of demand (read+write) accesses
257system.cpu.icache.overall_accesses::cpu.inst 61432767 # number of overall (read+write) accesses
258system.cpu.icache.overall_accesses::total 61432767 # number of overall (read+write) accesses
259system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013853 # miss rate for ReadReq accesses
260system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses
--- 6 unchanged lines hidden (view full) ---
267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
271system.cpu.icache.fast_writes 0 # number of fast writes performed
272system.cpu.icache.cache_copies 0 # number of cache copies performed
273system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
274system.cpu.l2cache.tags.replacements 62250 # number of replacements
275system.cpu.l2cache.tags.tagsinuse 50006.834636 # Cycle average of tags in use
276system.cpu.l2cache.tags.total_refs 1669916 # Total number of references to valid blocks.
277system.cpu.l2cache.tags.sampled_refs 127635 # Sample count of references to valid blocks.
278system.cpu.l2cache.tags.avg_refs 13.083527 # Average number of references to valid blocks.
279system.cpu.l2cache.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit.
280system.cpu.l2cache.tags.occ_blocks::writebacks 36897.866975 # Average occupied blocks per requestor
281system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959775 # Average occupied blocks per requestor
282system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993971 # Average occupied blocks per requestor
283system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.476656 # Average occupied blocks per requestor
284system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.537259 # Average occupied blocks per requestor
285system.cpu.l2cache.tags.occ_percent::writebacks 0.563017 # Average percentage of cache occupancy
286system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
287system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
288system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107032 # Average percentage of cache occupancy
289system.cpu.l2cache.tags.occ_percent::cpu.data 0.092934 # Average percentage of cache occupancy
290system.cpu.l2cache.tags.occ_percent::total 0.763044 # Average percentage of cache occupancy
291system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
292system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id
293system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
294system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
295system.cpu.l2cache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
296system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3672 # Occupied blocks per task id
297system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9281 # Occupied blocks per task id
298system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52125 # Occupied blocks per task id
299system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
300system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id
301system.cpu.l2cache.tags.tag_accesses 17035648 # Number of tag accesses
302system.cpu.l2cache.tags.data_accesses 17035648 # Number of data accesses
303system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7541 # number of ReadReq hits
304system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits
305system.cpu.l2cache.ReadReq_hits::cpu.inst 838793 # number of ReadReq hits
306system.cpu.l2cache.ReadReq_hits::cpu.data 366790 # number of ReadReq hits
307system.cpu.l2cache.ReadReq_hits::total 1216275 # number of ReadReq hits
308system.cpu.l2cache.Writeback_hits::writebacks 592642 # number of Writeback hits
309system.cpu.l2cache.Writeback_hits::total 592642 # number of Writeback hits
310system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
311system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
312system.cpu.l2cache.ReadExReq_hits::cpu.data 113706 # number of ReadExReq hits
313system.cpu.l2cache.ReadExReq_hits::total 113706 # number of ReadExReq hits
314system.cpu.l2cache.demand_hits::cpu.dtb.walker 7541 # number of demand (read+write) hits
315system.cpu.l2cache.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits
316system.cpu.l2cache.demand_hits::cpu.inst 838793 # number of demand (read+write) hits
317system.cpu.l2cache.demand_hits::cpu.data 480496 # number of demand (read+write) hits
318system.cpu.l2cache.demand_hits::total 1329981 # number of demand (read+write) hits
319system.cpu.l2cache.overall_hits::cpu.dtb.walker 7541 # number of overall hits
320system.cpu.l2cache.overall_hits::cpu.itb.walker 3151 # number of overall hits
321system.cpu.l2cache.overall_hits::cpu.inst 838793 # number of overall hits
322system.cpu.l2cache.overall_hits::cpu.data 480496 # number of overall hits
323system.cpu.l2cache.overall_hits::total 1329981 # number of overall hits
324system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
325system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
326system.cpu.l2cache.ReadReq_misses::cpu.inst 10608 # number of ReadReq misses
327system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
328system.cpu.l2cache.ReadReq_misses::total 20487 # number of ReadReq misses
329system.cpu.l2cache.UpgradeReq_misses::cpu.data 2917 # number of UpgradeReq misses
330system.cpu.l2cache.UpgradeReq_misses::total 2917 # number of UpgradeReq misses
331system.cpu.l2cache.ReadExReq_misses::cpu.data 133474 # number of ReadExReq misses
332system.cpu.l2cache.ReadExReq_misses::total 133474 # number of ReadExReq misses
333system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
334system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
335system.cpu.l2cache.demand_misses::cpu.inst 10608 # number of demand (read+write) misses
336system.cpu.l2cache.demand_misses::cpu.data 143345 # number of demand (read+write) misses
337system.cpu.l2cache.demand_misses::total 153961 # number of demand (read+write) misses
338system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
339system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
340system.cpu.l2cache.overall_misses::cpu.inst 10608 # number of overall misses
341system.cpu.l2cache.overall_misses::cpu.data 143345 # number of overall misses
342system.cpu.l2cache.overall_misses::total 153961 # number of overall misses
343system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7546 # number of ReadReq accesses(hits+misses)
344system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
345system.cpu.l2cache.ReadReq_accesses::cpu.inst 849401 # number of ReadReq accesses(hits+misses)
346system.cpu.l2cache.ReadReq_accesses::cpu.data 376661 # number of ReadReq accesses(hits+misses)
347system.cpu.l2cache.ReadReq_accesses::total 1236762 # number of ReadReq accesses(hits+misses)
348system.cpu.l2cache.Writeback_accesses::writebacks 592642 # number of Writeback accesses(hits+misses)
349system.cpu.l2cache.Writeback_accesses::total 592642 # number of Writeback accesses(hits+misses)
350system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2943 # number of UpgradeReq accesses(hits+misses)
351system.cpu.l2cache.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses)
352system.cpu.l2cache.ReadExReq_accesses::cpu.data 247180 # number of ReadExReq accesses(hits+misses)
353system.cpu.l2cache.ReadExReq_accesses::total 247180 # number of ReadExReq accesses(hits+misses)
354system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7546 # number of demand (read+write) accesses
355system.cpu.l2cache.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
356system.cpu.l2cache.demand_accesses::cpu.inst 849401 # number of demand (read+write) accesses
357system.cpu.l2cache.demand_accesses::cpu.data 623841 # number of demand (read+write) accesses
358system.cpu.l2cache.demand_accesses::total 1483942 # number of demand (read+write) accesses
359system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7546 # number of overall (read+write) accesses
360system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
361system.cpu.l2cache.overall_accesses::cpu.inst 849401 # number of overall (read+write) accesses
362system.cpu.l2cache.overall_accesses::cpu.data 623841 # number of overall (read+write) accesses
363system.cpu.l2cache.overall_accesses::total 1483942 # number of overall (read+write) accesses
364system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses
365system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses
366system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses
367system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses
368system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses
369system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses
370system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses
371system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539987 # miss rate for ReadExReq accesses
372system.cpu.l2cache.ReadExReq_miss_rate::total 0.539987 # miss rate for ReadExReq accesses
373system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses
374system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses
375system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses
376system.cpu.l2cache.demand_miss_rate::cpu.data 0.229778 # miss rate for demand accesses
377system.cpu.l2cache.demand_miss_rate::total 0.103751 # miss rate for demand accesses
378system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses
379system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses
380system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses
381system.cpu.l2cache.overall_miss_rate::cpu.data 0.229778 # miss rate for overall accesses
382system.cpu.l2cache.overall_miss_rate::total 0.103751 # miss rate for overall accesses
383system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
384system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
385system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
386system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
387system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
388system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
389system.cpu.l2cache.fast_writes 0 # number of fast writes performed
390system.cpu.l2cache.cache_copies 0 # number of cache copies performed
391system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks
392system.cpu.l2cache.writebacks::total 57873 # number of writebacks
393system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
394system.cpu.dcache.tags.replacements 623329 # number of replacements
395system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use
396system.cpu.dcache.tags.total_refs 21798545 # Total number of references to valid blocks.
397system.cpu.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks.
398system.cpu.dcache.tags.avg_refs 34.942469 # Average number of references to valid blocks.
399system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit.
400system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor
401system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
402system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
403system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
404system.cpu.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id
405system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
406system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
407system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
408system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses
409system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses
410system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits
411system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits
412system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits
413system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits
414system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits
415system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits
416system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits
417system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits
418system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits
419system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits
420system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits
421system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits
422system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits
423system.cpu.dcache.overall_hits::total 21312398 # number of overall hits
424system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses
425system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses
426system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses
427system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses
428system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses
429system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses
430system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses
431system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses
432system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses
433system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses
434system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses
435system.cpu.dcache.overall_misses::total 615595 # number of overall misses
436system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses)
437system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses)
438system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses)
439system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses)
440system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses)
441system.cpu.dcache.SoftPFReq_accesses::total 184298 # number of SoftPFReq accesses(hits+misses)
442system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197 # number of LoadLockedReq accesses(hits+misses)
443system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses)
444system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses)
445system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses)
446system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses
447system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses
448system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses
449system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses
450system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses
451system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses
452system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses
453system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses
454system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses
455system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses
456system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses
457system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses
458system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses
459system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses
460system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses
461system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses
462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
468system.cpu.dcache.fast_writes 0 # number of fast writes performed
469system.cpu.dcache.cache_copies 0 # number of cache copies performed
470system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks
471system.cpu.dcache.writebacks::total 592642 # number of writebacks
472system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
473system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s)
474system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes)
475system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
476system.iocache.tags.replacements 0 # number of replacements
477system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
478system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
479system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
480system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
481system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
482system.iocache.tags.tag_accesses 0 # Number of tag accesses
483system.iocache.tags.data_accesses 0 # Number of data accesses
484system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
485system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
486system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
487system.iocache.blocked::no_targets 0 # number of cycles access was blocked
488system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
489system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
490system.iocache.fast_writes 0 # number of fast writes performed
491system.iocache.cache_copies 0 # number of cache copies performed
492system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
493
494---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.321351 # Number of seconds simulated
4sim_ticks 2321351025500 # Number of ticks simulated
5final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 818788 # Simulator instruction rate (inst/s)
8host_op_rate 985991 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 31464875718 # Simulator tick rate (ticks/s)
10host_mem_usage 430844 # Number of bytes of host memory used
11host_seconds 73.78 # Real time elapsed on the host
12sim_insts 60406834 # Number of instructions simulated
13sim_ops 72742429 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 705416 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 9071832 # Number of bytes read from this memory
21system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 705416 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory
--- 4 unchanged lines hidden (view full) ---
28system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 17234 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 141773 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory
34system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory
36system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s)
54system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
55system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
56system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
57system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
58system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
59system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
60system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s)
61system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
62system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s)
63system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
64system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
65system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
66system.membus.throughput 55568847 # Throughput (bytes/s)
67system.membus.data_through_bus 128994799 # Total data (bytes)
68system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
69system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
70system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
71system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
72system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
73system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
74system.cf0.dma_write_txs 0 # Number of DMA write transactions.
75system.iobus.throughput 48459111 # Throughput (bytes/s)
76system.iobus.data_through_bus 112490607 # Total data (bytes)
77system.cpu_clk_domain.clock 500 # Clock period in ticks
78system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
79system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
80system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
81system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
82system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
83system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
84system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
--- 8 unchanged lines hidden (view full) ---
93system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
94system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
95system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
96system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
97system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
98system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
99system.cpu.dtb.inst_hits 0 # ITB inst hits
100system.cpu.dtb.inst_misses 0 # ITB inst misses
101system.cpu.dtb.read_hits 13142244 # DTB read hits
102system.cpu.dtb.read_misses 7297 # DTB read misses
103system.cpu.dtb.write_hits 11216207 # DTB write hits
104system.cpu.dtb.write_misses 2181 # DTB write misses
105system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
106system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
107system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
108system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
109system.cpu.dtb.flush_entries 3399 # Number of entries that have been flushed from TLB
110system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
111system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
112system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
113system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
114system.cpu.dtb.read_accesses 13149541 # DTB read accesses
115system.cpu.dtb.write_accesses 11218388 # DTB write accesses
116system.cpu.dtb.inst_accesses 0 # ITB inst accesses
117system.cpu.dtb.hits 24358451 # DTB hits
118system.cpu.dtb.misses 9478 # DTB misses
119system.cpu.dtb.accesses 24367929 # DTB accesses
120system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
121system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
122system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
123system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
124system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
125system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
126system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
127system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 26 unchanged lines hidden (view full) ---
154system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
156system.cpu.itb.read_accesses 0 # DTB read accesses
157system.cpu.itb.write_accesses 0 # DTB write accesses
158system.cpu.itb.inst_accesses 61434478 # ITB inst accesses
159system.cpu.itb.hits 61430007 # DTB hits
160system.cpu.itb.misses 4471 # DTB misses
161system.cpu.itb.accesses 61434478 # DTB accesses
162system.cpu.numCycles 4642702052 # number of cpu cycles simulated
163system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
164system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
165system.cpu.committedInsts 60406834 # Number of instructions committed
166system.cpu.committedOps 72742429 # Number of ops (including micro ops) committed
167system.cpu.num_int_alu_accesses 64191430 # Number of integer alu accesses
168system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
169system.cpu.num_func_calls 2135762 # number of times a function call or return occured
170system.cpu.num_conditional_control_insts 7544984 # number of instructions that are conditional controls
171system.cpu.num_int_insts 64191430 # number of integer instructions
172system.cpu.num_fp_insts 10269 # number of float instructions
173system.cpu.num_int_register_reads 116427347 # number of times the integer registers were read
174system.cpu.num_int_register_writes 42818107 # number of times the integer registers were written
175system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
176system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
177system.cpu.num_cc_register_reads 217570004 # number of times the CC registers were read
178system.cpu.num_cc_register_writes 28977741 # number of times the CC registers were written
179system.cpu.num_mem_refs 25221274 # number of memory refs
180system.cpu.num_load_insts 13499937 # Number of load instructions
181system.cpu.num_store_insts 11721337 # Number of store instructions
182system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles
183system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles
184system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles
185system.cpu.idle_fraction 0.984091 # Percentage of idle cycles
186system.cpu.Branches 10298517 # Number of branches fetched
187system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
188system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction
189system.cpu.op_class::IntMult 87771 0.12% 65.39% # Class of executed instruction
190system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction
191system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction
192system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction
193system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction
--- 22 unchanged lines hidden (view full) ---
216system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction
217system.cpu.op_class::MemRead 13499937 18.52% 83.92% # Class of executed instruction
218system.cpu.op_class::MemWrite 11721337 16.08% 100.00% # Class of executed instruction
219system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
220system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
221system.cpu.op_class::total 72875708 # Class of executed instruction
222system.cpu.kern.inst.arm 0 # number of arm instructions executed
223system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed
224system.cpu.icache.tags.replacements 850515 # number of replacements
225system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use
226system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks.
227system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks.
228system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks.
229system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit.
230system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor
231system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy
232system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy
233system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
234system.cpu.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
235system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
236system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id
237system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
238system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
239system.cpu.icache.tags.tag_accesses 62283794 # Number of tag accesses
240system.cpu.icache.tags.data_accesses 62283794 # Number of data accesses
241system.cpu.icache.ReadReq_hits::cpu.inst 60581740 # number of ReadReq hits
242system.cpu.icache.ReadReq_hits::total 60581740 # number of ReadReq hits
243system.cpu.icache.demand_hits::cpu.inst 60581740 # number of demand (read+write) hits
244system.cpu.icache.demand_hits::total 60581740 # number of demand (read+write) hits
245system.cpu.icache.overall_hits::cpu.inst 60581740 # number of overall hits
246system.cpu.icache.overall_hits::total 60581740 # number of overall hits
247system.cpu.icache.ReadReq_misses::cpu.inst 851027 # number of ReadReq misses
248system.cpu.icache.ReadReq_misses::total 851027 # number of ReadReq misses
249system.cpu.icache.demand_misses::cpu.inst 851027 # number of demand (read+write) misses
250system.cpu.icache.demand_misses::total 851027 # number of demand (read+write) misses
251system.cpu.icache.overall_misses::cpu.inst 851027 # number of overall misses
252system.cpu.icache.overall_misses::total 851027 # number of overall misses
253system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses)
254system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses)
255system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses
256system.cpu.icache.demand_accesses::total 61432767 # number of demand (read+write) accesses
257system.cpu.icache.overall_accesses::cpu.inst 61432767 # number of overall (read+write) accesses
258system.cpu.icache.overall_accesses::total 61432767 # number of overall (read+write) accesses
259system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013853 # miss rate for ReadReq accesses
260system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses
--- 6 unchanged lines hidden (view full) ---
267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
271system.cpu.icache.fast_writes 0 # number of fast writes performed
272system.cpu.icache.cache_copies 0 # number of cache copies performed
273system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
274system.cpu.l2cache.tags.replacements 62250 # number of replacements
275system.cpu.l2cache.tags.tagsinuse 50006.834636 # Cycle average of tags in use
276system.cpu.l2cache.tags.total_refs 1669916 # Total number of references to valid blocks.
277system.cpu.l2cache.tags.sampled_refs 127635 # Sample count of references to valid blocks.
278system.cpu.l2cache.tags.avg_refs 13.083527 # Average number of references to valid blocks.
279system.cpu.l2cache.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit.
280system.cpu.l2cache.tags.occ_blocks::writebacks 36897.866975 # Average occupied blocks per requestor
281system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959775 # Average occupied blocks per requestor
282system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993971 # Average occupied blocks per requestor
283system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.476656 # Average occupied blocks per requestor
284system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.537259 # Average occupied blocks per requestor
285system.cpu.l2cache.tags.occ_percent::writebacks 0.563017 # Average percentage of cache occupancy
286system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
287system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy
288system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107032 # Average percentage of cache occupancy
289system.cpu.l2cache.tags.occ_percent::cpu.data 0.092934 # Average percentage of cache occupancy
290system.cpu.l2cache.tags.occ_percent::total 0.763044 # Average percentage of cache occupancy
291system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
292system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id
293system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
294system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
295system.cpu.l2cache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
296system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3672 # Occupied blocks per task id
297system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9281 # Occupied blocks per task id
298system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52125 # Occupied blocks per task id
299system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
300system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id
301system.cpu.l2cache.tags.tag_accesses 17035648 # Number of tag accesses
302system.cpu.l2cache.tags.data_accesses 17035648 # Number of data accesses
303system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7541 # number of ReadReq hits
304system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits
305system.cpu.l2cache.ReadReq_hits::cpu.inst 838793 # number of ReadReq hits
306system.cpu.l2cache.ReadReq_hits::cpu.data 366790 # number of ReadReq hits
307system.cpu.l2cache.ReadReq_hits::total 1216275 # number of ReadReq hits
308system.cpu.l2cache.Writeback_hits::writebacks 592642 # number of Writeback hits
309system.cpu.l2cache.Writeback_hits::total 592642 # number of Writeback hits
310system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
311system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
312system.cpu.l2cache.ReadExReq_hits::cpu.data 113706 # number of ReadExReq hits
313system.cpu.l2cache.ReadExReq_hits::total 113706 # number of ReadExReq hits
314system.cpu.l2cache.demand_hits::cpu.dtb.walker 7541 # number of demand (read+write) hits
315system.cpu.l2cache.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits
316system.cpu.l2cache.demand_hits::cpu.inst 838793 # number of demand (read+write) hits
317system.cpu.l2cache.demand_hits::cpu.data 480496 # number of demand (read+write) hits
318system.cpu.l2cache.demand_hits::total 1329981 # number of demand (read+write) hits
319system.cpu.l2cache.overall_hits::cpu.dtb.walker 7541 # number of overall hits
320system.cpu.l2cache.overall_hits::cpu.itb.walker 3151 # number of overall hits
321system.cpu.l2cache.overall_hits::cpu.inst 838793 # number of overall hits
322system.cpu.l2cache.overall_hits::cpu.data 480496 # number of overall hits
323system.cpu.l2cache.overall_hits::total 1329981 # number of overall hits
324system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
325system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses
326system.cpu.l2cache.ReadReq_misses::cpu.inst 10608 # number of ReadReq misses
327system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses
328system.cpu.l2cache.ReadReq_misses::total 20487 # number of ReadReq misses
329system.cpu.l2cache.UpgradeReq_misses::cpu.data 2917 # number of UpgradeReq misses
330system.cpu.l2cache.UpgradeReq_misses::total 2917 # number of UpgradeReq misses
331system.cpu.l2cache.ReadExReq_misses::cpu.data 133474 # number of ReadExReq misses
332system.cpu.l2cache.ReadExReq_misses::total 133474 # number of ReadExReq misses
333system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
334system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses
335system.cpu.l2cache.demand_misses::cpu.inst 10608 # number of demand (read+write) misses
336system.cpu.l2cache.demand_misses::cpu.data 143345 # number of demand (read+write) misses
337system.cpu.l2cache.demand_misses::total 153961 # number of demand (read+write) misses
338system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
339system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses
340system.cpu.l2cache.overall_misses::cpu.inst 10608 # number of overall misses
341system.cpu.l2cache.overall_misses::cpu.data 143345 # number of overall misses
342system.cpu.l2cache.overall_misses::total 153961 # number of overall misses
343system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7546 # number of ReadReq accesses(hits+misses)
344system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
345system.cpu.l2cache.ReadReq_accesses::cpu.inst 849401 # number of ReadReq accesses(hits+misses)
346system.cpu.l2cache.ReadReq_accesses::cpu.data 376661 # number of ReadReq accesses(hits+misses)
347system.cpu.l2cache.ReadReq_accesses::total 1236762 # number of ReadReq accesses(hits+misses)
348system.cpu.l2cache.Writeback_accesses::writebacks 592642 # number of Writeback accesses(hits+misses)
349system.cpu.l2cache.Writeback_accesses::total 592642 # number of Writeback accesses(hits+misses)
350system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2943 # number of UpgradeReq accesses(hits+misses)
351system.cpu.l2cache.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses)
352system.cpu.l2cache.ReadExReq_accesses::cpu.data 247180 # number of ReadExReq accesses(hits+misses)
353system.cpu.l2cache.ReadExReq_accesses::total 247180 # number of ReadExReq accesses(hits+misses)
354system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7546 # number of demand (read+write) accesses
355system.cpu.l2cache.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
356system.cpu.l2cache.demand_accesses::cpu.inst 849401 # number of demand (read+write) accesses
357system.cpu.l2cache.demand_accesses::cpu.data 623841 # number of demand (read+write) accesses
358system.cpu.l2cache.demand_accesses::total 1483942 # number of demand (read+write) accesses
359system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7546 # number of overall (read+write) accesses
360system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
361system.cpu.l2cache.overall_accesses::cpu.inst 849401 # number of overall (read+write) accesses
362system.cpu.l2cache.overall_accesses::cpu.data 623841 # number of overall (read+write) accesses
363system.cpu.l2cache.overall_accesses::total 1483942 # number of overall (read+write) accesses
364system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses
365system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses
366system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses
367system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses
368system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses
369system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses
370system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses
371system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539987 # miss rate for ReadExReq accesses
372system.cpu.l2cache.ReadExReq_miss_rate::total 0.539987 # miss rate for ReadExReq accesses
373system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses
374system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses
375system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses
376system.cpu.l2cache.demand_miss_rate::cpu.data 0.229778 # miss rate for demand accesses
377system.cpu.l2cache.demand_miss_rate::total 0.103751 # miss rate for demand accesses
378system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses
379system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses
380system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses
381system.cpu.l2cache.overall_miss_rate::cpu.data 0.229778 # miss rate for overall accesses
382system.cpu.l2cache.overall_miss_rate::total 0.103751 # miss rate for overall accesses
383system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
384system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
385system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
386system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
387system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
388system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
389system.cpu.l2cache.fast_writes 0 # number of fast writes performed
390system.cpu.l2cache.cache_copies 0 # number of cache copies performed
391system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks
392system.cpu.l2cache.writebacks::total 57873 # number of writebacks
393system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
394system.cpu.dcache.tags.replacements 623329 # number of replacements
395system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use
396system.cpu.dcache.tags.total_refs 21798545 # Total number of references to valid blocks.
397system.cpu.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks.
398system.cpu.dcache.tags.avg_refs 34.942469 # Average number of references to valid blocks.
399system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit.
400system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor
401system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
402system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
403system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
404system.cpu.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id
405system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
406system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
407system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
408system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses
409system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses
410system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits
411system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits
412system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits
413system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits
414system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits
415system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits
416system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits
417system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits
418system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits
419system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits
420system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits
421system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits
422system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits
423system.cpu.dcache.overall_hits::total 21312398 # number of overall hits
424system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses
425system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses
426system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses
427system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses
428system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses
429system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses
430system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses
431system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses
432system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses
433system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses
434system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses
435system.cpu.dcache.overall_misses::total 615595 # number of overall misses
436system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses)
437system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses)
438system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses)
439system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses)
440system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses)
441system.cpu.dcache.SoftPFReq_accesses::total 184298 # number of SoftPFReq accesses(hits+misses)
442system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197 # number of LoadLockedReq accesses(hits+misses)
443system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses)
444system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses)
445system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses)
446system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses
447system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses
448system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses
449system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses
450system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses
451system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses
452system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses
453system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses
454system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses
455system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses
456system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses
457system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses
458system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses
459system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses
460system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses
461system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses
462system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
463system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
464system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
465system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
466system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
467system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
468system.cpu.dcache.fast_writes 0 # number of fast writes performed
469system.cpu.dcache.cache_copies 0 # number of cache copies performed
470system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks
471system.cpu.dcache.writebacks::total 592642 # number of writebacks
472system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
473system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s)
474system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes)
475system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
476system.iocache.tags.replacements 0 # number of replacements
477system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
478system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
479system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
480system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
481system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
482system.iocache.tags.tag_accesses 0 # Number of tag accesses
483system.iocache.tags.data_accesses 0 # Number of data accesses
484system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
485system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
486system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
487system.iocache.blocked::no_targets 0 # number of cycles access was blocked
488system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
489system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
490system.iocache.fast_writes 0 # number of fast writes performed
491system.iocache.cache_copies 0 # number of cache copies performed
492system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
493
494---------- End Simulation Statistics ----------