| config.ini (10636:9ac724889705) | config.ini (10736:4433fb00fa7d) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 24 unchanged lines hidden (view full) --- 33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM 38mem_mode=atomic 39mem_ranges=2147483648:2415919103 40memories=system.physmem system.realview.nvmem system.realview.vram | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 24 unchanged lines hidden (view full) --- 33kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM 38mem_mode=atomic 39mem_ranges=2147483648:2415919103 40memories=system.physmem system.realview.nvmem system.realview.vram |
| 41mmap_using_noreserve=false |
|
| 41multi_proc=true 42num_work_ids=16 43panic_on_oops=true 44panic_on_panic=true 45phys_addr_range_64=40 46readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 47reset_addr_64=0 48symbolfile= --- 123 unchanged lines hidden (view full) --- 172sequential_access=false 173size=32768 174 175[system.cpu.dstage2_mmu] 176type=ArmStage2MMU 177children=stage2_tlb 178eventq_index=0 179stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb | 42multi_proc=true 43num_work_ids=16 44panic_on_oops=true 45panic_on_panic=true 46phys_addr_range_64=40 47readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh 48reset_addr_64=0 49symbolfile= --- 123 unchanged lines hidden (view full) --- 173sequential_access=false 174size=32768 175 176[system.cpu.dstage2_mmu] 177type=ArmStage2MMU 178children=stage2_tlb 179eventq_index=0 180stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| 181sys=system |
|
| 180tlb=system.cpu.dtb 181 182[system.cpu.dstage2_mmu.stage2_tlb] 183type=ArmTLB 184children=walker 185eventq_index=0 186is_stage2=true 187size=32 188walker=system.cpu.dstage2_mmu.stage2_tlb.walker 189 190[system.cpu.dstage2_mmu.stage2_tlb.walker] 191type=ArmTableWalker 192clk_domain=system.cpu_clk_domain 193eventq_index=0 194is_stage2=true 195num_squash_per_cycle=2 196sys=system | 182tlb=system.cpu.dtb 183 184[system.cpu.dstage2_mmu.stage2_tlb] 185type=ArmTLB 186children=walker 187eventq_index=0 188is_stage2=true 189size=32 190walker=system.cpu.dstage2_mmu.stage2_tlb.walker 191 192[system.cpu.dstage2_mmu.stage2_tlb.walker] 193type=ArmTableWalker 194clk_domain=system.cpu_clk_domain 195eventq_index=0 196is_stage2=true 197num_squash_per_cycle=2 198sys=system |
| 197port=system.cpu.toL2Bus.slave[5] | |
| 198 199[system.cpu.dtb] 200type=ArmTLB 201children=walker 202eventq_index=0 203is_stage2=false 204size=64 205walker=system.cpu.dtb.walker --- 77 unchanged lines hidden (view full) --- 283pmu=Null 284system=system 285 286[system.cpu.istage2_mmu] 287type=ArmStage2MMU 288children=stage2_tlb 289eventq_index=0 290stage2_tlb=system.cpu.istage2_mmu.stage2_tlb | 199 200[system.cpu.dtb] 201type=ArmTLB 202children=walker 203eventq_index=0 204is_stage2=false 205size=64 206walker=system.cpu.dtb.walker --- 77 unchanged lines hidden (view full) --- 284pmu=Null 285system=system 286 287[system.cpu.istage2_mmu] 288type=ArmStage2MMU 289children=stage2_tlb 290eventq_index=0 291stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| 292sys=system |
|
| 291tlb=system.cpu.itb 292 293[system.cpu.istage2_mmu.stage2_tlb] 294type=ArmTLB 295children=walker 296eventq_index=0 297is_stage2=true 298size=32 299walker=system.cpu.istage2_mmu.stage2_tlb.walker 300 301[system.cpu.istage2_mmu.stage2_tlb.walker] 302type=ArmTableWalker 303clk_domain=system.cpu_clk_domain 304eventq_index=0 305is_stage2=true 306num_squash_per_cycle=2 307sys=system | 293tlb=system.cpu.itb 294 295[system.cpu.istage2_mmu.stage2_tlb] 296type=ArmTLB 297children=walker 298eventq_index=0 299is_stage2=true 300size=32 301walker=system.cpu.istage2_mmu.stage2_tlb.walker 302 303[system.cpu.istage2_mmu.stage2_tlb.walker] 304type=ArmTableWalker 305clk_domain=system.cpu_clk_domain 306eventq_index=0 307is_stage2=true 308num_squash_per_cycle=2 309sys=system |
| 308port=system.cpu.toL2Bus.slave[4] | |
| 309 310[system.cpu.itb] 311type=ArmTLB 312children=walker 313eventq_index=0 314is_stage2=false 315size=64 316walker=system.cpu.itb.walker --- 42 unchanged lines hidden (view full) --- 359hit_latency=20 360sequential_access=false 361size=4194304 362 363[system.cpu.toL2Bus] 364type=CoherentXBar 365clk_domain=system.cpu_clk_domain 366eventq_index=0 | 310 311[system.cpu.itb] 312type=ArmTLB 313children=walker 314eventq_index=0 315is_stage2=false 316size=64 317walker=system.cpu.itb.walker --- 42 unchanged lines hidden (view full) --- 360hit_latency=20 361sequential_access=false 362size=4194304 363 364[system.cpu.toL2Bus] 365type=CoherentXBar 366clk_domain=system.cpu_clk_domain 367eventq_index=0 |
| 367header_cycles=1 | 368forward_latency=0 369frontend_latency=1 370response_latency=1 |
| 368snoop_filter=Null | 371snoop_filter=Null |
| 372snoop_response_latency=1 |
|
| 369system=system 370use_default_range=false 371width=32 372master=system.cpu.l2cache.cpu_side | 373system=system 374use_default_range=false 375width=32 376master=system.cpu.l2cache.cpu_side |
| 373slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port | 377slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| 374 375[system.cpu.tracer] 376type=ExeTracer 377eventq_index=0 378 379[system.cpu_clk_domain] 380type=SrcClockDomain 381clock=500 --- 14 unchanged lines hidden (view full) --- 396type=IntrControl 397eventq_index=0 398sys=system 399 400[system.iobus] 401type=NoncoherentXBar 402clk_domain=system.clk_domain 403eventq_index=0 | 378 379[system.cpu.tracer] 380type=ExeTracer 381eventq_index=0 382 383[system.cpu_clk_domain] 384type=SrcClockDomain 385clock=500 --- 14 unchanged lines hidden (view full) --- 400type=IntrControl 401eventq_index=0 402sys=system 403 404[system.iobus] 405type=NoncoherentXBar 406clk_domain=system.clk_domain 407eventq_index=0 |
| 404header_cycles=1 | 408forward_latency=1 409frontend_latency=2 410response_latency=2 |
| 405use_default_range=true | 411use_default_range=true |
| 406width=8 | 412width=16 |
| 407default=system.realview.pciconfig.pio 408master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side 409slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 410 411[system.iocache] 412type=BaseCache 413children=tags 414addr_ranges=2147483648:2415919103 --- 29 unchanged lines hidden (view full) --- 444sequential_access=false 445size=1024 446 447[system.membus] 448type=CoherentXBar 449children=badaddr_responder 450clk_domain=system.clk_domain 451eventq_index=0 | 413default=system.realview.pciconfig.pio 414master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side 415slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 416 417[system.iocache] 418type=BaseCache 419children=tags 420addr_ranges=2147483648:2415919103 --- 29 unchanged lines hidden (view full) --- 450sequential_access=false 451size=1024 452 453[system.membus] 454type=CoherentXBar 455children=badaddr_responder 456clk_domain=system.clk_domain 457eventq_index=0 |
| 452header_cycles=1 | 458forward_latency=4 459frontend_latency=3 460response_latency=2 |
| 453snoop_filter=Null | 461snoop_filter=Null |
| 462snoop_response_latency=4 |
|
| 454system=system 455use_default_range=false | 463system=system 464use_default_range=false |
| 456width=8 | 465width=16 |
| 457default=system.membus.badaddr_responder.pio 458master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port 459slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 460 461[system.membus.badaddr_responder] 462type=IsaFake 463clk_domain=system.clk_domain 464eventq_index=0 --- 696 unchanged lines hidden --- | 466default=system.membus.badaddr_responder.pio 467master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port 468slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 469 470[system.membus.badaddr_responder] 471type=IsaFake 472clk_domain=system.clk_domain 473eventq_index=0 --- 696 unchanged lines hidden --- |