| stats.txt (11687:b3d5f0e9e258) | stats.txt (11754:c209cb86278a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802883274000 # Number of ticks simulated 5final_tick 2802883274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.802884 # Number of seconds simulated 4sim_ticks 2802884446000 # Number of ticks simulated 5final_tick 2802884446000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1537557 # Simulator instruction rate (inst/s) 8host_op_rate 1873488 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29353729253 # Simulator tick rate (ticks/s) 10host_mem_usage 598048 # Number of bytes of host memory used 11host_seconds 95.49 # Real time elapsed on the host 12sim_insts 146815798 # Number of instructions simulated 13sim_ops 178892721 # Number of ops (including micro ops) simulated | 7host_inst_rate 1499640 # Simulator instruction rate (inst/s) 8host_op_rate 1827287 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 28629719673 # Simulator tick rate (ticks/s) 10host_mem_usage 593616 # Number of bytes of host memory used 11host_seconds 97.90 # Real time elapsed on the host 12sim_insts 146816546 # Number of instructions simulated 13sim_ops 178893643 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu0.inst 1163300 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 9541412 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 165332 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 1112336 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu0.inst 1163556 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 9541156 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 165076 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 1111568 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 24system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 24system.physmem.bytes_read::total 11983980 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 1163300 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 165332 # Number of instructions bytes read from this memory | 25system.physmem.bytes_read::total 11983020 # Number of bytes read from this memory 26system.physmem.bytes_inst_read::cpu0.inst 1163556 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::cpu1.inst 165076 # Number of instructions bytes read from this memory |
| 27system.physmem.bytes_inst_read::total 1328632 # Number of instructions bytes read from this memory | 28system.physmem.bytes_inst_read::total 1328632 # Number of instructions bytes read from this memory |
| 28system.physmem.bytes_written::writebacks 8870080 # Number of bytes written to this memory | 29system.physmem.bytes_written::writebacks 8871872 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 30system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::total 8887644 # Number of bytes written to this memory | 32system.physmem.bytes_written::total 8889436 # Number of bytes written to this memory |
| 32system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 33system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 34system.physmem.num_reads::cpu0.inst 26630 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 149604 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 2738 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 17400 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu0.inst 26634 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 149600 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.inst 2734 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 17388 # Number of read requests responded to by this memory |
| 38system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 40system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 39system.physmem.num_reads::total 196397 # Number of read requests responded to by this memory 40system.physmem.num_writes::writebacks 138595 # Number of write requests responded to by this memory | 41system.physmem.num_reads::total 196382 # Number of read requests responded to by this memory 42system.physmem.num_writes::writebacks 138623 # Number of write requests responded to by this memory |
| 41system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 42system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 43system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 43system.physmem.num_writes::total 142986 # Number of write requests responded to by this memory | 45system.physmem.num_writes::total 143014 # Number of write requests responded to by this memory |
| 44system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) | 46system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) |
| 46system.physmem.bw_read::cpu0.inst 415037 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3404142 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.inst 58986 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.data 396854 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu0.inst 415128 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu0.data 3404049 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.inst 58895 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu1.data 396580 # Total read bandwidth from this memory (bytes/s) |
| 50system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) |
| 51system.physmem.bw_read::total 4275590 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 415037 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 58986 # Instruction read bandwidth from this memory (bytes/s) | 54system.physmem.bw_read::total 4275246 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu0.inst 415128 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu1.inst 58895 # Instruction read bandwidth from this memory (bytes/s) |
| 54system.physmem.bw_inst_read::total 474023 # Instruction read bandwidth from this memory (bytes/s) | 57system.physmem.bw_inst_read::total 474023 # Instruction read bandwidth from this memory (bytes/s) |
| 55system.physmem.bw_write::writebacks 3164627 # Write bandwidth from this memory (bytes/s) | 58system.physmem.bw_write::writebacks 3165265 # Write bandwidth from this memory (bytes/s) |
| 56system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 59system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 60system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 58system.physmem.bw_write::total 3170893 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3164627 # Total bandwidth to/from this memory (bytes/s) | 61system.physmem.bw_write::total 3171531 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_total::writebacks 3165265 # Total bandwidth to/from this memory (bytes/s) |
| 60system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) |
| 62system.physmem.bw_total::cpu0.inst 415037 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.data 3410394 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu1.inst 58986 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.data 396868 # Total bandwidth to/from this memory (bytes/s) | 65system.physmem.bw_total::cpu0.inst 415128 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.data 3410301 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.inst 58895 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu1.data 396594 # Total bandwidth to/from this memory (bytes/s) |
| 66system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) | 70system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) |
| 67system.physmem.bw_total::total 7446483 # Total bandwidth to/from this memory (bytes/s) 68system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 71system.physmem.bw_total::total 7446777 # Total bandwidth to/from this memory (bytes/s) 72system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 69system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) | 73system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 74system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 75system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 76system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 77system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 78system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 79system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 80system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 81system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 82system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 85system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 86system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 87system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 88system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 89system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 90system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) |
| 87system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 88system.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 89system.bridge.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 91system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 92system.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 93system.bridge.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 90system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 91system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 92system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 93system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 94system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 95system.cf0.dma_write_txs 631 # Number of DMA write transactions. 96system.cpu_clk_domain.clock 500 # Clock period in ticks | 94system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 95system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 96system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 97system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 98system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 99system.cf0.dma_write_txs 631 # Number of DMA write transactions. 100system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 97system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 101system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 98system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 119system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 102system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 123system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 127system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 131system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 128system.cpu0.dtb.walker.walks 7964 # Table walker walks requested 129system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 130system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 131system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 132system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 133system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 134system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 135system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution --- 4 unchanged lines hidden (view full) --- 140system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 141system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 142system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 143system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 144system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 145system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 146system.cpu0.dtb.inst_hits 0 # ITB inst hits 147system.cpu0.dtb.inst_misses 0 # ITB inst misses | 132system.cpu0.dtb.walker.walks 7964 # Table walker walks requested 133system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 134system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 135system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 136system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 137system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 138system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 139system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution --- 4 unchanged lines hidden (view full) --- 144system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 145system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 146system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 147system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 148system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 149system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 150system.cpu0.dtb.inst_hits 0 # ITB inst hits 151system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 148system.cpu0.dtb.read_hits 20338226 # DTB read hits | 152system.cpu0.dtb.read_hits 20338335 # DTB read hits |
| 149system.cpu0.dtb.read_misses 6871 # DTB read misses | 153system.cpu0.dtb.read_misses 6871 # DTB read misses |
| 150system.cpu0.dtb.write_hits 16389726 # DTB write hits | 154system.cpu0.dtb.write_hits 16389802 # DTB write hits |
| 151system.cpu0.dtb.write_misses 1093 # DTB write misses 152system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 153system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 154system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 155system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 156system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB 157system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 158system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 159system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 160system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions | 155system.cpu0.dtb.write_misses 1093 # DTB write misses 156system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 157system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 158system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 159system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 160system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB 161system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 162system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 163system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 164system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions |
| 161system.cpu0.dtb.read_accesses 20345097 # DTB read accesses 162system.cpu0.dtb.write_accesses 16390819 # DTB write accesses | 165system.cpu0.dtb.read_accesses 20345206 # DTB read accesses 166system.cpu0.dtb.write_accesses 16390895 # DTB write accesses |
| 163system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 167system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 164system.cpu0.dtb.hits 36727952 # DTB hits | 168system.cpu0.dtb.hits 36728137 # DTB hits |
| 165system.cpu0.dtb.misses 7964 # DTB misses | 169system.cpu0.dtb.misses 7964 # DTB misses |
| 166system.cpu0.dtb.accesses 36735916 # DTB accesses 167system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 170system.cpu0.dtb.accesses 36736101 # DTB accesses 171system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 168system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 169system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 170system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 171system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 172system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 173system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 174system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 175system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 189system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 190system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 191system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 192system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 193system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 194system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 195system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 196system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 172system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 173system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 174system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 175system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 176system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 177system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 178system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 179system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 193system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 194system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 195system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 196system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 197system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 198system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 199system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 200system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 197system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 201system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 198system.cpu0.itb.walker.walks 3358 # Table walker walks requested 199system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 200system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 201system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 202system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 203system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 204system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 205system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 206system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 207system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 208system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 209system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 210system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 211system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 212system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 213system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 214system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 215system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst | 202system.cpu0.itb.walker.walks 3358 # Table walker walks requested 203system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 204system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 205system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 206system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 207system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 208system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 209system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 210system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 211system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 212system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 213system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 214system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 215system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 216system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 217system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 218system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 219system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst |
| 216system.cpu0.itb.inst_hits 97433318 # ITB inst hits | 220system.cpu0.itb.inst_hits 97433825 # ITB inst hits |
| 217system.cpu0.itb.inst_misses 3358 # ITB inst misses 218system.cpu0.itb.read_hits 0 # DTB read hits 219system.cpu0.itb.read_misses 0 # DTB read misses 220system.cpu0.itb.write_hits 0 # DTB write hits 221system.cpu0.itb.write_misses 0 # DTB write misses 222system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 223system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 224system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 225system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 226system.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB 227system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 228system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 229system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 230system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu0.itb.read_accesses 0 # DTB read accesses 232system.cpu0.itb.write_accesses 0 # DTB write accesses | 221system.cpu0.itb.inst_misses 3358 # ITB inst misses 222system.cpu0.itb.read_hits 0 # DTB read hits 223system.cpu0.itb.read_misses 0 # DTB read misses 224system.cpu0.itb.write_hits 0 # DTB write hits 225system.cpu0.itb.write_misses 0 # DTB write misses 226system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 227system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 228system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 229system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 230system.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB 231system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 232system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 233system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 234system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 235system.cpu0.itb.read_accesses 0 # DTB read accesses 236system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 233system.cpu0.itb.inst_accesses 97436676 # ITB inst accesses 234system.cpu0.itb.hits 97433318 # DTB hits | 237system.cpu0.itb.inst_accesses 97437183 # ITB inst accesses 238system.cpu0.itb.hits 97433825 # DTB hits |
| 235system.cpu0.itb.misses 3358 # DTB misses | 239system.cpu0.itb.misses 3358 # DTB misses |
| 236system.cpu0.itb.accesses 97436676 # DTB accesses 237system.cpu0.numPwrStateTransitions 3946 # Number of power state transitions 238system.cpu0.pwrStateClkGateDist::samples 1973 # Distribution of time spent in the clock gated state 239system.cpu0.pwrStateClkGateDist::mean 1390823508.162189 # Distribution of time spent in the clock gated state 240system.cpu0.pwrStateClkGateDist::stdev 23082851772.246098 # Distribution of time spent in the clock gated state 241system.cpu0.pwrStateClkGateDist::underflows 1157 58.64% 58.64% # Distribution of time spent in the clock gated state 242system.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.05% 99.70% # Distribution of time spent in the clock gated state | 240system.cpu0.itb.accesses 97437183 # DTB accesses 241system.cpu0.numPwrStateTransitions 3948 # Number of power state transitions 242system.cpu0.pwrStateClkGateDist::samples 1974 # Distribution of time spent in the clock gated state 243system.cpu0.pwrStateClkGateDist::mean 1390119373.406788 # Distribution of time spent in the clock gated state 244system.cpu0.pwrStateClkGateDist::stdev 23077022550.794018 # Distribution of time spent in the clock gated state 245system.cpu0.pwrStateClkGateDist::underflows 1158 58.66% 58.66% # Distribution of time spent in the clock gated state 246system.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.03% 99.70% # Distribution of time spent in the clock gated state |
| 243system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state 244system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state 245system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state 246system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 247system.cpu0.pwrStateClkGateDist::max_value 499983361388 # Distribution of time spent in the clock gated state | 247system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state 248system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state 249system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state 250system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 251system.cpu0.pwrStateClkGateDist::max_value 499983361388 # Distribution of time spent in the clock gated state |
| 248system.cpu0.pwrStateClkGateDist::total 1973 # Distribution of time spent in the clock gated state 249system.cpu0.pwrStateResidencyTicks::ON 58788492396 # Cumulative time (in ticks) in various power states 250system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744094781604 # Cumulative time (in ticks) in various power states 251system.cpu0.numCycles 5605768522 # number of cpu cycles simulated | 252system.cpu0.pwrStateClkGateDist::total 1974 # Distribution of time spent in the clock gated state 253system.cpu0.pwrStateResidencyTicks::ON 58788802895 # Cumulative time (in ticks) in various power states 254system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744095643105 # Cumulative time (in ticks) in various power states 255system.cpu0.numCycles 5605770867 # number of cpu cycles simulated |
| 252system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 253system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 254system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 256system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 257system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 258system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 255system.cpu0.kern.inst.quiesce 1973 # number of quiesce instructions executed 256system.cpu0.committedInsts 95420875 # Number of instructions committed 257system.cpu0.committedOps 115552929 # Number of ops (including micro ops) committed 258system.cpu0.num_int_alu_accesses 100755950 # Number of integer alu accesses | 259system.cpu0.kern.inst.quiesce 1974 # number of quiesce instructions executed 260system.cpu0.committedInsts 95421368 # Number of instructions committed 261system.cpu0.committedOps 115553536 # Number of ops (including micro ops) committed 262system.cpu0.num_int_alu_accesses 100756492 # Number of integer alu accesses |
| 259system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses | 263system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses |
| 260system.cpu0.num_func_calls 8000037 # number of times a function call or return occured 261system.cpu0.num_conditional_control_insts 13203579 # number of instructions that are conditional controls 262system.cpu0.num_int_insts 100755950 # number of integer instructions | 264system.cpu0.num_func_calls 8000109 # number of times a function call or return occured 265system.cpu0.num_conditional_control_insts 13203633 # number of instructions that are conditional controls 266system.cpu0.num_int_insts 100756492 # number of integer instructions |
| 263system.cpu0.num_fp_insts 9755 # number of float instructions | 267system.cpu0.num_fp_insts 9755 # number of float instructions |
| 264system.cpu0.num_int_register_reads 182434923 # number of times the integer registers were read 265system.cpu0.num_int_register_writes 69130439 # number of times the integer registers were written | 268system.cpu0.num_int_register_reads 182435981 # number of times the integer registers were read 269system.cpu0.num_int_register_writes 69130832 # number of times the integer registers were written |
| 266system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 267system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written | 270system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 271system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written |
| 268system.cpu0.num_cc_register_reads 349948963 # number of times the CC registers were read 269system.cpu0.num_cc_register_writes 44904772 # number of times the CC registers were written 270system.cpu0.num_mem_refs 37870790 # number of memory refs 271system.cpu0.num_load_insts 20595754 # Number of load instructions 272system.cpu0.num_store_insts 17275036 # Number of store instructions 273system.cpu0.num_idle_cycles 5488191495.802790 # Number of idle cycles 274system.cpu0.num_busy_cycles 117577026.197211 # Number of busy cycles | 272system.cpu0.num_cc_register_reads 349950831 # number of times the CC registers were read 273system.cpu0.num_cc_register_writes 44904973 # number of times the CC registers were written 274system.cpu0.num_mem_refs 37870982 # number of memory refs 275system.cpu0.num_load_insts 20595866 # Number of load instructions 276system.cpu0.num_store_insts 17275116 # Number of store instructions 277system.cpu0.num_idle_cycles 5488193219.783614 # Number of idle cycles 278system.cpu0.num_busy_cycles 117577647.216386 # Number of busy cycles |
| 275system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles 276system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles | 279system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles 280system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles |
| 277system.cpu0.Branches 21940702 # Number of branches fetched | 281system.cpu0.Branches 21940830 # Number of branches fetched |
| 278system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction | 282system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction |
| 279system.cpu0.op_class::IntAlu 78882840 67.49% 67.50% # Class of executed instruction 280system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction | 283system.cpu0.op_class::IntAlu 78883265 67.49% 67.50% # Class of executed instruction 284system.cpu0.op_class::IntMult 110622 0.09% 67.59% # Class of executed instruction |
| 281system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 282system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 283system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 284system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 285system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 286system.cpu0.op_class::FloatMultAcc 0 0.00% 67.59% # Class of executed instruction 287system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 288system.cpu0.op_class::FloatMisc 0 0.00% 67.59% # Class of executed instruction --- 13 unchanged lines hidden (view full) --- 302system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 303system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 304system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 305system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 306system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 307system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 308system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 309system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction | 285system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 286system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 287system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 288system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 289system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 290system.cpu0.op_class::FloatMultAcc 0 0.00% 67.59% # Class of executed instruction 291system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 292system.cpu0.op_class::FloatMisc 0 0.00% 67.59% # Class of executed instruction --- 13 unchanged lines hidden (view full) --- 306system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 307system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 308system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 309system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 310system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 311system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 312system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 313system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction |
| 310system.cpu0.op_class::MemRead 20593498 17.62% 85.22% # Class of executed instruction 311system.cpu0.op_class::MemWrite 17267541 14.77% 99.99% # Class of executed instruction | 314system.cpu0.op_class::MemRead 20593610 17.62% 85.22% # Class of executed instruction 315system.cpu0.op_class::MemWrite 17267621 14.77% 99.99% # Class of executed instruction |
| 312system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction 313system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction 314system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 315system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 316system.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction 317system.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction 318system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 319system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 316system.cpu0.op_class::total 116874608 # Class of executed instruction 317system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 318system.cpu0.dcache.tags.replacements 693483 # number of replacements 319system.cpu0.dcache.tags.tagsinuse 494.728102 # Cycle average of tags in use 320system.cpu0.dcache.tags.total_refs 35929530 # Total number of references to valid blocks. 321system.cpu0.dcache.tags.sampled_refs 693995 # Sample count of references to valid blocks. 322system.cpu0.dcache.tags.avg_refs 51.772030 # Average number of references to valid blocks. | 320system.cpu0.op_class::total 116875229 # Class of executed instruction 321system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 322system.cpu0.dcache.tags.replacements 693487 # number of replacements 323system.cpu0.dcache.tags.tagsinuse 494.728118 # Cycle average of tags in use 324system.cpu0.dcache.tags.total_refs 35929711 # Total number of references to valid blocks. 325system.cpu0.dcache.tags.sampled_refs 693999 # Sample count of references to valid blocks. 326system.cpu0.dcache.tags.avg_refs 51.771992 # Average number of references to valid blocks. |
| 323system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. | 327system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. |
| 324system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728102 # Average occupied blocks per requestor | 328system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728118 # Average occupied blocks per requestor |
| 325system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966266 # Average percentage of cache occupancy 326system.cpu0.dcache.tags.occ_percent::total 0.966266 # Average percentage of cache occupancy 327system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 328system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 329system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 330system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 331system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 329system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966266 # Average percentage of cache occupancy 330system.cpu0.dcache.tags.occ_percent::total 0.966266 # Average percentage of cache occupancy 331system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 332system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 333system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 334system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 335system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 332system.cpu0.dcache.tags.tag_accesses 74108220 # Number of tag accesses 333system.cpu0.dcache.tags.data_accesses 74108220 # Number of data accesses 334system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 335system.cpu0.dcache.ReadReq_hits::cpu0.data 19107088 # number of ReadReq hits 336system.cpu0.dcache.ReadReq_hits::total 19107088 # number of ReadReq hits 337system.cpu0.dcache.WriteReq_hits::cpu0.data 15689072 # number of WriteReq hits 338system.cpu0.dcache.WriteReq_hits::total 15689072 # number of WriteReq hits 339system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346042 # number of SoftPFReq hits 340system.cpu0.dcache.SoftPFReq_hits::total 346042 # number of SoftPFReq hits 341system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379604 # number of LoadLockedReq hits 342system.cpu0.dcache.LoadLockedReq_hits::total 379604 # number of LoadLockedReq hits 343system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363048 # number of StoreCondReq hits 344system.cpu0.dcache.StoreCondReq_hits::total 363048 # number of StoreCondReq hits 345system.cpu0.dcache.demand_hits::cpu0.data 34796160 # number of demand (read+write) hits 346system.cpu0.dcache.demand_hits::total 34796160 # number of demand (read+write) hits 347system.cpu0.dcache.overall_hits::cpu0.data 35142202 # number of overall hits 348system.cpu0.dcache.overall_hits::total 35142202 # number of overall hits 349system.cpu0.dcache.ReadReq_misses::cpu0.data 373135 # number of ReadReq misses 350system.cpu0.dcache.ReadReq_misses::total 373135 # number of ReadReq misses 351system.cpu0.dcache.WriteReq_misses::cpu0.data 295787 # number of WriteReq misses 352system.cpu0.dcache.WriteReq_misses::total 295787 # number of WriteReq misses 353system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses 354system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses | 336system.cpu0.dcache.tags.tag_accesses 74108594 # Number of tag accesses 337system.cpu0.dcache.tags.data_accesses 74108594 # Number of data accesses 338system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 339system.cpu0.dcache.ReadReq_hits::cpu0.data 19107187 # number of ReadReq hits 340system.cpu0.dcache.ReadReq_hits::total 19107187 # number of ReadReq hits 341system.cpu0.dcache.WriteReq_hits::cpu0.data 15689146 # number of WriteReq hits 342system.cpu0.dcache.WriteReq_hits::total 15689146 # number of WriteReq hits 343system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346045 # number of SoftPFReq hits 344system.cpu0.dcache.SoftPFReq_hits::total 346045 # number of SoftPFReq hits 345system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379608 # number of LoadLockedReq hits 346system.cpu0.dcache.LoadLockedReq_hits::total 379608 # number of LoadLockedReq hits 347system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363041 # number of StoreCondReq hits 348system.cpu0.dcache.StoreCondReq_hits::total 363041 # number of StoreCondReq hits 349system.cpu0.dcache.demand_hits::cpu0.data 34796333 # number of demand (read+write) hits 350system.cpu0.dcache.demand_hits::total 34796333 # number of demand (read+write) hits 351system.cpu0.dcache.overall_hits::cpu0.data 35142378 # number of overall hits 352system.cpu0.dcache.overall_hits::total 35142378 # number of overall hits 353system.cpu0.dcache.ReadReq_misses::cpu0.data 373137 # number of ReadReq misses 354system.cpu0.dcache.ReadReq_misses::total 373137 # number of ReadReq misses 355system.cpu0.dcache.WriteReq_misses::cpu0.data 295785 # number of WriteReq misses 356system.cpu0.dcache.WriteReq_misses::total 295785 # number of WriteReq misses 357system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100323 # number of SoftPFReq misses 358system.cpu0.dcache.SoftPFReq_misses::total 100323 # number of SoftPFReq misses |
| 355system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses 356system.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses | 359system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses 360system.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses |
| 357system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18411 # number of StoreCondReq misses 358system.cpu0.dcache.StoreCondReq_misses::total 18411 # number of StoreCondReq misses | 361system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18422 # number of StoreCondReq misses 362system.cpu0.dcache.StoreCondReq_misses::total 18422 # number of StoreCondReq misses |
| 359system.cpu0.dcache.demand_misses::cpu0.data 668922 # number of demand (read+write) misses 360system.cpu0.dcache.demand_misses::total 668922 # number of demand (read+write) misses | 363system.cpu0.dcache.demand_misses::cpu0.data 668922 # number of demand (read+write) misses 364system.cpu0.dcache.demand_misses::total 668922 # number of demand (read+write) misses |
| 361system.cpu0.dcache.overall_misses::cpu0.data 769244 # number of overall misses 362system.cpu0.dcache.overall_misses::total 769244 # number of overall misses 363system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480223 # number of ReadReq accesses(hits+misses) 364system.cpu0.dcache.ReadReq_accesses::total 19480223 # number of ReadReq accesses(hits+misses) 365system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984859 # number of WriteReq accesses(hits+misses) 366system.cpu0.dcache.WriteReq_accesses::total 15984859 # number of WriteReq accesses(hits+misses) 367system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446364 # number of SoftPFReq accesses(hits+misses) 368system.cpu0.dcache.SoftPFReq_accesses::total 446364 # number of SoftPFReq accesses(hits+misses) 369system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386345 # number of LoadLockedReq accesses(hits+misses) 370system.cpu0.dcache.LoadLockedReq_accesses::total 386345 # number of LoadLockedReq accesses(hits+misses) 371system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381459 # number of StoreCondReq accesses(hits+misses) 372system.cpu0.dcache.StoreCondReq_accesses::total 381459 # number of StoreCondReq accesses(hits+misses) 373system.cpu0.dcache.demand_accesses::cpu0.data 35465082 # number of demand (read+write) accesses 374system.cpu0.dcache.demand_accesses::total 35465082 # number of demand (read+write) accesses 375system.cpu0.dcache.overall_accesses::cpu0.data 35911446 # number of overall (read+write) accesses 376system.cpu0.dcache.overall_accesses::total 35911446 # number of overall (read+write) accesses | 365system.cpu0.dcache.overall_misses::cpu0.data 769245 # number of overall misses 366system.cpu0.dcache.overall_misses::total 769245 # number of overall misses 367system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480324 # number of ReadReq accesses(hits+misses) 368system.cpu0.dcache.ReadReq_accesses::total 19480324 # number of ReadReq accesses(hits+misses) 369system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984931 # number of WriteReq accesses(hits+misses) 370system.cpu0.dcache.WriteReq_accesses::total 15984931 # number of WriteReq accesses(hits+misses) 371system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446368 # number of SoftPFReq accesses(hits+misses) 372system.cpu0.dcache.SoftPFReq_accesses::total 446368 # number of SoftPFReq accesses(hits+misses) 373system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386349 # number of LoadLockedReq accesses(hits+misses) 374system.cpu0.dcache.LoadLockedReq_accesses::total 386349 # number of LoadLockedReq accesses(hits+misses) 375system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381463 # number of StoreCondReq accesses(hits+misses) 376system.cpu0.dcache.StoreCondReq_accesses::total 381463 # number of StoreCondReq accesses(hits+misses) 377system.cpu0.dcache.demand_accesses::cpu0.data 35465255 # number of demand (read+write) accesses 378system.cpu0.dcache.demand_accesses::total 35465255 # number of demand (read+write) accesses 379system.cpu0.dcache.overall_accesses::cpu0.data 35911623 # number of overall (read+write) accesses 380system.cpu0.dcache.overall_accesses::total 35911623 # number of overall (read+write) accesses |
| 377system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses 378system.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses 379system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018504 # miss rate for WriteReq accesses 380system.cpu0.dcache.WriteReq_miss_rate::total 0.018504 # miss rate for WriteReq accesses 381system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 # miss rate for SoftPFReq accesses 382system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses 383system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses 384system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses | 381system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses 382system.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses 383system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018504 # miss rate for WriteReq accesses 384system.cpu0.dcache.WriteReq_miss_rate::total 0.018504 # miss rate for WriteReq accesses 385system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 # miss rate for SoftPFReq accesses 386system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses 387system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses 388system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses |
| 385system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048265 # miss rate for StoreCondReq accesses 386system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048265 # miss rate for StoreCondReq accesses | 389system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048293 # miss rate for StoreCondReq accesses 390system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048293 # miss rate for StoreCondReq accesses |
| 387system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses 388system.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses 389system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021421 # miss rate for overall accesses 390system.cpu0.dcache.overall_miss_rate::total 0.021421 # miss rate for overall accesses 391system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 392system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 393system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 394system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 395system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 396system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 391system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses 392system.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses 393system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021421 # miss rate for overall accesses 394system.cpu0.dcache.overall_miss_rate::total 0.021421 # miss rate for overall accesses 395system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 397system.cpu0.dcache.writebacks::writebacks 693483 # number of writebacks 398system.cpu0.dcache.writebacks::total 693483 # number of writebacks 399system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 400system.cpu0.icache.tags.replacements 1109362 # number of replacements | 401system.cpu0.dcache.writebacks::writebacks 693487 # number of writebacks 402system.cpu0.dcache.writebacks::total 693487 # number of writebacks 403system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 404system.cpu0.icache.tags.replacements 1109393 # number of replacements |
| 401system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use | 405system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use |
| 402system.cpu0.icache.tags.total_refs 96325777 # Total number of references to valid blocks. 403system.cpu0.icache.tags.sampled_refs 1109874 # Sample count of references to valid blocks. 404system.cpu0.icache.tags.avg_refs 86.789831 # Average number of references to valid blocks. | 406system.cpu0.icache.tags.total_refs 96326253 # Total number of references to valid blocks. 407system.cpu0.icache.tags.sampled_refs 1109905 # Sample count of references to valid blocks. 408system.cpu0.icache.tags.avg_refs 86.787836 # Average number of references to valid blocks. |
| 405system.cpu0.icache.tags.warmup_cycle 6345718500 # Cycle when the warmup percentage was hit. 406system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 407system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 408system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 409system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 410system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 411system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 412system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 413system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 409system.cpu0.icache.tags.warmup_cycle 6345718500 # Cycle when the warmup percentage was hit. 410system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 411system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 412system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 413system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 414system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 415system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 416system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 417system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 414system.cpu0.icache.tags.tag_accesses 195981203 # Number of tag accesses 415system.cpu0.icache.tags.data_accesses 195981203 # Number of data accesses 416system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 417system.cpu0.icache.ReadReq_hits::cpu0.inst 96325777 # number of ReadReq hits 418system.cpu0.icache.ReadReq_hits::total 96325777 # number of ReadReq hits 419system.cpu0.icache.demand_hits::cpu0.inst 96325777 # number of demand (read+write) hits 420system.cpu0.icache.demand_hits::total 96325777 # number of demand (read+write) hits 421system.cpu0.icache.overall_hits::cpu0.inst 96325777 # number of overall hits 422system.cpu0.icache.overall_hits::total 96325777 # number of overall hits 423system.cpu0.icache.ReadReq_misses::cpu0.inst 1109883 # number of ReadReq misses 424system.cpu0.icache.ReadReq_misses::total 1109883 # number of ReadReq misses 425system.cpu0.icache.demand_misses::cpu0.inst 1109883 # number of demand (read+write) misses 426system.cpu0.icache.demand_misses::total 1109883 # number of demand (read+write) misses 427system.cpu0.icache.overall_misses::cpu0.inst 1109883 # number of overall misses 428system.cpu0.icache.overall_misses::total 1109883 # number of overall misses 429system.cpu0.icache.ReadReq_accesses::cpu0.inst 97435660 # number of ReadReq accesses(hits+misses) 430system.cpu0.icache.ReadReq_accesses::total 97435660 # number of ReadReq accesses(hits+misses) 431system.cpu0.icache.demand_accesses::cpu0.inst 97435660 # number of demand (read+write) accesses 432system.cpu0.icache.demand_accesses::total 97435660 # number of demand (read+write) accesses 433system.cpu0.icache.overall_accesses::cpu0.inst 97435660 # number of overall (read+write) accesses 434system.cpu0.icache.overall_accesses::total 97435660 # number of overall (read+write) accesses | 418system.cpu0.icache.tags.tag_accesses 195982248 # Number of tag accesses 419system.cpu0.icache.tags.data_accesses 195982248 # Number of data accesses 420system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 421system.cpu0.icache.ReadReq_hits::cpu0.inst 96326253 # number of ReadReq hits 422system.cpu0.icache.ReadReq_hits::total 96326253 # number of ReadReq hits 423system.cpu0.icache.demand_hits::cpu0.inst 96326253 # number of demand (read+write) hits 424system.cpu0.icache.demand_hits::total 96326253 # number of demand (read+write) hits 425system.cpu0.icache.overall_hits::cpu0.inst 96326253 # number of overall hits 426system.cpu0.icache.overall_hits::total 96326253 # number of overall hits 427system.cpu0.icache.ReadReq_misses::cpu0.inst 1109914 # number of ReadReq misses 428system.cpu0.icache.ReadReq_misses::total 1109914 # number of ReadReq misses 429system.cpu0.icache.demand_misses::cpu0.inst 1109914 # number of demand (read+write) misses 430system.cpu0.icache.demand_misses::total 1109914 # number of demand (read+write) misses 431system.cpu0.icache.overall_misses::cpu0.inst 1109914 # number of overall misses 432system.cpu0.icache.overall_misses::total 1109914 # number of overall misses 433system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436167 # number of ReadReq accesses(hits+misses) 434system.cpu0.icache.ReadReq_accesses::total 97436167 # number of ReadReq accesses(hits+misses) 435system.cpu0.icache.demand_accesses::cpu0.inst 97436167 # number of demand (read+write) accesses 436system.cpu0.icache.demand_accesses::total 97436167 # number of demand (read+write) accesses 437system.cpu0.icache.overall_accesses::cpu0.inst 97436167 # number of overall (read+write) accesses 438system.cpu0.icache.overall_accesses::total 97436167 # number of overall (read+write) accesses |
| 435system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011391 # miss rate for ReadReq accesses 436system.cpu0.icache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 437system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011391 # miss rate for demand accesses 438system.cpu0.icache.demand_miss_rate::total 0.011391 # miss rate for demand accesses 439system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011391 # miss rate for overall accesses 440system.cpu0.icache.overall_miss_rate::total 0.011391 # miss rate for overall accesses 441system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 442system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 443system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 444system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 445system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 446system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 439system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011391 # miss rate for ReadReq accesses 440system.cpu0.icache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 441system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011391 # miss rate for demand accesses 442system.cpu0.icache.demand_miss_rate::total 0.011391 # miss rate for demand accesses 443system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011391 # miss rate for overall accesses 444system.cpu0.icache.overall_miss_rate::total 0.011391 # miss rate for overall accesses 445system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 446system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 447system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 448system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 449system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 450system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 447system.cpu0.icache.writebacks::writebacks 1109362 # number of writebacks 448system.cpu0.icache.writebacks::total 1109362 # number of writebacks 449system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 451system.cpu0.icache.writebacks::writebacks 1109393 # number of writebacks 452system.cpu0.icache.writebacks::total 1109393 # number of writebacks 453system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 450system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 451system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 452system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 453system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 454system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 455system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 454system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 455system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 456system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 457system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 458system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 459system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 456system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 457system.cpu0.l2cache.tags.replacements 244755 # number of replacements 458system.cpu0.l2cache.tags.tagsinuse 15690.306286 # Cycle average of tags in use 459system.cpu0.l2cache.tags.total_refs 1516961 # Total number of references to valid blocks. 460system.cpu0.l2cache.tags.sampled_refs 260398 # Sample count of references to valid blocks. 461system.cpu0.l2cache.tags.avg_refs 5.825548 # Average number of references to valid blocks. | 460system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 461system.cpu0.l2cache.tags.replacements 245116 # number of replacements 462system.cpu0.l2cache.tags.tagsinuse 15690.277500 # Cycle average of tags in use 463system.cpu0.l2cache.tags.total_refs 1517282 # Total number of references to valid blocks. 464system.cpu0.l2cache.tags.sampled_refs 260748 # Sample count of references to valid blocks. 465system.cpu0.l2cache.tags.avg_refs 5.818959 # Average number of references to valid blocks. |
| 462system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. | 466system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. |
| 463system.cpu0.l2cache.tags.occ_blocks::writebacks 15688.001822 # Average occupied blocks per requestor 464system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.238695 # Average occupied blocks per requestor 465system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065768 # Average occupied blocks per requestor | 467system.cpu0.l2cache.tags.occ_blocks::writebacks 15688.004723 # Average occupied blocks per requestor 468system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.222065 # Average occupied blocks per requestor 469system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.050711 # Average occupied blocks per requestor |
| 466system.cpu0.l2cache.tags.occ_percent::writebacks 0.957520 # Average percentage of cache occupancy | 470system.cpu0.l2cache.tags.occ_percent::writebacks 0.957520 # Average percentage of cache occupancy |
| 467system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000137 # Average percentage of cache occupancy 468system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 469system.cpu0.l2cache.tags.occ_percent::total 0.957660 # Average percentage of cache occupancy 470system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 471system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15637 # Occupied blocks per task id 472system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 473system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 527 # Occupied blocks per task id 476system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 887 # Occupied blocks per task id 477system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7822 # Occupied blocks per task id 478system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5177 # Occupied blocks per task id 479system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1224 # Occupied blocks per task id 480system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 481system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.954407 # Percentage of cache occupancy per task id 482system.cpu0.l2cache.tags.tag_accesses 60864487 # Number of tag accesses 483system.cpu0.l2cache.tags.data_accesses 60864487 # Number of data accesses 484system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 485system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10088 # number of ReadReq hits 486system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4467 # number of ReadReq hits 487system.cpu0.l2cache.ReadReq_hits::total 14555 # number of ReadReq hits 488system.cpu0.l2cache.WritebackDirty_hits::writebacks 510065 # number of WritebackDirty hits 489system.cpu0.l2cache.WritebackDirty_hits::total 510065 # number of WritebackDirty hits 490system.cpu0.l2cache.WritebackClean_hits::writebacks 1264919 # number of WritebackClean hits 491system.cpu0.l2cache.WritebackClean_hits::total 1264919 # number of WritebackClean hits 492system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94269 # number of ReadExReq hits 493system.cpu0.l2cache.ReadExReq_hits::total 94269 # number of ReadExReq hits 494system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1050188 # number of ReadCleanReq hits 495system.cpu0.l2cache.ReadCleanReq_hits::total 1050188 # number of ReadCleanReq hits 496system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 344415 # number of ReadSharedReq hits 497system.cpu0.l2cache.ReadSharedReq_hits::total 344415 # number of ReadSharedReq hits 498system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10088 # number of demand (read+write) hits 499system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4467 # number of demand (read+write) hits 500system.cpu0.l2cache.demand_hits::cpu0.inst 1050188 # number of demand (read+write) hits 501system.cpu0.l2cache.demand_hits::cpu0.data 438684 # number of demand (read+write) hits 502system.cpu0.l2cache.demand_hits::total 1503427 # number of demand (read+write) hits 503system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10088 # number of overall hits 504system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4467 # number of overall hits 505system.cpu0.l2cache.overall_hits::cpu0.inst 1050188 # number of overall hits 506system.cpu0.l2cache.overall_hits::cpu0.data 438684 # number of overall hits 507system.cpu0.l2cache.overall_hits::total 1503427 # number of overall hits 508system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses 509system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses 510system.cpu0.l2cache.ReadReq_misses::total 414 # number of ReadReq misses 511system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26265 # number of UpgradeReq misses 512system.cpu0.l2cache.UpgradeReq_misses::total 26265 # number of UpgradeReq misses 513system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18411 # number of SCUpgradeReq misses 514system.cpu0.l2cache.SCUpgradeReq_misses::total 18411 # number of SCUpgradeReq misses 515system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175253 # number of ReadExReq misses 516system.cpu0.l2cache.ReadExReq_misses::total 175253 # number of ReadExReq misses 517system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 59695 # number of ReadCleanReq misses 518system.cpu0.l2cache.ReadCleanReq_misses::total 59695 # number of ReadCleanReq misses 519system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 135783 # number of ReadSharedReq misses 520system.cpu0.l2cache.ReadSharedReq_misses::total 135783 # number of ReadSharedReq misses 521system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses 522system.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses 523system.cpu0.l2cache.demand_misses::cpu0.inst 59695 # number of demand (read+write) misses 524system.cpu0.l2cache.demand_misses::cpu0.data 311036 # number of demand (read+write) misses 525system.cpu0.l2cache.demand_misses::total 371145 # number of demand (read+write) misses 526system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses 527system.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses 528system.cpu0.l2cache.overall_misses::cpu0.inst 59695 # number of overall misses 529system.cpu0.l2cache.overall_misses::cpu0.data 311036 # number of overall misses 530system.cpu0.l2cache.overall_misses::total 371145 # number of overall misses 531system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10362 # number of ReadReq accesses(hits+misses) 532system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4607 # number of ReadReq accesses(hits+misses) 533system.cpu0.l2cache.ReadReq_accesses::total 14969 # number of ReadReq accesses(hits+misses) 534system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510065 # number of WritebackDirty accesses(hits+misses) 535system.cpu0.l2cache.WritebackDirty_accesses::total 510065 # number of WritebackDirty accesses(hits+misses) 536system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264919 # number of WritebackClean accesses(hits+misses) 537system.cpu0.l2cache.WritebackClean_accesses::total 1264919 # number of WritebackClean accesses(hits+misses) 538system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26265 # number of UpgradeReq accesses(hits+misses) 539system.cpu0.l2cache.UpgradeReq_accesses::total 26265 # number of UpgradeReq accesses(hits+misses) 540system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18411 # number of SCUpgradeReq accesses(hits+misses) 541system.cpu0.l2cache.SCUpgradeReq_accesses::total 18411 # number of SCUpgradeReq accesses(hits+misses) 542system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269522 # number of ReadExReq accesses(hits+misses) 543system.cpu0.l2cache.ReadExReq_accesses::total 269522 # number of ReadExReq accesses(hits+misses) 544system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109883 # number of ReadCleanReq accesses(hits+misses) 545system.cpu0.l2cache.ReadCleanReq_accesses::total 1109883 # number of ReadCleanReq accesses(hits+misses) 546system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480198 # number of ReadSharedReq accesses(hits+misses) 547system.cpu0.l2cache.ReadSharedReq_accesses::total 480198 # number of ReadSharedReq accesses(hits+misses) 548system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10362 # number of demand (read+write) accesses 549system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4607 # number of demand (read+write) accesses 550system.cpu0.l2cache.demand_accesses::cpu0.inst 1109883 # number of demand (read+write) accesses 551system.cpu0.l2cache.demand_accesses::cpu0.data 749720 # number of demand (read+write) accesses 552system.cpu0.l2cache.demand_accesses::total 1874572 # number of demand (read+write) accesses 553system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10362 # number of overall (read+write) accesses 554system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4607 # number of overall (read+write) accesses 555system.cpu0.l2cache.overall_accesses::cpu0.inst 1109883 # number of overall (read+write) accesses 556system.cpu0.l2cache.overall_accesses::cpu0.data 749720 # number of overall (read+write) accesses 557system.cpu0.l2cache.overall_accesses::total 1874572 # number of overall (read+write) accesses 558system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for ReadReq accesses 559system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030389 # miss rate for ReadReq accesses 560system.cpu0.l2cache.ReadReq_miss_rate::total 0.027657 # miss rate for ReadReq accesses | 471system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000136 # Average percentage of cache occupancy 472system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy 473system.cpu0.l2cache.tags.occ_percent::total 0.957659 # Average percentage of cache occupancy 474system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id 475system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15629 # Occupied blocks per task id 476system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 477system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 478system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 528 # Occupied blocks per task id 479system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 881 # Occupied blocks per task id 480system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7801 # Occupied blocks per task id 481system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5151 # Occupied blocks per task id 482system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1268 # Occupied blocks per task id 483system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id 484system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.953918 # Percentage of cache occupancy per task id 485system.cpu0.l2cache.tags.tag_accesses 60866660 # Number of tag accesses 486system.cpu0.l2cache.tags.data_accesses 60866660 # Number of data accesses 487system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 488system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10118 # number of ReadReq hits 489system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4491 # number of ReadReq hits 490system.cpu0.l2cache.ReadReq_hits::total 14609 # number of ReadReq hits 491system.cpu0.l2cache.WritebackDirty_hits::writebacks 509920 # number of WritebackDirty hits 492system.cpu0.l2cache.WritebackDirty_hits::total 509920 # number of WritebackDirty hits 493system.cpu0.l2cache.WritebackClean_hits::writebacks 1265098 # number of WritebackClean hits 494system.cpu0.l2cache.WritebackClean_hits::total 1265098 # number of WritebackClean hits 495system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94164 # number of ReadExReq hits 496system.cpu0.l2cache.ReadExReq_hits::total 94164 # number of ReadExReq hits 497system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1049983 # number of ReadCleanReq hits 498system.cpu0.l2cache.ReadCleanReq_hits::total 1049983 # number of ReadCleanReq hits 499system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 344453 # number of ReadSharedReq hits 500system.cpu0.l2cache.ReadSharedReq_hits::total 344453 # number of ReadSharedReq hits 501system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10118 # number of demand (read+write) hits 502system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4491 # number of demand (read+write) hits 503system.cpu0.l2cache.demand_hits::cpu0.inst 1049983 # number of demand (read+write) hits 504system.cpu0.l2cache.demand_hits::cpu0.data 438617 # number of demand (read+write) hits 505system.cpu0.l2cache.demand_hits::total 1503209 # number of demand (read+write) hits 506system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10118 # number of overall hits 507system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4491 # number of overall hits 508system.cpu0.l2cache.overall_hits::cpu0.inst 1049983 # number of overall hits 509system.cpu0.l2cache.overall_hits::cpu0.data 438617 # number of overall hits 510system.cpu0.l2cache.overall_hits::total 1503209 # number of overall hits 511system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 266 # number of ReadReq misses 512system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 132 # number of ReadReq misses 513system.cpu0.l2cache.ReadReq_misses::total 398 # number of ReadReq misses 514system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26262 # number of UpgradeReq misses 515system.cpu0.l2cache.UpgradeReq_misses::total 26262 # number of UpgradeReq misses 516system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18422 # number of SCUpgradeReq misses 517system.cpu0.l2cache.SCUpgradeReq_misses::total 18422 # number of SCUpgradeReq misses 518system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175359 # number of ReadExReq misses 519system.cpu0.l2cache.ReadExReq_misses::total 175359 # number of ReadExReq misses 520system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 59931 # number of ReadCleanReq misses 521system.cpu0.l2cache.ReadCleanReq_misses::total 59931 # number of ReadCleanReq misses 522system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 135748 # number of ReadSharedReq misses 523system.cpu0.l2cache.ReadSharedReq_misses::total 135748 # number of ReadSharedReq misses 524system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 266 # number of demand (read+write) misses 525system.cpu0.l2cache.demand_misses::cpu0.itb.walker 132 # number of demand (read+write) misses 526system.cpu0.l2cache.demand_misses::cpu0.inst 59931 # number of demand (read+write) misses 527system.cpu0.l2cache.demand_misses::cpu0.data 311107 # number of demand (read+write) misses 528system.cpu0.l2cache.demand_misses::total 371436 # number of demand (read+write) misses 529system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 266 # number of overall misses 530system.cpu0.l2cache.overall_misses::cpu0.itb.walker 132 # number of overall misses 531system.cpu0.l2cache.overall_misses::cpu0.inst 59931 # number of overall misses 532system.cpu0.l2cache.overall_misses::cpu0.data 311107 # number of overall misses 533system.cpu0.l2cache.overall_misses::total 371436 # number of overall misses 534system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10384 # number of ReadReq accesses(hits+misses) 535system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4623 # number of ReadReq accesses(hits+misses) 536system.cpu0.l2cache.ReadReq_accesses::total 15007 # number of ReadReq accesses(hits+misses) 537system.cpu0.l2cache.WritebackDirty_accesses::writebacks 509920 # number of WritebackDirty accesses(hits+misses) 538system.cpu0.l2cache.WritebackDirty_accesses::total 509920 # number of WritebackDirty accesses(hits+misses) 539system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265098 # number of WritebackClean accesses(hits+misses) 540system.cpu0.l2cache.WritebackClean_accesses::total 1265098 # number of WritebackClean accesses(hits+misses) 541system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26262 # number of UpgradeReq accesses(hits+misses) 542system.cpu0.l2cache.UpgradeReq_accesses::total 26262 # number of UpgradeReq accesses(hits+misses) 543system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18422 # number of SCUpgradeReq accesses(hits+misses) 544system.cpu0.l2cache.SCUpgradeReq_accesses::total 18422 # number of SCUpgradeReq accesses(hits+misses) 545system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) 546system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) 547system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109914 # number of ReadCleanReq accesses(hits+misses) 548system.cpu0.l2cache.ReadCleanReq_accesses::total 1109914 # number of ReadCleanReq accesses(hits+misses) 549system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480201 # number of ReadSharedReq accesses(hits+misses) 550system.cpu0.l2cache.ReadSharedReq_accesses::total 480201 # number of ReadSharedReq accesses(hits+misses) 551system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10384 # number of demand (read+write) accesses 552system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4623 # number of demand (read+write) accesses 553system.cpu0.l2cache.demand_accesses::cpu0.inst 1109914 # number of demand (read+write) accesses 554system.cpu0.l2cache.demand_accesses::cpu0.data 749724 # number of demand (read+write) accesses 555system.cpu0.l2cache.demand_accesses::total 1874645 # number of demand (read+write) accesses 556system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10384 # number of overall (read+write) accesses 557system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4623 # number of overall (read+write) accesses 558system.cpu0.l2cache.overall_accesses::cpu0.inst 1109914 # number of overall (read+write) accesses 559system.cpu0.l2cache.overall_accesses::cpu0.data 749724 # number of overall (read+write) accesses 560system.cpu0.l2cache.overall_accesses::total 1874645 # number of overall (read+write) accesses 561system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.025616 # miss rate for ReadReq accesses 562system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028553 # miss rate for ReadReq accesses 563system.cpu0.l2cache.ReadReq_miss_rate::total 0.026521 # miss rate for ReadReq accesses |
| 561system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 562system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 563system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 564system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 564system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 565system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 566system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 567system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 565system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650236 # miss rate for ReadExReq accesses 566system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650236 # miss rate for ReadExReq accesses 567system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.053785 # miss rate for ReadCleanReq accesses 568system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.053785 # miss rate for ReadCleanReq accesses 569system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.282765 # miss rate for ReadSharedReq accesses 570system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.282765 # miss rate for ReadSharedReq accesses 571system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for demand accesses 572system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030389 # miss rate for demand accesses 573system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.053785 # miss rate for demand accesses 574system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.414870 # miss rate for demand accesses 575system.cpu0.l2cache.demand_miss_rate::total 0.197989 # miss rate for demand accesses 576system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for overall accesses 577system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030389 # miss rate for overall accesses 578system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.053785 # miss rate for overall accesses 579system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.414870 # miss rate for overall accesses 580system.cpu0.l2cache.overall_miss_rate::total 0.197989 # miss rate for overall accesses | 568system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650627 # miss rate for ReadExReq accesses 569system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650627 # miss rate for ReadExReq accesses 570system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.053996 # miss rate for ReadCleanReq accesses 571system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.053996 # miss rate for ReadCleanReq accesses 572system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.282690 # miss rate for ReadSharedReq accesses 573system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.282690 # miss rate for ReadSharedReq accesses 574system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.025616 # miss rate for demand accesses 575system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028553 # miss rate for demand accesses 576system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.053996 # miss rate for demand accesses 577system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.414962 # miss rate for demand accesses 578system.cpu0.l2cache.demand_miss_rate::total 0.198137 # miss rate for demand accesses 579system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.025616 # miss rate for overall accesses 580system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028553 # miss rate for overall accesses 581system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.053996 # miss rate for overall accesses 582system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.414962 # miss rate for overall accesses 583system.cpu0.l2cache.overall_miss_rate::total 0.198137 # miss rate for overall accesses |
| 581system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 582system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 583system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 584system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 585system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 586system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 584system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 585system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 586system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 587system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 588system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 589system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 587system.cpu0.l2cache.writebacks::writebacks 192868 # number of writebacks 588system.cpu0.l2cache.writebacks::total 192868 # number of writebacks 589system.cpu0.toL2Bus.snoop_filter.tot_requests 3719490 # Total number of requests made to the snoop filter. 590system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859911 # Number of requests hitting in the snoop filter with a single holder of the requested data. 591system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 592system.cpu0.toL2Bus.snoop_filter.tot_snoops 111560 # Total number of snoops made to the snoop filter. 593system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 109856 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 594system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1704 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 595system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 590system.cpu0.l2cache.writebacks::writebacks 192903 # number of writebacks 591system.cpu0.l2cache.writebacks::total 192903 # number of writebacks 592system.cpu0.toL2Bus.snoop_filter.tot_requests 3719568 # Total number of requests made to the snoop filter. 593system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859945 # Number of requests hitting in the snoop filter with a single holder of the requested data. 594system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 595system.cpu0.toL2Bus.snoop_filter.tot_snoops 111615 # Total number of snoops made to the snoop filter. 596system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 109909 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 597system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1706 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 598system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 596system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution | 599system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution |
| 597system.cpu0.toL2Bus.trans_dist::ReadResp 1651491 # Transaction distribution | 600system.cpu0.toL2Bus.trans_dist::ReadResp 1651525 # Transaction distribution |
| 598system.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution | 601system.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution 602system.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution |
| 600system.cpu0.toL2Bus.trans_dist::WritebackDirty 510065 # Transaction distribution 601system.cpu0.toL2Bus.trans_dist::WritebackClean 1292780 # Transaction distribution 602system.cpu0.toL2Bus.trans_dist::UpgradeReq 26265 # Transaction distribution 603system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18411 # Transaction distribution 604system.cpu0.toL2Bus.trans_dist::UpgradeResp 44676 # Transaction distribution 605system.cpu0.toL2Bus.trans_dist::ReadExReq 269522 # Transaction distribution 606system.cpu0.toL2Bus.trans_dist::ReadExResp 269522 # Transaction distribution 607system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109883 # Transaction distribution 608system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480198 # Transaction distribution 609system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347172 # Packet count per connected master and slave (bytes) 610system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402107 # Packet count per connected master and slave (bytes) | 603system.cpu0.toL2Bus.trans_dist::WritebackDirty 509920 # Transaction distribution 604system.cpu0.toL2Bus.trans_dist::WritebackClean 1292960 # Transaction distribution 605system.cpu0.toL2Bus.trans_dist::UpgradeReq 26262 # Transaction distribution 606system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18422 # Transaction distribution 607system.cpu0.toL2Bus.trans_dist::UpgradeResp 44684 # Transaction distribution 608system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution 609system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution 610system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109914 # Transaction distribution 611system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480201 # Transaction distribution 612system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347265 # Packet count per connected master and slave (bytes) 613system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402135 # Packet count per connected master and slave (bytes) |
| 611system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 612system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) | 614system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 615system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) |
| 613system.cpu0.toL2Bus.pkt_count::total 5790903 # Packet count per connected master and slave (bytes) 614system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142067768 # Cumulative packet size per connected master and slave (bytes) 615system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92555520 # Cumulative packet size per connected master and slave (bytes) | 616system.cpu0.toL2Bus.pkt_count::total 5791024 # Packet count per connected master and slave (bytes) 617system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142071736 # Cumulative packet size per connected master and slave (bytes) 618system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92556032 # Cumulative packet size per connected master and slave (bytes) |
| 616system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 617system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) | 619system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 620system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) |
| 618system.cpu0.toL2Bus.pkt_size::total 234706536 # Cumulative packet size per connected master and slave (bytes) 619system.cpu0.toL2Bus.snoops 530280 # Total snoops (count) 620system.cpu0.toL2Bus.snoopTraffic 12377344 # Total snoop traffic (bytes) 621system.cpu0.toL2Bus.snoop_fanout::samples 4224545 # Request fanout histogram 622system.cpu0.toL2Bus.snoop_fanout::mean 0.042934 # Request fanout histogram 623system.cpu0.toL2Bus.snoop_fanout::stdev 0.204688 # Request fanout histogram | 621system.cpu0.toL2Bus.pkt_size::total 234711016 # Cumulative packet size per connected master and slave (bytes) 622system.cpu0.toL2Bus.snoops 530821 # Total snoops (count) 623system.cpu0.toL2Bus.snoopTraffic 12390272 # Total snoop traffic (bytes) 624system.cpu0.toL2Bus.snoop_fanout::samples 4225152 # Request fanout histogram 625system.cpu0.toL2Bus.snoop_fanout::mean 0.042946 # Request fanout histogram 626system.cpu0.toL2Bus.snoop_fanout::stdev 0.204717 # Request fanout histogram |
| 624system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 627system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 625system.cpu0.toL2Bus.snoop_fanout::0 4044873 95.75% 95.75% # Request fanout histogram 626system.cpu0.toL2Bus.snoop_fanout::1 177968 4.21% 99.96% # Request fanout histogram 627system.cpu0.toL2Bus.snoop_fanout::2 1704 0.04% 100.00% # Request fanout histogram | 628system.cpu0.toL2Bus.snoop_fanout::0 4045406 95.75% 95.75% # Request fanout histogram 629system.cpu0.toL2Bus.snoop_fanout::1 178040 4.21% 99.96% # Request fanout histogram 630system.cpu0.toL2Bus.snoop_fanout::2 1706 0.04% 100.00% # Request fanout histogram |
| 628system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 629system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 630system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 631system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 632system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 633system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 631system.cpu0.toL2Bus.snoop_fanout::total 4224545 # Request fanout histogram 632system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 634system.cpu0.toL2Bus.snoop_fanout::total 4225152 # Request fanout histogram 635system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 633system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 640system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 654system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 655system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 656system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 657system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 658system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 659system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 660system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 661system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 636system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 640system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 641system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 642system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 643system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 657system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 658system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 659system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 660system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 661system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 662system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 663system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 664system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 662system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 665system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 663system.cpu1.dtb.walker.walks 3359 # Table walker walks requested 664system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 665system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 666system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 667system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 668system.cpu1.dtb.walker.walksPending::samples -1804201736 # Table walker pending requests distribution 669system.cpu1.dtb.walker.walksPending::0 -1804201736 100.00% 100.00% # Table walker pending requests distribution 670system.cpu1.dtb.walker.walksPending::total -1804201736 # Table walker pending requests distribution --- 4 unchanged lines hidden (view full) --- 675system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 676system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 677system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 678system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 679system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 680system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 681system.cpu1.dtb.inst_hits 0 # ITB inst hits 682system.cpu1.dtb.inst_misses 0 # ITB inst misses | 666system.cpu1.dtb.walker.walks 3359 # Table walker walks requested 667system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 668system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 669system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 670system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 671system.cpu1.dtb.walker.walksPending::samples -1804201736 # Table walker pending requests distribution 672system.cpu1.dtb.walker.walksPending::0 -1804201736 100.00% 100.00% # Table walker pending requests distribution 673system.cpu1.dtb.walker.walksPending::total -1804201736 # Table walker pending requests distribution --- 4 unchanged lines hidden (view full) --- 678system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 679system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 680system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 681system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 682system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 683system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 684system.cpu1.dtb.inst_hits 0 # ITB inst hits 685system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 683system.cpu1.dtb.read_hits 12172373 # DTB read hits | 686system.cpu1.dtb.read_hits 12172433 # DTB read hits |
| 684system.cpu1.dtb.read_misses 2853 # DTB read misses | 687system.cpu1.dtb.read_misses 2853 # DTB read misses |
| 685system.cpu1.dtb.write_hits 7586083 # DTB write hits | 688system.cpu1.dtb.write_hits 7586113 # DTB write hits |
| 686system.cpu1.dtb.write_misses 506 # DTB write misses 687system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 688system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 689system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 690system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 691system.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB 692system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 693system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 694system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 695system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions | 689system.cpu1.dtb.write_misses 506 # DTB write misses 690system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 691system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 692system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 693system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 694system.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB 695system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 696system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 697system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 698system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions |
| 696system.cpu1.dtb.read_accesses 12175226 # DTB read accesses 697system.cpu1.dtb.write_accesses 7586589 # DTB write accesses | 699system.cpu1.dtb.read_accesses 12175286 # DTB read accesses 700system.cpu1.dtb.write_accesses 7586619 # DTB write accesses |
| 698system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 701system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 699system.cpu1.dtb.hits 19758456 # DTB hits | 702system.cpu1.dtb.hits 19758546 # DTB hits |
| 700system.cpu1.dtb.misses 3359 # DTB misses | 703system.cpu1.dtb.misses 3359 # DTB misses |
| 701system.cpu1.dtb.accesses 19761815 # DTB accesses 702system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 704system.cpu1.dtb.accesses 19761905 # DTB accesses 705system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 703system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 706system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 707system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 708system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 709system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 710system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 724system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 725system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 726system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 727system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 728system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 729system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 730system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 731system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 706system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 707system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 708system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 709system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 710system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 711system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 712system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 713system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 727system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 728system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 729system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 730system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 731system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 732system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 733system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 734system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 732system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 735system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 733system.cpu1.itb.walker.walks 1734 # Table walker walks requested 734system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 735system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 736system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 737system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 738system.cpu1.itb.walker.walksPending::samples -1804204236 # Table walker pending requests distribution 739system.cpu1.itb.walker.walksPending::0 -1804204236 100.00% 100.00% # Table walker pending requests distribution 740system.cpu1.itb.walker.walksPending::total -1804204236 # Table walker pending requests distribution 741system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 742system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 743system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 744system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 745system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 746system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 747system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 748system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 749system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 750system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst | 736system.cpu1.itb.walker.walks 1734 # Table walker walks requested 737system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 738system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 739system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 740system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 741system.cpu1.itb.walker.walksPending::samples -1804204236 # Table walker pending requests distribution 742system.cpu1.itb.walker.walksPending::0 -1804204236 100.00% 100.00% # Table walker pending requests distribution 743system.cpu1.itb.walker.walksPending::total -1804204236 # Table walker pending requests distribution 744system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 745system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 746system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 747system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 748system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 749system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 750system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 751system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 752system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 753system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst |
| 751system.cpu1.itb.inst_hits 53665127 # ITB inst hits | 754system.cpu1.itb.inst_hits 53665397 # ITB inst hits |
| 752system.cpu1.itb.inst_misses 1734 # ITB inst misses 753system.cpu1.itb.read_hits 0 # DTB read hits 754system.cpu1.itb.read_misses 0 # DTB read misses 755system.cpu1.itb.write_hits 0 # DTB write hits 756system.cpu1.itb.write_misses 0 # DTB write misses 757system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 758system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 759system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 760system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 761system.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB 762system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 763system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 764system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 765system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 766system.cpu1.itb.read_accesses 0 # DTB read accesses 767system.cpu1.itb.write_accesses 0 # DTB write accesses | 755system.cpu1.itb.inst_misses 1734 # ITB inst misses 756system.cpu1.itb.read_hits 0 # DTB read hits 757system.cpu1.itb.read_misses 0 # DTB read misses 758system.cpu1.itb.write_hits 0 # DTB write hits 759system.cpu1.itb.write_misses 0 # DTB write misses 760system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 761system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 762system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 763system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 764system.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB 765system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 766system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 767system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 768system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 769system.cpu1.itb.read_accesses 0 # DTB read accesses 770system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 768system.cpu1.itb.inst_accesses 53666861 # ITB inst accesses 769system.cpu1.itb.hits 53665127 # DTB hits | 771system.cpu1.itb.inst_accesses 53667131 # ITB inst accesses 772system.cpu1.itb.hits 53665397 # DTB hits |
| 770system.cpu1.itb.misses 1734 # DTB misses | 773system.cpu1.itb.misses 1734 # DTB misses |
| 771system.cpu1.itb.accesses 53666861 # DTB accesses | 774system.cpu1.itb.accesses 53667131 # DTB accesses |
| 772system.cpu1.numPwrStateTransitions 5467 # Number of power state transitions 773system.cpu1.pwrStateClkGateDist::samples 2734 # Distribution of time spent in the clock gated state | 775system.cpu1.numPwrStateTransitions 5467 # Number of power state transitions 776system.cpu1.pwrStateClkGateDist::samples 2734 # Distribution of time spent in the clock gated state |
| 774system.cpu1.pwrStateClkGateDist::mean 1013195942.406364 # Distribution of time spent in the clock gated state 775system.cpu1.pwrStateClkGateDist::stdev 25944771719.895676 # Distribution of time spent in the clock gated state | 777system.cpu1.pwrStateClkGateDist::mean 1013196310.731163 # Distribution of time spent in the clock gated state 778system.cpu1.pwrStateClkGateDist::stdev 25944771747.523987 # Distribution of time spent in the clock gated state |
| 776system.cpu1.pwrStateClkGateDist::underflows 1955 71.51% 71.51% # Distribution of time spent in the clock gated state 777system.cpu1.pwrStateClkGateDist::1000-5e+10 774 28.31% 99.82% # Distribution of time spent in the clock gated state 778system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state 779system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 780system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 781system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 782system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 783system.cpu1.pwrStateClkGateDist::max_value 979984970108 # Distribution of time spent in the clock gated state 784system.cpu1.pwrStateClkGateDist::total 2734 # Distribution of time spent in the clock gated state | 779system.cpu1.pwrStateClkGateDist::underflows 1955 71.51% 71.51% # Distribution of time spent in the clock gated state 780system.cpu1.pwrStateClkGateDist::1000-5e+10 774 28.31% 99.82% # Distribution of time spent in the clock gated state 781system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state 782system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 783system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 784system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 785system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 786system.cpu1.pwrStateClkGateDist::max_value 979984970108 # Distribution of time spent in the clock gated state 787system.cpu1.pwrStateClkGateDist::total 2734 # Distribution of time spent in the clock gated state |
| 785system.cpu1.pwrStateResidencyTicks::ON 32805567461 # Cumulative time (in ticks) in various power states 786system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770077706539 # Cumulative time (in ticks) in various power states 787system.cpu1.numCycles 5605297416 # number of cpu cycles simulated | 788system.cpu1.pwrStateResidencyTicks::ON 32805732461 # Cumulative time (in ticks) in various power states 789system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770078713539 # Cumulative time (in ticks) in various power states 790system.cpu1.numCycles 5605299760 # number of cpu cycles simulated |
| 788system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 789system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 790system.cpu1.kern.inst.arm 0 # number of arm instructions executed 791system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed | 791system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 792system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 793system.cpu1.kern.inst.arm 0 # number of arm instructions executed 794system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed |
| 792system.cpu1.committedInsts 51394923 # Number of instructions committed 793system.cpu1.committedOps 63339792 # Number of ops (including micro ops) committed 794system.cpu1.num_int_alu_accesses 56977163 # Number of integer alu accesses | 795system.cpu1.committedInsts 51395178 # Number of instructions committed 796system.cpu1.committedOps 63340107 # Number of ops (including micro ops) committed 797system.cpu1.num_int_alu_accesses 56977448 # Number of integer alu accesses |
| 795system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses | 798system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses |
| 796system.cpu1.num_func_calls 9170267 # number of times a function call or return occured 797system.cpu1.num_conditional_control_insts 5966436 # number of instructions that are conditional controls 798system.cpu1.num_int_insts 56977163 # number of integer instructions | 799system.cpu1.num_func_calls 9170327 # number of times a function call or return occured 800system.cpu1.num_conditional_control_insts 5966466 # number of instructions that are conditional controls 801system.cpu1.num_int_insts 56977448 # number of integer instructions |
| 799system.cpu1.num_fp_insts 1792 # number of float instructions | 802system.cpu1.num_fp_insts 1792 # number of float instructions |
| 800system.cpu1.num_int_register_reads 110657326 # number of times the integer registers were read 801system.cpu1.num_int_register_writes 41293408 # number of times the integer registers were written | 803system.cpu1.num_int_register_reads 110657896 # number of times the integer registers were read 804system.cpu1.num_int_register_writes 41293618 # number of times the integer registers were written |
| 802system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 803system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written | 805system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 806system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written |
| 804system.cpu1.num_cc_register_reads 196244999 # number of times the CC registers were read 805system.cpu1.num_cc_register_writes 18891882 # number of times the CC registers were written 806system.cpu1.num_mem_refs 20023552 # number of memory refs 807system.cpu1.num_load_insts 12287954 # Number of load instructions 808system.cpu1.num_store_insts 7735598 # Number of store instructions 809system.cpu1.num_idle_cycles 5539691771.902995 # Number of idle cycles 810system.cpu1.num_busy_cycles 65605644.097005 # Number of busy cycles | 807system.cpu1.num_cc_register_reads 196245989 # number of times the CC registers were read 808system.cpu1.num_cc_register_writes 18891972 # number of times the CC registers were written 809system.cpu1.num_mem_refs 20023642 # number of memory refs 810system.cpu1.num_load_insts 12288014 # Number of load instructions 811system.cpu1.num_store_insts 7735628 # Number of store instructions 812system.cpu1.num_idle_cycles 5539693785.928316 # Number of idle cycles 813system.cpu1.num_busy_cycles 65605974.071684 # Number of busy cycles |
| 811system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles 812system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles | 814system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles 815system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles |
| 813system.cpu1.Branches 15216243 # Number of branches fetched | 816system.cpu1.Branches 15216333 # Number of branches fetched |
| 814system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction | 817system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction |
| 815system.cpu1.op_class::IntAlu 45396317 69.36% 69.36% # Class of executed instruction | 818system.cpu1.op_class::IntAlu 45396557 69.36% 69.36% # Class of executed instruction |
| 816system.cpu1.op_class::IntMult 28337 0.04% 69.40% # Class of executed instruction 817system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 818system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 819system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 820system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 821system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 822system.cpu1.op_class::FloatMultAcc 0 0.00% 69.40% # Class of executed instruction 823system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction --- 14 unchanged lines hidden (view full) --- 838system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 839system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 840system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 841system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 842system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction 843system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 844system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 845system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction | 819system.cpu1.op_class::IntMult 28337 0.04% 69.40% # Class of executed instruction 820system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 821system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 822system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 823system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 824system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 825system.cpu1.op_class::FloatMultAcc 0 0.00% 69.40% # Class of executed instruction 826system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction --- 14 unchanged lines hidden (view full) --- 841system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 842system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 843system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 844system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 845system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction 846system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 847system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 848system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction |
| 846system.cpu1.op_class::MemRead 12287438 18.77% 88.18% # Class of executed instruction 847system.cpu1.op_class::MemWrite 7734322 11.82% 100.00% # Class of executed instruction | 849system.cpu1.op_class::MemRead 12287498 18.77% 88.18% # Class of executed instruction 850system.cpu1.op_class::MemWrite 7734352 11.82% 100.00% # Class of executed instruction |
| 848system.cpu1.op_class::FloatMemRead 516 0.00% 100.00% # Class of executed instruction 849system.cpu1.op_class::FloatMemWrite 1276 0.00% 100.00% # Class of executed instruction 850system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 851system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 851system.cpu1.op_class::FloatMemRead 516 0.00% 100.00% # Class of executed instruction 852system.cpu1.op_class::FloatMemWrite 1276 0.00% 100.00% # Class of executed instruction 853system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 854system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 852system.cpu1.op_class::total 65451587 # Class of executed instruction 853system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 854system.cpu1.dcache.tags.replacements 191903 # number of replacements 855system.cpu1.dcache.tags.tagsinuse 472.757938 # Cycle average of tags in use 856system.cpu1.dcache.tags.total_refs 19500903 # Total number of references to valid blocks. 857system.cpu1.dcache.tags.sampled_refs 192257 # Sample count of references to valid blocks. 858system.cpu1.dcache.tags.avg_refs 101.431433 # Average number of references to valid blocks. | 855system.cpu1.op_class::total 65451917 # Class of executed instruction 856system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 857system.cpu1.dcache.tags.replacements 191899 # number of replacements 858system.cpu1.dcache.tags.tagsinuse 472.757768 # Cycle average of tags in use 859system.cpu1.dcache.tags.total_refs 19500995 # Total number of references to valid blocks. 860system.cpu1.dcache.tags.sampled_refs 192253 # Sample count of references to valid blocks. 861system.cpu1.dcache.tags.avg_refs 101.434022 # Average number of references to valid blocks. |
| 859system.cpu1.dcache.tags.warmup_cycle 105851556000 # Cycle when the warmup percentage was hit. | 862system.cpu1.dcache.tags.warmup_cycle 105851556000 # Cycle when the warmup percentage was hit. |
| 860system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757938 # Average occupied blocks per requestor | 863system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757768 # Average occupied blocks per requestor |
| 861system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy 862system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy 863system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 864system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 865system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 866system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id | 864system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy 865system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy 866system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 867system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 868system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 869system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id |
| 867system.cpu1.dcache.tags.tag_accesses 39746590 # Number of tag accesses 868system.cpu1.dcache.tags.data_accesses 39746590 # Number of data accesses 869system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 870system.cpu1.dcache.ReadReq_hits::cpu1.data 11857228 # number of ReadReq hits 871system.cpu1.dcache.ReadReq_hits::total 11857228 # number of ReadReq hits 872system.cpu1.dcache.WriteReq_hits::cpu1.data 7396381 # number of WriteReq hits 873system.cpu1.dcache.WriteReq_hits::total 7396381 # number of WriteReq hits | 870system.cpu1.dcache.tags.tag_accesses 39746768 # Number of tag accesses 871system.cpu1.dcache.tags.data_accesses 39746768 # Number of data accesses 872system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 873system.cpu1.dcache.ReadReq_hits::cpu1.data 11857290 # number of ReadReq hits 874system.cpu1.dcache.ReadReq_hits::total 11857290 # number of ReadReq hits 875system.cpu1.dcache.WriteReq_hits::cpu1.data 7396404 # number of WriteReq hits 876system.cpu1.dcache.WriteReq_hits::total 7396404 # number of WriteReq hits |
| 874system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits 875system.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits 876system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits 877system.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits | 877system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits 878system.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits 879system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits 880system.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits |
| 878system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72441 # number of StoreCondReq hits 879system.cpu1.dcache.StoreCondReq_hits::total 72441 # number of StoreCondReq hits 880system.cpu1.dcache.demand_hits::cpu1.data 19253609 # number of demand (read+write) hits 881system.cpu1.dcache.demand_hits::total 19253609 # number of demand (read+write) hits 882system.cpu1.dcache.overall_hits::cpu1.data 19303712 # number of overall hits 883system.cpu1.dcache.overall_hits::total 19303712 # number of overall hits 884system.cpu1.dcache.ReadReq_misses::cpu1.data 136574 # number of ReadReq misses 885system.cpu1.dcache.ReadReq_misses::total 136574 # number of ReadReq misses 886system.cpu1.dcache.WriteReq_misses::cpu1.data 92475 # number of WriteReq misses 887system.cpu1.dcache.WriteReq_misses::total 92475 # number of WriteReq misses | 881system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72438 # number of StoreCondReq hits 882system.cpu1.dcache.StoreCondReq_hits::total 72438 # number of StoreCondReq hits 883system.cpu1.dcache.demand_hits::cpu1.data 19253694 # number of demand (read+write) hits 884system.cpu1.dcache.demand_hits::total 19253694 # number of demand (read+write) hits 885system.cpu1.dcache.overall_hits::cpu1.data 19303797 # number of overall hits 886system.cpu1.dcache.overall_hits::total 19303797 # number of overall hits 887system.cpu1.dcache.ReadReq_misses::cpu1.data 136572 # number of ReadReq misses 888system.cpu1.dcache.ReadReq_misses::total 136572 # number of ReadReq misses 889system.cpu1.dcache.WriteReq_misses::cpu1.data 92482 # number of WriteReq misses 890system.cpu1.dcache.WriteReq_misses::total 92482 # number of WriteReq misses |
| 888system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses 889system.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses 890system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 891system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses | 891system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses 892system.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses 893system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 894system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses |
| 892system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22520 # number of StoreCondReq misses 893system.cpu1.dcache.StoreCondReq_misses::total 22520 # number of StoreCondReq misses 894system.cpu1.dcache.demand_misses::cpu1.data 229049 # number of demand (read+write) misses 895system.cpu1.dcache.demand_misses::total 229049 # number of demand (read+write) misses 896system.cpu1.dcache.overall_misses::cpu1.data 259766 # number of overall misses 897system.cpu1.dcache.overall_misses::total 259766 # number of overall misses 898system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993802 # number of ReadReq accesses(hits+misses) 899system.cpu1.dcache.ReadReq_accesses::total 11993802 # number of ReadReq accesses(hits+misses) 900system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488856 # number of WriteReq accesses(hits+misses) 901system.cpu1.dcache.WriteReq_accesses::total 7488856 # number of WriteReq accesses(hits+misses) | 895system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22523 # number of StoreCondReq misses 896system.cpu1.dcache.StoreCondReq_misses::total 22523 # number of StoreCondReq misses 897system.cpu1.dcache.demand_misses::cpu1.data 229054 # number of demand (read+write) misses 898system.cpu1.dcache.demand_misses::total 229054 # number of demand (read+write) misses 899system.cpu1.dcache.overall_misses::cpu1.data 259771 # number of overall misses 900system.cpu1.dcache.overall_misses::total 259771 # number of overall misses 901system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993862 # number of ReadReq accesses(hits+misses) 902system.cpu1.dcache.ReadReq_accesses::total 11993862 # number of ReadReq accesses(hits+misses) 903system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488886 # number of WriteReq accesses(hits+misses) 904system.cpu1.dcache.WriteReq_accesses::total 7488886 # number of WriteReq accesses(hits+misses) |
| 902system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80820 # number of SoftPFReq accesses(hits+misses) 903system.cpu1.dcache.SoftPFReq_accesses::total 80820 # number of SoftPFReq accesses(hits+misses) 904system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96744 # number of LoadLockedReq accesses(hits+misses) 905system.cpu1.dcache.LoadLockedReq_accesses::total 96744 # number of LoadLockedReq accesses(hits+misses) 906system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94961 # number of StoreCondReq accesses(hits+misses) 907system.cpu1.dcache.StoreCondReq_accesses::total 94961 # number of StoreCondReq accesses(hits+misses) | 905system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80820 # number of SoftPFReq accesses(hits+misses) 906system.cpu1.dcache.SoftPFReq_accesses::total 80820 # number of SoftPFReq accesses(hits+misses) 907system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96744 # number of LoadLockedReq accesses(hits+misses) 908system.cpu1.dcache.LoadLockedReq_accesses::total 96744 # number of LoadLockedReq accesses(hits+misses) 909system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94961 # number of StoreCondReq accesses(hits+misses) 910system.cpu1.dcache.StoreCondReq_accesses::total 94961 # number of StoreCondReq accesses(hits+misses) |
| 908system.cpu1.dcache.demand_accesses::cpu1.data 19482658 # number of demand (read+write) accesses 909system.cpu1.dcache.demand_accesses::total 19482658 # number of demand (read+write) accesses 910system.cpu1.dcache.overall_accesses::cpu1.data 19563478 # number of overall (read+write) accesses 911system.cpu1.dcache.overall_accesses::total 19563478 # number of overall (read+write) accesses | 911system.cpu1.dcache.demand_accesses::cpu1.data 19482748 # number of demand (read+write) accesses 912system.cpu1.dcache.demand_accesses::total 19482748 # number of demand (read+write) accesses 913system.cpu1.dcache.overall_accesses::cpu1.data 19563568 # number of overall (read+write) accesses 914system.cpu1.dcache.overall_accesses::total 19563568 # number of overall (read+write) accesses |
| 912system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses 913system.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses | 915system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses 916system.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses |
| 914system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses 915system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses | 917system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012349 # miss rate for WriteReq accesses 918system.cpu1.dcache.WriteReq_miss_rate::total 0.012349 # miss rate for WriteReq accesses |
| 916system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses 917system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses 918system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses 919system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses | 919system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses 920system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses 921system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses 922system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses |
| 920system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237150 # miss rate for StoreCondReq accesses 921system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237150 # miss rate for StoreCondReq accesses | 923system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237182 # miss rate for StoreCondReq accesses 924system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237182 # miss rate for StoreCondReq accesses |
| 922system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 923system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 924system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013278 # miss rate for overall accesses 925system.cpu1.dcache.overall_miss_rate::total 0.013278 # miss rate for overall accesses 926system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 927system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 928system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 929system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 930system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 931system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 925system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 926system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 927system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013278 # miss rate for overall accesses 928system.cpu1.dcache.overall_miss_rate::total 0.013278 # miss rate for overall accesses 929system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 930system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 931system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 932system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 933system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 934system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 932system.cpu1.dcache.writebacks::writebacks 191903 # number of writebacks 933system.cpu1.dcache.writebacks::total 191903 # number of writebacks 934system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 935system.cpu1.icache.tags.replacements 523286 # number of replacements 936system.cpu1.icache.tags.tagsinuse 499.709347 # Cycle average of tags in use 937system.cpu1.icache.tags.total_refs 53142419 # Total number of references to valid blocks. 938system.cpu1.icache.tags.sampled_refs 523798 # Sample count of references to valid blocks. 939system.cpu1.icache.tags.avg_refs 101.455941 # Average number of references to valid blocks. | 935system.cpu1.dcache.writebacks::writebacks 191899 # number of writebacks 936system.cpu1.dcache.writebacks::total 191899 # number of writebacks 937system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 938system.cpu1.icache.tags.replacements 523278 # number of replacements 939system.cpu1.icache.tags.tagsinuse 499.709352 # Cycle average of tags in use 940system.cpu1.icache.tags.total_refs 53142697 # Total number of references to valid blocks. 941system.cpu1.icache.tags.sampled_refs 523790 # Sample count of references to valid blocks. 942system.cpu1.icache.tags.avg_refs 101.458021 # Average number of references to valid blocks. |
| 940system.cpu1.icache.tags.warmup_cycle 76931398500 # Cycle when the warmup percentage was hit. | 943system.cpu1.icache.tags.warmup_cycle 76931398500 # Cycle when the warmup percentage was hit. |
| 941system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709347 # Average occupied blocks per requestor | 944system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709352 # Average occupied blocks per requestor |
| 942system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975995 # Average percentage of cache occupancy 943system.cpu1.icache.tags.occ_percent::total 0.975995 # Average percentage of cache occupancy 944system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 945system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 946system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 947system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 945system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975995 # Average percentage of cache occupancy 946system.cpu1.icache.tags.occ_percent::total 0.975995 # Average percentage of cache occupancy 947system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 948system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 949system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 950system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 948system.cpu1.icache.tags.tag_accesses 107856232 # Number of tag accesses 949system.cpu1.icache.tags.data_accesses 107856232 # Number of data accesses 950system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 951system.cpu1.icache.ReadReq_hits::cpu1.inst 53142419 # number of ReadReq hits 952system.cpu1.icache.ReadReq_hits::total 53142419 # number of ReadReq hits 953system.cpu1.icache.demand_hits::cpu1.inst 53142419 # number of demand (read+write) hits 954system.cpu1.icache.demand_hits::total 53142419 # number of demand (read+write) hits 955system.cpu1.icache.overall_hits::cpu1.inst 53142419 # number of overall hits 956system.cpu1.icache.overall_hits::total 53142419 # number of overall hits 957system.cpu1.icache.ReadReq_misses::cpu1.inst 523798 # number of ReadReq misses 958system.cpu1.icache.ReadReq_misses::total 523798 # number of ReadReq misses 959system.cpu1.icache.demand_misses::cpu1.inst 523798 # number of demand (read+write) misses 960system.cpu1.icache.demand_misses::total 523798 # number of demand (read+write) misses 961system.cpu1.icache.overall_misses::cpu1.inst 523798 # number of overall misses 962system.cpu1.icache.overall_misses::total 523798 # number of overall misses 963system.cpu1.icache.ReadReq_accesses::cpu1.inst 53666217 # number of ReadReq accesses(hits+misses) 964system.cpu1.icache.ReadReq_accesses::total 53666217 # number of ReadReq accesses(hits+misses) 965system.cpu1.icache.demand_accesses::cpu1.inst 53666217 # number of demand (read+write) accesses 966system.cpu1.icache.demand_accesses::total 53666217 # number of demand (read+write) accesses 967system.cpu1.icache.overall_accesses::cpu1.inst 53666217 # number of overall (read+write) accesses 968system.cpu1.icache.overall_accesses::total 53666217 # number of overall (read+write) accesses | 951system.cpu1.icache.tags.tag_accesses 107856764 # Number of tag accesses 952system.cpu1.icache.tags.data_accesses 107856764 # Number of data accesses 953system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 954system.cpu1.icache.ReadReq_hits::cpu1.inst 53142697 # number of ReadReq hits 955system.cpu1.icache.ReadReq_hits::total 53142697 # number of ReadReq hits 956system.cpu1.icache.demand_hits::cpu1.inst 53142697 # number of demand (read+write) hits 957system.cpu1.icache.demand_hits::total 53142697 # number of demand (read+write) hits 958system.cpu1.icache.overall_hits::cpu1.inst 53142697 # number of overall hits 959system.cpu1.icache.overall_hits::total 53142697 # number of overall hits 960system.cpu1.icache.ReadReq_misses::cpu1.inst 523790 # number of ReadReq misses 961system.cpu1.icache.ReadReq_misses::total 523790 # number of ReadReq misses 962system.cpu1.icache.demand_misses::cpu1.inst 523790 # number of demand (read+write) misses 963system.cpu1.icache.demand_misses::total 523790 # number of demand (read+write) misses 964system.cpu1.icache.overall_misses::cpu1.inst 523790 # number of overall misses 965system.cpu1.icache.overall_misses::total 523790 # number of overall misses 966system.cpu1.icache.ReadReq_accesses::cpu1.inst 53666487 # number of ReadReq accesses(hits+misses) 967system.cpu1.icache.ReadReq_accesses::total 53666487 # number of ReadReq accesses(hits+misses) 968system.cpu1.icache.demand_accesses::cpu1.inst 53666487 # number of demand (read+write) accesses 969system.cpu1.icache.demand_accesses::total 53666487 # number of demand (read+write) accesses 970system.cpu1.icache.overall_accesses::cpu1.inst 53666487 # number of overall (read+write) accesses 971system.cpu1.icache.overall_accesses::total 53666487 # number of overall (read+write) accesses |
| 969system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009760 # miss rate for ReadReq accesses 970system.cpu1.icache.ReadReq_miss_rate::total 0.009760 # miss rate for ReadReq accesses 971system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009760 # miss rate for demand accesses 972system.cpu1.icache.demand_miss_rate::total 0.009760 # miss rate for demand accesses 973system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009760 # miss rate for overall accesses 974system.cpu1.icache.overall_miss_rate::total 0.009760 # miss rate for overall accesses 975system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 976system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 977system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 978system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 979system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 980system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 972system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009760 # miss rate for ReadReq accesses 973system.cpu1.icache.ReadReq_miss_rate::total 0.009760 # miss rate for ReadReq accesses 974system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009760 # miss rate for demand accesses 975system.cpu1.icache.demand_miss_rate::total 0.009760 # miss rate for demand accesses 976system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009760 # miss rate for overall accesses 977system.cpu1.icache.overall_miss_rate::total 0.009760 # miss rate for overall accesses 978system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 979system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 980system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 981system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 982system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 983system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 981system.cpu1.icache.writebacks::writebacks 523286 # number of writebacks 982system.cpu1.icache.writebacks::total 523286 # number of writebacks 983system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 984system.cpu1.icache.writebacks::writebacks 523278 # number of writebacks 985system.cpu1.icache.writebacks::total 523278 # number of writebacks 986system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 984system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 985system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 986system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 987system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 988system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 989system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 987system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 988system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 989system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 990system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 991system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 992system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 990system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 991system.cpu1.l2cache.tags.replacements 45747 # number of replacements 992system.cpu1.l2cache.tags.tagsinuse 14812.613567 # Cycle average of tags in use 993system.cpu1.l2cache.tags.total_refs 613917 # Total number of references to valid blocks. 994system.cpu1.l2cache.tags.sampled_refs 60319 # Sample count of references to valid blocks. 995system.cpu1.l2cache.tags.avg_refs 10.177838 # Average number of references to valid blocks. | 993system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 994system.cpu1.l2cache.tags.replacements 45622 # number of replacements 995system.cpu1.l2cache.tags.tagsinuse 14812.583642 # Cycle average of tags in use 996system.cpu1.l2cache.tags.total_refs 612745 # Total number of references to valid blocks. 997system.cpu1.l2cache.tags.sampled_refs 60182 # Sample count of references to valid blocks. 998system.cpu1.l2cache.tags.avg_refs 10.181533 # Average number of references to valid blocks. |
| 996system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 999system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 997system.cpu1.l2cache.tags.occ_blocks::writebacks 14808.372104 # Average occupied blocks per requestor 998system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.216207 # Average occupied blocks per requestor 999system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.025256 # Average occupied blocks per requestor 1000system.cpu1.l2cache.tags.occ_percent::writebacks 0.903831 # Average percentage of cache occupancy 1001system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy 1002system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 1003system.cpu1.l2cache.tags.occ_percent::total 0.904090 # Average percentage of cache occupancy 1004system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id 1005system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id | 1000system.cpu1.l2cache.tags.occ_blocks::writebacks 14808.341040 # Average occupied blocks per requestor 1001system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.229622 # Average occupied blocks per requestor 1002system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.012979 # Average occupied blocks per requestor 1003system.cpu1.l2cache.tags.occ_percent::writebacks 0.903829 # Average percentage of cache occupancy 1004system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000136 # Average percentage of cache occupancy 1005system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 1006system.cpu1.l2cache.tags.occ_percent::total 0.904088 # Average percentage of cache occupancy 1007system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id 1008system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14538 # Occupied blocks per task id |
| 1006system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 1007system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id | 1009system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 1010system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id |
| 1008system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 1009system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1590 # Occupied blocks per task id 1010system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8844 # Occupied blocks per task id 1011system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4115 # Occupied blocks per task id 1012system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id 1013system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id 1014system.cpu1.l2cache.tags.tag_accesses 25046952 # Number of tag accesses 1015system.cpu1.l2cache.tags.data_accesses 25046952 # Number of data accesses 1016system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1017system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3528 # number of ReadReq hits 1018system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1892 # number of ReadReq hits | 1011system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 1012system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1592 # Occupied blocks per task id 1013system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8923 # Occupied blocks per task id 1014system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4023 # Occupied blocks per task id 1015system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id 1016system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.887329 # Percentage of cache occupancy per task id 1017system.cpu1.l2cache.tags.tag_accesses 25046700 # Number of tag accesses 1018system.cpu1.l2cache.tags.data_accesses 25046700 # Number of data accesses 1019system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1020system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3523 # number of ReadReq hits 1021system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1897 # number of ReadReq hits |
| 1019system.cpu1.l2cache.ReadReq_hits::total 5420 # number of ReadReq hits | 1022system.cpu1.l2cache.ReadReq_hits::total 5420 # number of ReadReq hits |
| 1020system.cpu1.l2cache.WritebackDirty_hits::writebacks 120650 # number of WritebackDirty hits 1021system.cpu1.l2cache.WritebackDirty_hits::total 120650 # number of WritebackDirty hits 1022system.cpu1.l2cache.WritebackClean_hits::writebacks 583378 # number of WritebackClean hits 1023system.cpu1.l2cache.WritebackClean_hits::total 583378 # number of WritebackClean hits 1024system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19790 # number of ReadExReq hits 1025system.cpu1.l2cache.ReadExReq_hits::total 19790 # number of ReadExReq hits 1026system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 502408 # number of ReadCleanReq hits 1027system.cpu1.l2cache.ReadCleanReq_hits::total 502408 # number of ReadCleanReq hits 1028system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97451 # number of ReadSharedReq hits 1029system.cpu1.l2cache.ReadSharedReq_hits::total 97451 # number of ReadSharedReq hits 1030system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3528 # number of demand (read+write) hits 1031system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1892 # number of demand (read+write) hits 1032system.cpu1.l2cache.demand_hits::cpu1.inst 502408 # number of demand (read+write) hits 1033system.cpu1.l2cache.demand_hits::cpu1.data 117241 # number of demand (read+write) hits 1034system.cpu1.l2cache.demand_hits::total 625069 # number of demand (read+write) hits 1035system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3528 # number of overall hits 1036system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1892 # number of overall hits 1037system.cpu1.l2cache.overall_hits::cpu1.inst 502408 # number of overall hits 1038system.cpu1.l2cache.overall_hits::cpu1.data 117241 # number of overall hits 1039system.cpu1.l2cache.overall_hits::total 625069 # number of overall hits 1040system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 436 # number of ReadReq misses 1041system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 299 # number of ReadReq misses 1042system.cpu1.l2cache.ReadReq_misses::total 735 # number of ReadReq misses 1043system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28860 # number of UpgradeReq misses 1044system.cpu1.l2cache.UpgradeReq_misses::total 28860 # number of UpgradeReq misses 1045system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22520 # number of SCUpgradeReq misses 1046system.cpu1.l2cache.SCUpgradeReq_misses::total 22520 # number of SCUpgradeReq misses 1047system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43825 # number of ReadExReq misses 1048system.cpu1.l2cache.ReadExReq_misses::total 43825 # number of ReadExReq misses 1049system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21390 # number of ReadCleanReq misses 1050system.cpu1.l2cache.ReadCleanReq_misses::total 21390 # number of ReadCleanReq misses 1051system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75158 # number of ReadSharedReq misses 1052system.cpu1.l2cache.ReadSharedReq_misses::total 75158 # number of ReadSharedReq misses 1053system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 436 # number of demand (read+write) misses 1054system.cpu1.l2cache.demand_misses::cpu1.itb.walker 299 # number of demand (read+write) misses 1055system.cpu1.l2cache.demand_misses::cpu1.inst 21390 # number of demand (read+write) misses 1056system.cpu1.l2cache.demand_misses::cpu1.data 118983 # number of demand (read+write) misses 1057system.cpu1.l2cache.demand_misses::total 141108 # number of demand (read+write) misses 1058system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 436 # number of overall misses 1059system.cpu1.l2cache.overall_misses::cpu1.itb.walker 299 # number of overall misses 1060system.cpu1.l2cache.overall_misses::cpu1.inst 21390 # number of overall misses 1061system.cpu1.l2cache.overall_misses::cpu1.data 118983 # number of overall misses 1062system.cpu1.l2cache.overall_misses::total 141108 # number of overall misses 1063system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3964 # number of ReadReq accesses(hits+misses) | 1023system.cpu1.l2cache.WritebackDirty_hits::writebacks 120664 # number of WritebackDirty hits 1024system.cpu1.l2cache.WritebackDirty_hits::total 120664 # number of WritebackDirty hits 1025system.cpu1.l2cache.WritebackClean_hits::writebacks 583352 # number of WritebackClean hits 1026system.cpu1.l2cache.WritebackClean_hits::total 583352 # number of WritebackClean hits 1027system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19842 # number of ReadExReq hits 1028system.cpu1.l2cache.ReadExReq_hits::total 19842 # number of ReadExReq hits 1029system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 502374 # number of ReadCleanReq hits 1030system.cpu1.l2cache.ReadCleanReq_hits::total 502374 # number of ReadCleanReq hits 1031system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97505 # number of ReadSharedReq hits 1032system.cpu1.l2cache.ReadSharedReq_hits::total 97505 # number of ReadSharedReq hits 1033system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3523 # number of demand (read+write) hits 1034system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1897 # number of demand (read+write) hits 1035system.cpu1.l2cache.demand_hits::cpu1.inst 502374 # number of demand (read+write) hits 1036system.cpu1.l2cache.demand_hits::cpu1.data 117347 # number of demand (read+write) hits 1037system.cpu1.l2cache.demand_hits::total 625141 # number of demand (read+write) hits 1038system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3523 # number of overall hits 1039system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1897 # number of overall hits 1040system.cpu1.l2cache.overall_hits::cpu1.inst 502374 # number of overall hits 1041system.cpu1.l2cache.overall_hits::cpu1.data 117347 # number of overall hits 1042system.cpu1.l2cache.overall_hits::total 625141 # number of overall hits 1043system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 442 # number of ReadReq misses 1044system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 294 # number of ReadReq misses 1045system.cpu1.l2cache.ReadReq_misses::total 736 # number of ReadReq misses 1046system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28867 # number of UpgradeReq misses 1047system.cpu1.l2cache.UpgradeReq_misses::total 28867 # number of UpgradeReq misses 1048system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22523 # number of SCUpgradeReq misses 1049system.cpu1.l2cache.SCUpgradeReq_misses::total 22523 # number of SCUpgradeReq misses 1050system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43773 # number of ReadExReq misses 1051system.cpu1.l2cache.ReadExReq_misses::total 43773 # number of ReadExReq misses 1052system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21416 # number of ReadCleanReq misses 1053system.cpu1.l2cache.ReadCleanReq_misses::total 21416 # number of ReadCleanReq misses 1054system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75102 # number of ReadSharedReq misses 1055system.cpu1.l2cache.ReadSharedReq_misses::total 75102 # number of ReadSharedReq misses 1056system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 442 # number of demand (read+write) misses 1057system.cpu1.l2cache.demand_misses::cpu1.itb.walker 294 # number of demand (read+write) misses 1058system.cpu1.l2cache.demand_misses::cpu1.inst 21416 # number of demand (read+write) misses 1059system.cpu1.l2cache.demand_misses::cpu1.data 118875 # number of demand (read+write) misses 1060system.cpu1.l2cache.demand_misses::total 141027 # number of demand (read+write) misses 1061system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 442 # number of overall misses 1062system.cpu1.l2cache.overall_misses::cpu1.itb.walker 294 # number of overall misses 1063system.cpu1.l2cache.overall_misses::cpu1.inst 21416 # number of overall misses 1064system.cpu1.l2cache.overall_misses::cpu1.data 118875 # number of overall misses 1065system.cpu1.l2cache.overall_misses::total 141027 # number of overall misses 1066system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) |
| 1064system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) | 1067system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) |
| 1065system.cpu1.l2cache.ReadReq_accesses::total 6155 # number of ReadReq accesses(hits+misses) 1066system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120650 # number of WritebackDirty accesses(hits+misses) 1067system.cpu1.l2cache.WritebackDirty_accesses::total 120650 # number of WritebackDirty accesses(hits+misses) 1068system.cpu1.l2cache.WritebackClean_accesses::writebacks 583378 # number of WritebackClean accesses(hits+misses) 1069system.cpu1.l2cache.WritebackClean_accesses::total 583378 # number of WritebackClean accesses(hits+misses) 1070system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28860 # number of UpgradeReq accesses(hits+misses) 1071system.cpu1.l2cache.UpgradeReq_accesses::total 28860 # number of UpgradeReq accesses(hits+misses) 1072system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22520 # number of SCUpgradeReq accesses(hits+misses) 1073system.cpu1.l2cache.SCUpgradeReq_accesses::total 22520 # number of SCUpgradeReq accesses(hits+misses) | 1068system.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) 1069system.cpu1.l2cache.WritebackDirty_accesses::writebacks 120664 # number of WritebackDirty accesses(hits+misses) 1070system.cpu1.l2cache.WritebackDirty_accesses::total 120664 # number of WritebackDirty accesses(hits+misses) 1071system.cpu1.l2cache.WritebackClean_accesses::writebacks 583352 # number of WritebackClean accesses(hits+misses) 1072system.cpu1.l2cache.WritebackClean_accesses::total 583352 # number of WritebackClean accesses(hits+misses) 1073system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28867 # number of UpgradeReq accesses(hits+misses) 1074system.cpu1.l2cache.UpgradeReq_accesses::total 28867 # number of UpgradeReq accesses(hits+misses) 1075system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22523 # number of SCUpgradeReq accesses(hits+misses) 1076system.cpu1.l2cache.SCUpgradeReq_accesses::total 22523 # number of SCUpgradeReq accesses(hits+misses) |
| 1074system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 1075system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) | 1077system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 1078system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) |
| 1076system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523798 # number of ReadCleanReq accesses(hits+misses) 1077system.cpu1.l2cache.ReadCleanReq_accesses::total 523798 # number of ReadCleanReq accesses(hits+misses) 1078system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172609 # number of ReadSharedReq accesses(hits+misses) 1079system.cpu1.l2cache.ReadSharedReq_accesses::total 172609 # number of ReadSharedReq accesses(hits+misses) 1080system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3964 # number of demand (read+write) accesses | 1079system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523790 # number of ReadCleanReq accesses(hits+misses) 1080system.cpu1.l2cache.ReadCleanReq_accesses::total 523790 # number of ReadCleanReq accesses(hits+misses) 1081system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172607 # number of ReadSharedReq accesses(hits+misses) 1082system.cpu1.l2cache.ReadSharedReq_accesses::total 172607 # number of ReadSharedReq accesses(hits+misses) 1083system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses |
| 1081system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses | 1084system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses |
| 1082system.cpu1.l2cache.demand_accesses::cpu1.inst 523798 # number of demand (read+write) accesses 1083system.cpu1.l2cache.demand_accesses::cpu1.data 236224 # number of demand (read+write) accesses 1084system.cpu1.l2cache.demand_accesses::total 766177 # number of demand (read+write) accesses 1085system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3964 # number of overall (read+write) accesses | 1085system.cpu1.l2cache.demand_accesses::cpu1.inst 523790 # number of demand (read+write) accesses 1086system.cpu1.l2cache.demand_accesses::cpu1.data 236222 # number of demand (read+write) accesses 1087system.cpu1.l2cache.demand_accesses::total 766168 # number of demand (read+write) accesses 1088system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses |
| 1086system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses | 1089system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses |
| 1087system.cpu1.l2cache.overall_accesses::cpu1.inst 523798 # number of overall (read+write) accesses 1088system.cpu1.l2cache.overall_accesses::cpu1.data 236224 # number of overall (read+write) accesses 1089system.cpu1.l2cache.overall_accesses::total 766177 # number of overall (read+write) accesses 1090system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for ReadReq accesses 1091system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136467 # miss rate for ReadReq accesses 1092system.cpu1.l2cache.ReadReq_miss_rate::total 0.119415 # miss rate for ReadReq accesses | 1090system.cpu1.l2cache.overall_accesses::cpu1.inst 523790 # number of overall (read+write) accesses 1091system.cpu1.l2cache.overall_accesses::cpu1.data 236222 # number of overall (read+write) accesses 1092system.cpu1.l2cache.overall_accesses::total 766168 # number of overall (read+write) accesses 1093system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.111475 # miss rate for ReadReq accesses 1094system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.134185 # miss rate for ReadReq accesses 1095system.cpu1.l2cache.ReadReq_miss_rate::total 0.119558 # miss rate for ReadReq accesses |
| 1093system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1094system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1095system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1096system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1096system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1097system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1098system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1099system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1097system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688910 # miss rate for ReadExReq accesses 1098system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688910 # miss rate for ReadExReq accesses 1099system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040836 # miss rate for ReadCleanReq accesses 1100system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040836 # miss rate for ReadCleanReq accesses 1101system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.435423 # miss rate for ReadSharedReq accesses 1102system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.435423 # miss rate for ReadSharedReq accesses 1103system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for demand accesses 1104system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136467 # miss rate for demand accesses 1105system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040836 # miss rate for demand accesses 1106system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.503687 # miss rate for demand accesses 1107system.cpu1.l2cache.demand_miss_rate::total 0.184172 # miss rate for demand accesses 1108system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for overall accesses 1109system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136467 # miss rate for overall accesses 1110system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040836 # miss rate for overall accesses 1111system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.503687 # miss rate for overall accesses 1112system.cpu1.l2cache.overall_miss_rate::total 0.184172 # miss rate for overall accesses | 1100system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688092 # miss rate for ReadExReq accesses 1101system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688092 # miss rate for ReadExReq accesses 1102system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040887 # miss rate for ReadCleanReq accesses 1103system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040887 # miss rate for ReadCleanReq accesses 1104system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.435104 # miss rate for ReadSharedReq accesses 1105system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.435104 # miss rate for ReadSharedReq accesses 1106system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.111475 # miss rate for demand accesses 1107system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.134185 # miss rate for demand accesses 1108system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040887 # miss rate for demand accesses 1109system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.503234 # miss rate for demand accesses 1110system.cpu1.l2cache.demand_miss_rate::total 0.184068 # miss rate for demand accesses 1111system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.111475 # miss rate for overall accesses 1112system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.134185 # miss rate for overall accesses 1113system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040887 # miss rate for overall accesses 1114system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.503234 # miss rate for overall accesses 1115system.cpu1.l2cache.overall_miss_rate::total 0.184068 # miss rate for overall accesses |
| 1113system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1114system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1115system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1116system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1117system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1118system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1116system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1117system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1118system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1119system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1120system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1121system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1119system.cpu1.l2cache.writebacks::writebacks 32289 # number of writebacks 1120system.cpu1.l2cache.writebacks::total 32289 # number of writebacks 1121system.cpu1.toL2Bus.snoop_filter.tot_requests 1533143 # Total number of requests made to the snoop filter. 1122system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773124 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1122system.cpu1.l2cache.writebacks::writebacks 32251 # number of writebacks 1123system.cpu1.l2cache.writebacks::total 32251 # number of writebacks 1124system.cpu1.toL2Bus.snoop_filter.tot_requests 1533131 # Total number of requests made to the snoop filter. 1125system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773122 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1123system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1126system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1124system.cpu1.toL2Bus.snoop_filter.tot_snoops 97275 # Total number of snoops made to the snoop filter. 1125system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 90578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1126system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6697 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1127system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 1127system.cpu1.toL2Bus.snoop_filter.tot_snoops 97486 # Total number of snoops made to the snoop filter. 1128system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 90800 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1129system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6686 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1130system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 1128system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution | 1131system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution |
| 1129system.cpu1.toL2Bus.trans_dist::ReadResp 709156 # Transaction distribution | 1132system.cpu1.toL2Bus.trans_dist::ReadResp 709146 # Transaction distribution |
| 1130system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution 1131system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution | 1133system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution 1134system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution |
| 1132system.cpu1.toL2Bus.trans_dist::WritebackDirty 120650 # Transaction distribution 1133system.cpu1.toL2Bus.trans_dist::WritebackClean 594539 # Transaction distribution 1134system.cpu1.toL2Bus.trans_dist::UpgradeReq 28860 # Transaction distribution 1135system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22520 # Transaction distribution 1136system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution | 1135system.cpu1.toL2Bus.trans_dist::WritebackDirty 120664 # Transaction distribution 1136system.cpu1.toL2Bus.trans_dist::WritebackClean 594513 # Transaction distribution 1137system.cpu1.toL2Bus.trans_dist::UpgradeReq 28867 # Transaction distribution 1138system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22523 # Transaction distribution 1139system.cpu1.toL2Bus.trans_dist::UpgradeResp 51390 # Transaction distribution |
| 1137system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 1138system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution | 1140system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 1141system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution |
| 1139system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523798 # Transaction distribution 1140system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172609 # Transaction distribution 1141system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571236 # Packet count per connected master and slave (bytes) 1142system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778567 # Packet count per connected master and slave (bytes) | 1142system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523790 # Transaction distribution 1143system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172607 # Transaction distribution 1144system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571212 # Packet count per connected master and slave (bytes) 1145system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778579 # Packet count per connected master and slave (bytes) |
| 1143system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1144system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) | 1146system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1147system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) |
| 1145system.cpu1.toL2Bus.pkt_count::total 2368499 # Packet count per connected master and slave (bytes) 1146system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67014084 # Cumulative packet size per connected master and slave (bytes) 1147system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27419302 # Cumulative packet size per connected master and slave (bytes) | 1148system.cpu1.toL2Bus.pkt_count::total 2368487 # Packet count per connected master and slave (bytes) 1149system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67013060 # Cumulative packet size per connected master and slave (bytes) 1150system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27418918 # Cumulative packet size per connected master and slave (bytes) |
| 1148system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1149system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) | 1151system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1152system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) |
| 1150system.cpu1.toL2Bus.pkt_size::total 94470778 # Cumulative packet size per connected master and slave (bytes) 1151system.cpu1.toL2Bus.snoops 295837 # Total snoops (count) 1152system.cpu1.toL2Bus.snoopTraffic 2333632 # Total snoop traffic (bytes) 1153system.cpu1.toL2Bus.snoop_fanout::samples 1767980 # Request fanout histogram 1154system.cpu1.toL2Bus.snoop_fanout::mean 0.075142 # Request fanout histogram 1155system.cpu1.toL2Bus.snoop_fanout::stdev 0.277617 # Request fanout histogram | 1153system.cpu1.toL2Bus.pkt_size::total 94469370 # Cumulative packet size per connected master and slave (bytes) 1154system.cpu1.toL2Bus.snoops 297967 # Total snoops (count) 1155system.cpu1.toL2Bus.snoopTraffic 2396032 # Total snoop traffic (bytes) 1156system.cpu1.toL2Bus.snoop_fanout::samples 1770091 # Request fanout histogram 1157system.cpu1.toL2Bus.snoop_fanout::mean 0.075165 # Request fanout histogram 1158system.cpu1.toL2Bus.snoop_fanout::stdev 0.277614 # Request fanout histogram |
| 1156system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1159system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1157system.cpu1.toL2Bus.snoop_fanout::0 1641828 92.86% 92.86% # Request fanout histogram 1158system.cpu1.toL2Bus.snoop_fanout::1 119455 6.76% 99.62% # Request fanout histogram 1159system.cpu1.toL2Bus.snoop_fanout::2 6697 0.38% 100.00% # Request fanout histogram | 1160system.cpu1.toL2Bus.snoop_fanout::0 1643728 92.86% 92.86% # Request fanout histogram 1161system.cpu1.toL2Bus.snoop_fanout::1 119677 6.76% 99.62% # Request fanout histogram 1162system.cpu1.toL2Bus.snoop_fanout::2 6686 0.38% 100.00% # Request fanout histogram |
| 1160system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1161system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1162system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1163system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1164system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1165system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1163system.cpu1.toL2Bus.snoop_fanout::total 1767980 # Request fanout histogram 1164system.iobus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 1166system.cpu1.toL2Bus.snoop_fanout::total 1770091 # Request fanout histogram 1167system.iobus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 1165system.iobus.trans_dist::ReadReq 30995 # Transaction distribution 1166system.iobus.trans_dist::ReadResp 30995 # Transaction distribution 1167system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1168system.iobus.trans_dist::WriteResp 59419 # Transaction distribution 1169system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 1170system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1171system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1172system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 1207system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1208system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1209system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1210system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1211system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 1212system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) | 1168system.iobus.trans_dist::ReadReq 30995 # Transaction distribution 1169system.iobus.trans_dist::ReadResp 30995 # Transaction distribution 1170system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1171system.iobus.trans_dist::WriteResp 59419 # Transaction distribution 1172system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 1173system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1174system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1175system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 1210system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1211system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1212system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1213system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1214system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 1215system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1216system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1217system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) |
| 1215system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 1218system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 1216system.iocache.tags.replacements 36442 # number of replacements | 1219system.iocache.tags.replacements 36442 # number of replacements |
| 1217system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use | 1220system.iocache.tags.tagsinuse 14.586087 # Cycle average of tags in use |
| 1218system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1219system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1220system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1221system.iocache.tags.warmup_cycle 246641129509 # Cycle when the warmup percentage was hit. | 1221system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1222system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1223system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1224system.iocache.tags.warmup_cycle 246641129509 # Cycle when the warmup percentage was hit. |
| 1222system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor | 1225system.iocache.tags.occ_blocks::realview.ide 14.586087 # Average occupied blocks per requestor |
| 1223system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1224system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 1225system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1226system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1227system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1228system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1229system.iocache.tags.data_accesses 328284 # Number of data accesses | 1226system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1227system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 1228system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1229system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1230system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1231system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1232system.iocache.tags.data_accesses 328284 # Number of data accesses |
| 1230system.iocache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 1233system.iocache.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 1231system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1232system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1233system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1234system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1235system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 1236system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 1237system.iocache.overall_misses::realview.ide 36476 # number of overall misses 1238system.iocache.overall_misses::total 36476 # number of overall misses --- 16 unchanged lines hidden (view full) --- 1255system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1256system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1257system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1258system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1259system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1260system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1261system.iocache.writebacks::writebacks 36190 # number of writebacks 1262system.iocache.writebacks::total 36190 # number of writebacks | 1234system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1235system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1236system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1237system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1238system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 1239system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 1240system.iocache.overall_misses::realview.ide 36476 # number of overall misses 1241system.iocache.overall_misses::total 36476 # number of overall misses --- 16 unchanged lines hidden (view full) --- 1258system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1259system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1260system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1261system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1262system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1263system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1264system.iocache.writebacks::writebacks 36190 # number of writebacks 1265system.iocache.writebacks::total 36190 # number of writebacks |
| 1263system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1264system.l2c.tags.replacements 135163 # number of replacements 1265system.l2c.tags.tagsinuse 65177.726515 # Cycle average of tags in use 1266system.l2c.tags.total_refs 431584 # Total number of references to valid blocks. 1267system.l2c.tags.sampled_refs 200605 # Sample count of references to valid blocks. 1268system.l2c.tags.avg_refs 2.151412 # Average number of references to valid blocks. | 1266system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1267system.l2c.tags.replacements 135222 # number of replacements 1268system.l2c.tags.tagsinuse 65177.722092 # Cycle average of tags in use 1269system.l2c.tags.total_refs 431767 # Total number of references to valid blocks. 1270system.l2c.tags.sampled_refs 200667 # Sample count of references to valid blocks. 1271system.l2c.tags.avg_refs 2.151659 # Average number of references to valid blocks. |
| 1269system.l2c.tags.warmup_cycle 86559025000 # Cycle when the warmup percentage was hit. | 1272system.l2c.tags.warmup_cycle 86559025000 # Cycle when the warmup percentage was hit. |
| 1270system.l2c.tags.occ_blocks::writebacks 6643.934415 # Average occupied blocks per requestor | 1273system.l2c.tags.occ_blocks::writebacks 6644.063591 # Average occupied blocks per requestor |
| 1271system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.937413 # Average occupied blocks per requestor | 1274system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.937413 # Average occupied blocks per requestor |
| 1272system.l2c.tags.occ_blocks::cpu0.itb.walker 0.032741 # Average occupied blocks per requestor 1273system.l2c.tags.occ_blocks::cpu0.inst 7087.737158 # Average occupied blocks per requestor 1274system.l2c.tags.occ_blocks::cpu0.data 43017.411906 # Average occupied blocks per requestor 1275system.l2c.tags.occ_blocks::cpu1.inst 1645.646531 # Average occupied blocks per requestor 1276system.l2c.tags.occ_blocks::cpu1.data 6779.026349 # Average occupied blocks per requestor 1277system.l2c.tags.occ_percent::writebacks 0.101378 # Average percentage of cache occupancy | 1275system.l2c.tags.occ_blocks::cpu0.itb.walker 0.032742 # Average occupied blocks per requestor 1276system.l2c.tags.occ_blocks::cpu0.inst 7087.775672 # Average occupied blocks per requestor 1277system.l2c.tags.occ_blocks::cpu0.data 43017.281235 # Average occupied blocks per requestor 1278system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001947 # Average occupied blocks per requestor 1279system.l2c.tags.occ_blocks::cpu1.inst 1645.603615 # Average occupied blocks per requestor 1280system.l2c.tags.occ_blocks::cpu1.data 6779.025879 # Average occupied blocks per requestor 1281system.l2c.tags.occ_percent::writebacks 0.101380 # Average percentage of cache occupancy |
| 1278system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 1279system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 1282system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 1283system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 1280system.l2c.tags.occ_percent::cpu0.inst 0.108150 # Average percentage of cache occupancy 1281system.l2c.tags.occ_percent::cpu0.data 0.656394 # Average percentage of cache occupancy 1282system.l2c.tags.occ_percent::cpu1.inst 0.025111 # Average percentage of cache occupancy | 1284system.l2c.tags.occ_percent::cpu0.inst 0.108151 # Average percentage of cache occupancy 1285system.l2c.tags.occ_percent::cpu0.data 0.656392 # Average percentage of cache occupancy 1286system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 1287system.l2c.tags.occ_percent::cpu1.inst 0.025110 # Average percentage of cache occupancy |
| 1283system.l2c.tags.occ_percent::cpu1.data 0.103440 # Average percentage of cache occupancy 1284system.l2c.tags.occ_percent::total 0.994533 # Average percentage of cache occupancy | 1288system.l2c.tags.occ_percent::cpu1.data 0.103440 # Average percentage of cache occupancy 1289system.l2c.tags.occ_percent::total 0.994533 # Average percentage of cache occupancy |
| 1285system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1286system.l2c.tags.occ_task_id_blocks::1024 65436 # Occupied blocks per task id | 1290system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 1291system.l2c.tags.occ_task_id_blocks::1024 65438 # Occupied blocks per task id 1292system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id |
| 1287system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1288system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id | 1293system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1294system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id |
| 1289system.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id 1290system.l2c.tags.age_task_id_blocks_1024::3 15758 # Occupied blocks per task id 1291system.l2c.tags.age_task_id_blocks_1024::4 49214 # Occupied blocks per task id 1292system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 1293system.l2c.tags.occ_task_id_percent::1024 0.998474 # Percentage of cache occupancy per task id 1294system.l2c.tags.tag_accesses 5327823 # Number of tag accesses 1295system.l2c.tags.data_accesses 5327823 # Number of data accesses 1296system.l2c.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1297system.l2c.WritebackDirty_hits::writebacks 225157 # number of WritebackDirty hits 1298system.l2c.WritebackDirty_hits::total 225157 # number of WritebackDirty hits 1299system.l2c.UpgradeReq_hits::cpu0.data 10195 # number of UpgradeReq hits 1300system.l2c.UpgradeReq_hits::cpu1.data 3254 # number of UpgradeReq hits 1301system.l2c.UpgradeReq_hits::total 13449 # number of UpgradeReq hits 1302system.l2c.SCUpgradeReq_hits::cpu0.data 779 # number of SCUpgradeReq hits 1303system.l2c.SCUpgradeReq_hits::cpu1.data 1161 # number of SCUpgradeReq hits 1304system.l2c.SCUpgradeReq_hits::total 1940 # number of SCUpgradeReq hits 1305system.l2c.ReadExReq_hits::cpu0.data 13430 # number of ReadExReq hits 1306system.l2c.ReadExReq_hits::cpu1.data 3004 # number of ReadExReq hits 1307system.l2c.ReadExReq_hits::total 16434 # number of ReadExReq hits 1308system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 116 # number of ReadSharedReq hits 1309system.l2c.ReadSharedReq_hits::cpu0.itb.walker 70 # number of ReadSharedReq hits 1310system.l2c.ReadSharedReq_hits::cpu0.inst 42080 # number of ReadSharedReq hits 1311system.l2c.ReadSharedReq_hits::cpu0.data 82797 # number of ReadSharedReq hits 1312system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits 1313system.l2c.ReadSharedReq_hits::cpu1.itb.walker 24 # number of ReadSharedReq hits 1314system.l2c.ReadSharedReq_hits::cpu1.inst 18817 # number of ReadSharedReq hits 1315system.l2c.ReadSharedReq_hits::cpu1.data 12978 # number of ReadSharedReq hits 1316system.l2c.ReadSharedReq_hits::total 156918 # number of ReadSharedReq hits 1317system.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits 1318system.l2c.demand_hits::cpu0.itb.walker 70 # number of demand (read+write) hits 1319system.l2c.demand_hits::cpu0.inst 42080 # number of demand (read+write) hits 1320system.l2c.demand_hits::cpu0.data 96227 # number of demand (read+write) hits 1321system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits 1322system.l2c.demand_hits::cpu1.itb.walker 24 # number of demand (read+write) hits 1323system.l2c.demand_hits::cpu1.inst 18817 # number of demand (read+write) hits 1324system.l2c.demand_hits::cpu1.data 15982 # number of demand (read+write) hits 1325system.l2c.demand_hits::total 173352 # number of demand (read+write) hits 1326system.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits 1327system.l2c.overall_hits::cpu0.itb.walker 70 # number of overall hits 1328system.l2c.overall_hits::cpu0.inst 42080 # number of overall hits 1329system.l2c.overall_hits::cpu0.data 96227 # number of overall hits 1330system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits 1331system.l2c.overall_hits::cpu1.itb.walker 24 # number of overall hits 1332system.l2c.overall_hits::cpu1.inst 18817 # number of overall hits 1333system.l2c.overall_hits::cpu1.data 15982 # number of overall hits 1334system.l2c.overall_hits::total 173352 # number of overall hits 1335system.l2c.UpgradeReq_misses::cpu0.data 275 # number of UpgradeReq misses 1336system.l2c.UpgradeReq_misses::cpu1.data 112 # number of UpgradeReq misses 1337system.l2c.UpgradeReq_misses::total 387 # number of UpgradeReq misses 1338system.l2c.SCUpgradeReq_misses::cpu0.data 30 # number of SCUpgradeReq misses 1339system.l2c.SCUpgradeReq_misses::cpu1.data 26 # number of SCUpgradeReq misses 1340system.l2c.SCUpgradeReq_misses::total 56 # number of SCUpgradeReq misses 1341system.l2c.ReadExReq_misses::cpu0.data 137059 # number of ReadExReq misses 1342system.l2c.ReadExReq_misses::cpu1.data 15933 # number of ReadExReq misses 1343system.l2c.ReadExReq_misses::total 152992 # number of ReadExReq misses | 1295system.l2c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 1296system.l2c.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id 1297system.l2c.tags.age_task_id_blocks_1024::3 15850 # Occupied blocks per task id 1298system.l2c.tags.age_task_id_blocks_1024::4 49136 # Occupied blocks per task id 1299system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id 1300system.l2c.tags.occ_task_id_percent::1024 0.998505 # Percentage of cache occupancy per task id 1301system.l2c.tags.tag_accesses 5329877 # Number of tag accesses 1302system.l2c.tags.data_accesses 5329877 # Number of data accesses 1303system.l2c.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1304system.l2c.WritebackDirty_hits::writebacks 225154 # number of WritebackDirty hits 1305system.l2c.WritebackDirty_hits::total 225154 # number of WritebackDirty hits 1306system.l2c.UpgradeReq_hits::cpu0.data 10176 # number of UpgradeReq hits 1307system.l2c.UpgradeReq_hits::cpu1.data 3291 # number of UpgradeReq hits 1308system.l2c.UpgradeReq_hits::total 13467 # number of UpgradeReq hits 1309system.l2c.SCUpgradeReq_hits::cpu0.data 773 # number of SCUpgradeReq hits 1310system.l2c.SCUpgradeReq_hits::cpu1.data 1151 # number of SCUpgradeReq hits 1311system.l2c.SCUpgradeReq_hits::total 1924 # number of SCUpgradeReq hits 1312system.l2c.ReadExReq_hits::cpu0.data 13542 # number of ReadExReq hits 1313system.l2c.ReadExReq_hits::cpu1.data 2929 # number of ReadExReq hits 1314system.l2c.ReadExReq_hits::total 16471 # number of ReadExReq hits 1315system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 96 # number of ReadSharedReq hits 1316system.l2c.ReadSharedReq_hits::cpu0.itb.walker 62 # number of ReadSharedReq hits 1317system.l2c.ReadSharedReq_hits::cpu0.inst 42312 # number of ReadSharedReq hits 1318system.l2c.ReadSharedReq_hits::cpu0.data 82718 # number of ReadSharedReq hits 1319system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 38 # number of ReadSharedReq hits 1320system.l2c.ReadSharedReq_hits::cpu1.itb.walker 19 # number of ReadSharedReq hits 1321system.l2c.ReadSharedReq_hits::cpu1.inst 18847 # number of ReadSharedReq hits 1322system.l2c.ReadSharedReq_hits::cpu1.data 12996 # number of ReadSharedReq hits 1323system.l2c.ReadSharedReq_hits::total 157088 # number of ReadSharedReq hits 1324system.l2c.demand_hits::cpu0.dtb.walker 96 # number of demand (read+write) hits 1325system.l2c.demand_hits::cpu0.itb.walker 62 # number of demand (read+write) hits 1326system.l2c.demand_hits::cpu0.inst 42312 # number of demand (read+write) hits 1327system.l2c.demand_hits::cpu0.data 96260 # number of demand (read+write) hits 1328system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits 1329system.l2c.demand_hits::cpu1.itb.walker 19 # number of demand (read+write) hits 1330system.l2c.demand_hits::cpu1.inst 18847 # number of demand (read+write) hits 1331system.l2c.demand_hits::cpu1.data 15925 # number of demand (read+write) hits 1332system.l2c.demand_hits::total 173559 # number of demand (read+write) hits 1333system.l2c.overall_hits::cpu0.dtb.walker 96 # number of overall hits 1334system.l2c.overall_hits::cpu0.itb.walker 62 # number of overall hits 1335system.l2c.overall_hits::cpu0.inst 42312 # number of overall hits 1336system.l2c.overall_hits::cpu0.data 96260 # number of overall hits 1337system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits 1338system.l2c.overall_hits::cpu1.itb.walker 19 # number of overall hits 1339system.l2c.overall_hits::cpu1.inst 18847 # number of overall hits 1340system.l2c.overall_hits::cpu1.data 15925 # number of overall hits 1341system.l2c.overall_hits::total 173559 # number of overall hits 1342system.l2c.UpgradeReq_misses::cpu0.data 280 # number of UpgradeReq misses 1343system.l2c.UpgradeReq_misses::cpu1.data 93 # number of UpgradeReq misses 1344system.l2c.UpgradeReq_misses::total 373 # number of UpgradeReq misses 1345system.l2c.SCUpgradeReq_misses::cpu0.data 35 # number of SCUpgradeReq misses 1346system.l2c.SCUpgradeReq_misses::cpu1.data 37 # number of SCUpgradeReq misses 1347system.l2c.SCUpgradeReq_misses::total 72 # number of SCUpgradeReq misses 1348system.l2c.ReadExReq_misses::cpu0.data 137052 # number of ReadExReq misses 1349system.l2c.ReadExReq_misses::cpu1.data 15935 # number of ReadExReq misses 1350system.l2c.ReadExReq_misses::total 152987 # number of ReadExReq misses |
| 1344system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 1345system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses | 1351system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 1352system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses |
| 1346system.l2c.ReadSharedReq_misses::cpu0.inst 17615 # number of ReadSharedReq misses 1347system.l2c.ReadSharedReq_misses::cpu0.data 12278 # number of ReadSharedReq misses 1348system.l2c.ReadSharedReq_misses::cpu1.inst 2573 # number of ReadSharedReq misses 1349system.l2c.ReadSharedReq_misses::cpu1.data 1450 # number of ReadSharedReq misses 1350system.l2c.ReadSharedReq_misses::total 33926 # number of ReadSharedReq misses | 1353system.l2c.ReadSharedReq_misses::cpu0.inst 17619 # number of ReadSharedReq misses 1354system.l2c.ReadSharedReq_misses::cpu0.data 12284 # number of ReadSharedReq misses 1355system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses 1356system.l2c.ReadSharedReq_misses::cpu1.inst 2569 # number of ReadSharedReq misses 1357system.l2c.ReadSharedReq_misses::cpu1.data 1434 # number of ReadSharedReq misses 1358system.l2c.ReadSharedReq_misses::total 33917 # number of ReadSharedReq misses |
| 1351system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 1352system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 1359system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 1360system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 1353system.l2c.demand_misses::cpu0.inst 17615 # number of demand (read+write) misses 1354system.l2c.demand_misses::cpu0.data 149337 # number of demand (read+write) misses 1355system.l2c.demand_misses::cpu1.inst 2573 # number of demand (read+write) misses 1356system.l2c.demand_misses::cpu1.data 17383 # number of demand (read+write) misses 1357system.l2c.demand_misses::total 186918 # number of demand (read+write) misses | 1361system.l2c.demand_misses::cpu0.inst 17619 # number of demand (read+write) misses 1362system.l2c.demand_misses::cpu0.data 149336 # number of demand (read+write) misses 1363system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 1364system.l2c.demand_misses::cpu1.inst 2569 # number of demand (read+write) misses 1365system.l2c.demand_misses::cpu1.data 17369 # number of demand (read+write) misses 1366system.l2c.demand_misses::total 186904 # number of demand (read+write) misses |
| 1358system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 1359system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 1367system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 1368system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 1360system.l2c.overall_misses::cpu0.inst 17615 # number of overall misses 1361system.l2c.overall_misses::cpu0.data 149337 # number of overall misses 1362system.l2c.overall_misses::cpu1.inst 2573 # number of overall misses 1363system.l2c.overall_misses::cpu1.data 17383 # number of overall misses 1364system.l2c.overall_misses::total 186918 # number of overall misses 1365system.l2c.WritebackDirty_accesses::writebacks 225157 # number of WritebackDirty accesses(hits+misses) 1366system.l2c.WritebackDirty_accesses::total 225157 # number of WritebackDirty accesses(hits+misses) 1367system.l2c.UpgradeReq_accesses::cpu0.data 10470 # number of UpgradeReq accesses(hits+misses) 1368system.l2c.UpgradeReq_accesses::cpu1.data 3366 # number of UpgradeReq accesses(hits+misses) 1369system.l2c.UpgradeReq_accesses::total 13836 # number of UpgradeReq accesses(hits+misses) 1370system.l2c.SCUpgradeReq_accesses::cpu0.data 809 # number of SCUpgradeReq accesses(hits+misses) 1371system.l2c.SCUpgradeReq_accesses::cpu1.data 1187 # number of SCUpgradeReq accesses(hits+misses) | 1369system.l2c.overall_misses::cpu0.inst 17619 # number of overall misses 1370system.l2c.overall_misses::cpu0.data 149336 # number of overall misses 1371system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 1372system.l2c.overall_misses::cpu1.inst 2569 # number of overall misses 1373system.l2c.overall_misses::cpu1.data 17369 # number of overall misses 1374system.l2c.overall_misses::total 186904 # number of overall misses 1375system.l2c.WritebackDirty_accesses::writebacks 225154 # number of WritebackDirty accesses(hits+misses) 1376system.l2c.WritebackDirty_accesses::total 225154 # number of WritebackDirty accesses(hits+misses) 1377system.l2c.UpgradeReq_accesses::cpu0.data 10456 # number of UpgradeReq accesses(hits+misses) 1378system.l2c.UpgradeReq_accesses::cpu1.data 3384 # number of UpgradeReq accesses(hits+misses) 1379system.l2c.UpgradeReq_accesses::total 13840 # number of UpgradeReq accesses(hits+misses) 1380system.l2c.SCUpgradeReq_accesses::cpu0.data 808 # number of SCUpgradeReq accesses(hits+misses) 1381system.l2c.SCUpgradeReq_accesses::cpu1.data 1188 # number of SCUpgradeReq accesses(hits+misses) |
| 1372system.l2c.SCUpgradeReq_accesses::total 1996 # number of SCUpgradeReq accesses(hits+misses) | 1382system.l2c.SCUpgradeReq_accesses::total 1996 # number of SCUpgradeReq accesses(hits+misses) |
| 1373system.l2c.ReadExReq_accesses::cpu0.data 150489 # number of ReadExReq accesses(hits+misses) 1374system.l2c.ReadExReq_accesses::cpu1.data 18937 # number of ReadExReq accesses(hits+misses) 1375system.l2c.ReadExReq_accesses::total 169426 # number of ReadExReq accesses(hits+misses) 1376system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 124 # number of ReadSharedReq accesses(hits+misses) 1377system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 72 # number of ReadSharedReq accesses(hits+misses) 1378system.l2c.ReadSharedReq_accesses::cpu0.inst 59695 # number of ReadSharedReq accesses(hits+misses) 1379system.l2c.ReadSharedReq_accesses::cpu0.data 95075 # number of ReadSharedReq accesses(hits+misses) 1380system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) 1381system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 24 # number of ReadSharedReq accesses(hits+misses) 1382system.l2c.ReadSharedReq_accesses::cpu1.inst 21390 # number of ReadSharedReq accesses(hits+misses) 1383system.l2c.ReadSharedReq_accesses::cpu1.data 14428 # number of ReadSharedReq accesses(hits+misses) 1384system.l2c.ReadSharedReq_accesses::total 190844 # number of ReadSharedReq accesses(hits+misses) 1385system.l2c.demand_accesses::cpu0.dtb.walker 124 # number of demand (read+write) accesses 1386system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses 1387system.l2c.demand_accesses::cpu0.inst 59695 # number of demand (read+write) accesses 1388system.l2c.demand_accesses::cpu0.data 245564 # number of demand (read+write) accesses 1389system.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses 1390system.l2c.demand_accesses::cpu1.itb.walker 24 # number of demand (read+write) accesses 1391system.l2c.demand_accesses::cpu1.inst 21390 # number of demand (read+write) accesses 1392system.l2c.demand_accesses::cpu1.data 33365 # number of demand (read+write) accesses 1393system.l2c.demand_accesses::total 360270 # number of demand (read+write) accesses 1394system.l2c.overall_accesses::cpu0.dtb.walker 124 # number of overall (read+write) accesses 1395system.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses 1396system.l2c.overall_accesses::cpu0.inst 59695 # number of overall (read+write) accesses 1397system.l2c.overall_accesses::cpu0.data 245564 # number of overall (read+write) accesses 1398system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses 1399system.l2c.overall_accesses::cpu1.itb.walker 24 # number of overall (read+write) accesses 1400system.l2c.overall_accesses::cpu1.inst 21390 # number of overall (read+write) accesses 1401system.l2c.overall_accesses::cpu1.data 33365 # number of overall (read+write) accesses 1402system.l2c.overall_accesses::total 360270 # number of overall (read+write) accesses 1403system.l2c.UpgradeReq_miss_rate::cpu0.data 0.026266 # miss rate for UpgradeReq accesses 1404system.l2c.UpgradeReq_miss_rate::cpu1.data 0.033274 # miss rate for UpgradeReq accesses 1405system.l2c.UpgradeReq_miss_rate::total 0.027971 # miss rate for UpgradeReq accesses 1406system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037083 # miss rate for SCUpgradeReq accesses 1407system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.021904 # miss rate for SCUpgradeReq accesses 1408system.l2c.SCUpgradeReq_miss_rate::total 0.028056 # miss rate for SCUpgradeReq accesses 1409system.l2c.ReadExReq_miss_rate::cpu0.data 0.910758 # miss rate for ReadExReq accesses 1410system.l2c.ReadExReq_miss_rate::cpu1.data 0.841369 # miss rate for ReadExReq accesses 1411system.l2c.ReadExReq_miss_rate::total 0.903002 # miss rate for ReadExReq accesses 1412system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for ReadSharedReq accesses 1413system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027778 # miss rate for ReadSharedReq accesses 1414system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.295083 # miss rate for ReadSharedReq accesses 1415system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.129140 # miss rate for ReadSharedReq accesses 1416system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.120290 # miss rate for ReadSharedReq accesses 1417system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.100499 # miss rate for ReadSharedReq accesses 1418system.l2c.ReadSharedReq_miss_rate::total 0.177768 # miss rate for ReadSharedReq accesses 1419system.l2c.demand_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for demand accesses 1420system.l2c.demand_miss_rate::cpu0.itb.walker 0.027778 # miss rate for demand accesses 1421system.l2c.demand_miss_rate::cpu0.inst 0.295083 # miss rate for demand accesses 1422system.l2c.demand_miss_rate::cpu0.data 0.608139 # miss rate for demand accesses 1423system.l2c.demand_miss_rate::cpu1.inst 0.120290 # miss rate for demand accesses 1424system.l2c.demand_miss_rate::cpu1.data 0.520995 # miss rate for demand accesses 1425system.l2c.demand_miss_rate::total 0.518828 # miss rate for demand accesses 1426system.l2c.overall_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for overall accesses 1427system.l2c.overall_miss_rate::cpu0.itb.walker 0.027778 # miss rate for overall accesses 1428system.l2c.overall_miss_rate::cpu0.inst 0.295083 # miss rate for overall accesses 1429system.l2c.overall_miss_rate::cpu0.data 0.608139 # miss rate for overall accesses 1430system.l2c.overall_miss_rate::cpu1.inst 0.120290 # miss rate for overall accesses 1431system.l2c.overall_miss_rate::cpu1.data 0.520995 # miss rate for overall accesses 1432system.l2c.overall_miss_rate::total 0.518828 # miss rate for overall accesses | 1383system.l2c.ReadExReq_accesses::cpu0.data 150594 # number of ReadExReq accesses(hits+misses) 1384system.l2c.ReadExReq_accesses::cpu1.data 18864 # number of ReadExReq accesses(hits+misses) 1385system.l2c.ReadExReq_accesses::total 169458 # number of ReadExReq accesses(hits+misses) 1386system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 104 # number of ReadSharedReq accesses(hits+misses) 1387system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 64 # number of ReadSharedReq accesses(hits+misses) 1388system.l2c.ReadSharedReq_accesses::cpu0.inst 59931 # number of ReadSharedReq accesses(hits+misses) 1389system.l2c.ReadSharedReq_accesses::cpu0.data 95002 # number of ReadSharedReq accesses(hits+misses) 1390system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 38 # number of ReadSharedReq accesses(hits+misses) 1391system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses) 1392system.l2c.ReadSharedReq_accesses::cpu1.inst 21416 # number of ReadSharedReq accesses(hits+misses) 1393system.l2c.ReadSharedReq_accesses::cpu1.data 14430 # number of ReadSharedReq accesses(hits+misses) 1394system.l2c.ReadSharedReq_accesses::total 191005 # number of ReadSharedReq accesses(hits+misses) 1395system.l2c.demand_accesses::cpu0.dtb.walker 104 # number of demand (read+write) accesses 1396system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses 1397system.l2c.demand_accesses::cpu0.inst 59931 # number of demand (read+write) accesses 1398system.l2c.demand_accesses::cpu0.data 245596 # number of demand (read+write) accesses 1399system.l2c.demand_accesses::cpu1.dtb.walker 38 # number of demand (read+write) accesses 1400system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses 1401system.l2c.demand_accesses::cpu1.inst 21416 # number of demand (read+write) accesses 1402system.l2c.demand_accesses::cpu1.data 33294 # number of demand (read+write) accesses 1403system.l2c.demand_accesses::total 360463 # number of demand (read+write) accesses 1404system.l2c.overall_accesses::cpu0.dtb.walker 104 # number of overall (read+write) accesses 1405system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses 1406system.l2c.overall_accesses::cpu0.inst 59931 # number of overall (read+write) accesses 1407system.l2c.overall_accesses::cpu0.data 245596 # number of overall (read+write) accesses 1408system.l2c.overall_accesses::cpu1.dtb.walker 38 # number of overall (read+write) accesses 1409system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses 1410system.l2c.overall_accesses::cpu1.inst 21416 # number of overall (read+write) accesses 1411system.l2c.overall_accesses::cpu1.data 33294 # number of overall (read+write) accesses 1412system.l2c.overall_accesses::total 360463 # number of overall (read+write) accesses 1413system.l2c.UpgradeReq_miss_rate::cpu0.data 0.026779 # miss rate for UpgradeReq accesses 1414system.l2c.UpgradeReq_miss_rate::cpu1.data 0.027482 # miss rate for UpgradeReq accesses 1415system.l2c.UpgradeReq_miss_rate::total 0.026951 # miss rate for UpgradeReq accesses 1416system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.043317 # miss rate for SCUpgradeReq accesses 1417system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.031145 # miss rate for SCUpgradeReq accesses 1418system.l2c.SCUpgradeReq_miss_rate::total 0.036072 # miss rate for SCUpgradeReq accesses 1419system.l2c.ReadExReq_miss_rate::cpu0.data 0.910076 # miss rate for ReadExReq accesses 1420system.l2c.ReadExReq_miss_rate::cpu1.data 0.844731 # miss rate for ReadExReq accesses 1421system.l2c.ReadExReq_miss_rate::total 0.902802 # miss rate for ReadExReq accesses 1422system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.076923 # miss rate for ReadSharedReq accesses 1423system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.031250 # miss rate for ReadSharedReq accesses 1424system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.293988 # miss rate for ReadSharedReq accesses 1425system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.129303 # miss rate for ReadSharedReq accesses 1426system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.050000 # miss rate for ReadSharedReq accesses 1427system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.119957 # miss rate for ReadSharedReq accesses 1428system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.099376 # miss rate for ReadSharedReq accesses 1429system.l2c.ReadSharedReq_miss_rate::total 0.177571 # miss rate for ReadSharedReq accesses 1430system.l2c.demand_miss_rate::cpu0.dtb.walker 0.076923 # miss rate for demand accesses 1431system.l2c.demand_miss_rate::cpu0.itb.walker 0.031250 # miss rate for demand accesses 1432system.l2c.demand_miss_rate::cpu0.inst 0.293988 # miss rate for demand accesses 1433system.l2c.demand_miss_rate::cpu0.data 0.608056 # miss rate for demand accesses 1434system.l2c.demand_miss_rate::cpu1.itb.walker 0.050000 # miss rate for demand accesses 1435system.l2c.demand_miss_rate::cpu1.inst 0.119957 # miss rate for demand accesses 1436system.l2c.demand_miss_rate::cpu1.data 0.521686 # miss rate for demand accesses 1437system.l2c.demand_miss_rate::total 0.518511 # miss rate for demand accesses 1438system.l2c.overall_miss_rate::cpu0.dtb.walker 0.076923 # miss rate for overall accesses 1439system.l2c.overall_miss_rate::cpu0.itb.walker 0.031250 # miss rate for overall accesses 1440system.l2c.overall_miss_rate::cpu0.inst 0.293988 # miss rate for overall accesses 1441system.l2c.overall_miss_rate::cpu0.data 0.608056 # miss rate for overall accesses 1442system.l2c.overall_miss_rate::cpu1.itb.walker 0.050000 # miss rate for overall accesses 1443system.l2c.overall_miss_rate::cpu1.inst 0.119957 # miss rate for overall accesses 1444system.l2c.overall_miss_rate::cpu1.data 0.521686 # miss rate for overall accesses 1445system.l2c.overall_miss_rate::total 0.518511 # miss rate for overall accesses |
| 1433system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1434system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1435system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1436system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1437system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1438system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1446system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1447system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1448system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1449system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1450system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1451system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1439system.l2c.writebacks::writebacks 102405 # number of writebacks 1440system.l2c.writebacks::total 102405 # number of writebacks 1441system.membus.snoop_filter.tot_requests 459549 # Total number of requests made to the snoop filter. 1442system.membus.snoop_filter.hit_single_requests 242014 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1443system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1452system.l2c.writebacks::writebacks 102433 # number of writebacks 1453system.l2c.writebacks::total 102433 # number of writebacks 1454system.membus.snoop_filter.tot_requests 459623 # Total number of requests made to the snoop filter. 1455system.membus.snoop_filter.hit_single_requests 242074 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1456system.membus.snoop_filter.hit_multi_requests 539 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1444system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1445system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1446system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1457system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1458system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1459system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1447system.membus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 1460system.membus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 1448system.membus.trans_dist::ReadReq 43995 # Transaction distribution | 1461system.membus.trans_dist::ReadReq 43995 # Transaction distribution |
| 1449system.membus.trans_dist::ReadResp 78173 # Transaction distribution | 1462system.membus.trans_dist::ReadResp 78164 # Transaction distribution |
| 1450system.membus.trans_dist::WriteReq 30844 # Transaction distribution 1451system.membus.trans_dist::WriteResp 30844 # Transaction distribution | 1463system.membus.trans_dist::WriteReq 30844 # Transaction distribution 1464system.membus.trans_dist::WriteResp 30844 # Transaction distribution |
| 1452system.membus.trans_dist::WritebackDirty 138595 # Transaction distribution 1453system.membus.trans_dist::CleanEvict 11037 # Transaction distribution 1454system.membus.trans_dist::UpgradeReq 47132 # Transaction distribution 1455system.membus.trans_dist::SCUpgradeReq 38991 # Transaction distribution 1456system.membus.trans_dist::UpgradeResp 461 # Transaction distribution 1457system.membus.trans_dist::ReadExReq 153373 # Transaction distribution 1458system.membus.trans_dist::ReadExResp 152974 # Transaction distribution 1459system.membus.trans_dist::ReadSharedReq 34178 # Transaction distribution | 1465system.membus.trans_dist::WritebackDirty 138623 # Transaction distribution 1466system.membus.trans_dist::CleanEvict 11066 # Transaction distribution 1467system.membus.trans_dist::UpgradeReq 47127 # Transaction distribution 1468system.membus.trans_dist::SCUpgradeReq 39021 # Transaction distribution 1469system.membus.trans_dist::UpgradeResp 464 # Transaction distribution 1470system.membus.trans_dist::ReadExReq 153374 # Transaction distribution 1471system.membus.trans_dist::ReadExResp 152968 # Transaction distribution 1472system.membus.trans_dist::ReadSharedReq 34169 # Transaction distribution |
| 1460system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1461system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1462system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 1463system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1464system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) | 1473system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1474system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1475system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 1476system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1477system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) |
| 1465system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 602273 # Packet count per connected master and slave (bytes) 1466system.membus.pkt_count_system.l2c.mem_side::total 723651 # Packet count per connected master and slave (bytes) | 1478system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 602335 # Packet count per connected master and slave (bytes) 1479system.membus.pkt_count_system.l2c.mem_side::total 723713 # Packet count per connected master and slave (bytes) |
| 1467system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 1468system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) | 1480system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 1481system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) |
| 1469system.membus.pkt_count::total 833045 # Packet count per connected master and slave (bytes) | 1482system.membus.pkt_count::total 833107 # Packet count per connected master and slave (bytes) |
| 1470system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 1471system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1472system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) | 1483system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 1484system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1485system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) |
| 1473system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18572232 # Cumulative packet size per connected master and slave (bytes) 1474system.membus.pkt_size_system.l2c.mem_side::total 18762002 # Cumulative packet size per connected master and slave (bytes) | 1486system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18573064 # Cumulative packet size per connected master and slave (bytes) 1487system.membus.pkt_size_system.l2c.mem_side::total 18762834 # Cumulative packet size per connected master and slave (bytes) |
| 1475system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 1476system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) | 1488system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 1489system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) |
| 1477system.membus.pkt_size::total 21094290 # Cumulative packet size per connected master and slave (bytes) | 1490system.membus.pkt_size::total 21095122 # Cumulative packet size per connected master and slave (bytes) |
| 1478system.membus.snoops 0 # Total snoops (count) 1479system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1491system.membus.snoops 0 # Total snoops (count) 1492system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1480system.membus.snoop_fanout::samples 534369 # Request fanout histogram 1481system.membus.snoop_fanout::mean 0.010375 # Request fanout histogram 1482system.membus.snoop_fanout::stdev 0.101327 # Request fanout histogram | 1493system.membus.snoop_fanout::samples 534443 # Request fanout histogram 1494system.membus.snoop_fanout::mean 0.010413 # Request fanout histogram 1495system.membus.snoop_fanout::stdev 0.101510 # Request fanout histogram |
| 1483system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1496system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1484system.membus.snoop_fanout::0 528825 98.96% 98.96% # Request fanout histogram 1485system.membus.snoop_fanout::1 5544 1.04% 100.00% # Request fanout histogram | 1497system.membus.snoop_fanout::0 528878 98.96% 98.96% # Request fanout histogram 1498system.membus.snoop_fanout::1 5565 1.04% 100.00% # Request fanout histogram |
| 1486system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1487system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1488system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1489system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1499system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1500system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1501system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1502system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1490system.membus.snoop_fanout::total 534369 # Request fanout histogram 1491system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1492system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1493system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1494system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1495system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1496system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1497system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 1503system.membus.snoop_fanout::total 534443 # Request fanout histogram 1504system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1505system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1506system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1507system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1508system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1509system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1510system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 1498system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1499system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1500system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1501system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1502system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1503system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 1511system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1512system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1513system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1514system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1515system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1516system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1504system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1505system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 1517system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1518system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 1506system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1507system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1508system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1509system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1510system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1511system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1512system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1513system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1529system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1530system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1531system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1532system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1533system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1534system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1535system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1536system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1519system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1520system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1521system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1522system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1523system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1524system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1525system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1526system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1542system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1543system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1544system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1545system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1546system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1547system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1548system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1549system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1537system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1538system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1539system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1540system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1541system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1542system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1543system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 1550system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1551system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1552system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1553system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1554system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1555system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1556system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 1544system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1545system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1546system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1547system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 1557system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1558system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1559system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1560system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1548system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1549system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1550system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1551system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1552system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1553system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1554system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1555system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1556system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1557system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1558system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1559system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1560system.toL2Bus.snoop_filter.tot_requests 898844 # Total number of requests made to the snoop filter. 1561system.toL2Bus.snoop_filter.hit_single_requests 454083 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1562system.toL2Bus.snoop_filter.hit_multi_requests 154581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1563system.toL2Bus.snoop_filter.tot_snoops 30372 # Total number of snoops made to the snoop filter. 1564system.toL2Bus.snoop_filter.hit_single_snoops 29420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1565system.toL2Bus.snoop_filter.hit_multi_snoops 952 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1566system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states | 1561system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1562system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1563system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1564system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1565system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1566system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1567system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1568system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1569system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1570system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1571system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1572system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states 1573system.toL2Bus.snoop_filter.tot_requests 899310 # Total number of requests made to the snoop filter. 1574system.toL2Bus.snoop_filter.hit_single_requests 443343 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1575system.toL2Bus.snoop_filter.hit_multi_requests 166356 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1576system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter. 1577system.toL2Bus.snoop_filter.hit_single_snoops 29463 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1578system.toL2Bus.snoop_filter.hit_multi_snoops 1052 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1579system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802884446000 # Cumulative time (in ticks) in various power states |
| 1567system.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution | 1580system.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution |
| 1568system.toL2Bus.trans_dist::ReadResp 337174 # Transaction distribution | 1581system.toL2Bus.trans_dist::ReadResp 337330 # Transaction distribution |
| 1569system.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution 1570system.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution | 1582system.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution 1583system.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution |
| 1571system.toL2Bus.trans_dist::WritebackDirty 225157 # Transaction distribution 1572system.toL2Bus.trans_dist::CleanEvict 65355 # Transaction distribution 1573system.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution 1574system.toL2Bus.trans_dist::SCUpgradeReq 40931 # Transaction distribution 1575system.toL2Bus.trans_dist::UpgradeResp 101494 # Transaction distribution 1576system.toL2Bus.trans_dist::ReadExReq 213640 # Transaction distribution 1577system.toL2Bus.trans_dist::ReadExResp 213640 # Transaction distribution 1578system.toL2Bus.trans_dist::ReadSharedReq 293175 # Transaction distribution 1579system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1214281 # Packet count per connected master and slave (bytes) 1580system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 442535 # Packet count per connected master and slave (bytes) 1581system.toL2Bus.pkt_count::total 1656816 # Packet count per connected master and slave (bytes) 1582system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36095992 # Cumulative packet size per connected master and slave (bytes) 1583system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10996714 # Cumulative packet size per connected master and slave (bytes) 1584system.toL2Bus.pkt_size::total 47092706 # Cumulative packet size per connected master and slave (bytes) 1585system.toL2Bus.snoops 140680 # Total snoops (count) 1586system.toL2Bus.snoopTraffic 6570496 # Total snoop traffic (bytes) 1587system.toL2Bus.snoop_fanout::samples 1114107 # Request fanout histogram 1588system.toL2Bus.snoop_fanout::mean 0.326086 # Request fanout histogram 1589system.toL2Bus.snoop_fanout::stdev 0.470599 # Request fanout histogram | 1584system.toL2Bus.trans_dist::WritebackDirty 225154 # Transaction distribution 1585system.toL2Bus.trans_dist::CleanEvict 65596 # Transaction distribution 1586system.toL2Bus.trans_dist::UpgradeReq 60575 # Transaction distribution 1587system.toL2Bus.trans_dist::SCUpgradeReq 40945 # Transaction distribution 1588system.toL2Bus.trans_dist::UpgradeResp 101520 # Transaction distribution 1589system.toL2Bus.trans_dist::ReadExReq 213686 # Transaction distribution 1590system.toL2Bus.trans_dist::ReadExResp 213686 # Transaction distribution 1591system.toL2Bus.trans_dist::ReadSharedReq 293331 # Transaction distribution 1592system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1215242 # Packet count per connected master and slave (bytes) 1593system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 442268 # Packet count per connected master and slave (bytes) 1594system.toL2Bus.pkt_count::total 1657510 # Packet count per connected master and slave (bytes) 1595system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36117688 # Cumulative packet size per connected master and slave (bytes) 1596system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10987754 # Cumulative packet size per connected master and slave (bytes) 1597system.toL2Bus.pkt_size::total 47105442 # Cumulative packet size per connected master and slave (bytes) 1598system.toL2Bus.snoops 144217 # Total snoops (count) 1599system.toL2Bus.snoopTraffic 6573440 # Total snoop traffic (bytes) 1600system.toL2Bus.snoop_fanout::samples 1114653 # Request fanout histogram 1601system.toL2Bus.snoop_fanout::mean 0.328092 # Request fanout histogram 1602system.toL2Bus.snoop_fanout::stdev 0.471525 # Request fanout histogram |
| 1590system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1603system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1591system.toL2Bus.snoop_fanout::0 751764 67.48% 67.48% # Request fanout histogram 1592system.toL2Bus.snoop_fanout::1 361391 32.44% 99.91% # Request fanout histogram 1593system.toL2Bus.snoop_fanout::2 952 0.09% 100.00% # Request fanout histogram | 1604system.toL2Bus.snoop_fanout::0 749996 67.29% 67.29% # Request fanout histogram 1605system.toL2Bus.snoop_fanout::1 363605 32.62% 99.91% # Request fanout histogram 1606system.toL2Bus.snoop_fanout::2 1052 0.09% 100.00% # Request fanout histogram |
| 1594system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1595system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1596system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1607system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1608system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1609system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1597system.toL2Bus.snoop_fanout::total 1114107 # Request fanout histogram | 1610system.toL2Bus.snoop_fanout::total 1114653 # Request fanout histogram |
| 1598 1599---------- End Simulation Statistics ---------- | 1611 1612---------- End Simulation Statistics ---------- |