| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882797500 # Number of ticks simulated 5final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882797500 # Number of ticks simulated 5final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1371763 # Simulator instruction rate (inst/s) 8host_op_rate 1671473 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26186322462 # Simulator tick rate (ticks/s) 10host_mem_usage 640448 # Number of bytes of host memory used 11host_seconds 107.04 # Real time elapsed on the host | 7host_inst_rate 808897 # Simulator instruction rate (inst/s) 8host_op_rate 985629 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15441476365 # Simulator tick rate (ticks/s) 10host_mem_usage 596572 # Number of bytes of host memory used 11host_seconds 181.52 # Real time elapsed on the host |
| 12sim_insts 146828219 # Number of instructions simulated 13sim_ops 178907974 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory --- 128 unchanged lines hidden (view full) --- 148system.cpu0.dtb.read_hits 20339694 # DTB read hits 149system.cpu0.dtb.read_misses 6871 # DTB read misses 150system.cpu0.dtb.write_hits 16391004 # DTB write hits 151system.cpu0.dtb.write_misses 1093 # DTB write misses 152system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 153system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 154system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 155system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 12sim_insts 146828219 # Number of instructions simulated 13sim_ops 178907974 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory --- 128 unchanged lines hidden (view full) --- 148system.cpu0.dtb.read_hits 20339694 # DTB read hits 149system.cpu0.dtb.read_misses 6871 # DTB read misses 150system.cpu0.dtb.write_hits 16391004 # DTB write hits 151system.cpu0.dtb.write_misses 1093 # DTB write misses 152system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 153system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 154system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 155system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 156system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB | 156system.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB |
| 157system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 158system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 159system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 160system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 161system.cpu0.dtb.read_accesses 20346565 # DTB read accesses 162system.cpu0.dtb.write_accesses 16392097 # DTB write accesses 163system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 164system.cpu0.dtb.hits 36730698 # DTB hits --- 53 unchanged lines hidden (view full) --- 218system.cpu0.itb.read_hits 0 # DTB read hits 219system.cpu0.itb.read_misses 0 # DTB read misses 220system.cpu0.itb.write_hits 0 # DTB write hits 221system.cpu0.itb.write_misses 0 # DTB write misses 222system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 223system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 224system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 225system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 157system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 158system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 159system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 160system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 161system.cpu0.dtb.read_accesses 20346565 # DTB read accesses 162system.cpu0.dtb.write_accesses 16392097 # DTB write accesses 163system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 164system.cpu0.dtb.hits 36730698 # DTB hits --- 53 unchanged lines hidden (view full) --- 218system.cpu0.itb.read_hits 0 # DTB read hits 219system.cpu0.itb.read_misses 0 # DTB read misses 220system.cpu0.itb.write_hits 0 # DTB write hits 221system.cpu0.itb.write_misses 0 # DTB write misses 222system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 223system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 224system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 225system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 226system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB | 226system.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB |
| 227system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 228system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 229system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 230system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu0.itb.read_accesses 0 # DTB read accesses 232system.cpu0.itb.write_accesses 0 # DTB write accesses 233system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses 234system.cpu0.itb.hits 97439155 # DTB hits --- 443 unchanged lines hidden (view full) --- 678system.cpu1.dtb.read_hits 12173945 # DTB read hits 679system.cpu1.dtb.read_misses 2853 # DTB read misses 680system.cpu1.dtb.write_hits 7587221 # DTB write hits 681system.cpu1.dtb.write_misses 506 # DTB write misses 682system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 683system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 684system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 685system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 227system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 228system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 229system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 230system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu0.itb.read_accesses 0 # DTB read accesses 232system.cpu0.itb.write_accesses 0 # DTB write accesses 233system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses 234system.cpu0.itb.hits 97439155 # DTB hits --- 443 unchanged lines hidden (view full) --- 678system.cpu1.dtb.read_hits 12173945 # DTB read hits 679system.cpu1.dtb.read_misses 2853 # DTB read misses 680system.cpu1.dtb.write_hits 7587221 # DTB write hits 681system.cpu1.dtb.write_misses 506 # DTB write misses 682system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 683system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 684system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 685system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 686system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB | 686system.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB |
| 687system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 688system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 689system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 690system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 691system.cpu1.dtb.read_accesses 12176798 # DTB read accesses 692system.cpu1.dtb.write_accesses 7587727 # DTB write accesses 693system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 694system.cpu1.dtb.hits 19761166 # DTB hits --- 53 unchanged lines hidden (view full) --- 748system.cpu1.itb.read_hits 0 # DTB read hits 749system.cpu1.itb.read_misses 0 # DTB read misses 750system.cpu1.itb.write_hits 0 # DTB write hits 751system.cpu1.itb.write_misses 0 # DTB write misses 752system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 753system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 754system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 755system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID | 687system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 688system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 689system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 690system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 691system.cpu1.dtb.read_accesses 12176798 # DTB read accesses 692system.cpu1.dtb.write_accesses 7587727 # DTB write accesses 693system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 694system.cpu1.dtb.hits 19761166 # DTB hits --- 53 unchanged lines hidden (view full) --- 748system.cpu1.itb.read_hits 0 # DTB read hits 749system.cpu1.itb.read_misses 0 # DTB read misses 750system.cpu1.itb.write_hits 0 # DTB write hits 751system.cpu1.itb.write_misses 0 # DTB write misses 752system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 753system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 754system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 755system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| 756system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB | 756system.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB |
| 757system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 758system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 759system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 760system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 761system.cpu1.itb.read_accesses 0 # DTB read accesses 762system.cpu1.itb.write_accesses 0 # DTB write accesses 763system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses 764system.cpu1.itb.hits 53671758 # DTB hits --- 824 unchanged lines hidden --- | 757system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 758system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 759system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 760system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 761system.cpu1.itb.read_accesses 0 # DTB read accesses 762system.cpu1.itb.write_accesses 0 # DTB write accesses 763system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses 764system.cpu1.itb.hits 53671758 # DTB hits --- 824 unchanged lines hidden --- |