| stats.txt (11502:e273e86a873d) | stats.txt (11507:be6065c1d8d2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882797500 # Number of ticks simulated 5final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882797500 # Number of ticks simulated 5final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 797664 # Simulator instruction rate (inst/s) 8host_op_rate 971941 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15227033289 # Simulator tick rate (ticks/s) 10host_mem_usage 590380 # Number of bytes of host memory used 11host_seconds 184.07 # Real time elapsed on the host | 7host_inst_rate 748827 # Simulator instruction rate (inst/s) 8host_op_rate 912434 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14294755935 # Simulator tick rate (ticks/s) 10host_mem_usage 590384 # Number of bytes of host memory used 11host_seconds 196.08 # Real time elapsed on the host |
| 12sim_insts 146828219 # Number of instructions simulated 13sim_ops 178907974 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory --- 113 unchanged lines hidden (view full) --- 133system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 134system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 135system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 136system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 138system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 139system.cpu0.dtb.inst_hits 0 # ITB inst hits 140system.cpu0.dtb.inst_misses 0 # ITB inst misses | 12sim_insts 146828219 # Number of instructions simulated 13sim_ops 178907974 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory --- 113 unchanged lines hidden (view full) --- 133system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 134system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 135system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 136system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 138system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 139system.cpu0.dtb.inst_hits 0 # ITB inst hits 140system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 141system.cpu0.dtb.read_hits 20339693 # DTB read hits | 141system.cpu0.dtb.read_hits 20339694 # DTB read hits |
| 142system.cpu0.dtb.read_misses 6871 # DTB read misses | 142system.cpu0.dtb.read_misses 6871 # DTB read misses |
| 143system.cpu0.dtb.write_hits 16391003 # DTB write hits | 143system.cpu0.dtb.write_hits 16391004 # DTB write hits |
| 144system.cpu0.dtb.write_misses 1093 # DTB write misses 145system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 146system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 147system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 149system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 150system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 151system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 152system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 153system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions | 144system.cpu0.dtb.write_misses 1093 # DTB write misses 145system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 146system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 147system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 149system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 150system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 151system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 152system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 153system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions |
| 154system.cpu0.dtb.read_accesses 20346564 # DTB read accesses 155system.cpu0.dtb.write_accesses 16392096 # DTB write accesses | 154system.cpu0.dtb.read_accesses 20346565 # DTB read accesses 155system.cpu0.dtb.write_accesses 16392097 # DTB write accesses |
| 156system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 156system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 157system.cpu0.dtb.hits 36730696 # DTB hits | 157system.cpu0.dtb.hits 36730698 # DTB hits |
| 158system.cpu0.dtb.misses 7964 # DTB misses | 158system.cpu0.dtb.misses 7964 # DTB misses |
| 159system.cpu0.dtb.accesses 36738660 # DTB accesses | 159system.cpu0.dtb.accesses 36738662 # DTB accesses |
| 160system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 161system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 162system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 163system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 164system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 165system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 166system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 167system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 66 unchanged lines hidden (view full) --- 234system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed 235system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses 236system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 237system.cpu0.num_func_calls 8000241 # number of times a function call or return occured 238system.cpu0.num_conditional_control_insts 13204192 # number of instructions that are conditional controls 239system.cpu0.num_int_insts 100762477 # number of integer instructions 240system.cpu0.num_fp_insts 9755 # number of float instructions 241system.cpu0.num_int_register_reads 182456959 # number of times the integer registers were read | 160system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 161system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 162system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 163system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 164system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 165system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 166system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 167system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 66 unchanged lines hidden (view full) --- 234system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed 235system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses 236system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 237system.cpu0.num_func_calls 8000241 # number of times a function call or return occured 238system.cpu0.num_conditional_control_insts 13204192 # number of instructions that are conditional controls 239system.cpu0.num_int_insts 100762477 # number of integer instructions 240system.cpu0.num_fp_insts 9755 # number of float instructions 241system.cpu0.num_int_register_reads 182456959 # number of times the integer registers were read |
| 242system.cpu0.num_int_register_writes 69135393 # number of times the integer registers were written | 242system.cpu0.num_int_register_writes 69135397 # number of times the integer registers were written |
| 243system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 244system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 245system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read 246system.cpu0.num_cc_register_writes 44907357 # number of times the CC registers were written 247system.cpu0.num_mem_refs 37873679 # number of memory refs 248system.cpu0.num_load_insts 20597264 # Number of load instructions 249system.cpu0.num_store_insts 17276415 # Number of store instructions 250system.cpu0.num_idle_cycles 5488183302.205065 # Number of idle cycles --- 33 unchanged lines hidden (view full) --- 284system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 285system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction 286system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction 287system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 288system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 289system.cpu0.op_class::total 116881836 # Class of executed instruction 290system.cpu0.dcache.tags.replacements 693478 # number of replacements 291system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use | 243system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 244system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 245system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read 246system.cpu0.num_cc_register_writes 44907357 # number of times the CC registers were written 247system.cpu0.num_mem_refs 37873679 # number of memory refs 248system.cpu0.num_load_insts 20597264 # Number of load instructions 249system.cpu0.num_store_insts 17276415 # Number of store instructions 250system.cpu0.num_idle_cycles 5488183302.205065 # Number of idle cycles --- 33 unchanged lines hidden (view full) --- 284system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 285system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction 286system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction 287system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 288system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 289system.cpu0.op_class::total 116881836 # Class of executed instruction 290system.cpu0.dcache.tags.replacements 693478 # number of replacements 291system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use |
| 292system.cpu0.dcache.tags.total_refs 35932313 # Total number of references to valid blocks. | 292system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks. |
| 293system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. | 293system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. |
| 294system.cpu0.dcache.tags.avg_refs 51.776413 # Average number of references to valid blocks. | 294system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks. |
| 295system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 296system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor 297system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 298system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 299system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 300system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 301system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 302system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 303system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 295system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 296system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor 297system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 298system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 299system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 300system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 301system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 302system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 303system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 304system.cpu0.dcache.tags.tag_accesses 74113669 # Number of tag accesses 305system.cpu0.dcache.tags.data_accesses 74113669 # Number of data accesses 306system.cpu0.dcache.ReadReq_hits::cpu0.data 19108530 # number of ReadReq hits 307system.cpu0.dcache.ReadReq_hits::total 19108530 # number of ReadReq hits 308system.cpu0.dcache.WriteReq_hits::cpu0.data 15690319 # number of WriteReq hits 309system.cpu0.dcache.WriteReq_hits::total 15690319 # number of WriteReq hits | 304system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses 305system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses 306system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits 307system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits 308system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits 309system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits |
| 310system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits 311system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits 312system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits 313system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits 314system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits 315system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits | 310system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits 311system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits 312system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits 313system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits 314system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits 315system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits |
| 316system.cpu0.dcache.demand_hits::cpu0.data 34798849 # number of demand (read+write) hits 317system.cpu0.dcache.demand_hits::total 34798849 # number of demand (read+write) hits 318system.cpu0.dcache.overall_hits::cpu0.data 35144934 # number of overall hits 319system.cpu0.dcache.overall_hits::total 35144934 # number of overall hits | 316system.cpu0.dcache.demand_hits::cpu0.data 34798851 # number of demand (read+write) hits 317system.cpu0.dcache.demand_hits::total 34798851 # number of demand (read+write) hits 318system.cpu0.dcache.overall_hits::cpu0.data 35144936 # number of overall hits 319system.cpu0.dcache.overall_hits::total 35144936 # number of overall hits |
| 320system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses 321system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses 322system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses 323system.cpu0.dcache.WriteReq_misses::total 295799 # number of WriteReq misses 324system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 325system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 326system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 327system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 328system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18431 # number of StoreCondReq misses 329system.cpu0.dcache.StoreCondReq_misses::total 18431 # number of StoreCondReq misses 330system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses 331system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses 332system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses 333system.cpu0.dcache.overall_misses::total 769220 # number of overall misses | 320system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses 321system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses 322system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses 323system.cpu0.dcache.WriteReq_misses::total 295799 # number of WriteReq misses 324system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 325system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 326system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 327system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 328system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18431 # number of StoreCondReq misses 329system.cpu0.dcache.StoreCondReq_misses::total 18431 # number of StoreCondReq misses 330system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses 331system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses 332system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses 333system.cpu0.dcache.overall_misses::total 769220 # number of overall misses |
| 334system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481630 # number of ReadReq accesses(hits+misses) 335system.cpu0.dcache.ReadReq_accesses::total 19481630 # number of ReadReq accesses(hits+misses) 336system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986118 # number of WriteReq accesses(hits+misses) 337system.cpu0.dcache.WriteReq_accesses::total 15986118 # number of WriteReq accesses(hits+misses) | 334system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481631 # number of ReadReq accesses(hits+misses) 335system.cpu0.dcache.ReadReq_accesses::total 19481631 # number of ReadReq accesses(hits+misses) 336system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986119 # number of WriteReq accesses(hits+misses) 337system.cpu0.dcache.WriteReq_accesses::total 15986119 # number of WriteReq accesses(hits+misses) |
| 338system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) 339system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) 340system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) 341system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) 342system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) 343system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) | 338system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) 339system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) 340system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) 341system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) 342system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) 343system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) |
| 344system.cpu0.dcache.demand_accesses::cpu0.data 35467748 # number of demand (read+write) accesses 345system.cpu0.dcache.demand_accesses::total 35467748 # number of demand (read+write) accesses 346system.cpu0.dcache.overall_accesses::cpu0.data 35914154 # number of overall (read+write) accesses 347system.cpu0.dcache.overall_accesses::total 35914154 # number of overall (read+write) accesses | 344system.cpu0.dcache.demand_accesses::cpu0.data 35467750 # number of demand (read+write) accesses 345system.cpu0.dcache.demand_accesses::total 35467750 # number of demand (read+write) accesses 346system.cpu0.dcache.overall_accesses::cpu0.data 35914156 # number of overall (read+write) accesses 347system.cpu0.dcache.overall_accesses::total 35914156 # number of overall (read+write) accesses |
| 348system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 349system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 350system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 351system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 352system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224730 # miss rate for SoftPFReq accesses 353system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224730 # miss rate for SoftPFReq accesses 354system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 355system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses --- 1140 unchanged lines hidden --- | 348system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 349system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 350system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 351system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 352system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224730 # miss rate for SoftPFReq accesses 353system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224730 # miss rate for SoftPFReq accesses 354system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 355system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses --- 1140 unchanged lines hidden --- |