| stats.txt (10585:1c9d5d9417b3) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802895 # Number of seconds simulated 4sim_ticks 2802895103500 # Number of ticks simulated 5final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802895 # Number of seconds simulated 4sim_ticks 2802895103500 # Number of ticks simulated 5final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 967895 # Simulator instruction rate (inst/s) 8host_op_rate 1179365 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18476638236 # Simulator tick rate (ticks/s) 10host_mem_usage 571628 # Number of bytes of host memory used 11host_seconds 151.70 # Real time elapsed on the host | 7host_inst_rate 834307 # Simulator instruction rate (inst/s) 8host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15926512431 # Simulator tick rate (ticks/s) 10host_mem_usage 572876 # Number of bytes of host memory used 11host_seconds 175.99 # Real time elapsed on the host |
| 12sim_insts 146829031 # Number of instructions simulated 13sim_ops 178908942 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory --- 68 unchanged lines hidden (view full) --- 88system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 89system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 90system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 91system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 92system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 93system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 94system.cf0.dma_write_txs 631 # Number of DMA write transactions. 95system.cpu_clk_domain.clock 500 # Clock period in ticks | 12sim_insts 146829031 # Number of instructions simulated 13sim_ops 178908942 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory --- 68 unchanged lines hidden (view full) --- 88system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 89system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 90system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 91system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 92system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 93system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 94system.cf0.dma_write_txs 631 # Number of DMA write transactions. 95system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 96system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 96system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 97system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 98system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 99system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 100system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 101system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 102system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 103system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 109system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 110system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 111system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 112system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 113system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 114system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 115system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 116system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 104system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 105system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 106system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 107system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 108system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 109system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 110system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 111system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 117system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 125system.cpu0.dtb.walker.walks 7967 # Table walker walks requested 126system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors 127system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency 128system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency 129system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency 130system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 131system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 132system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 133system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated 134system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated 135system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated 136system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst 137system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst 139system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst 140system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 141system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst 142system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst |
|
| 117system.cpu0.dtb.inst_hits 0 # ITB inst hits 118system.cpu0.dtb.inst_misses 0 # ITB inst misses 119system.cpu0.dtb.read_hits 20339962 # DTB read hits 120system.cpu0.dtb.read_misses 6874 # DTB read misses 121system.cpu0.dtb.write_hits 16391171 # DTB write hits 122system.cpu0.dtb.write_misses 1093 # DTB write misses 123system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 124system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 130system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 131system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 132system.cpu0.dtb.read_accesses 20346836 # DTB read accesses 133system.cpu0.dtb.write_accesses 16392264 # DTB write accesses 134system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 135system.cpu0.dtb.hits 36731133 # DTB hits 136system.cpu0.dtb.misses 7967 # DTB misses 137system.cpu0.dtb.accesses 36739100 # DTB accesses | 143system.cpu0.dtb.inst_hits 0 # ITB inst hits 144system.cpu0.dtb.inst_misses 0 # ITB inst misses 145system.cpu0.dtb.read_hits 20339962 # DTB read hits 146system.cpu0.dtb.read_misses 6874 # DTB read misses 147system.cpu0.dtb.write_hits 16391171 # DTB write hits 148system.cpu0.dtb.write_misses 1093 # DTB write misses 149system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 150system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 156system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 157system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 158system.cpu0.dtb.read_accesses 20346836 # DTB read accesses 159system.cpu0.dtb.write_accesses 16392264 # DTB write accesses 160system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 161system.cpu0.dtb.hits 36731133 # DTB hits 162system.cpu0.dtb.misses 7967 # DTB misses 163system.cpu0.dtb.accesses 36739100 # DTB accesses |
| 164system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 165system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 166system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 167system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 168system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 169system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 170system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 171system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 138system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 139system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 140system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 141system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 142system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 143system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 144system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 145system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 151system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 152system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 153system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 154system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 155system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 156system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 157system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 158system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 172system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 173system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 174system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 175system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 176system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 177system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 178system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 179system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 185system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 186system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 187system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 188system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 189system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 190system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 191system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 192system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 193system.cpu0.itb.walker.walks 3358 # Table walker walks requested 194system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 195system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 196system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 197system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 198system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 199system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 200system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 201system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 202system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 203system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 204system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 205system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 206system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 207system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 208system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 209system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 210system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst |
|
| 159system.cpu0.itb.inst_hits 97440315 # ITB inst hits 160system.cpu0.itb.inst_misses 3358 # ITB inst misses 161system.cpu0.itb.read_hits 0 # DTB read hits 162system.cpu0.itb.read_misses 0 # DTB read misses 163system.cpu0.itb.write_hits 0 # DTB write hits 164system.cpu0.itb.write_misses 0 # DTB write misses 165system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 166system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 199 unchanged lines hidden (view full) --- 366system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 367system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 368system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 369system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 370system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 371system.cpu0.icache.fast_writes 0 # number of fast writes performed 372system.cpu0.icache.cache_copies 0 # number of cache copies performed 373system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 211system.cpu0.itb.inst_hits 97440315 # ITB inst hits 212system.cpu0.itb.inst_misses 3358 # ITB inst misses 213system.cpu0.itb.read_hits 0 # DTB read hits 214system.cpu0.itb.read_misses 0 # DTB read misses 215system.cpu0.itb.write_hits 0 # DTB write hits 216system.cpu0.itb.write_misses 0 # DTB write misses 217system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 218system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 199 unchanged lines hidden (view full) --- 418system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 419system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 420system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 421system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 422system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 423system.cpu0.icache.fast_writes 0 # number of fast writes performed 424system.cpu0.icache.cache_copies 0 # number of cache copies performed 425system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 374system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 375system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 376system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 377system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 378system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 379system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 380system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 381system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 382system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 426system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 427system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 428system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 429system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 430system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 431system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 383system.cpu0.l2cache.tags.replacements 252403 # number of replacements 384system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use 385system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. 386system.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks. 387system.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks. 388system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. 389system.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor 390system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor --- 148 unchanged lines hidden (view full) --- 539system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 540system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 541system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram 542system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram 543system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 544system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 545system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 546system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram | 432system.cpu0.l2cache.tags.replacements 252403 # number of replacements 433system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use 434system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. 435system.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks. 436system.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks. 437system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. 438system.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor 439system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor --- 148 unchanged lines hidden (view full) --- 588system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 589system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 590system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram 591system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram 592system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 593system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 594system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 595system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram |
| 596system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 597system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 598system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 599system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 600system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 601system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 602system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 603system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 547system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 548system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 549system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 550system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 551system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 552system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 553system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 554system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 560system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 561system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 562system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 563system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 564system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 565system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 566system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 567system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 604system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 605system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 606system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 607system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 608system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 609system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 610system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 611system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 617system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 618system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 619system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 620system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 621system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 622system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 623system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 624system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 625system.cpu1.dtb.walker.walks 3358 # Table walker walks requested 626system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 627system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 628system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 629system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 630system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 631system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 632system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 633system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated 634system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated 635system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated 636system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst 637system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 638system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 639system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst 640system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 641system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst 642system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst |
|
| 568system.cpu1.dtb.inst_hits 0 # ITB inst hits 569system.cpu1.dtb.inst_misses 0 # ITB inst misses 570system.cpu1.dtb.read_hits 12173884 # DTB read hits 571system.cpu1.dtb.read_misses 2852 # DTB read misses 572system.cpu1.dtb.write_hits 7587193 # DTB write hits 573system.cpu1.dtb.write_misses 506 # DTB write misses 574system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 575system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 581system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 582system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 583system.cpu1.dtb.read_accesses 12176736 # DTB read accesses 584system.cpu1.dtb.write_accesses 7587699 # DTB write accesses 585system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 586system.cpu1.dtb.hits 19761077 # DTB hits 587system.cpu1.dtb.misses 3358 # DTB misses 588system.cpu1.dtb.accesses 19764435 # DTB accesses | 643system.cpu1.dtb.inst_hits 0 # ITB inst hits 644system.cpu1.dtb.inst_misses 0 # ITB inst misses 645system.cpu1.dtb.read_hits 12173884 # DTB read hits 646system.cpu1.dtb.read_misses 2852 # DTB read misses 647system.cpu1.dtb.write_hits 7587193 # DTB write hits 648system.cpu1.dtb.write_misses 506 # DTB write misses 649system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 650system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 656system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 657system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 658system.cpu1.dtb.read_accesses 12176736 # DTB read accesses 659system.cpu1.dtb.write_accesses 7587699 # DTB write accesses 660system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 661system.cpu1.dtb.hits 19761077 # DTB hits 662system.cpu1.dtb.misses 3358 # DTB misses 663system.cpu1.dtb.accesses 19764435 # DTB accesses |
| 664system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 665system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 666system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 667system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 668system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 669system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 670system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 671system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 589system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 590system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 591system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 592system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 593system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 594system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 595system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 596system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 602system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 603system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 604system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 605system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 606system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 607system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 608system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 609system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 672system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 673system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 674system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 675system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 676system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 677system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 678system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 679system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 685system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 686system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 687system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 688system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 689system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 690system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 691system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 692system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 693system.cpu1.itb.walker.walks 1734 # Table walker walks requested 694system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 695system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 696system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 697system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 698system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 699system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 700system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 701system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 702system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 703system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 704system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 705system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 706system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 707system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 708system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 709system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 710system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst |
|
| 610system.cpu1.itb.inst_hits 53671431 # ITB inst hits 611system.cpu1.itb.inst_misses 1734 # ITB inst misses 612system.cpu1.itb.read_hits 0 # DTB read hits 613system.cpu1.itb.read_misses 0 # DTB read misses 614system.cpu1.itb.write_hits 0 # DTB write hits 615system.cpu1.itb.write_misses 0 # DTB write misses 616system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 617system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 197 unchanged lines hidden (view full) --- 815system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 816system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 817system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 818system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 819system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 820system.cpu1.icache.fast_writes 0 # number of fast writes performed 821system.cpu1.icache.cache_copies 0 # number of cache copies performed 822system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 711system.cpu1.itb.inst_hits 53671431 # ITB inst hits 712system.cpu1.itb.inst_misses 1734 # ITB inst misses 713system.cpu1.itb.read_hits 0 # DTB read hits 714system.cpu1.itb.read_misses 0 # DTB read misses 715system.cpu1.itb.write_hits 0 # DTB write hits 716system.cpu1.itb.write_misses 0 # DTB write misses 717system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 718system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA --- 197 unchanged lines hidden (view full) --- 916system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 917system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 918system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 919system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 920system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 921system.cpu1.icache.fast_writes 0 # number of fast writes performed 922system.cpu1.icache.cache_copies 0 # number of cache copies performed 923system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 823system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 824system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 825system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 826system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 827system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 828system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 829system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 830system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 831system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 924system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 925system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 926system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 927system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 928system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 929system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 832system.cpu1.l2cache.tags.replacements 48598 # number of replacements 833system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use 834system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. 835system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks. 836system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks. 837system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 838system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor 839system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor --- 547 unchanged lines hidden --- | 930system.cpu1.l2cache.tags.replacements 48598 # number of replacements 931system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use 932system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. 933system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks. 934system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks. 935system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 936system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor 937system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor --- 547 unchanged lines hidden --- |