| stats.txt (10535:4ccec5baf82c) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882634000 # Number of ticks simulated 5final_tick 2802882634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.802895 # Number of seconds simulated 4sim_ticks 2802895103500 # Number of ticks simulated 5final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1078207 # Simulator instruction rate (inst/s) 8host_op_rate 1313778 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20582448891 # Simulator tick rate (ticks/s) 10host_mem_usage 574132 # Number of bytes of host memory used 11host_seconds 136.18 # Real time elapsed on the host 12sim_insts 146828350 # Number of instructions simulated 13sim_ops 178908035 # Number of ops (including micro ops) simulated | 7host_inst_rate 967895 # Simulator instruction rate (inst/s) 8host_op_rate 1179365 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18476638236 # Simulator tick rate (ticks/s) 10host_mem_usage 571628 # Number of bytes of host memory used 11host_seconds 151.70 # Real time elapsed on the host 12sim_insts 146829031 # Number of instructions simulated 13sim_ops 178908942 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu0.inst 1117092 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9456444 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory | 20system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::cpu1.inst 151956 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 1081888 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu1.inst 152404 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 1082016 # Number of bytes read from this memory |
| 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 24system.physmem.bytes_read::total 11809044 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 1117092 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 151956 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 1269048 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 6071744 # Number of bytes written to this memory | 24system.physmem.bytes_read::total 11794004 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 1117540 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 152404 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 1269944 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 8387200 # Number of bytes written to this memory |
| 29system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 29system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 31system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 32system.physmem.bytes_written::total 8407824 # Number of bytes written to this memory | 31system.physmem.bytes_written::total 8404944 # Number of bytes written to this memory |
| 33system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 32system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 35system.physmem.num_reads::cpu0.inst 25908 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.data 148282 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu0.inst 25915 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 148031 # Number of read requests responded to by this memory |
| 37system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory |
| 38system.physmem.num_reads::cpu1.inst 2529 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.data 16928 # Number of read requests responded to by this memory | 37system.physmem.num_reads::cpu1.inst 2536 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu1.data 16930 # Number of read requests responded to by this memory |
| 40system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 39system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 41system.physmem.num_reads::total 193673 # Number of read requests responded to by this memory 42system.physmem.num_writes::writebacks 94871 # Number of write requests responded to by this memory | 40system.physmem.num_reads::total 193438 # Number of read requests responded to by this memory 41system.physmem.num_writes::writebacks 131050 # Number of write requests responded to by this memory |
| 43system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 42system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 43system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 45system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 46system.physmem.num_writes::total 135531 # Number of write requests responded to by this memory | 44system.physmem.num_writes::total 135486 # Number of write requests responded to by this memory |
| 47system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) | 45system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) |
| 49system.physmem.bw_read::cpu0.inst 398551 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.data 3373828 # Total read bandwidth from this memory (bytes/s) | 47system.physmem.bw_read::cpu0.inst 398709 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu0.data 3368082 # Total read bandwidth from this memory (bytes/s) |
| 51system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) | 49system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) |
| 52system.physmem.bw_read::cpu1.inst 54214 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu1.data 385991 # Total read bandwidth from this memory (bytes/s) | 50system.physmem.bw_read::cpu1.inst 54374 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu1.data 386035 # Total read bandwidth from this memory (bytes/s) |
| 54system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) | 52system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) |
| 55system.physmem.bw_read::total 4213178 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu0.inst 398551 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu1.inst 54214 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::total 452765 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_write::writebacks 2166250 # Write bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::total 4207794 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::cpu0.inst 398709 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_inst_read::cpu1.inst 54374 # Instruction read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::total 453083 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_write::writebacks 2992335 # Write bandwidth from this memory (bytes/s) |
| 60system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 58system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 62system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) 63system.physmem.bw_write::total 2999706 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2166250 # Total bandwidth to/from this memory (bytes/s) | 60system.physmem.bw_write::total 2998665 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_total::writebacks 2992335 # Total bandwidth to/from this memory (bytes/s) |
| 65system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) | 62system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) |
| 67system.physmem.bw_total::cpu0.inst 398551 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.data 3380144 # Total bandwidth to/from this memory (bytes/s) | 64system.physmem.bw_total::cpu0.inst 398709 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu0.data 3374398 # Total bandwidth to/from this memory (bytes/s) |
| 69system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) | 66system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) |
| 70system.physmem.bw_total::cpu1.inst 54214 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu1.data 386005 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::total 7212884 # Total bandwidth to/from this memory (bytes/s) | 67system.physmem.bw_total::cpu1.inst 54374 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu1.data 386049 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::total 7206459 # Total bandwidth to/from this memory (bytes/s) |
| 74system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 75system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 77system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 78system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 79system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 80system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 81system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory --- 32 unchanged lines hidden (view full) --- 114system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 120system.cpu0.dtb.inst_hits 0 # ITB inst hits 121system.cpu0.dtb.inst_misses 0 # ITB inst misses | 71system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 72system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 73system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 74system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 75system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 76system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 77system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 78system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory --- 32 unchanged lines hidden (view full) --- 111system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 112system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 113system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 114system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 115system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 116system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 117system.cpu0.dtb.inst_hits 0 # ITB inst hits 118system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 122system.cpu0.dtb.read_hits 20339775 # DTB read hits 123system.cpu0.dtb.read_misses 6871 # DTB read misses 124system.cpu0.dtb.write_hits 16390998 # DTB write hits | 119system.cpu0.dtb.read_hits 20339962 # DTB read hits 120system.cpu0.dtb.read_misses 6874 # DTB read misses 121system.cpu0.dtb.write_hits 16391171 # DTB write hits |
| 125system.cpu0.dtb.write_misses 1093 # DTB write misses 126system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 127system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 128system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 129system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 130system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 131system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 132system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 133system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 134system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions | 122system.cpu0.dtb.write_misses 1093 # DTB write misses 123system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 124system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 125system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 126system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 127system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 128system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 129system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 130system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 131system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions |
| 135system.cpu0.dtb.read_accesses 20346646 # DTB read accesses 136system.cpu0.dtb.write_accesses 16392091 # DTB write accesses | 132system.cpu0.dtb.read_accesses 20346836 # DTB read accesses 133system.cpu0.dtb.write_accesses 16392264 # DTB write accesses |
| 137system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 134system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 138system.cpu0.dtb.hits 36730773 # DTB hits 139system.cpu0.dtb.misses 7964 # DTB misses 140system.cpu0.dtb.accesses 36738737 # DTB accesses | 135system.cpu0.dtb.hits 36731133 # DTB hits 136system.cpu0.dtb.misses 7967 # DTB misses 137system.cpu0.dtb.accesses 36739100 # DTB accesses |
| 141system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 142system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 143system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 144system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 145system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 146system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 147system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 148system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 154system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 155system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 157system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 158system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 159system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 160system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 161system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 138system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 139system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 140system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 141system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 142system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 143system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 144system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 145system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 151system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 152system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 153system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 154system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 155system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 156system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 157system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 158system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 162system.cpu0.itb.inst_hits 97439484 # ITB inst hits | 159system.cpu0.itb.inst_hits 97440315 # ITB inst hits |
| 163system.cpu0.itb.inst_misses 3358 # ITB inst misses 164system.cpu0.itb.read_hits 0 # DTB read hits 165system.cpu0.itb.read_misses 0 # DTB read misses 166system.cpu0.itb.write_hits 0 # DTB write hits 167system.cpu0.itb.write_misses 0 # DTB write misses 168system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 169system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 170system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 171system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 172system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 173system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 174system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 175system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 176system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 177system.cpu0.itb.read_accesses 0 # DTB read accesses 178system.cpu0.itb.write_accesses 0 # DTB write accesses | 160system.cpu0.itb.inst_misses 3358 # ITB inst misses 161system.cpu0.itb.read_hits 0 # DTB read hits 162system.cpu0.itb.read_misses 0 # DTB read misses 163system.cpu0.itb.write_hits 0 # DTB write hits 164system.cpu0.itb.write_misses 0 # DTB write misses 165system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 166system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 167system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 168system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 169system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 170system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 171system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 172system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 173system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 174system.cpu0.itb.read_accesses 0 # DTB read accesses 175system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 179system.cpu0.itb.inst_accesses 97442842 # ITB inst accesses 180system.cpu0.itb.hits 97439484 # DTB hits | 176system.cpu0.itb.inst_accesses 97443673 # ITB inst accesses 177system.cpu0.itb.hits 97440315 # DTB hits |
| 181system.cpu0.itb.misses 3358 # DTB misses | 178system.cpu0.itb.misses 3358 # DTB misses |
| 182system.cpu0.itb.accesses 97442842 # DTB accesses 183system.cpu0.numCycles 5605767234 # number of cpu cycles simulated | 179system.cpu0.itb.accesses 97443673 # DTB accesses 180system.cpu0.numCycles 5605792176 # number of cpu cycles simulated |
| 184system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 185system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 181system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 182system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 186system.cpu0.committedInsts 95427026 # Number of instructions committed 187system.cpu0.committedOps 115560441 # Number of ops (including micro ops) committed 188system.cpu0.num_int_alu_accesses 100762684 # Number of integer alu accesses | 183system.cpu0.committedInsts 95427853 # Number of instructions committed 184system.cpu0.committedOps 115561498 # Number of ops (including micro ops) committed 185system.cpu0.num_int_alu_accesses 100763618 # Number of integer alu accesses |
| 189system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses | 186system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses |
| 190system.cpu0.num_func_calls 8000257 # number of times a function call or return occured 191system.cpu0.num_conditional_control_insts 13204260 # number of instructions that are conditional controls 192system.cpu0.num_int_insts 100762684 # number of integer instructions | 187system.cpu0.num_func_calls 8000324 # number of times a function call or return occured 188system.cpu0.num_conditional_control_insts 13204344 # number of instructions that are conditional controls 189system.cpu0.num_int_insts 100763618 # number of integer instructions |
| 193system.cpu0.num_fp_insts 9755 # number of float instructions | 190system.cpu0.num_fp_insts 9755 # number of float instructions |
| 194system.cpu0.num_int_register_reads 182457418 # number of times the integer registers were read 195system.cpu0.num_int_register_writes 69135520 # number of times the integer registers were written | 191system.cpu0.num_int_register_reads 182459108 # number of times the integer registers were read 192system.cpu0.num_int_register_writes 69136203 # number of times the integer registers were written |
| 196system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 197system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written | 193system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 194system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written |
| 198system.cpu0.num_cc_register_reads 349971578 # number of times the CC registers were read 199system.cpu0.num_cc_register_writes 44907537 # number of times the CC registers were written 200system.cpu0.num_mem_refs 37873766 # number of memory refs 201system.cpu0.num_load_insts 20597356 # Number of load instructions 202system.cpu0.num_store_insts 17276410 # Number of store instructions 203system.cpu0.num_idle_cycles 5488182675.223932 # Number of idle cycles 204system.cpu0.num_busy_cycles 117584558.776067 # Number of busy cycles | 195system.cpu0.num_cc_register_reads 349974767 # number of times the CC registers were read 196system.cpu0.num_cc_register_writes 44907843 # number of times the CC registers were written 197system.cpu0.num_mem_refs 37874145 # number of memory refs 198system.cpu0.num_load_insts 20597552 # Number of load instructions 199system.cpu0.num_store_insts 17276593 # Number of store instructions 200system.cpu0.num_idle_cycles 5488206556.246817 # Number of idle cycles 201system.cpu0.num_busy_cycles 117585619.753183 # Number of busy cycles |
| 205system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 206system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles | 202system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 203system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles |
| 207system.cpu0.Branches 21941641 # Number of branches fetched | 204system.cpu0.Branches 21941792 # Number of branches fetched |
| 208system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction | 205system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction |
| 209system.cpu0.op_class::IntAlu 78887374 67.49% 67.50% # Class of executed instruction 210system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction | 206system.cpu0.op_class::IntAlu 78888049 67.49% 67.50% # Class of executed instruction 207system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction |
| 211system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 212system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 213system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 214system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 215system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 216system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 217system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 218system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 230system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 231system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 232system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 233system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 234system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 235system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 236system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 237system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction | 208system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 209system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 210system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 211system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 212system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 213system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 214system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 215system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 227system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 228system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 229system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 230system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 231system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 232system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 233system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 234system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction |
| 238system.cpu0.op_class::MemRead 20597356 17.62% 85.22% # Class of executed instruction 239system.cpu0.op_class::MemWrite 17276410 14.78% 100.00% # Class of executed instruction | 235system.cpu0.op_class::MemRead 20597552 17.62% 85.22% # Class of executed instruction 236system.cpu0.op_class::MemWrite 17276593 14.78% 100.00% # Class of executed instruction |
| 240system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 241system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 237system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 238system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 242system.cpu0.op_class::total 116882135 # Class of executed instruction | 239system.cpu0.op_class::total 116883193 # Class of executed instruction |
| 243system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 240system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 244system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed 245system.cpu0.dcache.tags.replacements 693468 # number of replacements 246system.cpu0.dcache.tags.tagsinuse 494.853471 # Cycle average of tags in use 247system.cpu0.dcache.tags.total_refs 35932329 # Total number of references to valid blocks. 248system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. 249system.cpu0.dcache.tags.avg_refs 51.777182 # Average number of references to valid blocks. | 241system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed 242system.cpu0.dcache.tags.replacements 693476 # number of replacements 243system.cpu0.dcache.tags.tagsinuse 494.853661 # Cycle average of tags in use 244system.cpu0.dcache.tags.total_refs 35932684 # Total number of references to valid blocks. 245system.cpu0.dcache.tags.sampled_refs 693988 # Sample count of references to valid blocks. 246system.cpu0.dcache.tags.avg_refs 51.777097 # Average number of references to valid blocks. |
| 250system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. | 247system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. |
| 251system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853471 # Average occupied blocks per requestor | 248system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853661 # Average occupied blocks per requestor |
| 252system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 253system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 254system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 255system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 256system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 257system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 258system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 249system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 250system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 251system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 252system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 253system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 254system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 255system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 259system.cpu0.dcache.tags.tag_accesses 74113668 # Number of tag accesses 260system.cpu0.dcache.tags.data_accesses 74113668 # Number of data accesses 261system.cpu0.dcache.ReadReq_hits::cpu0.data 19108613 # number of ReadReq hits 262system.cpu0.dcache.ReadReq_hits::total 19108613 # number of ReadReq hits 263system.cpu0.dcache.WriteReq_hits::cpu0.data 15690292 # number of WriteReq hits 264system.cpu0.dcache.WriteReq_hits::total 15690292 # number of WriteReq hits 265system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits 266system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits 267system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits 268system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits 269system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363025 # number of StoreCondReq hits 270system.cpu0.dcache.StoreCondReq_hits::total 363025 # number of StoreCondReq hits 271system.cpu0.dcache.demand_hits::cpu0.data 34798905 # number of demand (read+write) hits 272system.cpu0.dcache.demand_hits::total 34798905 # number of demand (read+write) hits 273system.cpu0.dcache.overall_hits::cpu0.data 35144985 # number of overall hits 274system.cpu0.dcache.overall_hits::total 35144985 # number of overall hits 275system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses 276system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses 277system.cpu0.dcache.WriteReq_misses::cpu0.data 295766 # number of WriteReq misses 278system.cpu0.dcache.WriteReq_misses::total 295766 # number of WriteReq misses 279system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses 280system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses 281system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 282system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 283system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18448 # number of StoreCondReq misses 284system.cpu0.dcache.StoreCondReq_misses::total 18448 # number of StoreCondReq misses 285system.cpu0.dcache.demand_misses::cpu0.data 668860 # number of demand (read+write) misses 286system.cpu0.dcache.demand_misses::total 668860 # number of demand (read+write) misses 287system.cpu0.dcache.overall_misses::cpu0.data 769182 # number of overall misses 288system.cpu0.dcache.overall_misses::total 769182 # number of overall misses 289system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481707 # number of ReadReq accesses(hits+misses) 290system.cpu0.dcache.ReadReq_accesses::total 19481707 # number of ReadReq accesses(hits+misses) 291system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986058 # number of WriteReq accesses(hits+misses) 292system.cpu0.dcache.WriteReq_accesses::total 15986058 # number of WriteReq accesses(hits+misses) 293system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) 294system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) 295system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) 296system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) 297system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) 298system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) 299system.cpu0.dcache.demand_accesses::cpu0.data 35467765 # number of demand (read+write) accesses 300system.cpu0.dcache.demand_accesses::total 35467765 # number of demand (read+write) accesses 301system.cpu0.dcache.overall_accesses::cpu0.data 35914167 # number of overall (read+write) accesses 302system.cpu0.dcache.overall_accesses::total 35914167 # number of overall (read+write) accesses | 256system.cpu0.dcache.tags.tag_accesses 74114402 # Number of tag accesses 257system.cpu0.dcache.tags.data_accesses 74114402 # Number of data accesses 258system.cpu0.dcache.ReadReq_hits::cpu0.data 19108775 # number of ReadReq hits 259system.cpu0.dcache.ReadReq_hits::total 19108775 # number of ReadReq hits 260system.cpu0.dcache.WriteReq_hits::cpu0.data 15690454 # number of WriteReq hits 261system.cpu0.dcache.WriteReq_hits::total 15690454 # number of WriteReq hits 262system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits 263system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits 264system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits 265system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits 266system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363052 # number of StoreCondReq hits 267system.cpu0.dcache.StoreCondReq_hits::total 363052 # number of StoreCondReq hits 268system.cpu0.dcache.demand_hits::cpu0.data 34799229 # number of demand (read+write) hits 269system.cpu0.dcache.demand_hits::total 34799229 # number of demand (read+write) hits 270system.cpu0.dcache.overall_hits::cpu0.data 35145322 # number of overall hits 271system.cpu0.dcache.overall_hits::total 35145322 # number of overall hits 272system.cpu0.dcache.ReadReq_misses::cpu0.data 373098 # number of ReadReq misses 273system.cpu0.dcache.ReadReq_misses::total 373098 # number of ReadReq misses 274system.cpu0.dcache.WriteReq_misses::cpu0.data 295765 # number of WriteReq misses 275system.cpu0.dcache.WriteReq_misses::total 295765 # number of WriteReq misses 276system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 277system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 278system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 279system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 280system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18433 # number of StoreCondReq misses 281system.cpu0.dcache.StoreCondReq_misses::total 18433 # number of StoreCondReq misses 282system.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses 283system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses 284system.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses 285system.cpu0.dcache.overall_misses::total 769184 # number of overall misses 286system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481873 # number of ReadReq accesses(hits+misses) 287system.cpu0.dcache.ReadReq_accesses::total 19481873 # number of ReadReq accesses(hits+misses) 288system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986219 # number of WriteReq accesses(hits+misses) 289system.cpu0.dcache.WriteReq_accesses::total 15986219 # number of WriteReq accesses(hits+misses) 290system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) 291system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) 292system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) 293system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) 294system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) 295system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) 296system.cpu0.dcache.demand_accesses::cpu0.data 35468092 # number of demand (read+write) accesses 297system.cpu0.dcache.demand_accesses::total 35468092 # number of demand (read+write) accesses 298system.cpu0.dcache.overall_accesses::cpu0.data 35914506 # number of overall (read+write) accesses 299system.cpu0.dcache.overall_accesses::total 35914506 # number of overall (read+write) accesses |
| 303system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 304system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 305system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses 306system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses | 300system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 301system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 302system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses 303system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses |
| 307system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses 308system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses 309system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 310system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses 311system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048360 # miss rate for StoreCondReq accesses 312system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048360 # miss rate for StoreCondReq accesses | 304system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses 305system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses 306system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses 307system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses 308system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048319 # miss rate for StoreCondReq accesses 309system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048319 # miss rate for StoreCondReq accesses |
| 313system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses 314system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses 315system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses 316system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses 317system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 318system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 319system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 320system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 321system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 322system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 323system.cpu0.dcache.fast_writes 0 # number of fast writes performed 324system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 310system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses 311system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses 312system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses 313system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses 314system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 315system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 316system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 317system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 318system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 319system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 320system.cpu0.dcache.fast_writes 0 # number of fast writes performed 321system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 325system.cpu0.dcache.writebacks::writebacks 511566 # number of writebacks 326system.cpu0.dcache.writebacks::total 511566 # number of writebacks | 322system.cpu0.dcache.writebacks::writebacks 511648 # number of writebacks 323system.cpu0.dcache.writebacks::total 511648 # number of writebacks |
| 327system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 324system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 328system.cpu0.icache.tags.replacements 1109631 # number of replacements 329system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 330system.cpu0.icache.tags.total_refs 96331674 # Total number of references to valid blocks. 331system.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. 332system.cpu0.icache.tags.avg_refs 86.774113 # Average number of references to valid blocks. | 325system.cpu0.icache.tags.replacements 1109742 # number of replacements 326system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use 327system.cpu0.icache.tags.total_refs 96332394 # Total number of references to valid blocks. 328system.cpu0.icache.tags.sampled_refs 1110254 # Sample count of references to valid blocks. 329system.cpu0.icache.tags.avg_refs 86.766086 # Average number of references to valid blocks. |
| 333system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. | 330system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. |
| 334system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor | 331system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor |
| 335system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 336system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 337system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 338system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 339system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 340system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 341system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 332system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 333system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 334system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 335system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 336system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 337system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 338system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 342system.cpu0.icache.tags.tag_accesses 195993804 # Number of tag accesses 343system.cpu0.icache.tags.data_accesses 195993804 # Number of data accesses 344system.cpu0.icache.ReadReq_hits::cpu0.inst 96331674 # number of ReadReq hits 345system.cpu0.icache.ReadReq_hits::total 96331674 # number of ReadReq hits 346system.cpu0.icache.demand_hits::cpu0.inst 96331674 # number of demand (read+write) hits 347system.cpu0.icache.demand_hits::total 96331674 # number of demand (read+write) hits 348system.cpu0.icache.overall_hits::cpu0.inst 96331674 # number of overall hits 349system.cpu0.icache.overall_hits::total 96331674 # number of overall hits 350system.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses 351system.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses 352system.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses 353system.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses 354system.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses 355system.cpu0.icache.overall_misses::total 1110152 # number of overall misses 356system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441826 # number of ReadReq accesses(hits+misses) 357system.cpu0.icache.ReadReq_accesses::total 97441826 # number of ReadReq accesses(hits+misses) 358system.cpu0.icache.demand_accesses::cpu0.inst 97441826 # number of demand (read+write) accesses 359system.cpu0.icache.demand_accesses::total 97441826 # number of demand (read+write) accesses 360system.cpu0.icache.overall_accesses::cpu0.inst 97441826 # number of overall (read+write) accesses 361system.cpu0.icache.overall_accesses::total 97441826 # number of overall (read+write) accesses 362system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses 363system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses 364system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses 365system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses 366system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 367system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses | 339system.cpu0.icache.tags.tag_accesses 195995577 # Number of tag accesses 340system.cpu0.icache.tags.data_accesses 195995577 # Number of data accesses 341system.cpu0.icache.ReadReq_hits::cpu0.inst 96332394 # number of ReadReq hits 342system.cpu0.icache.ReadReq_hits::total 96332394 # number of ReadReq hits 343system.cpu0.icache.demand_hits::cpu0.inst 96332394 # number of demand (read+write) hits 344system.cpu0.icache.demand_hits::total 96332394 # number of demand (read+write) hits 345system.cpu0.icache.overall_hits::cpu0.inst 96332394 # number of overall hits 346system.cpu0.icache.overall_hits::total 96332394 # number of overall hits 347system.cpu0.icache.ReadReq_misses::cpu0.inst 1110263 # number of ReadReq misses 348system.cpu0.icache.ReadReq_misses::total 1110263 # number of ReadReq misses 349system.cpu0.icache.demand_misses::cpu0.inst 1110263 # number of demand (read+write) misses 350system.cpu0.icache.demand_misses::total 1110263 # number of demand (read+write) misses 351system.cpu0.icache.overall_misses::cpu0.inst 1110263 # number of overall misses 352system.cpu0.icache.overall_misses::total 1110263 # number of overall misses 353system.cpu0.icache.ReadReq_accesses::cpu0.inst 97442657 # number of ReadReq accesses(hits+misses) 354system.cpu0.icache.ReadReq_accesses::total 97442657 # number of ReadReq accesses(hits+misses) 355system.cpu0.icache.demand_accesses::cpu0.inst 97442657 # number of demand (read+write) accesses 356system.cpu0.icache.demand_accesses::total 97442657 # number of demand (read+write) accesses 357system.cpu0.icache.overall_accesses::cpu0.inst 97442657 # number of overall (read+write) accesses 358system.cpu0.icache.overall_accesses::total 97442657 # number of overall (read+write) accesses 359system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses 360system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses 361system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses 362system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses 363system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses 364system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses |
| 368system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 369system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 370system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 371system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 372system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 373system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 374system.cpu0.icache.fast_writes 0 # number of fast writes performed 375system.cpu0.icache.cache_copies 0 # number of cache copies performed 376system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 377system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 378system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 379system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 380system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 381system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 382system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 383system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 384system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 385system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 365system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 366system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 367system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 368system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 369system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 370system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 371system.cpu0.icache.fast_writes 0 # number of fast writes performed 372system.cpu0.icache.cache_copies 0 # number of cache copies performed 373system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 374system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 375system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 376system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 377system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 378system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 379system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 380system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 381system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 382system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 386system.cpu0.l2cache.tags.replacements 252467 # number of replacements 387system.cpu0.l2cache.tags.tagsinuse 16137.499100 # Cycle average of tags in use 388system.cpu0.l2cache.tags.total_refs 1809671 # Total number of references to valid blocks. 389system.cpu0.l2cache.tags.sampled_refs 268655 # Sample count of references to valid blocks. 390system.cpu0.l2cache.tags.avg_refs 6.736041 # Average number of references to valid blocks. | 383system.cpu0.l2cache.tags.replacements 252403 # number of replacements 384system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use 385system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. 386system.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks. 387system.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks. |
| 391system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. | 388system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. |
| 392system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.791544 # Average occupied blocks per requestor 393system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.201142 # Average occupied blocks per requestor 394system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081297 # Average occupied blocks per requestor 395system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.858530 # Average occupied blocks per requestor 396system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.566587 # Average occupied blocks per requestor 397system.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy 398system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy | 389system.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor 390system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor 391system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.086115 # Average occupied blocks per requestor 392system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.591048 # Average occupied blocks per requestor 393system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.325333 # Average occupied blocks per requestor 394system.cpu0.l2cache.tags.occ_percent::writebacks 0.492437 # Average percentage of cache occupancy 395system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy |
| 399system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy | 396system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy |
| 400system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.291373 # Average percentage of cache occupancy 401system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201329 # Average percentage of cache occupancy 402system.cpu0.l2cache.tags.occ_percent::total 0.984955 # Average percentage of cache occupancy 403system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 404system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id 405system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 406system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 407system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 408system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 409system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id 410system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5647 # Occupied blocks per task id 411system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7609 # Occupied blocks per task id 412system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2581 # Occupied blocks per task id 413system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id 414system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id 415system.cpu0.l2cache.tags.tag_accesses 39448657 # Number of tag accesses 416system.cpu0.l2cache.tags.data_accesses 39448657 # Number of data accesses 417system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7673 # number of ReadReq hits 418system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3273 # number of ReadReq hits 419system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065177 # number of ReadReq hits 420system.cpu0.l2cache.ReadReq_hits::cpu0.data 351940 # number of ReadReq hits 421system.cpu0.l2cache.ReadReq_hits::total 1428063 # number of ReadReq hits 422system.cpu0.l2cache.Writeback_hits::writebacks 511566 # number of Writeback hits 423system.cpu0.l2cache.Writeback_hits::total 511566 # number of Writeback hits 424system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits 425system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 426system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94243 # number of ReadExReq hits 427system.cpu0.l2cache.ReadExReq_hits::total 94243 # number of ReadExReq hits 428system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7673 # number of demand (read+write) hits 429system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3273 # number of demand (read+write) hits 430system.cpu0.l2cache.demand_hits::cpu0.inst 1065177 # number of demand (read+write) hits 431system.cpu0.l2cache.demand_hits::cpu0.data 446183 # number of demand (read+write) hits 432system.cpu0.l2cache.demand_hits::total 1522306 # number of demand (read+write) hits 433system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7673 # number of overall hits 434system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3273 # number of overall hits 435system.cpu0.l2cache.overall_hits::cpu0.inst 1065177 # number of overall hits 436system.cpu0.l2cache.overall_hits::cpu0.data 446183 # number of overall hits 437system.cpu0.l2cache.overall_hits::total 1522306 # number of overall hits 438system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 211 # number of ReadReq misses 439system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses 440system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44975 # number of ReadReq misses 441system.cpu0.l2cache.ReadReq_misses::cpu0.data 128216 # number of ReadReq misses 442system.cpu0.l2cache.ReadReq_misses::total 173525 # number of ReadReq misses 443system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26236 # number of UpgradeReq misses 444system.cpu0.l2cache.UpgradeReq_misses::total 26236 # number of UpgradeReq misses 445system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18448 # number of SCUpgradeReq misses 446system.cpu0.l2cache.SCUpgradeReq_misses::total 18448 # number of SCUpgradeReq misses 447system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175271 # number of ReadExReq misses 448system.cpu0.l2cache.ReadExReq_misses::total 175271 # number of ReadExReq misses 449system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 211 # number of demand (read+write) misses 450system.cpu0.l2cache.demand_misses::cpu0.itb.walker 123 # number of demand (read+write) misses 451system.cpu0.l2cache.demand_misses::cpu0.inst 44975 # number of demand (read+write) misses 452system.cpu0.l2cache.demand_misses::cpu0.data 303487 # number of demand (read+write) misses 453system.cpu0.l2cache.demand_misses::total 348796 # number of demand (read+write) misses 454system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 211 # number of overall misses 455system.cpu0.l2cache.overall_misses::cpu0.itb.walker 123 # number of overall misses 456system.cpu0.l2cache.overall_misses::cpu0.inst 44975 # number of overall misses 457system.cpu0.l2cache.overall_misses::cpu0.data 303487 # number of overall misses 458system.cpu0.l2cache.overall_misses::total 348796 # number of overall misses 459system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7884 # number of ReadReq accesses(hits+misses) 460system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3396 # number of ReadReq accesses(hits+misses) 461system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110152 # number of ReadReq accesses(hits+misses) 462system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480156 # number of ReadReq accesses(hits+misses) 463system.cpu0.l2cache.ReadReq_accesses::total 1601588 # number of ReadReq accesses(hits+misses) 464system.cpu0.l2cache.Writeback_accesses::writebacks 511566 # number of Writeback accesses(hits+misses) 465system.cpu0.l2cache.Writeback_accesses::total 511566 # number of Writeback accesses(hits+misses) 466system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26252 # number of UpgradeReq accesses(hits+misses) 467system.cpu0.l2cache.UpgradeReq_accesses::total 26252 # number of UpgradeReq accesses(hits+misses) 468system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18448 # number of SCUpgradeReq accesses(hits+misses) 469system.cpu0.l2cache.SCUpgradeReq_accesses::total 18448 # number of SCUpgradeReq accesses(hits+misses) 470system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) 471system.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) 472system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7884 # number of demand (read+write) accesses 473system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3396 # number of demand (read+write) accesses 474system.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses 475system.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses 476system.cpu0.l2cache.demand_accesses::total 1871102 # number of demand (read+write) accesses 477system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7884 # number of overall (read+write) accesses 478system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3396 # number of overall (read+write) accesses 479system.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses 480system.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses 481system.cpu0.l2cache.overall_accesses::total 1871102 # number of overall (read+write) accesses 482system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for ReadReq accesses 483system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.036219 # miss rate for ReadReq accesses 484system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040512 # miss rate for ReadReq accesses 485system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267030 # miss rate for ReadReq accesses 486system.cpu0.l2cache.ReadReq_miss_rate::total 0.108346 # miss rate for ReadReq accesses 487system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999391 # miss rate for UpgradeReq accesses 488system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999391 # miss rate for UpgradeReq accesses | 397system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289831 # Average percentage of cache occupancy 398system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201985 # Average percentage of cache occupancy 399system.cpu0.l2cache.tags.occ_percent::total 0.984453 # Average percentage of cache occupancy 400system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id 401system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16192 # Occupied blocks per task id 402system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 403system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id 404system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 405system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 406system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id 407system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5587 # Occupied blocks per task id 408system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7674 # Occupied blocks per task id 409system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2571 # Occupied blocks per task id 410system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id 411system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id 412system.cpu0.l2cache.tags.tag_accesses 39450391 # Number of tag accesses 413system.cpu0.l2cache.tags.data_accesses 39450391 # Number of data accesses 414system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7605 # number of ReadReq hits 415system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3248 # number of ReadReq hits 416system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065251 # number of ReadReq hits 417system.cpu0.l2cache.ReadReq_hits::cpu0.data 352125 # number of ReadReq hits 418system.cpu0.l2cache.ReadReq_hits::total 1428229 # number of ReadReq hits 419system.cpu0.l2cache.Writeback_hits::writebacks 511648 # number of Writeback hits 420system.cpu0.l2cache.Writeback_hits::total 511648 # number of Writeback hits 421system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits 422system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits 423system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94130 # number of ReadExReq hits 424system.cpu0.l2cache.ReadExReq_hits::total 94130 # number of ReadExReq hits 425system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7605 # number of demand (read+write) hits 426system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3248 # number of demand (read+write) hits 427system.cpu0.l2cache.demand_hits::cpu0.inst 1065251 # number of demand (read+write) hits 428system.cpu0.l2cache.demand_hits::cpu0.data 446255 # number of demand (read+write) hits 429system.cpu0.l2cache.demand_hits::total 1522359 # number of demand (read+write) hits 430system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7605 # number of overall hits 431system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3248 # number of overall hits 432system.cpu0.l2cache.overall_hits::cpu0.inst 1065251 # number of overall hits 433system.cpu0.l2cache.overall_hits::cpu0.data 446255 # number of overall hits 434system.cpu0.l2cache.overall_hits::total 1522359 # number of overall hits 435system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses 436system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 134 # number of ReadReq misses 437system.cpu0.l2cache.ReadReq_misses::cpu0.inst 45012 # number of ReadReq misses 438system.cpu0.l2cache.ReadReq_misses::cpu0.data 128036 # number of ReadReq misses 439system.cpu0.l2cache.ReadReq_misses::total 173407 # number of ReadReq misses 440system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses 441system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses 442system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18433 # number of SCUpgradeReq misses 443system.cpu0.l2cache.SCUpgradeReq_misses::total 18433 # number of SCUpgradeReq misses 444system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175387 # number of ReadExReq misses 445system.cpu0.l2cache.ReadExReq_misses::total 175387 # number of ReadExReq misses 446system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses 447system.cpu0.l2cache.demand_misses::cpu0.itb.walker 134 # number of demand (read+write) misses 448system.cpu0.l2cache.demand_misses::cpu0.inst 45012 # number of demand (read+write) misses 449system.cpu0.l2cache.demand_misses::cpu0.data 303423 # number of demand (read+write) misses 450system.cpu0.l2cache.demand_misses::total 348794 # number of demand (read+write) misses 451system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses 452system.cpu0.l2cache.overall_misses::cpu0.itb.walker 134 # number of overall misses 453system.cpu0.l2cache.overall_misses::cpu0.inst 45012 # number of overall misses 454system.cpu0.l2cache.overall_misses::cpu0.data 303423 # number of overall misses 455system.cpu0.l2cache.overall_misses::total 348794 # number of overall misses 456system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7830 # number of ReadReq accesses(hits+misses) 457system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3382 # number of ReadReq accesses(hits+misses) 458system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110263 # number of ReadReq accesses(hits+misses) 459system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480161 # number of ReadReq accesses(hits+misses) 460system.cpu0.l2cache.ReadReq_accesses::total 1601636 # number of ReadReq accesses(hits+misses) 461system.cpu0.l2cache.Writeback_accesses::writebacks 511648 # number of Writeback accesses(hits+misses) 462system.cpu0.l2cache.Writeback_accesses::total 511648 # number of Writeback accesses(hits+misses) 463system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses) 464system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses) 465system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18433 # number of SCUpgradeReq accesses(hits+misses) 466system.cpu0.l2cache.SCUpgradeReq_accesses::total 18433 # number of SCUpgradeReq accesses(hits+misses) 467system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) 468system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) 469system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7830 # number of demand (read+write) accesses 470system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3382 # number of demand (read+write) accesses 471system.cpu0.l2cache.demand_accesses::cpu0.inst 1110263 # number of demand (read+write) accesses 472system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses 473system.cpu0.l2cache.demand_accesses::total 1871153 # number of demand (read+write) accesses 474system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7830 # number of overall (read+write) accesses 475system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3382 # number of overall (read+write) accesses 476system.cpu0.l2cache.overall_accesses::cpu0.inst 1110263 # number of overall (read+write) accesses 477system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses 478system.cpu0.l2cache.overall_accesses::total 1871153 # number of overall (read+write) accesses 479system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for ReadReq accesses 480system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039622 # miss rate for ReadReq accesses 481system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040542 # miss rate for ReadReq accesses 482system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266652 # miss rate for ReadReq accesses 483system.cpu0.l2cache.ReadReq_miss_rate::total 0.108269 # miss rate for ReadReq accesses 484system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses 485system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses |
| 489system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 490system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 486system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 487system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 491system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650322 # miss rate for ReadExReq accesses 492system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650322 # miss rate for ReadExReq accesses 493system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for demand accesses 494system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.036219 # miss rate for demand accesses 495system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040512 # miss rate for demand accesses 496system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404827 # miss rate for demand accesses 497system.cpu0.l2cache.demand_miss_rate::total 0.186412 # miss rate for demand accesses 498system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for overall accesses 499system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.036219 # miss rate for overall accesses 500system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040512 # miss rate for overall accesses 501system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404827 # miss rate for overall accesses 502system.cpu0.l2cache.overall_miss_rate::total 0.186412 # miss rate for overall accesses | 488system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650746 # miss rate for ReadExReq accesses 489system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650746 # miss rate for ReadExReq accesses 490system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for demand accesses 491system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039622 # miss rate for demand accesses 492system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040542 # miss rate for demand accesses 493system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404738 # miss rate for demand accesses 494system.cpu0.l2cache.demand_miss_rate::total 0.186406 # miss rate for demand accesses 495system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for overall accesses 496system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039622 # miss rate for overall accesses 497system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040542 # miss rate for overall accesses 498system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404738 # miss rate for overall accesses 499system.cpu0.l2cache.overall_miss_rate::total 0.186406 # miss rate for overall accesses |
| 503system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 504system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 505system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 506system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 507system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 508system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 509system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 510system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 500system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 501system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 502system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 503system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 504system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 505system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 506system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 507system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 511system.cpu0.l2cache.writebacks::writebacks 192870 # number of writebacks 512system.cpu0.l2cache.writebacks::total 192870 # number of writebacks | 508system.cpu0.l2cache.writebacks::writebacks 192841 # number of writebacks 509system.cpu0.l2cache.writebacks::total 192841 # number of writebacks |
| 513system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 510system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 514system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution 515system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution | 511system.cpu0.toL2Bus.trans_dist::ReadReq 1651853 # Transaction distribution 512system.cpu0.toL2Bus.trans_dist::ReadResp 1651853 # Transaction distribution |
| 516system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution 517system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution | 513system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution 514system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution |
| 518system.cpu0.toL2Bus.trans_dist::Writeback 511566 # Transaction distribution 519system.cpu0.toL2Bus.trans_dist::UpgradeReq 26252 # Transaction distribution 520system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18448 # Transaction distribution 521system.cpu0.toL2Bus.trans_dist::UpgradeResp 44700 # Transaction distribution 522system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution 523system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution 524system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) 525system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220284 # Packet count per connected master and slave (bytes) | 515system.cpu0.toL2Bus.trans_dist::Writeback 511648 # Transaction distribution 516system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution 517system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18433 # Transaction distribution 518system.cpu0.toL2Bus.trans_dist::UpgradeResp 44681 # Transaction distribution 519system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution 520system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution 521system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238570 # Packet count per connected master and slave (bytes) 522system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220344 # Packet count per connected master and slave (bytes) |
| 526system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) | 523system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) |
| 527system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 528system.cpu0.toL2Bus.pkt_count::total 4500256 # Packet count per connected master and slave (bytes) 529system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) 530system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80909882 # Cumulative packet size per connected master and slave (bytes) | 524system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) 525system.cpu0.toL2Bus.pkt_count::total 4500550 # Packet count per connected master and slave (bytes) 526system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092920 # Cumulative packet size per connected master and slave (bytes) 527system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80915642 # Cumulative packet size per connected master and slave (bytes) |
| 531system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) | 528system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) |
| 532system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 533system.cpu0.toL2Bus.pkt_size::total 152078946 # Cumulative packet size per connected master and slave (bytes) 534system.cpu0.toL2Bus.snoops 322137 # Total snoops (count) 535system.cpu0.toL2Bus.snoop_fanout::samples 2656435 # Request fanout histogram 536system.cpu0.toL2Bus.snoop_fanout::mean 5.082643 # Request fanout histogram 537system.cpu0.toL2Bus.snoop_fanout::stdev 0.275341 # Request fanout histogram | 529system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) 530system.cpu0.toL2Bus.pkt_size::total 152091834 # Cumulative packet size per connected master and slave (bytes) 531system.cpu0.toL2Bus.snoops 322042 # Total snoops (count) 532system.cpu0.toL2Bus.snoop_fanout::samples 2656528 # Request fanout histogram 533system.cpu0.toL2Bus.snoop_fanout::mean 5.082604 # Request fanout histogram 534system.cpu0.toL2Bus.snoop_fanout::stdev 0.275283 # Request fanout histogram |
| 538system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 539system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 540system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 541system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 542system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 543system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 535system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 536system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 537system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 538system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 539system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 540system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 544system.cpu0.toL2Bus.snoop_fanout::5 2436900 91.74% 91.74% # Request fanout histogram 545system.cpu0.toL2Bus.snoop_fanout::6 219535 8.26% 100.00% # Request fanout histogram | 541system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram 542system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram |
| 546system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 547system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 548system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 543system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 544system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 545system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 549system.cpu0.toL2Bus.snoop_fanout::total 2656435 # Request fanout histogram | 546system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram |
| 550system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 551system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 552system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 553system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 554system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 555system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 556system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 557system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 565system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 566system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 567system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 568system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 569system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 570system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 571system.cpu1.dtb.inst_hits 0 # ITB inst hits 572system.cpu1.dtb.inst_misses 0 # ITB inst misses | 547system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 548system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 549system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 550system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 551system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 552system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 553system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 554system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 562system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 563system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 564system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 565system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 566system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 567system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 568system.cpu1.dtb.inst_hits 0 # ITB inst hits 569system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 573system.cpu1.dtb.read_hits 12173905 # DTB read hits 574system.cpu1.dtb.read_misses 2853 # DTB read misses 575system.cpu1.dtb.write_hits 7587201 # DTB write hits | 570system.cpu1.dtb.read_hits 12173884 # DTB read hits 571system.cpu1.dtb.read_misses 2852 # DTB read misses 572system.cpu1.dtb.write_hits 7587193 # DTB write hits |
| 576system.cpu1.dtb.write_misses 506 # DTB write misses 577system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 578system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 579system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 580system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 581system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 582system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 583system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 584system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 585system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions | 573system.cpu1.dtb.write_misses 506 # DTB write misses 574system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 575system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 576system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 577system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 578system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 579system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 580system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 581system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 582system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions |
| 586system.cpu1.dtb.read_accesses 12176758 # DTB read accesses 587system.cpu1.dtb.write_accesses 7587707 # DTB write accesses | 583system.cpu1.dtb.read_accesses 12176736 # DTB read accesses 584system.cpu1.dtb.write_accesses 7587699 # DTB write accesses |
| 588system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 585system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 589system.cpu1.dtb.hits 19761106 # DTB hits 590system.cpu1.dtb.misses 3359 # DTB misses 591system.cpu1.dtb.accesses 19764465 # DTB accesses | 586system.cpu1.dtb.hits 19761077 # DTB hits 587system.cpu1.dtb.misses 3358 # DTB misses 588system.cpu1.dtb.accesses 19764435 # DTB accesses |
| 592system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 593system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 594system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 595system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 596system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 597system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 598system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 599system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 605system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 606system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 607system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 608system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 609system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 610system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 611system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 612system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 589system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 590system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 591system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 592system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 593system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 594system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 595system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 596system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 602system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 603system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 604system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 605system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 606system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 607system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 608system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 609system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 613system.cpu1.itb.inst_hits 53671578 # ITB inst hits | 610system.cpu1.itb.inst_hits 53671431 # ITB inst hits |
| 614system.cpu1.itb.inst_misses 1734 # ITB inst misses 615system.cpu1.itb.read_hits 0 # DTB read hits 616system.cpu1.itb.read_misses 0 # DTB read misses 617system.cpu1.itb.write_hits 0 # DTB write hits 618system.cpu1.itb.write_misses 0 # DTB write misses 619system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 620system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 621system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 622system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 623system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 624system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 625system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 626system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 627system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 628system.cpu1.itb.read_accesses 0 # DTB read accesses 629system.cpu1.itb.write_accesses 0 # DTB write accesses | 611system.cpu1.itb.inst_misses 1734 # ITB inst misses 612system.cpu1.itb.read_hits 0 # DTB read hits 613system.cpu1.itb.read_misses 0 # DTB read misses 614system.cpu1.itb.write_hits 0 # DTB write hits 615system.cpu1.itb.write_misses 0 # DTB write misses 616system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 617system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 618system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 619system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 620system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 621system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 622system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 623system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 624system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 625system.cpu1.itb.read_accesses 0 # DTB read accesses 626system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 630system.cpu1.itb.inst_accesses 53673312 # ITB inst accesses 631system.cpu1.itb.hits 53671578 # DTB hits | 627system.cpu1.itb.inst_accesses 53673165 # ITB inst accesses 628system.cpu1.itb.hits 53671431 # DTB hits |
| 632system.cpu1.itb.misses 1734 # DTB misses | 629system.cpu1.itb.misses 1734 # DTB misses |
| 633system.cpu1.itb.accesses 53673312 # DTB accesses 634system.cpu1.numCycles 5605296143 # number of cpu cycles simulated | 630system.cpu1.itb.accesses 53673165 # DTB accesses 631system.cpu1.numCycles 5605321082 # number of cpu cycles simulated |
| 635system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 636system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 632system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 633system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 637system.cpu1.committedInsts 51401324 # Number of instructions committed 638system.cpu1.committedOps 63347594 # Number of ops (including micro ops) committed 639system.cpu1.num_int_alu_accesses 56984226 # Number of integer alu accesses | 634system.cpu1.committedInsts 51401178 # Number of instructions committed 635system.cpu1.committedOps 63347444 # Number of ops (including micro ops) committed 636system.cpu1.num_int_alu_accesses 56984089 # Number of integer alu accesses |
| 640system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses | 637system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses |
| 641system.cpu1.num_func_calls 9170833 # number of times a function call or return occured 642system.cpu1.num_conditional_control_insts 5967095 # number of instructions that are conditional controls 643system.cpu1.num_int_insts 56984226 # number of integer instructions | 638system.cpu1.num_func_calls 9170823 # number of times a function call or return occured 639system.cpu1.num_conditional_control_insts 5967084 # number of instructions that are conditional controls 640system.cpu1.num_int_insts 56984089 # number of integer instructions |
| 644system.cpu1.num_fp_insts 1792 # number of float instructions | 641system.cpu1.num_fp_insts 1792 # number of float instructions |
| 645system.cpu1.num_int_register_reads 110674651 # number of times the integer registers were read 646system.cpu1.num_int_register_writes 41298354 # number of times the integer registers were written | 642system.cpu1.num_int_register_reads 110674435 # number of times the integer registers were read 643system.cpu1.num_int_register_writes 41298241 # number of times the integer registers were written |
| 647system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 648system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written | 644system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 645system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written |
| 649system.cpu1.num_cc_register_reads 196268580 # number of times the CC registers were read 650system.cpu1.num_cc_register_writes 18894392 # number of times the CC registers were written 651system.cpu1.num_mem_refs 20026364 # number of memory refs 652system.cpu1.num_load_insts 12289528 # Number of load instructions 653system.cpu1.num_store_insts 7736836 # Number of store instructions 654system.cpu1.num_idle_cycles 5539682653.586912 # Number of idle cycles 655system.cpu1.num_busy_cycles 65613489.413088 # Number of busy cycles | 646system.cpu1.num_cc_register_reads 196268127 # number of times the CC registers were read 647system.cpu1.num_cc_register_writes 18894317 # number of times the CC registers were written 648system.cpu1.num_mem_refs 20026333 # number of memory refs 649system.cpu1.num_load_insts 12289505 # Number of load instructions 650system.cpu1.num_store_insts 7736828 # Number of store instructions 651system.cpu1.num_idle_cycles 5539707743.549846 # Number of idle cycles 652system.cpu1.num_busy_cycles 65613338.450155 # Number of busy cycles |
| 656system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 657system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles | 653system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 654system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles |
| 658system.cpu1.Branches 15217468 # Number of branches fetched | 655system.cpu1.Branches 15217445 # Number of branches fetched |
| 659system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction | 656system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction |
| 660system.cpu1.op_class::IntAlu 45401296 69.36% 69.36% # Class of executed instruction 661system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction | 657system.cpu1.op_class::IntAlu 45401182 69.36% 69.36% # Class of executed instruction 658system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction |
| 662system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 663system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 664system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 665system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 666system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 667system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 668system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 669system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 681system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 682system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 683system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 684system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 685system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 686system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 687system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 688system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction | 659system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 660system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 661system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 662system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 663system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 664system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 665system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 666system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 678system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 679system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 680system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 681system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 682system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 683system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 684system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 685system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction |
| 689system.cpu1.op_class::MemRead 12289528 18.77% 88.18% # Class of executed instruction 690system.cpu1.op_class::MemWrite 7736836 11.82% 100.00% # Class of executed instruction | 686system.cpu1.op_class::MemRead 12289505 18.77% 88.18% # Class of executed instruction 687system.cpu1.op_class::MemWrite 7736828 11.82% 100.00% # Class of executed instruction |
| 691system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 692system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 688system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 689system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 693system.cpu1.op_class::total 65459439 # Class of executed instruction | 690system.cpu1.op_class::total 65459288 # Class of executed instruction |
| 694system.cpu1.kern.inst.arm 0 # number of arm instructions executed 695system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed | 691system.cpu1.kern.inst.arm 0 # number of arm instructions executed 692system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed |
| 696system.cpu1.dcache.tags.replacements 191947 # number of replacements 697system.cpu1.dcache.tags.tagsinuse 472.736020 # Cycle average of tags in use 698system.cpu1.dcache.tags.total_refs 19503484 # Total number of references to valid blocks. 699system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. 700system.cpu1.dcache.tags.avg_refs 101.421646 # Average number of references to valid blocks. | 693system.cpu1.dcache.tags.replacements 191938 # number of replacements 694system.cpu1.dcache.tags.tagsinuse 472.735401 # Cycle average of tags in use 695system.cpu1.dcache.tags.total_refs 19503461 # Total number of references to valid blocks. 696system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. 697system.cpu1.dcache.tags.avg_refs 101.426274 # Average number of references to valid blocks. |
| 701system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. | 698system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. |
| 702system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736020 # Average occupied blocks per requestor 703system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 704system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy | 699system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735401 # Average occupied blocks per requestor 700system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy 701system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy |
| 705system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 706system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 707system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 708system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id | 702system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 703system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 704system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 705system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id |
| 709system.cpu1.dcache.tags.tag_accesses 39751950 # Number of tag accesses 710system.cpu1.dcache.tags.data_accesses 39751950 # Number of data accesses 711system.cpu1.dcache.ReadReq_hits::cpu1.data 11858675 # number of ReadReq hits 712system.cpu1.dcache.ReadReq_hits::total 11858675 # number of ReadReq hits 713system.cpu1.dcache.WriteReq_hits::cpu1.data 7397476 # number of WriteReq hits 714system.cpu1.dcache.WriteReq_hits::total 7397476 # number of WriteReq hits 715system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 716system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits | 706system.cpu1.dcache.tags.tag_accesses 39751883 # Number of tag accesses 707system.cpu1.dcache.tags.data_accesses 39751883 # Number of data accesses 708system.cpu1.dcache.ReadReq_hits::cpu1.data 11858662 # number of ReadReq hits 709system.cpu1.dcache.ReadReq_hits::total 11858662 # number of ReadReq hits 710system.cpu1.dcache.WriteReq_hits::cpu1.data 7397475 # number of WriteReq hits 711system.cpu1.dcache.WriteReq_hits::total 7397475 # number of WriteReq hits 712system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits 713system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits |
| 717system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 718system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits | 714system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 715system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits |
| 719system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72420 # number of StoreCondReq hits 720system.cpu1.dcache.StoreCondReq_hits::total 72420 # number of StoreCondReq hits 721system.cpu1.dcache.demand_hits::cpu1.data 19256151 # number of demand (read+write) hits 722system.cpu1.dcache.demand_hits::total 19256151 # number of demand (read+write) hits 723system.cpu1.dcache.overall_hits::cpu1.data 19306251 # number of overall hits 724system.cpu1.dcache.overall_hits::total 19306251 # number of overall hits 725system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses 726system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses 727system.cpu1.dcache.WriteReq_misses::cpu1.data 92478 # number of WriteReq misses 728system.cpu1.dcache.WriteReq_misses::total 92478 # number of WriteReq misses 729system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses 730system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses | 716system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72435 # number of StoreCondReq hits 717system.cpu1.dcache.StoreCondReq_hits::total 72435 # number of StoreCondReq hits 718system.cpu1.dcache.demand_hits::cpu1.data 19256137 # number of demand (read+write) hits 719system.cpu1.dcache.demand_hits::total 19256137 # number of demand (read+write) hits 720system.cpu1.dcache.overall_hits::cpu1.data 19306236 # number of overall hits 721system.cpu1.dcache.overall_hits::total 19306236 # number of overall hits 722system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses 723system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses 724system.cpu1.dcache.WriteReq_misses::cpu1.data 92471 # number of WriteReq misses 725system.cpu1.dcache.WriteReq_misses::total 92471 # number of WriteReq misses 726system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses 727system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses |
| 731system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 732system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses | 728system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 729system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses |
| 733system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22559 # number of StoreCondReq misses 734system.cpu1.dcache.StoreCondReq_misses::total 22559 # number of StoreCondReq misses 735system.cpu1.dcache.demand_misses::cpu1.data 229117 # number of demand (read+write) misses 736system.cpu1.dcache.demand_misses::total 229117 # number of demand (read+write) misses 737system.cpu1.dcache.overall_misses::cpu1.data 259835 # number of overall misses 738system.cpu1.dcache.overall_misses::total 259835 # number of overall misses 739system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995314 # number of ReadReq accesses(hits+misses) 740system.cpu1.dcache.ReadReq_accesses::total 11995314 # number of ReadReq accesses(hits+misses) 741system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489954 # number of WriteReq accesses(hits+misses) 742system.cpu1.dcache.WriteReq_accesses::total 7489954 # number of WriteReq accesses(hits+misses) | 730system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22544 # number of StoreCondReq misses 731system.cpu1.dcache.StoreCondReq_misses::total 22544 # number of StoreCondReq misses 732system.cpu1.dcache.demand_misses::cpu1.data 229101 # number of demand (read+write) misses 733system.cpu1.dcache.demand_misses::total 229101 # number of demand (read+write) misses 734system.cpu1.dcache.overall_misses::cpu1.data 259820 # number of overall misses 735system.cpu1.dcache.overall_misses::total 259820 # number of overall misses 736system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995292 # number of ReadReq accesses(hits+misses) 737system.cpu1.dcache.ReadReq_accesses::total 11995292 # number of ReadReq accesses(hits+misses) 738system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489946 # number of WriteReq accesses(hits+misses) 739system.cpu1.dcache.WriteReq_accesses::total 7489946 # number of WriteReq accesses(hits+misses) |
| 743system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 744system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 745system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 746system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 747system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 748system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) | 740system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 741system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 742system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 743system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 744system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 745system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) |
| 749system.cpu1.dcache.demand_accesses::cpu1.data 19485268 # number of demand (read+write) accesses 750system.cpu1.dcache.demand_accesses::total 19485268 # number of demand (read+write) accesses 751system.cpu1.dcache.overall_accesses::cpu1.data 19566086 # number of overall (read+write) accesses 752system.cpu1.dcache.overall_accesses::total 19566086 # number of overall (read+write) accesses 753system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses 754system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 755system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses 756system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses 757system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses 758system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses | 746system.cpu1.dcache.demand_accesses::cpu1.data 19485238 # number of demand (read+write) accesses 747system.cpu1.dcache.demand_accesses::total 19485238 # number of demand (read+write) accesses 748system.cpu1.dcache.overall_accesses::cpu1.data 19566056 # number of overall (read+write) accesses 749system.cpu1.dcache.overall_accesses::total 19566056 # number of overall (read+write) accesses 750system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses 751system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses 752system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses 753system.cpu1.dcache.WriteReq_miss_rate::total 0.012346 # miss rate for WriteReq accesses 754system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses 755system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses |
| 759system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 760system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses | 756system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 757system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses |
| 761system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237516 # miss rate for StoreCondReq accesses 762system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237516 # miss rate for StoreCondReq accesses | 758system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237358 # miss rate for StoreCondReq accesses 759system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237358 # miss rate for StoreCondReq accesses |
| 763system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses 764system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses | 760system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses 761system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses |
| 765system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses 766system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses | 762system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 763system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses |
| 767system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 768system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 769system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 770system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 771system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 772system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 773system.cpu1.dcache.fast_writes 0 # number of fast writes performed 774system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 764system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 765system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 766system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 767system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 768system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 769system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 770system.cpu1.dcache.fast_writes 0 # number of fast writes performed 771system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 775system.cpu1.dcache.writebacks::writebacks 120692 # number of writebacks 776system.cpu1.dcache.writebacks::total 120692 # number of writebacks | 772system.cpu1.dcache.writebacks::writebacks 120709 # number of writebacks 773system.cpu1.dcache.writebacks::total 120709 # number of writebacks |
| 777system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 774system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 778system.cpu1.icache.tags.replacements 523402 # number of replacements 779system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use 780system.cpu1.icache.tags.total_refs 53148754 # Total number of references to valid blocks. 781system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. 782system.cpu1.icache.tags.avg_refs 101.445569 # Average number of references to valid blocks. | 775system.cpu1.icache.tags.replacements 523373 # number of replacements 776system.cpu1.icache.tags.tagsinuse 499.711131 # Cycle average of tags in use 777system.cpu1.icache.tags.total_refs 53148636 # Total number of references to valid blocks. 778system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. 779system.cpu1.icache.tags.avg_refs 101.450960 # Average number of references to valid blocks. |
| 783system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. | 780system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. |
| 784system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor | 781system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711131 # Average occupied blocks per requestor |
| 785system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 786system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 787system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 788system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 789system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 790system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 782system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 783system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 784system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 785system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 786system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 787system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 791system.cpu1.icache.tags.tag_accesses 107869250 # Number of tag accesses 792system.cpu1.icache.tags.data_accesses 107869250 # Number of data accesses 793system.cpu1.icache.ReadReq_hits::cpu1.inst 53148754 # number of ReadReq hits 794system.cpu1.icache.ReadReq_hits::total 53148754 # number of ReadReq hits 795system.cpu1.icache.demand_hits::cpu1.inst 53148754 # number of demand (read+write) hits 796system.cpu1.icache.demand_hits::total 53148754 # number of demand (read+write) hits 797system.cpu1.icache.overall_hits::cpu1.inst 53148754 # number of overall hits 798system.cpu1.icache.overall_hits::total 53148754 # number of overall hits 799system.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses 800system.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses 801system.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses 802system.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses 803system.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses 804system.cpu1.icache.overall_misses::total 523914 # number of overall misses 805system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672668 # number of ReadReq accesses(hits+misses) 806system.cpu1.icache.ReadReq_accesses::total 53672668 # number of ReadReq accesses(hits+misses) 807system.cpu1.icache.demand_accesses::cpu1.inst 53672668 # number of demand (read+write) accesses 808system.cpu1.icache.demand_accesses::total 53672668 # number of demand (read+write) accesses 809system.cpu1.icache.overall_accesses::cpu1.inst 53672668 # number of overall (read+write) accesses 810system.cpu1.icache.overall_accesses::total 53672668 # number of overall (read+write) accesses | 788system.cpu1.icache.tags.tag_accesses 107868927 # Number of tag accesses 789system.cpu1.icache.tags.data_accesses 107868927 # Number of data accesses 790system.cpu1.icache.ReadReq_hits::cpu1.inst 53148636 # number of ReadReq hits 791system.cpu1.icache.ReadReq_hits::total 53148636 # number of ReadReq hits 792system.cpu1.icache.demand_hits::cpu1.inst 53148636 # number of demand (read+write) hits 793system.cpu1.icache.demand_hits::total 53148636 # number of demand (read+write) hits 794system.cpu1.icache.overall_hits::cpu1.inst 53148636 # number of overall hits 795system.cpu1.icache.overall_hits::total 53148636 # number of overall hits 796system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses 797system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses 798system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses 799system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses 800system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses 801system.cpu1.icache.overall_misses::total 523885 # number of overall misses 802system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672521 # number of ReadReq accesses(hits+misses) 803system.cpu1.icache.ReadReq_accesses::total 53672521 # number of ReadReq accesses(hits+misses) 804system.cpu1.icache.demand_accesses::cpu1.inst 53672521 # number of demand (read+write) accesses 805system.cpu1.icache.demand_accesses::total 53672521 # number of demand (read+write) accesses 806system.cpu1.icache.overall_accesses::cpu1.inst 53672521 # number of overall (read+write) accesses 807system.cpu1.icache.overall_accesses::total 53672521 # number of overall (read+write) accesses |
| 811system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 812system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 813system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 814system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 815system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 816system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 817system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 818system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 8 unchanged lines hidden (view full) --- 827system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 828system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 829system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 830system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 831system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 832system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 833system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 834system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 808system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 809system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 810system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 811system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 812system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 813system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 814system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 815system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 8 unchanged lines hidden (view full) --- 824system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 825system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 826system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 827system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 828system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 829system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 830system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 831system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 835system.cpu1.l2cache.tags.replacements 48632 # number of replacements 836system.cpu1.l2cache.tags.tagsinuse 15302.414906 # Cycle average of tags in use 837system.cpu1.l2cache.tags.total_refs 716436 # Total number of references to valid blocks. 838system.cpu1.l2cache.tags.sampled_refs 63462 # Sample count of references to valid blocks. 839system.cpu1.l2cache.tags.avg_refs 11.289212 # Average number of references to valid blocks. | 832system.cpu1.l2cache.tags.replacements 48598 # number of replacements 833system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use 834system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. 835system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks. 836system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks. |
| 840system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 837system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 841system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.533576 # Average occupied blocks per requestor 842system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.964027 # Average occupied blocks per requestor 843system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.029845 # Average occupied blocks per requestor 844system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.932073 # Average occupied blocks per requestor 845system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.955385 # Average occupied blocks per requestor 846system.cpu1.l2cache.tags.occ_percent::writebacks 0.505953 # Average percentage of cache occupancy 847system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy | 838system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor 839system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor 840system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030831 # Average occupied blocks per requestor 841system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.951411 # Average occupied blocks per requestor 842system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.465503 # Average occupied blocks per requestor 843system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy 844system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy |
| 848system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy | 845system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy |
| 849system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200374 # Average percentage of cache occupancy 850system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227231 # Average percentage of cache occupancy 851system.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy 852system.cpu1.l2cache.tags.occ_task_id_blocks::1023 26 # Occupied blocks per task id 853system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14804 # Occupied blocks per task id | 846system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200131 # Average percentage of cache occupancy 847system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225370 # Average percentage of cache occupancy 848system.cpu1.l2cache.tags.occ_percent::total 0.934164 # Average percentage of cache occupancy 849system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id 850system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14799 # Occupied blocks per task id |
| 854system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id | 851system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id |
| 855system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 856system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id 857system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id 858system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9309 # Occupied blocks per task id 859system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4941 # Occupied blocks per task id 860system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001587 # Percentage of cache occupancy per task id 861system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903564 # Percentage of cache occupancy per task id 862system.cpu1.l2cache.tags.tag_accesses 15214590 # Number of tag accesses 863system.cpu1.l2cache.tags.data_accesses 15214590 # Number of data accesses 864system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3250 # number of ReadReq hits 865system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1767 # number of ReadReq hits 866system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510040 # number of ReadReq hits 867system.cpu1.l2cache.ReadReq_hits::cpu1.data 99338 # number of ReadReq hits 868system.cpu1.l2cache.ReadReq_hits::total 614395 # number of ReadReq hits 869system.cpu1.l2cache.Writeback_hits::writebacks 120692 # number of Writeback hits 870system.cpu1.l2cache.Writeback_hits::total 120692 # number of Writeback hits 871system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits 872system.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits 873system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19796 # number of ReadExReq hits 874system.cpu1.l2cache.ReadExReq_hits::total 19796 # number of ReadExReq hits 875system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3250 # number of demand (read+write) hits 876system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1767 # number of demand (read+write) hits 877system.cpu1.l2cache.demand_hits::cpu1.inst 510040 # number of demand (read+write) hits 878system.cpu1.l2cache.demand_hits::cpu1.data 119134 # number of demand (read+write) hits 879system.cpu1.l2cache.demand_hits::total 634191 # number of demand (read+write) hits 880system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3250 # number of overall hits 881system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1767 # number of overall hits 882system.cpu1.l2cache.overall_hits::cpu1.inst 510040 # number of overall hits 883system.cpu1.l2cache.overall_hits::cpu1.data 119134 # number of overall hits 884system.cpu1.l2cache.overall_hits::total 634191 # number of overall hits 885system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 345 # number of ReadReq misses 886system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 269 # number of ReadReq misses 887system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13874 # number of ReadReq misses 888system.cpu1.l2cache.ReadReq_misses::cpu1.data 73337 # number of ReadReq misses 889system.cpu1.l2cache.ReadReq_misses::total 87825 # number of ReadReq misses 890system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28856 # number of UpgradeReq misses 891system.cpu1.l2cache.UpgradeReq_misses::total 28856 # number of UpgradeReq misses 892system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22559 # number of SCUpgradeReq misses 893system.cpu1.l2cache.SCUpgradeReq_misses::total 22559 # number of SCUpgradeReq misses 894system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43819 # number of ReadExReq misses 895system.cpu1.l2cache.ReadExReq_misses::total 43819 # number of ReadExReq misses 896system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 345 # number of demand (read+write) misses 897system.cpu1.l2cache.demand_misses::cpu1.itb.walker 269 # number of demand (read+write) misses 898system.cpu1.l2cache.demand_misses::cpu1.inst 13874 # number of demand (read+write) misses 899system.cpu1.l2cache.demand_misses::cpu1.data 117156 # number of demand (read+write) misses 900system.cpu1.l2cache.demand_misses::total 131644 # number of demand (read+write) misses 901system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 345 # number of overall misses 902system.cpu1.l2cache.overall_misses::cpu1.itb.walker 269 # number of overall misses 903system.cpu1.l2cache.overall_misses::cpu1.inst 13874 # number of overall misses 904system.cpu1.l2cache.overall_misses::cpu1.data 117156 # number of overall misses 905system.cpu1.l2cache.overall_misses::total 131644 # number of overall misses 906system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3595 # number of ReadReq accesses(hits+misses) 907system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2036 # number of ReadReq accesses(hits+misses) 908system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses) 909system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses) 910system.cpu1.l2cache.ReadReq_accesses::total 702220 # number of ReadReq accesses(hits+misses) 911system.cpu1.l2cache.Writeback_accesses::writebacks 120692 # number of Writeback accesses(hits+misses) 912system.cpu1.l2cache.Writeback_accesses::total 120692 # number of Writeback accesses(hits+misses) 913system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28863 # number of UpgradeReq accesses(hits+misses) 914system.cpu1.l2cache.UpgradeReq_accesses::total 28863 # number of UpgradeReq accesses(hits+misses) 915system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22559 # number of SCUpgradeReq accesses(hits+misses) 916system.cpu1.l2cache.SCUpgradeReq_accesses::total 22559 # number of SCUpgradeReq accesses(hits+misses) 917system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 918system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 919system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3595 # number of demand (read+write) accesses 920system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2036 # number of demand (read+write) accesses 921system.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses 922system.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses 923system.cpu1.l2cache.demand_accesses::total 765835 # number of demand (read+write) accesses 924system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3595 # number of overall (read+write) accesses 925system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2036 # number of overall (read+write) accesses 926system.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses 927system.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses 928system.cpu1.l2cache.overall_accesses::total 765835 # number of overall (read+write) accesses 929system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for ReadReq accesses 930system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.132122 # miss rate for ReadReq accesses 931system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026481 # miss rate for ReadReq accesses 932system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424711 # miss rate for ReadReq accesses 933system.cpu1.l2cache.ReadReq_miss_rate::total 0.125068 # miss rate for ReadReq accesses 934system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses 935system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses | 852system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 853system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 854system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id 855system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9279 # Occupied blocks per task id 856system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4981 # Occupied blocks per task id 857system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id 858system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903259 # Percentage of cache occupancy per task id 859system.cpu1.l2cache.tags.tag_accesses 15211446 # Number of tag accesses 860system.cpu1.l2cache.tags.data_accesses 15211446 # Number of data accesses 861system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3145 # number of ReadReq hits 862system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1724 # number of ReadReq hits 863system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510078 # number of ReadReq hits 864system.cpu1.l2cache.ReadReq_hits::cpu1.data 99331 # number of ReadReq hits 865system.cpu1.l2cache.ReadReq_hits::total 614278 # number of ReadReq hits 866system.cpu1.l2cache.Writeback_hits::writebacks 120709 # number of Writeback hits 867system.cpu1.l2cache.Writeback_hits::total 120709 # number of Writeback hits 868system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits 869system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits 870system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19802 # number of ReadExReq hits 871system.cpu1.l2cache.ReadExReq_hits::total 19802 # number of ReadExReq hits 872system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3145 # number of demand (read+write) hits 873system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1724 # number of demand (read+write) hits 874system.cpu1.l2cache.demand_hits::cpu1.inst 510078 # number of demand (read+write) hits 875system.cpu1.l2cache.demand_hits::cpu1.data 119133 # number of demand (read+write) hits 876system.cpu1.l2cache.demand_hits::total 634080 # number of demand (read+write) hits 877system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3145 # number of overall hits 878system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1724 # number of overall hits 879system.cpu1.l2cache.overall_hits::cpu1.inst 510078 # number of overall hits 880system.cpu1.l2cache.overall_hits::cpu1.data 119133 # number of overall hits 881system.cpu1.l2cache.overall_hits::total 634080 # number of overall hits 882system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses 883system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses 884system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13807 # number of ReadReq misses 885system.cpu1.l2cache.ReadReq_misses::cpu1.data 73336 # number of ReadReq misses 886system.cpu1.l2cache.ReadReq_misses::total 87759 # number of ReadReq misses 887system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28847 # number of UpgradeReq misses 888system.cpu1.l2cache.UpgradeReq_misses::total 28847 # number of UpgradeReq misses 889system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22544 # number of SCUpgradeReq misses 890system.cpu1.l2cache.SCUpgradeReq_misses::total 22544 # number of SCUpgradeReq misses 891system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43814 # number of ReadExReq misses 892system.cpu1.l2cache.ReadExReq_misses::total 43814 # number of ReadExReq misses 893system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses 894system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses 895system.cpu1.l2cache.demand_misses::cpu1.inst 13807 # number of demand (read+write) misses 896system.cpu1.l2cache.demand_misses::cpu1.data 117150 # number of demand (read+write) misses 897system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses 898system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses 899system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses 900system.cpu1.l2cache.overall_misses::cpu1.inst 13807 # number of overall misses 901system.cpu1.l2cache.overall_misses::cpu1.data 117150 # number of overall misses 902system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses 903system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses) 904system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) 905system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses) 906system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses) 907system.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses) 908system.cpu1.l2cache.Writeback_accesses::writebacks 120709 # number of Writeback accesses(hits+misses) 909system.cpu1.l2cache.Writeback_accesses::total 120709 # number of Writeback accesses(hits+misses) 910system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28855 # number of UpgradeReq accesses(hits+misses) 911system.cpu1.l2cache.UpgradeReq_accesses::total 28855 # number of UpgradeReq accesses(hits+misses) 912system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22544 # number of SCUpgradeReq accesses(hits+misses) 913system.cpu1.l2cache.SCUpgradeReq_accesses::total 22544 # number of SCUpgradeReq accesses(hits+misses) 914system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) 915system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) 916system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses 917system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses 918system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses 919system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses 920system.cpu1.l2cache.demand_accesses::total 765653 # number of demand (read+write) accesses 921system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3489 # number of overall (read+write) accesses 922system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses 923system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses 924system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses 925system.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses 926system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for ReadReq accesses 927system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136273 # miss rate for ReadReq accesses 928system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026355 # miss rate for ReadReq accesses 929system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424725 # miss rate for ReadReq accesses 930system.cpu1.l2cache.ReadReq_miss_rate::total 0.125006 # miss rate for ReadReq accesses 931system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses 932system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses |
| 936system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 937system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 933system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 934system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 938system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688816 # miss rate for ReadExReq accesses 939system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688816 # miss rate for ReadExReq accesses 940system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for demand accesses 941system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.132122 # miss rate for demand accesses 942system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026481 # miss rate for demand accesses 943system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495814 # miss rate for demand accesses 944system.cpu1.l2cache.demand_miss_rate::total 0.171896 # miss rate for demand accesses 945system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095967 # miss rate for overall accesses 946system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.132122 # miss rate for overall accesses 947system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026481 # miss rate for overall accesses 948system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495814 # miss rate for overall accesses 949system.cpu1.l2cache.overall_miss_rate::total 0.171896 # miss rate for overall accesses | 935system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688726 # miss rate for ReadExReq accesses 936system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688726 # miss rate for ReadExReq accesses 937system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for demand accesses 938system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136273 # miss rate for demand accesses 939system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026355 # miss rate for demand accesses 940system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495804 # miss rate for demand accesses 941system.cpu1.l2cache.demand_miss_rate::total 0.171844 # miss rate for demand accesses 942system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for overall accesses 943system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136273 # miss rate for overall accesses 944system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026355 # miss rate for overall accesses 945system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495804 # miss rate for overall accesses 946system.cpu1.l2cache.overall_miss_rate::total 0.171844 # miss rate for overall accesses |
| 950system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 951system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 952system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 953system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 954system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 955system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 956system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 957system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 947system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 948system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 949system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 950system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 951system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 952system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 953system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 954system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 958system.cpu1.l2cache.writebacks::writebacks 32939 # number of writebacks 959system.cpu1.l2cache.writebacks::total 32939 # number of writebacks | 955system.cpu1.l2cache.writebacks::writebacks 32919 # number of writebacks 956system.cpu1.l2cache.writebacks::total 32919 # number of writebacks |
| 960system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 957system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 961system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution 962system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution | 958system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution 959system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution |
| 963system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 964system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution | 960system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 961system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution |
| 965system.cpu1.toL2Bus.trans_dist::Writeback 120692 # Transaction distribution 966system.cpu1.toL2Bus.trans_dist::UpgradeReq 28863 # Transaction distribution 967system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22559 # Transaction distribution 968system.cpu1.toL2Bus.trans_dist::UpgradeResp 51422 # Transaction distribution 969system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 970system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 971system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) 972system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707576 # Packet count per connected master and slave (bytes) | 962system.cpu1.toL2Bus.trans_dist::Writeback 120709 # Transaction distribution 963system.cpu1.toL2Bus.trans_dist::UpgradeReq 28855 # Transaction distribution 964system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22544 # Transaction distribution 965system.cpu1.toL2Bus.trans_dist::UpgradeResp 51399 # Transaction distribution 966system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution 967system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution 968system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes) 969system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707533 # Packet count per connected master and slave (bytes) |
| 973system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) | 970system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) |
| 974system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 975system.cpu1.toL2Bus.pkt_count::total 1774454 # Packet count per connected master and slave (bytes) 976system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) 977system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866030 # Cumulative packet size per connected master and slave (bytes) | 971system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) 972system.cpu1.toL2Bus.pkt_count::total 1774351 # Packet count per connected master and slave (bytes) 973system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) 974system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866670 # Cumulative packet size per connected master and slave (bytes) |
| 978system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) | 975system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) |
| 979system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 980system.cpu1.toL2Bus.pkt_size::total 56434626 # Cumulative packet size per connected master and slave (bytes) 981system.cpu1.toL2Bus.snoops 499621 # Total snoops (count) 982system.cpu1.toL2Bus.snoop_fanout::samples 1371622 # Request fanout histogram 983system.cpu1.toL2Bus.snoop_fanout::mean 5.313465 # Request fanout histogram 984system.cpu1.toL2Bus.snoop_fanout::stdev 0.463902 # Request fanout histogram | 976system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) 977system.cpu1.toL2Bus.pkt_size::total 56433406 # Cumulative packet size per connected master and slave (bytes) 978system.cpu1.toL2Bus.snoops 499587 # Total snoops (count) 979system.cpu1.toL2Bus.snoop_fanout::samples 1371557 # Request fanout histogram 980system.cpu1.toL2Bus.snoop_fanout::mean 5.313464 # Request fanout histogram 981system.cpu1.toL2Bus.snoop_fanout::stdev 0.463901 # Request fanout histogram |
| 985system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 986system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 987system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 988system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 989system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 990system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 982system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 983system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 984system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 985system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 986system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 987system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 991system.cpu1.toL2Bus.snoop_fanout::5 941666 68.65% 68.65% # Request fanout histogram 992system.cpu1.toL2Bus.snoop_fanout::6 429956 31.35% 100.00% # Request fanout histogram | 988system.cpu1.toL2Bus.snoop_fanout::5 941623 68.65% 68.65% # Request fanout histogram 989system.cpu1.toL2Bus.snoop_fanout::6 429934 31.35% 100.00% # Request fanout histogram |
| 993system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 994system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 995system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 990system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 991system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 992system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 996system.cpu1.toL2Bus.snoop_fanout::total 1371622 # Request fanout histogram | 993system.cpu1.toL2Bus.snoop_fanout::total 1371557 # Request fanout histogram |
| 997system.iobus.trans_dist::ReadReq 31002 # Transaction distribution 998system.iobus.trans_dist::ReadResp 31002 # Transaction distribution 999system.iobus.trans_dist::WriteReq 59433 # Transaction distribution 1000system.iobus.trans_dist::WriteResp 23209 # Transaction distribution 1001system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1002system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) 1003system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1004system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 40 unchanged lines hidden (view full) --- 1045system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1046system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1047system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) 1049system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1050system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1051system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) 1052system.iocache.tags.replacements 36442 # number of replacements | 994system.iobus.trans_dist::ReadReq 31002 # Transaction distribution 995system.iobus.trans_dist::ReadResp 31002 # Transaction distribution 996system.iobus.trans_dist::WriteReq 59433 # Transaction distribution 997system.iobus.trans_dist::WriteResp 23209 # Transaction distribution 998system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 999system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) 1000system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1001system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 40 unchanged lines hidden (view full) --- 1042system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1043system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1044system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1045system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) 1046system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1047system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1048system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) 1049system.iocache.tags.replacements 36442 # number of replacements |
| 1053system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use | 1050system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use |
| 1054system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1055system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1056system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1057system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. | 1051system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1052system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1053system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1054system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. |
| 1058system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor 1059system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1060system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy | 1055system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor 1056system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy 1057system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy |
| 1061system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1062system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1063system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1064system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1065system.iocache.tags.data_accesses 328284 # Number of data accesses | 1058system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1059system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1060system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1061system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1062system.iocache.tags.data_accesses 328284 # Number of data accesses |
| 1066system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1067system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits | |
| 1068system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1069system.iocache.ReadReq_misses::total 252 # number of ReadReq misses | 1063system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1064system.iocache.ReadReq_misses::total 252 # number of ReadReq misses |
| 1065system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 1066system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses |
|
| 1070system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 1071system.iocache.demand_misses::total 252 # number of demand (read+write) misses 1072system.iocache.overall_misses::realview.ide 252 # number of overall misses 1073system.iocache.overall_misses::total 252 # number of overall misses 1074system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1075system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1076system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1077system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1078system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 1079system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 1080system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 1081system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 1082system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1083system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 1067system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 1068system.iocache.demand_misses::total 252 # number of demand (read+write) misses 1069system.iocache.overall_misses::realview.ide 252 # number of overall misses 1070system.iocache.overall_misses::total 252 # number of overall misses 1071system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1072system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1073system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1074system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1075system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 1076system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 1077system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 1078system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 1079system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1080system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 1081system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 1082system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses |
|
| 1084system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1085system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1086system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1087system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1088system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1089system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1090system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1091system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1092system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1093system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1083system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1084system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1085system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1086system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1087system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1088system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1089system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1090system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1091system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1092system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1094system.iocache.fast_writes 36224 # number of fast writes performed | 1093system.iocache.fast_writes 0 # number of fast writes performed |
| 1095system.iocache.cache_copies 0 # number of cache copies performed | 1094system.iocache.cache_copies 0 # number of cache copies performed |
| 1095system.iocache.writebacks::writebacks 36190 # number of writebacks 1096system.iocache.writebacks::total 36190 # number of writebacks |
|
| 1096system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1097system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1097system.l2c.tags.replacements 107659 # number of replacements 1098system.l2c.tags.tagsinuse 62143.932416 # Cycle average of tags in use 1099system.l2c.tags.total_refs 208094 # Total number of references to valid blocks. 1100system.l2c.tags.sampled_refs 168104 # Sample count of references to valid blocks. 1101system.l2c.tags.avg_refs 1.237888 # Average number of references to valid blocks. | 1098system.l2c.tags.replacements 107620 # number of replacements 1099system.l2c.tags.tagsinuse 62052.354763 # Cycle average of tags in use 1100system.l2c.tags.total_refs 207975 # Total number of references to valid blocks. 1101system.l2c.tags.sampled_refs 168018 # Sample count of references to valid blocks. 1102system.l2c.tags.avg_refs 1.237814 # Average number of references to valid blocks. |
| 1102system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1103system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1103system.l2c.tags.occ_blocks::writebacks 48688.063077 # Average occupied blocks per requestor 1104system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor 1105system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor 1106system.l2c.tags.occ_blocks::cpu0.inst 7324.743178 # Average occupied blocks per requestor 1107system.l2c.tags.occ_blocks::cpu0.data 3758.906335 # Average occupied blocks per requestor 1108system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor 1109system.l2c.tags.occ_blocks::cpu1.inst 1656.372339 # Average occupied blocks per requestor 1110system.l2c.tags.occ_blocks::cpu1.data 711.015210 # Average occupied blocks per requestor 1111system.l2c.tags.occ_percent::writebacks 0.742921 # Average percentage of cache occupancy | 1104system.l2c.tags.occ_blocks::writebacks 48595.577563 # Average occupied blocks per requestor 1105system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.970677 # Average occupied blocks per requestor 1106system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor 1107system.l2c.tags.occ_blocks::cpu0.inst 7329.733330 # Average occupied blocks per requestor 1108system.l2c.tags.occ_blocks::cpu0.data 3756.722499 # Average occupied blocks per requestor 1109system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823230 # Average occupied blocks per requestor 1110system.l2c.tags.occ_blocks::cpu1.inst 1654.519056 # Average occupied blocks per requestor 1111system.l2c.tags.occ_blocks::cpu1.data 710.978017 # Average occupied blocks per requestor 1112system.l2c.tags.occ_percent::writebacks 0.741510 # Average percentage of cache occupancy |
| 1112system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 1113system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 1113system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 1114system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 1114system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy 1115system.l2c.tags.occ_percent::cpu0.data 0.057356 # Average percentage of cache occupancy | 1115system.l2c.tags.occ_percent::cpu0.inst 0.111843 # Average percentage of cache occupancy 1116system.l2c.tags.occ_percent::cpu0.data 0.057323 # Average percentage of cache occupancy |
| 1116system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy | 1117system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy |
| 1117system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy | 1118system.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy |
| 1118system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy | 1119system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy |
| 1119system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy 1120system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 1121system.l2c.tags.occ_task_id_blocks::1024 60436 # Occupied blocks per task id 1122system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 1123system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 1124system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 1125system.l2c.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 1126system.l2c.tags.age_task_id_blocks_1024::2 1910 # Occupied blocks per task id 1127system.l2c.tags.age_task_id_blocks_1024::3 13081 # Occupied blocks per task id 1128system.l2c.tags.age_task_id_blocks_1024::4 45354 # Occupied blocks per task id 1129system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id 1130system.l2c.tags.occ_task_id_percent::1024 0.922180 # Percentage of cache occupancy per task id 1131system.l2c.tags.tag_accesses 4903872 # Number of tag accesses 1132system.l2c.tags.data_accesses 4903872 # Number of data accesses 1133system.l2c.ReadReq_hits::cpu0.dtb.walker 74 # number of ReadReq hits 1134system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits 1135system.l2c.ReadReq_hits::cpu0.inst 28084 # number of ReadReq hits 1136system.l2c.ReadReq_hits::cpu0.data 76119 # number of ReadReq hits 1137system.l2c.ReadReq_hits::cpu1.dtb.walker 40 # number of ReadReq hits 1138system.l2c.ReadReq_hits::cpu1.itb.walker 38 # number of ReadReq hits 1139system.l2c.ReadReq_hits::cpu1.inst 11510 # number of ReadReq hits 1140system.l2c.ReadReq_hits::cpu1.data 11381 # number of ReadReq hits 1141system.l2c.ReadReq_hits::total 127309 # number of ReadReq hits 1142system.l2c.Writeback_hits::writebacks 225809 # number of Writeback hits 1143system.l2c.Writeback_hits::total 225809 # number of Writeback hits 1144system.l2c.UpgradeReq_hits::cpu0.data 496 # number of UpgradeReq hits 1145system.l2c.UpgradeReq_hits::cpu1.data 63 # number of UpgradeReq hits 1146system.l2c.UpgradeReq_hits::total 559 # number of UpgradeReq hits 1147system.l2c.SCUpgradeReq_hits::cpu0.data 61 # number of SCUpgradeReq hits | 1120system.l2c.tags.occ_percent::total 0.946844 # Average percentage of cache occupancy 1121system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 1122system.l2c.tags.occ_task_id_blocks::1024 60392 # Occupied blocks per task id 1123system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 1124system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 1125system.l2c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id 1126system.l2c.tags.age_task_id_blocks_1024::2 1918 # Occupied blocks per task id 1127system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id 1128system.l2c.tags.age_task_id_blocks_1024::4 45390 # Occupied blocks per task id 1129system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 1130system.l2c.tags.occ_task_id_percent::1024 0.921509 # Percentage of cache occupancy per task id 1131system.l2c.tags.tag_accesses 4903951 # Number of tag accesses 1132system.l2c.tags.data_accesses 4903951 # Number of data accesses 1133system.l2c.ReadReq_hits::cpu0.dtb.walker 85 # number of ReadReq hits 1134system.l2c.ReadReq_hits::cpu0.itb.walker 75 # number of ReadReq hits 1135system.l2c.ReadReq_hits::cpu0.inst 28112 # number of ReadReq hits 1136system.l2c.ReadReq_hits::cpu0.data 75977 # number of ReadReq hits 1137system.l2c.ReadReq_hits::cpu1.dtb.walker 41 # number of ReadReq hits 1138system.l2c.ReadReq_hits::cpu1.itb.walker 36 # number of ReadReq hits 1139system.l2c.ReadReq_hits::cpu1.inst 11436 # number of ReadReq hits 1140system.l2c.ReadReq_hits::cpu1.data 11429 # number of ReadReq hits 1141system.l2c.ReadReq_hits::total 127191 # number of ReadReq hits 1142system.l2c.Writeback_hits::writebacks 225760 # number of Writeback hits 1143system.l2c.Writeback_hits::total 225760 # number of Writeback hits 1144system.l2c.UpgradeReq_hits::cpu0.data 516 # number of UpgradeReq hits 1145system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits 1146system.l2c.UpgradeReq_hits::total 573 # number of UpgradeReq hits 1147system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits |
| 1148system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits | 1148system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits |
| 1149system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits 1150system.l2c.ReadExReq_hits::cpu0.data 13793 # number of ReadExReq hits 1151system.l2c.ReadExReq_hits::cpu1.data 3108 # number of ReadExReq hits 1152system.l2c.ReadExReq_hits::total 16901 # number of ReadExReq hits 1153system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits 1154system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits 1155system.l2c.demand_hits::cpu0.inst 28084 # number of demand (read+write) hits 1156system.l2c.demand_hits::cpu0.data 89912 # number of demand (read+write) hits 1157system.l2c.demand_hits::cpu1.dtb.walker 40 # number of demand (read+write) hits 1158system.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits 1159system.l2c.demand_hits::cpu1.inst 11510 # number of demand (read+write) hits 1160system.l2c.demand_hits::cpu1.data 14489 # number of demand (read+write) hits 1161system.l2c.demand_hits::total 144210 # number of demand (read+write) hits 1162system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits 1163system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits 1164system.l2c.overall_hits::cpu0.inst 28084 # number of overall hits 1165system.l2c.overall_hits::cpu0.data 89912 # number of overall hits 1166system.l2c.overall_hits::cpu1.dtb.walker 40 # number of overall hits 1167system.l2c.overall_hits::cpu1.itb.walker 38 # number of overall hits 1168system.l2c.overall_hits::cpu1.inst 11510 # number of overall hits 1169system.l2c.overall_hits::cpu1.data 14489 # number of overall hits 1170system.l2c.overall_hits::total 144210 # number of overall hits | 1149system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits 1150system.l2c.ReadExReq_hits::cpu0.data 13918 # number of ReadExReq hits 1151system.l2c.ReadExReq_hits::cpu1.data 3099 # number of ReadExReq hits 1152system.l2c.ReadExReq_hits::total 17017 # number of ReadExReq hits 1153system.l2c.demand_hits::cpu0.dtb.walker 85 # number of demand (read+write) hits 1154system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits 1155system.l2c.demand_hits::cpu0.inst 28112 # number of demand (read+write) hits 1156system.l2c.demand_hits::cpu0.data 89895 # number of demand (read+write) hits 1157system.l2c.demand_hits::cpu1.dtb.walker 41 # number of demand (read+write) hits 1158system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits 1159system.l2c.demand_hits::cpu1.inst 11436 # number of demand (read+write) hits 1160system.l2c.demand_hits::cpu1.data 14528 # number of demand (read+write) hits 1161system.l2c.demand_hits::total 144208 # number of demand (read+write) hits 1162system.l2c.overall_hits::cpu0.dtb.walker 85 # number of overall hits 1163system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits 1164system.l2c.overall_hits::cpu0.inst 28112 # number of overall hits 1165system.l2c.overall_hits::cpu0.data 89895 # number of overall hits 1166system.l2c.overall_hits::cpu1.dtb.walker 41 # number of overall hits 1167system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits 1168system.l2c.overall_hits::cpu1.inst 11436 # number of overall hits 1169system.l2c.overall_hits::cpu1.data 14528 # number of overall hits 1170system.l2c.overall_hits::total 144208 # number of overall hits |
| 1171system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses 1172system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 1171system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses 1172system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 1173system.l2c.ReadReq_misses::cpu0.inst 16891 # number of ReadReq misses 1174system.l2c.ReadReq_misses::cpu0.data 11305 # number of ReadReq misses | 1173system.l2c.ReadReq_misses::cpu0.inst 16900 # number of ReadReq misses 1174system.l2c.ReadReq_misses::cpu0.data 11311 # number of ReadReq misses |
| 1175system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses | 1175system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses |
| 1176system.l2c.ReadReq_misses::cpu1.inst 2364 # number of ReadReq misses 1177system.l2c.ReadReq_misses::cpu1.data 1123 # number of ReadReq misses 1178system.l2c.ReadReq_misses::total 31694 # number of ReadReq misses 1179system.l2c.UpgradeReq_misses::cpu0.data 10009 # number of UpgradeReq misses 1180system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses 1181system.l2c.UpgradeReq_misses::total 13304 # number of UpgradeReq misses 1182system.l2c.SCUpgradeReq_misses::cpu0.data 759 # number of SCUpgradeReq misses 1183system.l2c.SCUpgradeReq_misses::cpu1.data 1183 # number of SCUpgradeReq misses 1184system.l2c.SCUpgradeReq_misses::total 1942 # number of SCUpgradeReq misses 1185system.l2c.ReadExReq_misses::cpu0.data 136769 # number of ReadExReq misses 1186system.l2c.ReadExReq_misses::cpu1.data 15820 # number of ReadExReq misses 1187system.l2c.ReadExReq_misses::total 152589 # number of ReadExReq misses | 1176system.l2c.ReadReq_misses::cpu1.inst 2371 # number of ReadReq misses 1177system.l2c.ReadReq_misses::cpu1.data 1120 # number of ReadReq misses 1178system.l2c.ReadReq_misses::total 31713 # number of ReadReq misses 1179system.l2c.UpgradeReq_misses::cpu0.data 9991 # number of UpgradeReq misses 1180system.l2c.UpgradeReq_misses::cpu1.data 3299 # number of UpgradeReq misses 1181system.l2c.UpgradeReq_misses::total 13290 # number of UpgradeReq misses 1182system.l2c.SCUpgradeReq_misses::cpu0.data 771 # number of SCUpgradeReq misses 1183system.l2c.SCUpgradeReq_misses::cpu1.data 1177 # number of SCUpgradeReq misses 1184system.l2c.SCUpgradeReq_misses::total 1948 # number of SCUpgradeReq misses 1185system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses 1186system.l2c.ReadExReq_misses::cpu1.data 15826 # number of ReadExReq misses 1187system.l2c.ReadExReq_misses::total 152622 # number of ReadExReq misses |
| 1188system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 1189system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 1188system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 1189system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 1190system.l2c.demand_misses::cpu0.inst 16891 # number of demand (read+write) misses 1191system.l2c.demand_misses::cpu0.data 148074 # number of demand (read+write) misses | 1190system.l2c.demand_misses::cpu0.inst 16900 # number of demand (read+write) misses 1191system.l2c.demand_misses::cpu0.data 148107 # number of demand (read+write) misses |
| 1192system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses | 1192system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses |
| 1193system.l2c.demand_misses::cpu1.inst 2364 # number of demand (read+write) misses 1194system.l2c.demand_misses::cpu1.data 16943 # number of demand (read+write) misses 1195system.l2c.demand_misses::total 184283 # number of demand (read+write) misses | 1193system.l2c.demand_misses::cpu1.inst 2371 # number of demand (read+write) misses 1194system.l2c.demand_misses::cpu1.data 16946 # number of demand (read+write) misses 1195system.l2c.demand_misses::total 184335 # number of demand (read+write) misses |
| 1196system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 1197system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 1196system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 1197system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 1198system.l2c.overall_misses::cpu0.inst 16891 # number of overall misses 1199system.l2c.overall_misses::cpu0.data 148074 # number of overall misses | 1198system.l2c.overall_misses::cpu0.inst 16900 # number of overall misses 1199system.l2c.overall_misses::cpu0.data 148107 # number of overall misses |
| 1200system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses | 1200system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses |
| 1201system.l2c.overall_misses::cpu1.inst 2364 # number of overall misses 1202system.l2c.overall_misses::cpu1.data 16943 # number of overall misses 1203system.l2c.overall_misses::total 184283 # number of overall misses 1204system.l2c.ReadReq_accesses::cpu0.dtb.walker 81 # number of ReadReq accesses(hits+misses) 1205system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) 1206system.l2c.ReadReq_accesses::cpu0.inst 44975 # number of ReadReq accesses(hits+misses) 1207system.l2c.ReadReq_accesses::cpu0.data 87424 # number of ReadReq accesses(hits+misses) 1208system.l2c.ReadReq_accesses::cpu1.dtb.walker 42 # number of ReadReq accesses(hits+misses) 1209system.l2c.ReadReq_accesses::cpu1.itb.walker 38 # number of ReadReq accesses(hits+misses) 1210system.l2c.ReadReq_accesses::cpu1.inst 13874 # number of ReadReq accesses(hits+misses) 1211system.l2c.ReadReq_accesses::cpu1.data 12504 # number of ReadReq accesses(hits+misses) 1212system.l2c.ReadReq_accesses::total 159003 # number of ReadReq accesses(hits+misses) 1213system.l2c.Writeback_accesses::writebacks 225809 # number of Writeback accesses(hits+misses) 1214system.l2c.Writeback_accesses::total 225809 # number of Writeback accesses(hits+misses) 1215system.l2c.UpgradeReq_accesses::cpu0.data 10505 # number of UpgradeReq accesses(hits+misses) 1216system.l2c.UpgradeReq_accesses::cpu1.data 3358 # number of UpgradeReq accesses(hits+misses) | 1201system.l2c.overall_misses::cpu1.inst 2371 # number of overall misses 1202system.l2c.overall_misses::cpu1.data 16946 # number of overall misses 1203system.l2c.overall_misses::total 184335 # number of overall misses 1204system.l2c.ReadReq_accesses::cpu0.dtb.walker 92 # number of ReadReq accesses(hits+misses) 1205system.l2c.ReadReq_accesses::cpu0.itb.walker 77 # number of ReadReq accesses(hits+misses) 1206system.l2c.ReadReq_accesses::cpu0.inst 45012 # number of ReadReq accesses(hits+misses) 1207system.l2c.ReadReq_accesses::cpu0.data 87288 # number of ReadReq accesses(hits+misses) 1208system.l2c.ReadReq_accesses::cpu1.dtb.walker 43 # number of ReadReq accesses(hits+misses) 1209system.l2c.ReadReq_accesses::cpu1.itb.walker 36 # number of ReadReq accesses(hits+misses) 1210system.l2c.ReadReq_accesses::cpu1.inst 13807 # number of ReadReq accesses(hits+misses) 1211system.l2c.ReadReq_accesses::cpu1.data 12549 # number of ReadReq accesses(hits+misses) 1212system.l2c.ReadReq_accesses::total 158904 # number of ReadReq accesses(hits+misses) 1213system.l2c.Writeback_accesses::writebacks 225760 # number of Writeback accesses(hits+misses) 1214system.l2c.Writeback_accesses::total 225760 # number of Writeback accesses(hits+misses) 1215system.l2c.UpgradeReq_accesses::cpu0.data 10507 # number of UpgradeReq accesses(hits+misses) 1216system.l2c.UpgradeReq_accesses::cpu1.data 3356 # number of UpgradeReq accesses(hits+misses) |
| 1217system.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses) | 1217system.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses) |
| 1218system.l2c.SCUpgradeReq_accesses::cpu0.data 820 # number of SCUpgradeReq accesses(hits+misses) 1219system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) 1220system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) 1221system.l2c.ReadExReq_accesses::cpu0.data 150562 # number of ReadExReq accesses(hits+misses) 1222system.l2c.ReadExReq_accesses::cpu1.data 18928 # number of ReadExReq accesses(hits+misses) 1223system.l2c.ReadExReq_accesses::total 169490 # number of ReadExReq accesses(hits+misses) 1224system.l2c.demand_accesses::cpu0.dtb.walker 81 # number of demand (read+write) accesses 1225system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses 1226system.l2c.demand_accesses::cpu0.inst 44975 # number of demand (read+write) accesses 1227system.l2c.demand_accesses::cpu0.data 237986 # number of demand (read+write) accesses 1228system.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses 1229system.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses 1230system.l2c.demand_accesses::cpu1.inst 13874 # number of demand (read+write) accesses 1231system.l2c.demand_accesses::cpu1.data 31432 # number of demand (read+write) accesses 1232system.l2c.demand_accesses::total 328493 # number of demand (read+write) accesses 1233system.l2c.overall_accesses::cpu0.dtb.walker 81 # number of overall (read+write) accesses 1234system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses 1235system.l2c.overall_accesses::cpu0.inst 44975 # number of overall (read+write) accesses 1236system.l2c.overall_accesses::cpu0.data 237986 # number of overall (read+write) accesses 1237system.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses 1238system.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses 1239system.l2c.overall_accesses::cpu1.inst 13874 # number of overall (read+write) accesses 1240system.l2c.overall_accesses::cpu1.data 31432 # number of overall (read+write) accesses 1241system.l2c.overall_accesses::total 328493 # number of overall (read+write) accesses 1242system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for ReadReq accesses 1243system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses 1244system.l2c.ReadReq_miss_rate::cpu0.inst 0.375564 # miss rate for ReadReq accesses 1245system.l2c.ReadReq_miss_rate::cpu0.data 0.129312 # miss rate for ReadReq accesses 1246system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for ReadReq accesses 1247system.l2c.ReadReq_miss_rate::cpu1.inst 0.170391 # miss rate for ReadReq accesses 1248system.l2c.ReadReq_miss_rate::cpu1.data 0.089811 # miss rate for ReadReq accesses 1249system.l2c.ReadReq_miss_rate::total 0.199330 # miss rate for ReadReq accesses 1250system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952784 # miss rate for UpgradeReq accesses 1251system.l2c.UpgradeReq_miss_rate::cpu1.data 0.981239 # miss rate for UpgradeReq accesses 1252system.l2c.UpgradeReq_miss_rate::total 0.959677 # miss rate for UpgradeReq accesses 1253system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.925610 # miss rate for SCUpgradeReq accesses 1254system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992450 # miss rate for SCUpgradeReq accesses 1255system.l2c.SCUpgradeReq_miss_rate::total 0.965209 # miss rate for SCUpgradeReq accesses 1256system.l2c.ReadExReq_miss_rate::cpu0.data 0.908390 # miss rate for ReadExReq accesses 1257system.l2c.ReadExReq_miss_rate::cpu1.data 0.835799 # miss rate for ReadExReq accesses 1258system.l2c.ReadExReq_miss_rate::total 0.900283 # miss rate for ReadExReq accesses 1259system.l2c.demand_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for demand accesses 1260system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses 1261system.l2c.demand_miss_rate::cpu0.inst 0.375564 # miss rate for demand accesses 1262system.l2c.demand_miss_rate::cpu0.data 0.622196 # miss rate for demand accesses 1263system.l2c.demand_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for demand accesses 1264system.l2c.demand_miss_rate::cpu1.inst 0.170391 # miss rate for demand accesses 1265system.l2c.demand_miss_rate::cpu1.data 0.539037 # miss rate for demand accesses 1266system.l2c.demand_miss_rate::total 0.560995 # miss rate for demand accesses 1267system.l2c.overall_miss_rate::cpu0.dtb.walker 0.086420 # miss rate for overall accesses 1268system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses 1269system.l2c.overall_miss_rate::cpu0.inst 0.375564 # miss rate for overall accesses 1270system.l2c.overall_miss_rate::cpu0.data 0.622196 # miss rate for overall accesses 1271system.l2c.overall_miss_rate::cpu1.dtb.walker 0.047619 # miss rate for overall accesses 1272system.l2c.overall_miss_rate::cpu1.inst 0.170391 # miss rate for overall accesses 1273system.l2c.overall_miss_rate::cpu1.data 0.539037 # miss rate for overall accesses 1274system.l2c.overall_miss_rate::total 0.560995 # miss rate for overall accesses | 1218system.l2c.SCUpgradeReq_accesses::cpu0.data 823 # number of SCUpgradeReq accesses(hits+misses) 1219system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) 1220system.l2c.SCUpgradeReq_accesses::total 2009 # number of SCUpgradeReq accesses(hits+misses) 1221system.l2c.ReadExReq_accesses::cpu0.data 150714 # number of ReadExReq accesses(hits+misses) 1222system.l2c.ReadExReq_accesses::cpu1.data 18925 # number of ReadExReq accesses(hits+misses) 1223system.l2c.ReadExReq_accesses::total 169639 # number of ReadExReq accesses(hits+misses) 1224system.l2c.demand_accesses::cpu0.dtb.walker 92 # number of demand (read+write) accesses 1225system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses 1226system.l2c.demand_accesses::cpu0.inst 45012 # number of demand (read+write) accesses 1227system.l2c.demand_accesses::cpu0.data 238002 # number of demand (read+write) accesses 1228system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses 1229system.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses 1230system.l2c.demand_accesses::cpu1.inst 13807 # number of demand (read+write) accesses 1231system.l2c.demand_accesses::cpu1.data 31474 # number of demand (read+write) accesses 1232system.l2c.demand_accesses::total 328543 # number of demand (read+write) accesses 1233system.l2c.overall_accesses::cpu0.dtb.walker 92 # number of overall (read+write) accesses 1234system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses 1235system.l2c.overall_accesses::cpu0.inst 45012 # number of overall (read+write) accesses 1236system.l2c.overall_accesses::cpu0.data 238002 # number of overall (read+write) accesses 1237system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses 1238system.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses 1239system.l2c.overall_accesses::cpu1.inst 13807 # number of overall (read+write) accesses 1240system.l2c.overall_accesses::cpu1.data 31474 # number of overall (read+write) accesses 1241system.l2c.overall_accesses::total 328543 # number of overall (read+write) accesses 1242system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for ReadReq accesses 1243system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadReq accesses 1244system.l2c.ReadReq_miss_rate::cpu0.inst 0.375455 # miss rate for ReadReq accesses 1245system.l2c.ReadReq_miss_rate::cpu0.data 0.129583 # miss rate for ReadReq accesses 1246system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for ReadReq accesses 1247system.l2c.ReadReq_miss_rate::cpu1.inst 0.171724 # miss rate for ReadReq accesses 1248system.l2c.ReadReq_miss_rate::cpu1.data 0.089250 # miss rate for ReadReq accesses 1249system.l2c.ReadReq_miss_rate::total 0.199573 # miss rate for ReadReq accesses 1250system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950890 # miss rate for UpgradeReq accesses 1251system.l2c.UpgradeReq_miss_rate::cpu1.data 0.983015 # miss rate for UpgradeReq accesses 1252system.l2c.UpgradeReq_miss_rate::total 0.958667 # miss rate for UpgradeReq accesses 1253system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.936817 # miss rate for SCUpgradeReq accesses 1254system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992411 # miss rate for SCUpgradeReq accesses 1255system.l2c.SCUpgradeReq_miss_rate::total 0.969637 # miss rate for SCUpgradeReq accesses 1256system.l2c.ReadExReq_miss_rate::cpu0.data 0.907653 # miss rate for ReadExReq accesses 1257system.l2c.ReadExReq_miss_rate::cpu1.data 0.836248 # miss rate for ReadExReq accesses 1258system.l2c.ReadExReq_miss_rate::total 0.899687 # miss rate for ReadExReq accesses 1259system.l2c.demand_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for demand accesses 1260system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses 1261system.l2c.demand_miss_rate::cpu0.inst 0.375455 # miss rate for demand accesses 1262system.l2c.demand_miss_rate::cpu0.data 0.622293 # miss rate for demand accesses 1263system.l2c.demand_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for demand accesses 1264system.l2c.demand_miss_rate::cpu1.inst 0.171724 # miss rate for demand accesses 1265system.l2c.demand_miss_rate::cpu1.data 0.538413 # miss rate for demand accesses 1266system.l2c.demand_miss_rate::total 0.561068 # miss rate for demand accesses 1267system.l2c.overall_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for overall accesses 1268system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses 1269system.l2c.overall_miss_rate::cpu0.inst 0.375455 # miss rate for overall accesses 1270system.l2c.overall_miss_rate::cpu0.data 0.622293 # miss rate for overall accesses 1271system.l2c.overall_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for overall accesses 1272system.l2c.overall_miss_rate::cpu1.inst 0.171724 # miss rate for overall accesses 1273system.l2c.overall_miss_rate::cpu1.data 0.538413 # miss rate for overall accesses 1274system.l2c.overall_miss_rate::total 0.561068 # miss rate for overall accesses |
| 1275system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1276system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1277system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1278system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1279system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1280system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1281system.l2c.fast_writes 0 # number of fast writes performed 1282system.l2c.cache_copies 0 # number of cache copies performed | 1275system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1276system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1277system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1278system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1279system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1280system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1281system.l2c.fast_writes 0 # number of fast writes performed 1282system.l2c.cache_copies 0 # number of cache copies performed |
| 1283system.l2c.writebacks::writebacks 94871 # number of writebacks 1284system.l2c.writebacks::total 94871 # number of writebacks | 1283system.l2c.writebacks::writebacks 94860 # number of writebacks 1284system.l2c.writebacks::total 94860 # number of writebacks |
| 1285system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 1285system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1286system.membus.trans_dist::ReadReq 75959 # Transaction distribution 1287system.membus.trans_dist::ReadResp 75959 # Transaction distribution | 1286system.membus.trans_dist::ReadReq 75978 # Transaction distribution 1287system.membus.trans_dist::ReadResp 75978 # Transaction distribution |
| 1288system.membus.trans_dist::WriteReq 30905 # Transaction distribution 1289system.membus.trans_dist::WriteResp 30905 # Transaction distribution | 1288system.membus.trans_dist::WriteReq 30905 # Transaction distribution 1289system.membus.trans_dist::WriteResp 30905 # Transaction distribution |
| 1290system.membus.trans_dist::Writeback 94871 # Transaction distribution | 1290system.membus.trans_dist::Writeback 131050 # Transaction distribution |
| 1291system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1292system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 1291system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1292system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 1293system.membus.trans_dist::UpgradeReq 60398 # Transaction distribution 1294system.membus.trans_dist::SCUpgradeReq 40937 # Transaction distribution 1295system.membus.trans_dist::UpgradeResp 15640 # Transaction distribution 1296system.membus.trans_dist::ReadExReq 196324 # Transaction distribution 1297system.membus.trans_dist::ReadExResp 152195 # Transaction distribution | 1293system.membus.trans_dist::UpgradeReq 60385 # Transaction distribution 1294system.membus.trans_dist::SCUpgradeReq 40916 # Transaction distribution 1295system.membus.trans_dist::UpgradeResp 15642 # Transaction distribution 1296system.membus.trans_dist::ReadExReq 196304 # Transaction distribution 1297system.membus.trans_dist::ReadExResp 152218 # Transaction distribution |
| 1298system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) 1299system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1300system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) | 1298system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) 1299system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1300system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) |
| 1301system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652163 # Packet count per connected master and slave (bytes) 1302system.membus.pkt_count_system.l2c.mem_side::total 773589 # Packet count per connected master and slave (bytes) 1303system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) 1304system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) 1305system.membus.pkt_count::total 846541 # Packet count per connected master and slave (bytes) | 1301system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652161 # Packet count per connected master and slave (bytes) 1302system.membus.pkt_count_system.l2c.mem_side::total 773587 # Packet count per connected master and slave (bytes) 1303system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes) 1304system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes) 1305system.membus.pkt_count::total 882729 # Packet count per connected master and slave (bytes) |
| 1306system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) 1307system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1308system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) | 1306system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) 1307system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1308system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) |
| 1309system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897572 # Cumulative packet size per connected master and slave (bytes) 1310system.membus.pkt_size_system.l2c.mem_side::total 18087396 # Cumulative packet size per connected master and slave (bytes) 1311system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) 1312system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) 1313system.membus.pkt_size::total 20421860 # Cumulative packet size per connected master and slave (bytes) | 1309system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17899556 # Cumulative packet size per connected master and slave (bytes) 1310system.membus.pkt_size_system.l2c.mem_side::total 18089380 # Cumulative packet size per connected master and slave (bytes) 1311system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes) 1312system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes) 1313system.membus.pkt_size::total 22740004 # Cumulative packet size per connected master and slave (bytes) |
| 1314system.membus.snoops 0 # Total snoops (count) | 1314system.membus.snoops 0 # Total snoops (count) |
| 1315system.membus.snoop_fanout::samples 460700 # Request fanout histogram | 1315system.membus.snoop_fanout::samples 496844 # Request fanout histogram |
| 1316system.membus.snoop_fanout::mean 1 # Request fanout histogram 1317system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1318system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1319system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1316system.membus.snoop_fanout::mean 1 # Request fanout histogram 1317system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1318system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1319system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1320system.membus.snoop_fanout::1 460700 100.00% 100.00% # Request fanout histogram | 1320system.membus.snoop_fanout::1 496844 100.00% 100.00% # Request fanout histogram |
| 1321system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1322system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1323system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1324system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1321system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1322system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1323system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1324system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1325system.membus.snoop_fanout::total 460700 # Request fanout histogram | 1325system.membus.snoop_fanout::total 496844 # Request fanout histogram |
| 1326system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1327system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1328system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1329system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1330system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1331system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1332system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1333system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1349system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1350system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1351system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1352system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1353system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1354system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1355system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1356system.realview.ethernet.droppedPackets 0 # number of packets dropped | 1326system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1327system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1328system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1329system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1330system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1331system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1332system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1333system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1349system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1350system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1351system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1352system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1353system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1354system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1355system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1356system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1357system.toL2Bus.trans_dist::ReadReq 305363 # Transaction distribution 1358system.toL2Bus.trans_dist::ReadResp 305363 # Transaction distribution | 1357system.toL2Bus.trans_dist::ReadReq 305179 # Transaction distribution 1358system.toL2Bus.trans_dist::ReadResp 305179 # Transaction distribution |
| 1359system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution 1360system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution | 1359system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution 1360system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution |
| 1361system.toL2Bus.trans_dist::Writeback 225809 # Transaction distribution 1362system.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution 1363system.toL2Bus.trans_dist::SCUpgradeReq 41007 # Transaction distribution 1364system.toL2Bus.trans_dist::UpgradeResp 101570 # Transaction distribution 1365system.toL2Bus.trans_dist::ReadExReq 213619 # Transaction distribution 1366system.toL2Bus.trans_dist::ReadExResp 213619 # Transaction distribution 1367system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117852 # Packet count per connected master and slave (bytes) 1368system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410871 # Packet count per connected master and slave (bytes) 1369system.toL2Bus.pkt_count::total 1528723 # Packet count per connected master and slave (bytes) 1370system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34663730 # Cumulative packet size per connected master and slave (bytes) 1371system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432818 # Cumulative packet size per connected master and slave (bytes) 1372system.toL2Bus.pkt_size::total 45096548 # Cumulative packet size per connected master and slave (bytes) | 1361system.toL2Bus.trans_dist::Writeback 225760 # Transaction distribution 1362system.toL2Bus.trans_dist::UpgradeReq 60554 # Transaction distribution 1363system.toL2Bus.trans_dist::SCUpgradeReq 40977 # Transaction distribution 1364system.toL2Bus.trans_dist::UpgradeResp 101531 # Transaction distribution 1365system.toL2Bus.trans_dist::ReadExReq 213725 # Transaction distribution 1366system.toL2Bus.trans_dist::ReadExResp 213725 # Transaction distribution 1367system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117779 # Packet count per connected master and slave (bytes) 1368system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes) 1369system.toL2Bus.pkt_count::total 1528440 # Packet count per connected master and slave (bytes) 1370system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34662706 # Cumulative packet size per connected master and slave (bytes) 1371system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425714 # Cumulative packet size per connected master and slave (bytes) 1372system.toL2Bus.pkt_size::total 45088420 # Cumulative packet size per connected master and slave (bytes) |
| 1373system.toL2Bus.snoops 36713 # Total snoops (count) | 1373system.toL2Bus.snoops 36713 # Total snoops (count) |
| 1374system.toL2Bus.snoop_fanout::samples 838824 # Request fanout histogram 1375system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram 1376system.toL2Bus.snoop_fanout::stdev 0.203946 # Request fanout histogram | 1374system.toL2Bus.snoop_fanout::samples 838658 # Request fanout histogram 1375system.toL2Bus.snoop_fanout::mean 1.043493 # Request fanout histogram 1376system.toL2Bus.snoop_fanout::stdev 0.203965 # Request fanout histogram |
| 1377system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1378system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1377system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1378system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1379system.toL2Bus.snoop_fanout::1 802348 95.65% 95.65% # Request fanout histogram | 1379system.toL2Bus.snoop_fanout::1 802182 95.65% 95.65% # Request fanout histogram |
| 1380system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram 1381system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1382system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1383system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1380system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram 1381system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1382system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1383system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1384system.toL2Bus.snoop_fanout::total 838824 # Request fanout histogram | 1384system.toL2Bus.snoop_fanout::total 838658 # Request fanout histogram |
| 1385 1386---------- End Simulation Statistics ---------- | 1385 1386---------- End Simulation Statistics ---------- |