| stats.txt (10513:ca4438b6e39a) | stats.txt (10517:ba51f8572571) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.802882 # Number of seconds simulated 4sim_ticks 2802882496500 # Number of ticks simulated 5final_tick 2802882496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882713500 # Number of ticks simulated 5final_tick 2802882713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1330236 # Simulator instruction rate (inst/s) 8host_op_rate 1620871 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25395755903 # Simulator tick rate (ticks/s) 10host_mem_usage 564312 # Number of bytes of host memory used 11host_seconds 110.37 # Real time elapsed on the host 12sim_insts 146815698 # Number of instructions simulated 13sim_ops 178892459 # Number of ops (including micro ops) simulated | 7host_inst_rate 1349319 # Simulator instruction rate (inst/s) 8host_op_rate 1644123 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25757810314 # Simulator tick rate (ticks/s) 10host_mem_usage 564420 # Number of bytes of host memory used 11host_seconds 108.82 # Real time elapsed on the host 12sim_insts 146828498 # Number of instructions simulated 13sim_ops 178908222 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 19 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 19 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 19 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s) | |
| 34system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory | 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory |
| 35system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory |
| 36system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 37system.physmem.bytes_read::cpu0.inst 1117476 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 9458684 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu0.inst 1116900 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 9456508 # Number of bytes read from this memory |
| 39system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory | 21system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory |
| 40system.physmem.bytes_read::cpu1.inst 149780 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.data 1082912 # Number of bytes read from this memory 42system.physmem.bytes_read::total 11810580 # Number of bytes read from this memory 43system.physmem.bytes_inst_read::cpu0.inst 1117476 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::cpu1.inst 149780 # Number of instructions bytes read from this memory 45system.physmem.bytes_inst_read::total 1267256 # Number of instructions bytes read from this memory 46system.physmem.bytes_written::writebacks 6081216 # Number of bytes written to this memory | 22system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 1081824 # Number of bytes read from this memory 24system.physmem.bytes_read::total 11808788 # Number of bytes read from this memory 25system.physmem.bytes_inst_read::cpu0.inst 1116900 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory 27system.physmem.bytes_inst_read::total 1268792 # Number of instructions bytes read from this memory 28system.physmem.bytes_written::writebacks 6072384 # Number of bytes written to this memory |
| 47system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 48system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 49system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 29system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 30system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 50system.physmem.bytes_written::total 8417296 # Number of bytes written to this memory | 32system.physmem.bytes_written::total 8408464 # Number of bytes written to this memory |
| 51system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory | 33system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory |
| 52system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory | 34system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory |
| 53system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 54system.physmem.num_reads::cpu0.inst 25914 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu0.data 148317 # Number of read requests responded to by this memory | 36system.physmem.num_reads::cpu0.inst 25905 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 148283 # Number of read requests responded to by this memory |
| 56system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory | 38system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory |
| 57system.physmem.num_reads::cpu1.inst 2495 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu1.data 16944 # Number of read requests responded to by this memory 59system.physmem.num_reads::total 193697 # Number of read requests responded to by this memory 60system.physmem.num_writes::writebacks 95019 # Number of write requests responded to by this memory | 39system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.data 16927 # Number of read requests responded to by this memory 41system.physmem.num_reads::total 193669 # Number of read requests responded to by this memory 42system.physmem.num_writes::writebacks 94881 # Number of write requests responded to by this memory |
| 61system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 62system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 63system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 43system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 44system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory 45system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 64system.physmem.num_writes::total 135679 # Number of write requests responded to by this memory | 46system.physmem.num_writes::total 135541 # Number of write requests responded to by this memory |
| 65system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) | 47system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) |
| 66system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) | 48system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) |
| 67system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) | 49system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) |
| 68system.physmem.bw_read::cpu0.inst 398688 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu0.data 3374627 # Total read bandwidth from this memory (bytes/s) | 50system.physmem.bw_read::cpu0.inst 398483 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.data 3373851 # Total read bandwidth from this memory (bytes/s) |
| 70system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) | 52system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) |
| 71system.physmem.bw_read::cpu1.inst 53438 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu1.data 386357 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::total 4213726 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_inst_read::cpu0.inst 398688 # Instruction read bandwidth from this memory (bytes/s) 75system.physmem.bw_inst_read::cpu1.inst 53438 # Instruction read bandwidth from this memory (bytes/s) 76system.physmem.bw_inst_read::total 452126 # Instruction read bandwidth from this memory (bytes/s) 77system.physmem.bw_write::writebacks 2169629 # Write bandwidth from this memory (bytes/s) | 53system.physmem.bw_read::cpu1.inst 54191 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.data 385968 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::total 4213087 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_inst_read::cpu0.inst 398483 # Instruction read bandwidth from this memory (bytes/s) 57system.physmem.bw_inst_read::cpu1.inst 54191 # Instruction read bandwidth from this memory (bytes/s) 58system.physmem.bw_inst_read::total 452674 # Instruction read bandwidth from this memory (bytes/s) 59system.physmem.bw_write::writebacks 2166478 # Write bandwidth from this memory (bytes/s) |
| 78system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) 80system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) | 60system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) 61system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) 62system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) |
| 81system.physmem.bw_write::total 3003086 # Write bandwidth from this memory (bytes/s) 82system.physmem.bw_total::writebacks 2169629 # Total bandwidth to/from this memory (bytes/s) | 63system.physmem.bw_write::total 2999934 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_total::writebacks 2166478 # Total bandwidth to/from this memory (bytes/s) |
| 83system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) | 65system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) |
| 84system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) | 66system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) |
| 85system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) | 67system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) |
| 86system.physmem.bw_total::cpu0.inst 398688 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu0.data 3380944 # Total bandwidth to/from this memory (bytes/s) | 68system.physmem.bw_total::cpu0.inst 398483 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.data 3380167 # Total bandwidth to/from this memory (bytes/s) |
| 88system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) | 70system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) |
| 89system.physmem.bw_total::cpu1.inst 53438 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::cpu1.data 386371 # Total bandwidth to/from this memory (bytes/s) 91system.physmem.bw_total::total 7216812 # Total bandwidth to/from this memory (bytes/s) 92system.membus.trans_dist::ReadReq 75963 # Transaction distribution 93system.membus.trans_dist::ReadResp 75963 # Transaction distribution 94system.membus.trans_dist::WriteReq 30903 # Transaction distribution 95system.membus.trans_dist::WriteResp 30903 # Transaction distribution 96system.membus.trans_dist::Writeback 95019 # Transaction distribution | 71system.physmem.bw_total::cpu1.inst 54191 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu1.data 385983 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::total 7213021 # Total bandwidth to/from this memory (bytes/s) 74system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 75system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 76system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 77system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 78system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 79system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 80system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 81system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 82system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 83system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 85system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 86system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 87system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 88system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 89system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 90system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 91system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 92system.membus.trans_dist::ReadReq 75957 # Transaction distribution 93system.membus.trans_dist::ReadResp 75957 # Transaction distribution 94system.membus.trans_dist::WriteReq 30905 # Transaction distribution 95system.membus.trans_dist::WriteResp 30905 # Transaction distribution 96system.membus.trans_dist::Writeback 94881 # Transaction distribution |
| 97system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 98system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution | 97system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 98system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution |
| 99system.membus.trans_dist::UpgradeReq 60332 # Transaction distribution 100system.membus.trans_dist::SCUpgradeReq 40886 # Transaction distribution 101system.membus.trans_dist::UpgradeResp 15607 # Transaction distribution 102system.membus.trans_dist::ReadExReq 196321 # Transaction distribution 103system.membus.trans_dist::ReadExResp 152216 # Transaction distribution | 99system.membus.trans_dist::UpgradeReq 60384 # Transaction distribution 100system.membus.trans_dist::SCUpgradeReq 40930 # Transaction distribution 101system.membus.trans_dist::UpgradeResp 15620 # Transaction distribution 102system.membus.trans_dist::ReadExReq 196326 # Transaction distribution 103system.membus.trans_dist::ReadExResp 152193 # Transaction distribution |
| 104system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) | 104system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) |
| 105system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) 106system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) 107system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652185 # Packet count per connected master and slave (bytes) 108system.membus.pkt_count_system.l2c.mem_side::total 773609 # Packet count per connected master and slave (bytes) | 105system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 106system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 107system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652128 # Packet count per connected master and slave (bytes) 108system.membus.pkt_count_system.l2c.mem_side::total 773554 # Packet count per connected master and slave (bytes) |
| 109system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) 110system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) | 109system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) 110system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) |
| 111system.membus.pkt_count::total 846561 # Packet count per connected master and slave (bytes) | 111system.membus.pkt_count::total 846506 # Packet count per connected master and slave (bytes) |
| 112system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) | 112system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) |
| 113system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes) 114system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) 115system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17908580 # Cumulative packet size per connected master and slave (bytes) 116system.membus.pkt_size_system.l2c.mem_side::total 18098400 # Cumulative packet size per connected master and slave (bytes) | 113system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 114system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 115system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897956 # Cumulative packet size per connected master and slave (bytes) 116system.membus.pkt_size_system.l2c.mem_side::total 18087780 # Cumulative packet size per connected master and slave (bytes) |
| 117system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) 118system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) | 117system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) 118system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) |
| 119system.membus.pkt_size::total 20432864 # Cumulative packet size per connected master and slave (bytes) | 119system.membus.pkt_size::total 20422244 # Cumulative packet size per connected master and slave (bytes) |
| 120system.membus.snoops 0 # Total snoops (count) | 120system.membus.snoops 0 # Total snoops (count) |
| 121system.membus.snoop_fanout::samples 460731 # Request fanout histogram | 121system.membus.snoop_fanout::samples 460689 # Request fanout histogram |
| 122system.membus.snoop_fanout::mean 1 # Request fanout histogram 123system.membus.snoop_fanout::stdev 0 # Request fanout histogram 124system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 125system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 122system.membus.snoop_fanout::mean 1 # Request fanout histogram 123system.membus.snoop_fanout::stdev 0 # Request fanout histogram 124system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 125system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 126system.membus.snoop_fanout::1 460731 100.00% 100.00% # Request fanout histogram | 126system.membus.snoop_fanout::1 460689 100.00% 100.00% # Request fanout histogram |
| 127system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 128system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 129system.membus.snoop_fanout::min_value 1 # Request fanout histogram 130system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 127system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 128system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 129system.membus.snoop_fanout::min_value 1 # Request fanout histogram 130system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 131system.membus.snoop_fanout::total 460731 # Request fanout histogram | 131system.membus.snoop_fanout::total 460689 # Request fanout histogram |
| 132system.cpu_clk_domain.clock 500 # Clock period in ticks | 132system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 133system.l2c.tags.replacements 107723 # number of replacements 134system.l2c.tags.tagsinuse 62123.921751 # Cycle average of tags in use 135system.l2c.tags.total_refs 208051 # Total number of references to valid blocks. 136system.l2c.tags.sampled_refs 168144 # Sample count of references to valid blocks. 137system.l2c.tags.avg_refs 1.237338 # Average number of references to valid blocks. | 133system.l2c.tags.replacements 107632 # number of replacements 134system.l2c.tags.tagsinuse 62143.934871 # Cycle average of tags in use 135system.l2c.tags.total_refs 207938 # Total number of references to valid blocks. 136system.l2c.tags.sampled_refs 168025 # Sample count of references to valid blocks. 137system.l2c.tags.avg_refs 1.237542 # Average number of references to valid blocks. |
| 138system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 138system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 139system.l2c.tags.occ_blocks::writebacks 48622.171138 # Average occupied blocks per requestor 140system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.975943 # Average occupied blocks per requestor | 139system.l2c.tags.occ_blocks::writebacks 48688.027343 # Average occupied blocks per requestor 140system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor |
| 141system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor | 141system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor |
| 142system.l2c.tags.occ_blocks::cpu0.inst 7348.709599 # Average occupied blocks per requestor 143system.l2c.tags.occ_blocks::cpu0.data 3778.182164 # Average occupied blocks per requestor 144system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823425 # Average occupied blocks per requestor 145system.l2c.tags.occ_blocks::cpu1.inst 1628.255131 # Average occupied blocks per requestor 146system.l2c.tags.occ_blocks::cpu1.data 741.773959 # Average occupied blocks per requestor 147system.l2c.tags.occ_percent::writebacks 0.741915 # Average percentage of cache occupancy | 142system.l2c.tags.occ_blocks::cpu0.inst 7324.741121 # Average occupied blocks per requestor 143system.l2c.tags.occ_blocks::cpu0.data 3758.950125 # Average occupied blocks per requestor 144system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor 145system.l2c.tags.occ_blocks::cpu1.inst 1656.363289 # Average occupied blocks per requestor 146system.l2c.tags.occ_blocks::cpu1.data 711.020717 # Average occupied blocks per requestor 147system.l2c.tags.occ_percent::writebacks 0.742920 # Average percentage of cache occupancy |
| 148system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 149system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy | 148system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 149system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy |
| 150system.l2c.tags.occ_percent::cpu0.inst 0.112132 # Average percentage of cache occupancy 151system.l2c.tags.occ_percent::cpu0.data 0.057650 # Average percentage of cache occupancy | 150system.l2c.tags.occ_percent::cpu0.inst 0.111767 # Average percentage of cache occupancy 151system.l2c.tags.occ_percent::cpu0.data 0.057357 # Average percentage of cache occupancy |
| 152system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy | 152system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy |
| 153system.l2c.tags.occ_percent::cpu1.inst 0.024845 # Average percentage of cache occupancy 154system.l2c.tags.occ_percent::cpu1.data 0.011319 # Average percentage of cache occupancy 155system.l2c.tags.occ_percent::total 0.947936 # Average percentage of cache occupancy 156system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 157system.l2c.tags.occ_task_id_blocks::1024 60415 # Occupied blocks per task id 158system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 159system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id | 153system.l2c.tags.occ_percent::cpu1.inst 0.025274 # Average percentage of cache occupancy 154system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy 155system.l2c.tags.occ_percent::total 0.948241 # Average percentage of cache occupancy 156system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 157system.l2c.tags.occ_task_id_blocks::1024 60384 # Occupied blocks per task id 158system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 159system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 160system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id |
| 160system.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id | 161system.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id |
| 161system.l2c.tags.age_task_id_blocks_1024::2 1884 # Occupied blocks per task id 162system.l2c.tags.age_task_id_blocks_1024::3 13069 # Occupied blocks per task id 163system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id 164system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 165system.l2c.tags.occ_task_id_percent::1024 0.921860 # Percentage of cache occupancy per task id 166system.l2c.tags.tag_accesses 4905185 # Number of tag accesses 167system.l2c.tags.data_accesses 4905185 # Number of data accesses 168system.l2c.ReadReq_hits::cpu0.dtb.walker 79 # number of ReadReq hits 169system.l2c.ReadReq_hits::cpu0.itb.walker 74 # number of ReadReq hits 170system.l2c.ReadReq_hits::cpu0.inst 28057 # number of ReadReq hits 171system.l2c.ReadReq_hits::cpu0.data 75985 # number of ReadReq hits 172system.l2c.ReadReq_hits::cpu1.dtb.walker 42 # number of ReadReq hits 173system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits 174system.l2c.ReadReq_hits::cpu1.inst 11512 # number of ReadReq hits 175system.l2c.ReadReq_hits::cpu1.data 11347 # number of ReadReq hits 176system.l2c.ReadReq_hits::total 127129 # number of ReadReq hits 177system.l2c.Writeback_hits::writebacks 225966 # number of Writeback hits 178system.l2c.Writeback_hits::total 225966 # number of Writeback hits 179system.l2c.UpgradeReq_hits::cpu0.data 512 # number of UpgradeReq hits | 162system.l2c.tags.age_task_id_blocks_1024::2 1906 # Occupied blocks per task id 163system.l2c.tags.age_task_id_blocks_1024::3 12994 # Occupied blocks per task id 164system.l2c.tags.age_task_id_blocks_1024::4 45387 # Occupied blocks per task id 165system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id 166system.l2c.tags.occ_task_id_percent::1024 0.921387 # Percentage of cache occupancy per task id 167system.l2c.tags.tag_accesses 4903910 # Number of tag accesses 168system.l2c.tags.data_accesses 4903910 # Number of data accesses 169system.l2c.ReadReq_hits::cpu0.dtb.walker 69 # number of ReadReq hits 170system.l2c.ReadReq_hits::cpu0.itb.walker 59 # number of ReadReq hits 171system.l2c.ReadReq_hits::cpu0.inst 28044 # number of ReadReq hits 172system.l2c.ReadReq_hits::cpu0.data 76113 # number of ReadReq hits 173system.l2c.ReadReq_hits::cpu1.dtb.walker 38 # number of ReadReq hits 174system.l2c.ReadReq_hits::cpu1.itb.walker 35 # number of ReadReq hits 175system.l2c.ReadReq_hits::cpu1.inst 11456 # number of ReadReq hits 176system.l2c.ReadReq_hits::cpu1.data 11379 # number of ReadReq hits 177system.l2c.ReadReq_hits::total 127193 # number of ReadReq hits 178system.l2c.Writeback_hits::writebacks 225882 # number of Writeback hits 179system.l2c.Writeback_hits::total 225882 # number of Writeback hits 180system.l2c.UpgradeReq_hits::cpu0.data 506 # number of UpgradeReq hits |
| 180system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits | 181system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits |
| 181system.l2c.UpgradeReq_hits::total 577 # number of UpgradeReq hits 182system.l2c.SCUpgradeReq_hits::cpu0.data 56 # number of SCUpgradeReq hits 183system.l2c.SCUpgradeReq_hits::cpu1.data 11 # number of SCUpgradeReq hits 184system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits 185system.l2c.ReadExReq_hits::cpu0.data 13971 # number of ReadExReq hits 186system.l2c.ReadExReq_hits::cpu1.data 3083 # number of ReadExReq hits 187system.l2c.ReadExReq_hits::total 17054 # number of ReadExReq hits 188system.l2c.demand_hits::cpu0.dtb.walker 79 # number of demand (read+write) hits 189system.l2c.demand_hits::cpu0.itb.walker 74 # number of demand (read+write) hits 190system.l2c.demand_hits::cpu0.inst 28057 # number of demand (read+write) hits 191system.l2c.demand_hits::cpu0.data 89956 # number of demand (read+write) hits 192system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits 193system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits 194system.l2c.demand_hits::cpu1.inst 11512 # number of demand (read+write) hits 195system.l2c.demand_hits::cpu1.data 14430 # number of demand (read+write) hits 196system.l2c.demand_hits::total 144183 # number of demand (read+write) hits 197system.l2c.overall_hits::cpu0.dtb.walker 79 # number of overall hits 198system.l2c.overall_hits::cpu0.itb.walker 74 # number of overall hits 199system.l2c.overall_hits::cpu0.inst 28057 # number of overall hits 200system.l2c.overall_hits::cpu0.data 89956 # number of overall hits 201system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits 202system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits 203system.l2c.overall_hits::cpu1.inst 11512 # number of overall hits 204system.l2c.overall_hits::cpu1.data 14430 # number of overall hits 205system.l2c.overall_hits::total 144183 # number of overall hits 206system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses | 182system.l2c.UpgradeReq_hits::total 571 # number of UpgradeReq hits 183system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits 184system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits 185system.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits 186system.l2c.ReadExReq_hits::cpu0.data 13825 # number of ReadExReq hits 187system.l2c.ReadExReq_hits::cpu1.data 3137 # number of ReadExReq hits 188system.l2c.ReadExReq_hits::total 16962 # number of ReadExReq hits 189system.l2c.demand_hits::cpu0.dtb.walker 69 # number of demand (read+write) hits 190system.l2c.demand_hits::cpu0.itb.walker 59 # number of demand (read+write) hits 191system.l2c.demand_hits::cpu0.inst 28044 # number of demand (read+write) hits 192system.l2c.demand_hits::cpu0.data 89938 # number of demand (read+write) hits 193system.l2c.demand_hits::cpu1.dtb.walker 38 # number of demand (read+write) hits 194system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits 195system.l2c.demand_hits::cpu1.inst 11456 # number of demand (read+write) hits 196system.l2c.demand_hits::cpu1.data 14516 # number of demand (read+write) hits 197system.l2c.demand_hits::total 144155 # number of demand (read+write) hits 198system.l2c.overall_hits::cpu0.dtb.walker 69 # number of overall hits 199system.l2c.overall_hits::cpu0.itb.walker 59 # number of overall hits 200system.l2c.overall_hits::cpu0.inst 28044 # number of overall hits 201system.l2c.overall_hits::cpu0.data 89938 # number of overall hits 202system.l2c.overall_hits::cpu1.dtb.walker 38 # number of overall hits 203system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits 204system.l2c.overall_hits::cpu1.inst 11456 # number of overall hits 205system.l2c.overall_hits::cpu1.data 14516 # number of overall hits 206system.l2c.overall_hits::total 144155 # number of overall hits 207system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses |
| 207system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 208system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 208system.l2c.ReadReq_misses::cpu0.inst 16897 # number of ReadReq misses 209system.l2c.ReadReq_misses::cpu0.data 11316 # number of ReadReq misses | 209system.l2c.ReadReq_misses::cpu0.inst 16888 # number of ReadReq misses 210system.l2c.ReadReq_misses::cpu0.data 11308 # number of ReadReq misses |
| 210system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses | 211system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses |
| 211system.l2c.ReadReq_misses::cpu1.inst 2330 # number of ReadReq misses 212system.l2c.ReadReq_misses::cpu1.data 1142 # number of ReadReq misses 213system.l2c.ReadReq_misses::total 31697 # number of ReadReq misses 214system.l2c.UpgradeReq_misses::cpu0.data 9967 # number of UpgradeReq misses 215system.l2c.UpgradeReq_misses::cpu1.data 3302 # number of UpgradeReq misses 216system.l2c.UpgradeReq_misses::total 13269 # number of UpgradeReq misses 217system.l2c.SCUpgradeReq_misses::cpu0.data 763 # number of SCUpgradeReq misses 218system.l2c.SCUpgradeReq_misses::cpu1.data 1181 # number of SCUpgradeReq misses 219system.l2c.SCUpgradeReq_misses::total 1944 # number of SCUpgradeReq misses 220system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses 221system.l2c.ReadExReq_misses::cpu1.data 15814 # number of ReadExReq misses 222system.l2c.ReadExReq_misses::total 152610 # number of ReadExReq misses 223system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses | 212system.l2c.ReadReq_misses::cpu1.inst 2363 # number of ReadReq misses 213system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses 214system.l2c.ReadReq_misses::total 31692 # number of ReadReq misses 215system.l2c.UpgradeReq_misses::cpu0.data 9982 # number of UpgradeReq misses 216system.l2c.UpgradeReq_misses::cpu1.data 3290 # number of UpgradeReq misses 217system.l2c.UpgradeReq_misses::total 13272 # number of UpgradeReq misses 218system.l2c.SCUpgradeReq_misses::cpu0.data 756 # number of SCUpgradeReq misses 219system.l2c.SCUpgradeReq_misses::cpu1.data 1185 # number of SCUpgradeReq misses 220system.l2c.SCUpgradeReq_misses::total 1941 # number of SCUpgradeReq misses 221system.l2c.ReadExReq_misses::cpu0.data 136781 # number of ReadExReq misses 222system.l2c.ReadExReq_misses::cpu1.data 15819 # number of ReadExReq misses 223system.l2c.ReadExReq_misses::total 152600 # number of ReadExReq misses 224system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses |
| 224system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 225system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 225system.l2c.demand_misses::cpu0.inst 16897 # number of demand (read+write) misses 226system.l2c.demand_misses::cpu0.data 148112 # number of demand (read+write) misses | 226system.l2c.demand_misses::cpu0.inst 16888 # number of demand (read+write) misses 227system.l2c.demand_misses::cpu0.data 148089 # number of demand (read+write) misses |
| 227system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses | 228system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses |
| 228system.l2c.demand_misses::cpu1.inst 2330 # number of demand (read+write) misses 229system.l2c.demand_misses::cpu1.data 16956 # number of demand (read+write) misses 230system.l2c.demand_misses::total 184307 # number of demand (read+write) misses 231system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses | 229system.l2c.demand_misses::cpu1.inst 2363 # number of demand (read+write) misses 230system.l2c.demand_misses::cpu1.data 16941 # number of demand (read+write) misses 231system.l2c.demand_misses::total 184292 # number of demand (read+write) misses 232system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses |
| 232system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 233system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 233system.l2c.overall_misses::cpu0.inst 16897 # number of overall misses 234system.l2c.overall_misses::cpu0.data 148112 # number of overall misses | 234system.l2c.overall_misses::cpu0.inst 16888 # number of overall misses 235system.l2c.overall_misses::cpu0.data 148089 # number of overall misses |
| 235system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses | 236system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses |
| 236system.l2c.overall_misses::cpu1.inst 2330 # number of overall misses 237system.l2c.overall_misses::cpu1.data 16956 # number of overall misses 238system.l2c.overall_misses::total 184307 # number of overall misses 239system.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses) 240system.l2c.ReadReq_accesses::cpu0.itb.walker 76 # number of ReadReq accesses(hits+misses) 241system.l2c.ReadReq_accesses::cpu0.inst 44954 # number of ReadReq accesses(hits+misses) 242system.l2c.ReadReq_accesses::cpu0.data 87301 # number of ReadReq accesses(hits+misses) 243system.l2c.ReadReq_accesses::cpu1.dtb.walker 44 # number of ReadReq accesses(hits+misses) 244system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses) 245system.l2c.ReadReq_accesses::cpu1.inst 13842 # number of ReadReq accesses(hits+misses) 246system.l2c.ReadReq_accesses::cpu1.data 12489 # number of ReadReq accesses(hits+misses) 247system.l2c.ReadReq_accesses::total 158826 # number of ReadReq accesses(hits+misses) 248system.l2c.Writeback_accesses::writebacks 225966 # number of Writeback accesses(hits+misses) 249system.l2c.Writeback_accesses::total 225966 # number of Writeback accesses(hits+misses) 250system.l2c.UpgradeReq_accesses::cpu0.data 10479 # number of UpgradeReq accesses(hits+misses) 251system.l2c.UpgradeReq_accesses::cpu1.data 3367 # number of UpgradeReq accesses(hits+misses) 252system.l2c.UpgradeReq_accesses::total 13846 # number of UpgradeReq accesses(hits+misses) 253system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) 254system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) 255system.l2c.SCUpgradeReq_accesses::total 2011 # number of SCUpgradeReq accesses(hits+misses) 256system.l2c.ReadExReq_accesses::cpu0.data 150767 # number of ReadExReq accesses(hits+misses) 257system.l2c.ReadExReq_accesses::cpu1.data 18897 # number of ReadExReq accesses(hits+misses) 258system.l2c.ReadExReq_accesses::total 169664 # number of ReadExReq accesses(hits+misses) 259system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses 260system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses 261system.l2c.demand_accesses::cpu0.inst 44954 # number of demand (read+write) accesses 262system.l2c.demand_accesses::cpu0.data 238068 # number of demand (read+write) accesses 263system.l2c.demand_accesses::cpu1.dtb.walker 44 # number of demand (read+write) accesses 264system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses 265system.l2c.demand_accesses::cpu1.inst 13842 # number of demand (read+write) accesses 266system.l2c.demand_accesses::cpu1.data 31386 # number of demand (read+write) accesses 267system.l2c.demand_accesses::total 328490 # number of demand (read+write) accesses 268system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses 269system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses 270system.l2c.overall_accesses::cpu0.inst 44954 # number of overall (read+write) accesses 271system.l2c.overall_accesses::cpu0.data 238068 # number of overall (read+write) accesses 272system.l2c.overall_accesses::cpu1.dtb.walker 44 # number of overall (read+write) accesses 273system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses 274system.l2c.overall_accesses::cpu1.inst 13842 # number of overall (read+write) accesses 275system.l2c.overall_accesses::cpu1.data 31386 # number of overall (read+write) accesses 276system.l2c.overall_accesses::total 328490 # number of overall (read+write) accesses 277system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses 278system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.026316 # miss rate for ReadReq accesses 279system.l2c.ReadReq_miss_rate::cpu0.inst 0.375873 # miss rate for ReadReq accesses 280system.l2c.ReadReq_miss_rate::cpu0.data 0.129621 # miss rate for ReadReq accesses 281system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses 282system.l2c.ReadReq_miss_rate::cpu1.inst 0.168328 # miss rate for ReadReq accesses 283system.l2c.ReadReq_miss_rate::cpu1.data 0.091440 # miss rate for ReadReq accesses 284system.l2c.ReadReq_miss_rate::total 0.199571 # miss rate for ReadReq accesses 285system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951140 # miss rate for UpgradeReq accesses 286system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980695 # miss rate for UpgradeReq accesses 287system.l2c.UpgradeReq_miss_rate::total 0.958327 # miss rate for UpgradeReq accesses 288system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.931624 # miss rate for SCUpgradeReq accesses 289system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.990772 # miss rate for SCUpgradeReq accesses 290system.l2c.SCUpgradeReq_miss_rate::total 0.966683 # miss rate for SCUpgradeReq accesses 291system.l2c.ReadExReq_miss_rate::cpu0.data 0.907334 # miss rate for ReadExReq accesses 292system.l2c.ReadExReq_miss_rate::cpu1.data 0.836852 # miss rate for ReadExReq accesses 293system.l2c.ReadExReq_miss_rate::total 0.899484 # miss rate for ReadExReq accesses 294system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses 295system.l2c.demand_miss_rate::cpu0.itb.walker 0.026316 # miss rate for demand accesses 296system.l2c.demand_miss_rate::cpu0.inst 0.375873 # miss rate for demand accesses 297system.l2c.demand_miss_rate::cpu0.data 0.622142 # miss rate for demand accesses 298system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses 299system.l2c.demand_miss_rate::cpu1.inst 0.168328 # miss rate for demand accesses 300system.l2c.demand_miss_rate::cpu1.data 0.540241 # miss rate for demand accesses 301system.l2c.demand_miss_rate::total 0.561073 # miss rate for demand accesses 302system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses 303system.l2c.overall_miss_rate::cpu0.itb.walker 0.026316 # miss rate for overall accesses 304system.l2c.overall_miss_rate::cpu0.inst 0.375873 # miss rate for overall accesses 305system.l2c.overall_miss_rate::cpu0.data 0.622142 # miss rate for overall accesses 306system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses 307system.l2c.overall_miss_rate::cpu1.inst 0.168328 # miss rate for overall accesses 308system.l2c.overall_miss_rate::cpu1.data 0.540241 # miss rate for overall accesses 309system.l2c.overall_miss_rate::total 0.561073 # miss rate for overall accesses | 237system.l2c.overall_misses::cpu1.inst 2363 # number of overall misses 238system.l2c.overall_misses::cpu1.data 16941 # number of overall misses 239system.l2c.overall_misses::total 184292 # number of overall misses 240system.l2c.ReadReq_accesses::cpu0.dtb.walker 76 # number of ReadReq accesses(hits+misses) 241system.l2c.ReadReq_accesses::cpu0.itb.walker 61 # number of ReadReq accesses(hits+misses) 242system.l2c.ReadReq_accesses::cpu0.inst 44932 # number of ReadReq accesses(hits+misses) 243system.l2c.ReadReq_accesses::cpu0.data 87421 # number of ReadReq accesses(hits+misses) 244system.l2c.ReadReq_accesses::cpu1.dtb.walker 40 # number of ReadReq accesses(hits+misses) 245system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses) 246system.l2c.ReadReq_accesses::cpu1.inst 13819 # number of ReadReq accesses(hits+misses) 247system.l2c.ReadReq_accesses::cpu1.data 12501 # number of ReadReq accesses(hits+misses) 248system.l2c.ReadReq_accesses::total 158885 # number of ReadReq accesses(hits+misses) 249system.l2c.Writeback_accesses::writebacks 225882 # number of Writeback accesses(hits+misses) 250system.l2c.Writeback_accesses::total 225882 # number of Writeback accesses(hits+misses) 251system.l2c.UpgradeReq_accesses::cpu0.data 10488 # number of UpgradeReq accesses(hits+misses) 252system.l2c.UpgradeReq_accesses::cpu1.data 3355 # number of UpgradeReq accesses(hits+misses) 253system.l2c.UpgradeReq_accesses::total 13843 # number of UpgradeReq accesses(hits+misses) 254system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) 255system.l2c.SCUpgradeReq_accesses::cpu1.data 1191 # number of SCUpgradeReq accesses(hits+misses) 256system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses) 257system.l2c.ReadExReq_accesses::cpu0.data 150606 # number of ReadExReq accesses(hits+misses) 258system.l2c.ReadExReq_accesses::cpu1.data 18956 # number of ReadExReq accesses(hits+misses) 259system.l2c.ReadExReq_accesses::total 169562 # number of ReadExReq accesses(hits+misses) 260system.l2c.demand_accesses::cpu0.dtb.walker 76 # number of demand (read+write) accesses 261system.l2c.demand_accesses::cpu0.itb.walker 61 # number of demand (read+write) accesses 262system.l2c.demand_accesses::cpu0.inst 44932 # number of demand (read+write) accesses 263system.l2c.demand_accesses::cpu0.data 238027 # number of demand (read+write) accesses 264system.l2c.demand_accesses::cpu1.dtb.walker 40 # number of demand (read+write) accesses 265system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses 266system.l2c.demand_accesses::cpu1.inst 13819 # number of demand (read+write) accesses 267system.l2c.demand_accesses::cpu1.data 31457 # number of demand (read+write) accesses 268system.l2c.demand_accesses::total 328447 # number of demand (read+write) accesses 269system.l2c.overall_accesses::cpu0.dtb.walker 76 # number of overall (read+write) accesses 270system.l2c.overall_accesses::cpu0.itb.walker 61 # number of overall (read+write) accesses 271system.l2c.overall_accesses::cpu0.inst 44932 # number of overall (read+write) accesses 272system.l2c.overall_accesses::cpu0.data 238027 # number of overall (read+write) accesses 273system.l2c.overall_accesses::cpu1.dtb.walker 40 # number of overall (read+write) accesses 274system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses 275system.l2c.overall_accesses::cpu1.inst 13819 # number of overall (read+write) accesses 276system.l2c.overall_accesses::cpu1.data 31457 # number of overall (read+write) accesses 277system.l2c.overall_accesses::total 328447 # number of overall (read+write) accesses 278system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for ReadReq accesses 279system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.032787 # miss rate for ReadReq accesses 280system.l2c.ReadReq_miss_rate::cpu0.inst 0.375857 # miss rate for ReadReq accesses 281system.l2c.ReadReq_miss_rate::cpu0.data 0.129351 # miss rate for ReadReq accesses 282system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for ReadReq accesses 283system.l2c.ReadReq_miss_rate::cpu1.inst 0.170996 # miss rate for ReadReq accesses 284system.l2c.ReadReq_miss_rate::cpu1.data 0.089753 # miss rate for ReadReq accesses 285system.l2c.ReadReq_miss_rate::total 0.199465 # miss rate for ReadReq accesses 286system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951754 # miss rate for UpgradeReq accesses 287system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980626 # miss rate for UpgradeReq accesses 288system.l2c.UpgradeReq_miss_rate::total 0.958752 # miss rate for UpgradeReq accesses 289system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920828 # miss rate for SCUpgradeReq accesses 290system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994962 # miss rate for SCUpgradeReq accesses 291system.l2c.SCUpgradeReq_miss_rate::total 0.964712 # miss rate for SCUpgradeReq accesses 292system.l2c.ReadExReq_miss_rate::cpu0.data 0.908204 # miss rate for ReadExReq accesses 293system.l2c.ReadExReq_miss_rate::cpu1.data 0.834512 # miss rate for ReadExReq accesses 294system.l2c.ReadExReq_miss_rate::total 0.899966 # miss rate for ReadExReq accesses 295system.l2c.demand_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for demand accesses 296system.l2c.demand_miss_rate::cpu0.itb.walker 0.032787 # miss rate for demand accesses 297system.l2c.demand_miss_rate::cpu0.inst 0.375857 # miss rate for demand accesses 298system.l2c.demand_miss_rate::cpu0.data 0.622152 # miss rate for demand accesses 299system.l2c.demand_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for demand accesses 300system.l2c.demand_miss_rate::cpu1.inst 0.170996 # miss rate for demand accesses 301system.l2c.demand_miss_rate::cpu1.data 0.538545 # miss rate for demand accesses 302system.l2c.demand_miss_rate::total 0.561101 # miss rate for demand accesses 303system.l2c.overall_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for overall accesses 304system.l2c.overall_miss_rate::cpu0.itb.walker 0.032787 # miss rate for overall accesses 305system.l2c.overall_miss_rate::cpu0.inst 0.375857 # miss rate for overall accesses 306system.l2c.overall_miss_rate::cpu0.data 0.622152 # miss rate for overall accesses 307system.l2c.overall_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for overall accesses 308system.l2c.overall_miss_rate::cpu1.inst 0.170996 # miss rate for overall accesses 309system.l2c.overall_miss_rate::cpu1.data 0.538545 # miss rate for overall accesses 310system.l2c.overall_miss_rate::total 0.561101 # miss rate for overall accesses |
| 310system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 311system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 312system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 313system.l2c.blocked::no_targets 0 # number of cycles access was blocked 314system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 315system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 316system.l2c.fast_writes 0 # number of fast writes performed 317system.l2c.cache_copies 0 # number of cache copies performed | 311system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 312system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 313system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 314system.l2c.blocked::no_targets 0 # number of cycles access was blocked 315system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 316system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 317system.l2c.fast_writes 0 # number of fast writes performed 318system.l2c.cache_copies 0 # number of cache copies performed |
| 318system.l2c.writebacks::writebacks 95019 # number of writebacks 319system.l2c.writebacks::total 95019 # number of writebacks | 319system.l2c.writebacks::writebacks 94881 # number of writebacks 320system.l2c.writebacks::total 94881 # number of writebacks |
| 320system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 321system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 322system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 323system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 324system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 325system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 326system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 327system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 22 unchanged lines hidden (view full) --- 350system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 351system.realview.ethernet.droppedPackets 0 # number of packets dropped 352system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 353system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 354system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 355system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 356system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 357system.cf0.dma_write_txs 631 # Number of DMA write transactions. | 321system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 322system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 323system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 324system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 325system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 326system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 327system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 328system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR --- 22 unchanged lines hidden (view full) --- 351system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 352system.realview.ethernet.droppedPackets 0 # number of packets dropped 353system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 354system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 355system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 356system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 357system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 358system.cf0.dma_write_txs 631 # Number of DMA write transactions. |
| 358system.toL2Bus.trans_dist::ReadReq 305028 # Transaction distribution 359system.toL2Bus.trans_dist::ReadResp 305028 # Transaction distribution 360system.toL2Bus.trans_dist::WriteReq 30903 # Transaction distribution 361system.toL2Bus.trans_dist::WriteResp 30903 # Transaction distribution 362system.toL2Bus.trans_dist::Writeback 225966 # Transaction distribution 363system.toL2Bus.trans_dist::UpgradeReq 60515 # Transaction distribution 364system.toL2Bus.trans_dist::SCUpgradeReq 40953 # Transaction distribution 365system.toL2Bus.trans_dist::UpgradeResp 101468 # Transaction distribution 366system.toL2Bus.trans_dist::ReadExReq 213769 # Transaction distribution 367system.toL2Bus.trans_dist::ReadExResp 213769 # Transaction distribution 368system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117772 # Packet count per connected master and slave (bytes) 369system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410530 # Packet count per connected master and slave (bytes) 370system.toL2Bus.pkt_count::total 1528302 # Packet count per connected master and slave (bytes) 371system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34667382 # Cumulative packet size per connected master and slave (bytes) 372system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10427306 # Cumulative packet size per connected master and slave (bytes) 373system.toL2Bus.pkt_size::total 45094688 # Cumulative packet size per connected master and slave (bytes) | 359system.toL2Bus.trans_dist::ReadReq 305223 # Transaction distribution 360system.toL2Bus.trans_dist::ReadResp 305223 # Transaction distribution 361system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution 362system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution 363system.toL2Bus.trans_dist::Writeback 225882 # Transaction distribution 364system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution 365system.toL2Bus.trans_dist::SCUpgradeReq 41001 # Transaction distribution 366system.toL2Bus.trans_dist::UpgradeResp 101549 # Transaction distribution 367system.toL2Bus.trans_dist::ReadExReq 213695 # Transaction distribution 368system.toL2Bus.trans_dist::ReadExResp 213695 # Transaction distribution 369system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117774 # Packet count per connected master and slave (bytes) 370system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410852 # Packet count per connected master and slave (bytes) 371system.toL2Bus.pkt_count::total 1528626 # Packet count per connected master and slave (bytes) 372system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664498 # Cumulative packet size per connected master and slave (bytes) 373system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432626 # Cumulative packet size per connected master and slave (bytes) 374system.toL2Bus.pkt_size::total 45097124 # Cumulative packet size per connected master and slave (bytes) |
| 374system.toL2Bus.snoops 36713 # Total snoops (count) | 375system.toL2Bus.snoops 36713 # Total snoops (count) |
| 375system.toL2Bus.snoop_fanout::samples 838693 # Request fanout histogram 376system.toL2Bus.snoop_fanout::mean 1.043491 # Request fanout histogram 377system.toL2Bus.snoop_fanout::stdev 0.203961 # Request fanout histogram | 376system.toL2Bus.snoop_fanout::samples 838812 # Request fanout histogram 377system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram 378system.toL2Bus.snoop_fanout::stdev 0.203947 # Request fanout histogram |
| 378system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 379system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 379system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 380system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 380system.toL2Bus.snoop_fanout::1 802217 95.65% 95.65% # Request fanout histogram | 381system.toL2Bus.snoop_fanout::1 802336 95.65% 95.65% # Request fanout histogram |
| 381system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram 382system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 383system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 384system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 382system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram 383system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 384system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 385system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 385system.toL2Bus.snoop_fanout::total 838693 # Request fanout histogram | 386system.toL2Bus.snoop_fanout::total 838812 # Request fanout histogram |
| 386system.iobus.trans_dist::ReadReq 31002 # Transaction distribution 387system.iobus.trans_dist::ReadResp 31002 # Transaction distribution 388system.iobus.trans_dist::WriteReq 59433 # Transaction distribution 389system.iobus.trans_dist::WriteResp 23209 # Transaction distribution 390system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 391system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) 392system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 393system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 62 unchanged lines hidden (view full) --- 456system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 457system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 458system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 459system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 460system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 461system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 462system.cpu0.dtb.inst_hits 0 # ITB inst hits 463system.cpu0.dtb.inst_misses 0 # ITB inst misses | 387system.iobus.trans_dist::ReadReq 31002 # Transaction distribution 388system.iobus.trans_dist::ReadResp 31002 # Transaction distribution 389system.iobus.trans_dist::WriteReq 59433 # Transaction distribution 390system.iobus.trans_dist::WriteResp 23209 # Transaction distribution 391system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 392system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) 393system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 394system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 62 unchanged lines hidden (view full) --- 457system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 458system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 459system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 460system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 461system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 462system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 463system.cpu0.dtb.inst_hits 0 # ITB inst hits 464system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 464system.cpu0.dtb.read_hits 20338466 # DTB read hits | 465system.cpu0.dtb.read_hits 20339791 # DTB read hits |
| 465system.cpu0.dtb.read_misses 6871 # DTB read misses | 466system.cpu0.dtb.read_misses 6871 # DTB read misses |
| 466system.cpu0.dtb.write_hits 16389914 # DTB write hits | 467system.cpu0.dtb.write_hits 16391007 # DTB write hits |
| 467system.cpu0.dtb.write_misses 1093 # DTB write misses 468system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 469system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 470system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 471system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 472system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 473system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 474system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 475system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 476system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions | 468system.cpu0.dtb.write_misses 1093 # DTB write misses 469system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 470system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 471system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 472system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 473system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 474system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 475system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 476system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 477system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions |
| 477system.cpu0.dtb.read_accesses 20345337 # DTB read accesses 478system.cpu0.dtb.write_accesses 16391007 # DTB write accesses | 478system.cpu0.dtb.read_accesses 20346662 # DTB read accesses 479system.cpu0.dtb.write_accesses 16392100 # DTB write accesses |
| 479system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 480system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 480system.cpu0.dtb.hits 36728380 # DTB hits | 481system.cpu0.dtb.hits 36730798 # DTB hits |
| 481system.cpu0.dtb.misses 7964 # DTB misses | 482system.cpu0.dtb.misses 7964 # DTB misses |
| 482system.cpu0.dtb.accesses 36736344 # DTB accesses | 483system.cpu0.dtb.accesses 36738762 # DTB accesses |
| 483system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 484system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 485system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 486system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 487system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 488system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 489system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 496system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 497system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 498system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 499system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 500system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 501system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 502system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 503system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 484system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 485system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 486system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 487system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 488system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 489system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 491system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 497system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 498system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 499system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 500system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 501system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 502system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 503system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 504system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 504system.cpu0.itb.inst_hits 97433991 # ITB inst hits | 505system.cpu0.itb.inst_hits 97439560 # ITB inst hits |
| 505system.cpu0.itb.inst_misses 3358 # ITB inst misses 506system.cpu0.itb.read_hits 0 # DTB read hits 507system.cpu0.itb.read_misses 0 # DTB read misses 508system.cpu0.itb.write_hits 0 # DTB write hits 509system.cpu0.itb.write_misses 0 # DTB write misses 510system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 511system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 512system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 513system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 514system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 515system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 516system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 517system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 518system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 519system.cpu0.itb.read_accesses 0 # DTB read accesses 520system.cpu0.itb.write_accesses 0 # DTB write accesses | 506system.cpu0.itb.inst_misses 3358 # ITB inst misses 507system.cpu0.itb.read_hits 0 # DTB read hits 508system.cpu0.itb.read_misses 0 # DTB read misses 509system.cpu0.itb.write_hits 0 # DTB write hits 510system.cpu0.itb.write_misses 0 # DTB write misses 511system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 512system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 513system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 514system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 515system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 516system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 517system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 518system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 519system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 520system.cpu0.itb.read_accesses 0 # DTB read accesses 521system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 521system.cpu0.itb.inst_accesses 97437349 # ITB inst accesses 522system.cpu0.itb.hits 97433991 # DTB hits | 522system.cpu0.itb.inst_accesses 97442918 # ITB inst accesses 523system.cpu0.itb.hits 97439560 # DTB hits |
| 523system.cpu0.itb.misses 3358 # DTB misses | 524system.cpu0.itb.misses 3358 # DTB misses |
| 524system.cpu0.itb.accesses 97437349 # DTB accesses 525system.cpu0.numCycles 5605766965 # number of cpu cycles simulated | 525system.cpu0.itb.accesses 97442918 # DTB accesses 526system.cpu0.numCycles 5605767393 # number of cpu cycles simulated |
| 526system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 527system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 527system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 528system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 528system.cpu0.committedInsts 95421538 # Number of instructions committed 529system.cpu0.committedOps 115553717 # Number of ops (including micro ops) committed 530system.cpu0.num_int_alu_accesses 100756647 # Number of integer alu accesses | 529system.cpu0.committedInsts 95427097 # Number of instructions committed 530system.cpu0.committedOps 115560530 # Number of ops (including micro ops) committed 531system.cpu0.num_int_alu_accesses 100762762 # Number of integer alu accesses |
| 531system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses | 532system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses |
| 532system.cpu0.num_func_calls 7999979 # number of times a function call or return occured 533system.cpu0.num_conditional_control_insts 13203645 # number of instructions that are conditional controls 534system.cpu0.num_int_insts 100756647 # number of integer instructions | 533system.cpu0.num_func_calls 8000275 # number of times a function call or return occured 534system.cpu0.num_conditional_control_insts 13204265 # number of instructions that are conditional controls 535system.cpu0.num_int_insts 100762762 # number of integer instructions |
| 535system.cpu0.num_fp_insts 9755 # number of float instructions | 536system.cpu0.num_fp_insts 9755 # number of float instructions |
| 536system.cpu0.num_int_register_reads 182446507 # number of times the integer registers were read 537system.cpu0.num_int_register_writes 69131058 # number of times the integer registers were written | 537system.cpu0.num_int_register_reads 182457576 # number of times the integer registers were read 538system.cpu0.num_int_register_writes 69135597 # number of times the integer registers were written |
| 538system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 539system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written | 539system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 540system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written |
| 540system.cpu0.num_cc_register_reads 349951369 # number of times the CC registers were read 541system.cpu0.num_cc_register_writes 44905035 # number of times the CC registers were written 542system.cpu0.num_mem_refs 37871263 # number of memory refs 543system.cpu0.num_load_insts 20596038 # Number of load instructions 544system.cpu0.num_store_insts 17275225 # Number of store instructions 545system.cpu0.num_idle_cycles 5488189135.402444 # Number of idle cycles 546system.cpu0.num_busy_cycles 117577829.597556 # Number of busy cycles 547system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles 548system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles 549system.cpu0.Branches 21940727 # Number of branches fetched | 541system.cpu0.num_cc_register_reads 349971872 # number of times the CC registers were read 542system.cpu0.num_cc_register_writes 44907557 # number of times the CC registers were written 543system.cpu0.num_mem_refs 37873781 # number of memory refs 544system.cpu0.num_load_insts 20597370 # Number of load instructions 545system.cpu0.num_store_insts 17276411 # Number of store instructions 546system.cpu0.num_idle_cycles 5488182740.223901 # Number of idle cycles 547system.cpu0.num_busy_cycles 117584652.776099 # Number of busy cycles 548system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 549system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 550system.cpu0.Branches 21941666 # Number of branches fetched |
| 550system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction | 551system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction |
| 551system.cpu0.op_class::IntAlu 78883166 67.49% 67.50% # Class of executed instruction 552system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction | 552system.cpu0.op_class::IntAlu 78887449 67.49% 67.50% # Class of executed instruction 553system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction |
| 553system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 554system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 555system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 556system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 557system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 558system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 559system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 560system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 572system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 573system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 574system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 575system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 576system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 577system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 578system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 579system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction | 554system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 555system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 556system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 557system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 558system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 559system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 560system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 561system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 573system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 574system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 575system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 576system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 577system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 578system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 579system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 580system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction |
| 580system.cpu0.op_class::MemRead 20596038 17.62% 85.22% # Class of executed instruction 581system.cpu0.op_class::MemWrite 17275225 14.78% 100.00% # Class of executed instruction | 581system.cpu0.op_class::MemRead 20597370 17.62% 85.22% # Class of executed instruction 582system.cpu0.op_class::MemWrite 17276411 14.78% 100.00% # Class of executed instruction |
| 582system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 583system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 583system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 584system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 584system.cpu0.op_class::total 116875407 # Class of executed instruction | 585system.cpu0.op_class::total 116882229 # Class of executed instruction |
| 585system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 586system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 586system.cpu0.kern.inst.quiesce 1971 # number of quiesce instructions executed 587system.cpu0.icache.tags.replacements 1109428 # number of replacements | 587system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed 588system.cpu0.icache.tags.replacements 1109631 # number of replacements |
| 588system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use | 589system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use |
| 589system.cpu0.icache.tags.total_refs 96326384 # Total number of references to valid blocks. 590system.cpu0.icache.tags.sampled_refs 1109940 # Sample count of references to valid blocks. 591system.cpu0.icache.tags.avg_refs 86.785217 # Average number of references to valid blocks. 592system.cpu0.icache.tags.warmup_cycle 6345717500 # Cycle when the warmup percentage was hit. | 590system.cpu0.icache.tags.total_refs 96331750 # Total number of references to valid blocks. 591system.cpu0.icache.tags.sampled_refs 1110143 # Sample count of references to valid blocks. 592system.cpu0.icache.tags.avg_refs 86.774181 # Average number of references to valid blocks. 593system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. |
| 593system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 594system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 595system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 596system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 597system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 598system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 599system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 600system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 594system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 595system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 596system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 597system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 598system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 599system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 600system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 601system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 601system.cpu0.icache.tags.tag_accesses 195982615 # Number of tag accesses 602system.cpu0.icache.tags.data_accesses 195982615 # Number of data accesses 603system.cpu0.icache.ReadReq_hits::cpu0.inst 96326384 # number of ReadReq hits 604system.cpu0.icache.ReadReq_hits::total 96326384 # number of ReadReq hits 605system.cpu0.icache.demand_hits::cpu0.inst 96326384 # number of demand (read+write) hits 606system.cpu0.icache.demand_hits::total 96326384 # number of demand (read+write) hits 607system.cpu0.icache.overall_hits::cpu0.inst 96326384 # number of overall hits 608system.cpu0.icache.overall_hits::total 96326384 # number of overall hits 609system.cpu0.icache.ReadReq_misses::cpu0.inst 1109949 # number of ReadReq misses 610system.cpu0.icache.ReadReq_misses::total 1109949 # number of ReadReq misses 611system.cpu0.icache.demand_misses::cpu0.inst 1109949 # number of demand (read+write) misses 612system.cpu0.icache.demand_misses::total 1109949 # number of demand (read+write) misses 613system.cpu0.icache.overall_misses::cpu0.inst 1109949 # number of overall misses 614system.cpu0.icache.overall_misses::total 1109949 # number of overall misses 615system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436333 # number of ReadReq accesses(hits+misses) 616system.cpu0.icache.ReadReq_accesses::total 97436333 # number of ReadReq accesses(hits+misses) 617system.cpu0.icache.demand_accesses::cpu0.inst 97436333 # number of demand (read+write) accesses 618system.cpu0.icache.demand_accesses::total 97436333 # number of demand (read+write) accesses 619system.cpu0.icache.overall_accesses::cpu0.inst 97436333 # number of overall (read+write) accesses 620system.cpu0.icache.overall_accesses::total 97436333 # number of overall (read+write) accesses 621system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011392 # miss rate for ReadReq accesses 622system.cpu0.icache.ReadReq_miss_rate::total 0.011392 # miss rate for ReadReq accesses 623system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011392 # miss rate for demand accesses 624system.cpu0.icache.demand_miss_rate::total 0.011392 # miss rate for demand accesses 625system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011392 # miss rate for overall accesses 626system.cpu0.icache.overall_miss_rate::total 0.011392 # miss rate for overall accesses | 602system.cpu0.icache.tags.tag_accesses 195993956 # Number of tag accesses 603system.cpu0.icache.tags.data_accesses 195993956 # Number of data accesses 604system.cpu0.icache.ReadReq_hits::cpu0.inst 96331750 # number of ReadReq hits 605system.cpu0.icache.ReadReq_hits::total 96331750 # number of ReadReq hits 606system.cpu0.icache.demand_hits::cpu0.inst 96331750 # number of demand (read+write) hits 607system.cpu0.icache.demand_hits::total 96331750 # number of demand (read+write) hits 608system.cpu0.icache.overall_hits::cpu0.inst 96331750 # number of overall hits 609system.cpu0.icache.overall_hits::total 96331750 # number of overall hits 610system.cpu0.icache.ReadReq_misses::cpu0.inst 1110152 # number of ReadReq misses 611system.cpu0.icache.ReadReq_misses::total 1110152 # number of ReadReq misses 612system.cpu0.icache.demand_misses::cpu0.inst 1110152 # number of demand (read+write) misses 613system.cpu0.icache.demand_misses::total 1110152 # number of demand (read+write) misses 614system.cpu0.icache.overall_misses::cpu0.inst 1110152 # number of overall misses 615system.cpu0.icache.overall_misses::total 1110152 # number of overall misses 616system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441902 # number of ReadReq accesses(hits+misses) 617system.cpu0.icache.ReadReq_accesses::total 97441902 # number of ReadReq accesses(hits+misses) 618system.cpu0.icache.demand_accesses::cpu0.inst 97441902 # number of demand (read+write) accesses 619system.cpu0.icache.demand_accesses::total 97441902 # number of demand (read+write) accesses 620system.cpu0.icache.overall_accesses::cpu0.inst 97441902 # number of overall (read+write) accesses 621system.cpu0.icache.overall_accesses::total 97441902 # number of overall (read+write) accesses 622system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses 623system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses 624system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses 625system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses 626system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 627system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses |
| 627system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 628system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 629system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 630system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 631system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 632system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 633system.cpu0.icache.fast_writes 0 # number of fast writes performed 634system.cpu0.icache.cache_copies 0 # number of cache copies performed 635system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 636system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 637system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 638system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 639system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 640system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 641system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 642system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 643system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 644system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 628system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 629system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 630system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 631system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 632system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 633system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 634system.cpu0.icache.fast_writes 0 # number of fast writes performed 635system.cpu0.icache.cache_copies 0 # number of cache copies performed 636system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 637system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 638system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 639system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 640system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 641system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 642system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 643system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 644system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 645system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 645system.cpu0.l2cache.tags.replacements 252470 # number of replacements 646system.cpu0.l2cache.tags.tagsinuse 16140.899010 # Cycle average of tags in use 647system.cpu0.l2cache.tags.total_refs 1809063 # Total number of references to valid blocks. 648system.cpu0.l2cache.tags.sampled_refs 268660 # Sample count of references to valid blocks. 649system.cpu0.l2cache.tags.avg_refs 6.733652 # Average number of references to valid blocks. 650system.cpu0.l2cache.tags.warmup_cycle 1814551000 # Cycle when the warmup percentage was hit. 651system.cpu0.l2cache.tags.occ_blocks::writebacks 8130.897895 # Average occupied blocks per requestor 652system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.403919 # Average occupied blocks per requestor 653system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.095149 # Average occupied blocks per requestor 654system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4678.277611 # Average occupied blocks per requestor 655system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3330.224436 # Average occupied blocks per requestor 656system.cpu0.l2cache.tags.occ_percent::writebacks 0.496271 # Average percentage of cache occupancy 657system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000086 # Average percentage of cache occupancy 658system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy 659system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285539 # Average percentage of cache occupancy 660system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.203261 # Average percentage of cache occupancy 661system.cpu0.l2cache.tags.occ_percent::total 0.985162 # Average percentage of cache occupancy 662system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 663system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id 664system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 665system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 666system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 667system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 668system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id 669system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5558 # Occupied blocks per task id 670system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id | 646system.cpu0.l2cache.tags.replacements 252387 # number of replacements 647system.cpu0.l2cache.tags.tagsinuse 16137.494570 # Cycle average of tags in use 648system.cpu0.l2cache.tags.total_refs 1809761 # Total number of references to valid blocks. 649system.cpu0.l2cache.tags.sampled_refs 268581 # Sample count of references to valid blocks. 650system.cpu0.l2cache.tags.avg_refs 6.738232 # Average number of references to valid blocks. 651system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. 652system.cpu0.l2cache.tags.occ_blocks::writebacks 8061.802195 # Average occupied blocks per requestor 653system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.197687 # Average occupied blocks per requestor 654system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.081095 # Average occupied blocks per requestor 655system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4773.849314 # Average occupied blocks per requestor 656system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.564278 # Average occupied blocks per requestor 657system.cpu0.l2cache.tags.occ_percent::writebacks 0.492053 # Average percentage of cache occupancy 658system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy 659system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 660system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.291373 # Average percentage of cache occupancy 661system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201328 # Average percentage of cache occupancy 662system.cpu0.l2cache.tags.occ_percent::total 0.984955 # Average percentage of cache occupancy 663system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 664system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16188 # Occupied blocks per task id 665system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 666system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 667system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 668system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id 669system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 670system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5625 # Occupied blocks per task id 671system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7524 # Occupied blocks per task id |
| 671system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2662 # Occupied blocks per task id | 672system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2662 # Occupied blocks per task id |
| 672system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 673system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id 674system.cpu0.l2cache.tags.tag_accesses 39435786 # Number of tag accesses 675system.cpu0.l2cache.tags.data_accesses 39435786 # Number of data accesses 676system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7516 # number of ReadReq hits 677system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3210 # number of ReadReq hits 678system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1064995 # number of ReadReq hits 679system.cpu0.l2cache.ReadReq_hits::cpu0.data 352145 # number of ReadReq hits 680system.cpu0.l2cache.ReadReq_hits::total 1427866 # number of ReadReq hits 681system.cpu0.l2cache.Writeback_hits::writebacks 511188 # number of Writeback hits 682system.cpu0.l2cache.Writeback_hits::total 511188 # number of Writeback hits | 673system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 674system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988037 # Percentage of cache occupancy per task id 675system.cpu0.l2cache.tags.tag_accesses 39447588 # Number of tag accesses 676system.cpu0.l2cache.tags.data_accesses 39447588 # Number of data accesses 677system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7603 # number of ReadReq hits 678system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3246 # number of ReadReq hits 679system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065220 # number of ReadReq hits 680system.cpu0.l2cache.ReadReq_hits::cpu0.data 351970 # number of ReadReq hits 681system.cpu0.l2cache.ReadReq_hits::total 1428039 # number of ReadReq hits 682system.cpu0.l2cache.Writeback_hits::writebacks 511617 # number of Writeback hits 683system.cpu0.l2cache.Writeback_hits::total 511617 # number of Writeback hits |
| 683system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits 684system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits | 684system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits 685system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits |
| 685system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94088 # number of ReadExReq hits 686system.cpu0.l2cache.ReadExReq_hits::total 94088 # number of ReadExReq hits 687system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7516 # number of demand (read+write) hits 688system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3210 # number of demand (read+write) hits 689system.cpu0.l2cache.demand_hits::cpu0.inst 1064995 # number of demand (read+write) hits 690system.cpu0.l2cache.demand_hits::cpu0.data 446233 # number of demand (read+write) hits 691system.cpu0.l2cache.demand_hits::total 1521954 # number of demand (read+write) hits 692system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7516 # number of overall hits 693system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3210 # number of overall hits 694system.cpu0.l2cache.overall_hits::cpu0.inst 1064995 # number of overall hits 695system.cpu0.l2cache.overall_hits::cpu0.data 446233 # number of overall hits 696system.cpu0.l2cache.overall_hits::total 1521954 # number of overall hits 697system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses 698system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 135 # number of ReadReq misses 699system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44954 # number of ReadReq misses 700system.cpu0.l2cache.ReadReq_misses::cpu0.data 128031 # number of ReadReq misses 701system.cpu0.l2cache.ReadReq_misses::total 173336 # number of ReadReq misses 702system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26217 # number of UpgradeReq misses 703system.cpu0.l2cache.UpgradeReq_misses::total 26217 # number of UpgradeReq misses 704system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18426 # number of SCUpgradeReq misses 705system.cpu0.l2cache.SCUpgradeReq_misses::total 18426 # number of SCUpgradeReq misses 706system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175429 # number of ReadExReq misses 707system.cpu0.l2cache.ReadExReq_misses::total 175429 # number of ReadExReq misses 708system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses 709system.cpu0.l2cache.demand_misses::cpu0.itb.walker 135 # number of demand (read+write) misses 710system.cpu0.l2cache.demand_misses::cpu0.inst 44954 # number of demand (read+write) misses 711system.cpu0.l2cache.demand_misses::cpu0.data 303460 # number of demand (read+write) misses 712system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses 713system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses 714system.cpu0.l2cache.overall_misses::cpu0.itb.walker 135 # number of overall misses 715system.cpu0.l2cache.overall_misses::cpu0.inst 44954 # number of overall misses 716system.cpu0.l2cache.overall_misses::cpu0.data 303460 # number of overall misses 717system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses 718system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7732 # number of ReadReq accesses(hits+misses) 719system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3345 # number of ReadReq accesses(hits+misses) 720system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1109949 # number of ReadReq accesses(hits+misses) 721system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480176 # number of ReadReq accesses(hits+misses) 722system.cpu0.l2cache.ReadReq_accesses::total 1601202 # number of ReadReq accesses(hits+misses) 723system.cpu0.l2cache.Writeback_accesses::writebacks 511188 # number of Writeback accesses(hits+misses) 724system.cpu0.l2cache.Writeback_accesses::total 511188 # number of Writeback accesses(hits+misses) 725system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26234 # number of UpgradeReq accesses(hits+misses) 726system.cpu0.l2cache.UpgradeReq_accesses::total 26234 # number of UpgradeReq accesses(hits+misses) 727system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18426 # number of SCUpgradeReq accesses(hits+misses) 728system.cpu0.l2cache.SCUpgradeReq_accesses::total 18426 # number of SCUpgradeReq accesses(hits+misses) 729system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) 730system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) 731system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7732 # number of demand (read+write) accesses 732system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3345 # number of demand (read+write) accesses 733system.cpu0.l2cache.demand_accesses::cpu0.inst 1109949 # number of demand (read+write) accesses 734system.cpu0.l2cache.demand_accesses::cpu0.data 749693 # number of demand (read+write) accesses 735system.cpu0.l2cache.demand_accesses::total 1870719 # number of demand (read+write) accesses 736system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7732 # number of overall (read+write) accesses 737system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3345 # number of overall (read+write) accesses 738system.cpu0.l2cache.overall_accesses::cpu0.inst 1109949 # number of overall (read+write) accesses 739system.cpu0.l2cache.overall_accesses::cpu0.data 749693 # number of overall (read+write) accesses 740system.cpu0.l2cache.overall_accesses::total 1870719 # number of overall (read+write) accesses 741system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for ReadReq accesses 742system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040359 # miss rate for ReadReq accesses 743system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040501 # miss rate for ReadReq accesses 744system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266633 # miss rate for ReadReq accesses 745system.cpu0.l2cache.ReadReq_miss_rate::total 0.108254 # miss rate for ReadReq accesses | 686system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94214 # number of ReadExReq hits 687system.cpu0.l2cache.ReadExReq_hits::total 94214 # number of ReadExReq hits 688system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7603 # number of demand (read+write) hits 689system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3246 # number of demand (read+write) hits 690system.cpu0.l2cache.demand_hits::cpu0.inst 1065220 # number of demand (read+write) hits 691system.cpu0.l2cache.demand_hits::cpu0.data 446184 # number of demand (read+write) hits 692system.cpu0.l2cache.demand_hits::total 1522253 # number of demand (read+write) hits 693system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7603 # number of overall hits 694system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3246 # number of overall hits 695system.cpu0.l2cache.overall_hits::cpu0.inst 1065220 # number of overall hits 696system.cpu0.l2cache.overall_hits::cpu0.data 446184 # number of overall hits 697system.cpu0.l2cache.overall_hits::total 1522253 # number of overall hits 698system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 205 # number of ReadReq misses 699system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 119 # number of ReadReq misses 700system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44932 # number of ReadReq misses 701system.cpu0.l2cache.ReadReq_misses::cpu0.data 128186 # number of ReadReq misses 702system.cpu0.l2cache.ReadReq_misses::total 173442 # number of ReadReq misses 703system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26232 # number of UpgradeReq misses 704system.cpu0.l2cache.UpgradeReq_misses::total 26232 # number of UpgradeReq misses 705system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses 706system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses 707system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175300 # number of ReadExReq misses 708system.cpu0.l2cache.ReadExReq_misses::total 175300 # number of ReadExReq misses 709system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 205 # number of demand (read+write) misses 710system.cpu0.l2cache.demand_misses::cpu0.itb.walker 119 # number of demand (read+write) misses 711system.cpu0.l2cache.demand_misses::cpu0.inst 44932 # number of demand (read+write) misses 712system.cpu0.l2cache.demand_misses::cpu0.data 303486 # number of demand (read+write) misses 713system.cpu0.l2cache.demand_misses::total 348742 # number of demand (read+write) misses 714system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 205 # number of overall misses 715system.cpu0.l2cache.overall_misses::cpu0.itb.walker 119 # number of overall misses 716system.cpu0.l2cache.overall_misses::cpu0.inst 44932 # number of overall misses 717system.cpu0.l2cache.overall_misses::cpu0.data 303486 # number of overall misses 718system.cpu0.l2cache.overall_misses::total 348742 # number of overall misses 719system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7808 # number of ReadReq accesses(hits+misses) 720system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3365 # number of ReadReq accesses(hits+misses) 721system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110152 # number of ReadReq accesses(hits+misses) 722system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480156 # number of ReadReq accesses(hits+misses) 723system.cpu0.l2cache.ReadReq_accesses::total 1601481 # number of ReadReq accesses(hits+misses) 724system.cpu0.l2cache.Writeback_accesses::writebacks 511617 # number of Writeback accesses(hits+misses) 725system.cpu0.l2cache.Writeback_accesses::total 511617 # number of Writeback accesses(hits+misses) 726system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26249 # number of UpgradeReq accesses(hits+misses) 727system.cpu0.l2cache.UpgradeReq_accesses::total 26249 # number of UpgradeReq accesses(hits+misses) 728system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) 729system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) 730system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269514 # number of ReadExReq accesses(hits+misses) 731system.cpu0.l2cache.ReadExReq_accesses::total 269514 # number of ReadExReq accesses(hits+misses) 732system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7808 # number of demand (read+write) accesses 733system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3365 # number of demand (read+write) accesses 734system.cpu0.l2cache.demand_accesses::cpu0.inst 1110152 # number of demand (read+write) accesses 735system.cpu0.l2cache.demand_accesses::cpu0.data 749670 # number of demand (read+write) accesses 736system.cpu0.l2cache.demand_accesses::total 1870995 # number of demand (read+write) accesses 737system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7808 # number of overall (read+write) accesses 738system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3365 # number of overall (read+write) accesses 739system.cpu0.l2cache.overall_accesses::cpu0.inst 1110152 # number of overall (read+write) accesses 740system.cpu0.l2cache.overall_accesses::cpu0.data 749670 # number of overall (read+write) accesses 741system.cpu0.l2cache.overall_accesses::total 1870995 # number of overall (read+write) accesses 742system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for ReadReq accesses 743system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035364 # miss rate for ReadReq accesses 744system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040474 # miss rate for ReadReq accesses 745system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266967 # miss rate for ReadReq accesses 746system.cpu0.l2cache.ReadReq_miss_rate::total 0.108301 # miss rate for ReadReq accesses |
| 746system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses 747system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses 748system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 749system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 747system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses 748system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses 749system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 750system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 750system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650901 # miss rate for ReadExReq accesses 751system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650901 # miss rate for ReadExReq accesses 752system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for demand accesses 753system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040359 # miss rate for demand accesses 754system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040501 # miss rate for demand accesses 755system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404779 # miss rate for demand accesses 756system.cpu0.l2cache.demand_miss_rate::total 0.186434 # miss rate for demand accesses 757system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for overall accesses 758system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040359 # miss rate for overall accesses 759system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040501 # miss rate for overall accesses 760system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404779 # miss rate for overall accesses 761system.cpu0.l2cache.overall_miss_rate::total 0.186434 # miss rate for overall accesses | 751system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650430 # miss rate for ReadExReq accesses 752system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650430 # miss rate for ReadExReq accesses 753system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for demand accesses 754system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035364 # miss rate for demand accesses 755system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040474 # miss rate for demand accesses 756system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404826 # miss rate for demand accesses 757system.cpu0.l2cache.demand_miss_rate::total 0.186394 # miss rate for demand accesses 758system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for overall accesses 759system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035364 # miss rate for overall accesses 760system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040474 # miss rate for overall accesses 761system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404826 # miss rate for overall accesses 762system.cpu0.l2cache.overall_miss_rate::total 0.186394 # miss rate for overall accesses |
| 762system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 763system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 765system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 767system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 769system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 763system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 764system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 765system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 766system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 767system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 768system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 769system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 770system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 770system.cpu0.l2cache.writebacks::writebacks 192932 # number of writebacks 771system.cpu0.l2cache.writebacks::total 192932 # number of writebacks | 771system.cpu0.l2cache.writebacks::writebacks 192916 # number of writebacks 772system.cpu0.l2cache.writebacks::total 192916 # number of writebacks |
| 772system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 773system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 773system.cpu0.dcache.tags.replacements 693475 # number of replacements 774system.cpu0.dcache.tags.tagsinuse 494.745909 # Cycle average of tags in use 775system.cpu0.dcache.tags.total_refs 35929913 # Total number of references to valid blocks. 776system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. 777system.cpu0.dcache.tags.avg_refs 51.773179 # Average number of references to valid blocks. 778system.cpu0.dcache.tags.warmup_cycle 23662000 # Cycle when the warmup percentage was hit. 779system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.745909 # Average occupied blocks per requestor 780system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966301 # Average percentage of cache occupancy 781system.cpu0.dcache.tags.occ_percent::total 0.966301 # Average percentage of cache occupancy | 774system.cpu0.dcache.tags.replacements 693468 # number of replacements 775system.cpu0.dcache.tags.tagsinuse 494.853462 # Cycle average of tags in use 776system.cpu0.dcache.tags.total_refs 35932354 # Total number of references to valid blocks. 777system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks. 778system.cpu0.dcache.tags.avg_refs 51.777218 # Average number of references to valid blocks. 779system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. 780system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853462 # Average occupied blocks per requestor 781system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 782system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy |
| 782system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 783system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 784system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 785system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 786system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 783system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 784system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 785system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 786system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 787system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 787system.cpu0.dcache.tags.tag_accesses 74108905 # Number of tag accesses 788system.cpu0.dcache.tags.data_accesses 74108905 # Number of data accesses 789system.cpu0.dcache.ReadReq_hits::cpu0.data 19107323 # number of ReadReq hits 790system.cpu0.dcache.ReadReq_hits::total 19107323 # number of ReadReq hits 791system.cpu0.dcache.WriteReq_hits::cpu0.data 15689235 # number of WriteReq hits 792system.cpu0.dcache.WriteReq_hits::total 15689235 # number of WriteReq hits 793system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346054 # number of SoftPFReq hits 794system.cpu0.dcache.SoftPFReq_hits::total 346054 # number of SoftPFReq hits 795system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379605 # number of LoadLockedReq hits 796system.cpu0.dcache.LoadLockedReq_hits::total 379605 # number of LoadLockedReq hits 797system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363036 # number of StoreCondReq hits 798system.cpu0.dcache.StoreCondReq_hits::total 363036 # number of StoreCondReq hits 799system.cpu0.dcache.demand_hits::cpu0.data 34796558 # number of demand (read+write) hits 800system.cpu0.dcache.demand_hits::total 34796558 # number of demand (read+write) hits 801system.cpu0.dcache.overall_hits::cpu0.data 35142612 # number of overall hits 802system.cpu0.dcache.overall_hits::total 35142612 # number of overall hits 803system.cpu0.dcache.ReadReq_misses::cpu0.data 373110 # number of ReadReq misses 804system.cpu0.dcache.ReadReq_misses::total 373110 # number of ReadReq misses 805system.cpu0.dcache.WriteReq_misses::cpu0.data 295751 # number of WriteReq misses 806system.cpu0.dcache.WriteReq_misses::total 295751 # number of WriteReq misses 807system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100324 # number of SoftPFReq misses 808system.cpu0.dcache.SoftPFReq_misses::total 100324 # number of SoftPFReq misses 809system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 810system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 811system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18426 # number of StoreCondReq misses 812system.cpu0.dcache.StoreCondReq_misses::total 18426 # number of StoreCondReq misses 813system.cpu0.dcache.demand_misses::cpu0.data 668861 # number of demand (read+write) misses 814system.cpu0.dcache.demand_misses::total 668861 # number of demand (read+write) misses 815system.cpu0.dcache.overall_misses::cpu0.data 769185 # number of overall misses 816system.cpu0.dcache.overall_misses::total 769185 # number of overall misses 817system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480433 # number of ReadReq accesses(hits+misses) 818system.cpu0.dcache.ReadReq_accesses::total 19480433 # number of ReadReq accesses(hits+misses) 819system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984986 # number of WriteReq accesses(hits+misses) 820system.cpu0.dcache.WriteReq_accesses::total 15984986 # number of WriteReq accesses(hits+misses) 821system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446378 # number of SoftPFReq accesses(hits+misses) 822system.cpu0.dcache.SoftPFReq_accesses::total 446378 # number of SoftPFReq accesses(hits+misses) 823system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386347 # number of LoadLockedReq accesses(hits+misses) 824system.cpu0.dcache.LoadLockedReq_accesses::total 386347 # number of LoadLockedReq accesses(hits+misses) 825system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381462 # number of StoreCondReq accesses(hits+misses) 826system.cpu0.dcache.StoreCondReq_accesses::total 381462 # number of StoreCondReq accesses(hits+misses) 827system.cpu0.dcache.demand_accesses::cpu0.data 35465419 # number of demand (read+write) accesses 828system.cpu0.dcache.demand_accesses::total 35465419 # number of demand (read+write) accesses 829system.cpu0.dcache.overall_accesses::cpu0.data 35911797 # number of overall (read+write) accesses 830system.cpu0.dcache.overall_accesses::total 35911797 # number of overall (read+write) accesses 831system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019153 # miss rate for ReadReq accesses 832system.cpu0.dcache.ReadReq_miss_rate::total 0.019153 # miss rate for ReadReq accesses 833system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses 834system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses 835system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224751 # miss rate for SoftPFReq accesses 836system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224751 # miss rate for SoftPFReq accesses 837system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017451 # miss rate for LoadLockedReq accesses 838system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017451 # miss rate for LoadLockedReq accesses 839system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048304 # miss rate for StoreCondReq accesses 840system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048304 # miss rate for StoreCondReq accesses 841system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018860 # miss rate for demand accesses 842system.cpu0.dcache.demand_miss_rate::total 0.018860 # miss rate for demand accesses 843system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021419 # miss rate for overall accesses 844system.cpu0.dcache.overall_miss_rate::total 0.021419 # miss rate for overall accesses | 788system.cpu0.dcache.tags.tag_accesses 74113718 # Number of tag accesses 789system.cpu0.dcache.tags.data_accesses 74113718 # Number of data accesses 790system.cpu0.dcache.ReadReq_hits::cpu0.data 19108629 # number of ReadReq hits 791system.cpu0.dcache.ReadReq_hits::total 19108629 # number of ReadReq hits 792system.cpu0.dcache.WriteReq_hits::cpu0.data 15690304 # number of WriteReq hits 793system.cpu0.dcache.WriteReq_hits::total 15690304 # number of WriteReq hits 794system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits 795system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits 796system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits 797system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits 798system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits 799system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits 800system.cpu0.dcache.demand_hits::cpu0.data 34798933 # number of demand (read+write) hits 801system.cpu0.dcache.demand_hits::total 34798933 # number of demand (read+write) hits 802system.cpu0.dcache.overall_hits::cpu0.data 35145013 # number of overall hits 803system.cpu0.dcache.overall_hits::total 35145013 # number of overall hits 804system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses 805system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses 806system.cpu0.dcache.WriteReq_misses::cpu0.data 295763 # number of WriteReq misses 807system.cpu0.dcache.WriteReq_misses::total 295763 # number of WriteReq misses 808system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses 809system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses 810system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 811system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 812system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses 813system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses 814system.cpu0.dcache.demand_misses::cpu0.data 668857 # number of demand (read+write) misses 815system.cpu0.dcache.demand_misses::total 668857 # number of demand (read+write) misses 816system.cpu0.dcache.overall_misses::cpu0.data 769179 # number of overall misses 817system.cpu0.dcache.overall_misses::total 769179 # number of overall misses 818system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481723 # number of ReadReq accesses(hits+misses) 819system.cpu0.dcache.ReadReq_accesses::total 19481723 # number of ReadReq accesses(hits+misses) 820system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986067 # number of WriteReq accesses(hits+misses) 821system.cpu0.dcache.WriteReq_accesses::total 15986067 # number of WriteReq accesses(hits+misses) 822system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) 823system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) 824system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) 825system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) 826system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) 827system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) 828system.cpu0.dcache.demand_accesses::cpu0.data 35467790 # number of demand (read+write) accesses 829system.cpu0.dcache.demand_accesses::total 35467790 # number of demand (read+write) accesses 830system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses 831system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses 832system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 833system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 834system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses 835system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses 836system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses 837system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses 838system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 839system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses 840system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses 841system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses 842system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses 843system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses 844system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses 845system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses |
| 845system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 846system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 847system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 848system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 849system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 850system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 851system.cpu0.dcache.fast_writes 0 # number of fast writes performed 852system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 846system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 847system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 848system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 849system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 850system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 851system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 852system.cpu0.dcache.fast_writes 0 # number of fast writes performed 853system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 853system.cpu0.dcache.writebacks::writebacks 511188 # number of writebacks 854system.cpu0.dcache.writebacks::total 511188 # number of writebacks | 854system.cpu0.dcache.writebacks::writebacks 511617 # number of writebacks 855system.cpu0.dcache.writebacks::total 511617 # number of writebacks |
| 855system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 856system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 856system.cpu0.toL2Bus.trans_dist::ReadReq 1651550 # Transaction distribution 857system.cpu0.toL2Bus.trans_dist::ReadResp 1651550 # Transaction distribution 858system.cpu0.toL2Bus.trans_dist::WriteReq 28399 # Transaction distribution 859system.cpu0.toL2Bus.trans_dist::WriteResp 28399 # Transaction distribution 860system.cpu0.toL2Bus.trans_dist::Writeback 511188 # Transaction distribution 861system.cpu0.toL2Bus.trans_dist::UpgradeReq 26234 # Transaction distribution 862system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18426 # Transaction distribution 863system.cpu0.toL2Bus.trans_dist::UpgradeResp 44660 # Transaction distribution 864system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution 865system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution 866system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2237944 # Packet count per connected master and slave (bytes) 867system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2219872 # Packet count per connected master and slave (bytes) | 857system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution 858system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution 859system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution 860system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution 861system.cpu0.toL2Bus.trans_dist::Writeback 511617 # Transaction distribution 862system.cpu0.toL2Bus.trans_dist::UpgradeReq 26249 # Transaction distribution 863system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution 864system.cpu0.toL2Bus.trans_dist::UpgradeResp 44693 # Transaction distribution 865system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution 866system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution 867system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes) 868system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220321 # Packet count per connected master and slave (bytes) |
| 868system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 869system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) | 869system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 870system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) |
| 870system.cpu0.toL2Bus.pkt_count::total 4499440 # Packet count per connected master and slave (bytes) 871system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71072828 # Cumulative packet size per connected master and slave (bytes) 872system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887162 # Cumulative packet size per connected master and slave (bytes) | 871system.cpu0.toL2Bus.pkt_count::total 4500293 # Packet count per connected master and slave (bytes) 872system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes) 873system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80913146 # Cumulative packet size per connected master and slave (bytes) |
| 873system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 874system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) | 874system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 875system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) |
| 875system.cpu0.toL2Bus.pkt_size::total 152043238 # Cumulative packet size per connected master and slave (bytes) 876system.cpu0.toL2Bus.snoops 321922 # Total snoops (count) 877system.cpu0.toL2Bus.snoop_fanout::samples 2655621 # Request fanout histogram 878system.cpu0.toL2Bus.snoop_fanout::mean 5.082587 # Request fanout histogram 879system.cpu0.toL2Bus.snoop_fanout::stdev 0.275257 # Request fanout histogram | 876system.cpu0.toL2Bus.pkt_size::total 152082210 # Cumulative packet size per connected master and slave (bytes) 877system.cpu0.toL2Bus.snoops 322119 # Total snoops (count) 878system.cpu0.toL2Bus.snoop_fanout::samples 2656456 # Request fanout histogram 879system.cpu0.toL2Bus.snoop_fanout::mean 5.082633 # Request fanout histogram 880system.cpu0.toL2Bus.snoop_fanout::stdev 0.275327 # Request fanout histogram |
| 880system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 881system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 882system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 883system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 884system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 885system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 881system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 882system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 883system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 884system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 885system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 886system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 886system.cpu0.toL2Bus.snoop_fanout::5 2436302 91.74% 91.74% # Request fanout histogram 887system.cpu0.toL2Bus.snoop_fanout::6 219319 8.26% 100.00% # Request fanout histogram | 887system.cpu0.toL2Bus.snoop_fanout::5 2436944 91.74% 91.74% # Request fanout histogram 888system.cpu0.toL2Bus.snoop_fanout::6 219512 8.26% 100.00% # Request fanout histogram |
| 888system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 889system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 890system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 889system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 890system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 891system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 891system.cpu0.toL2Bus.snoop_fanout::total 2655621 # Request fanout histogram | 892system.cpu0.toL2Bus.snoop_fanout::total 2656456 # Request fanout histogram |
| 892system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 893system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 894system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 895system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 896system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 897system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 898system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 899system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 907system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 908system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 909system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 910system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 911system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 912system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 913system.cpu1.dtb.inst_hits 0 # ITB inst hits 914system.cpu1.dtb.inst_misses 0 # ITB inst misses | 893system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 894system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 895system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 896system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 897system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 898system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 899system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 900system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 908system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 909system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 910system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 911system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 912system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 913system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 914system.cpu1.dtb.inst_hits 0 # ITB inst hits 915system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 915system.cpu1.dtb.read_hits 12172110 # DTB read hits | 916system.cpu1.dtb.read_hits 12173926 # DTB read hits |
| 916system.cpu1.dtb.read_misses 2853 # DTB read misses | 917system.cpu1.dtb.read_misses 2853 # DTB read misses |
| 917system.cpu1.dtb.write_hits 7585805 # DTB write hits | 918system.cpu1.dtb.write_hits 7587211 # DTB write hits |
| 918system.cpu1.dtb.write_misses 506 # DTB write misses 919system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 920system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 921system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 922system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 923system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 924system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 925system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 926system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 927system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions | 919system.cpu1.dtb.write_misses 506 # DTB write misses 920system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 921system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 922system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 923system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 924system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 925system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 926system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 927system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 928system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions |
| 928system.cpu1.dtb.read_accesses 12174963 # DTB read accesses 929system.cpu1.dtb.write_accesses 7586311 # DTB write accesses | 929system.cpu1.dtb.read_accesses 12176779 # DTB read accesses 930system.cpu1.dtb.write_accesses 7587717 # DTB write accesses |
| 930system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 931system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 931system.cpu1.dtb.hits 19757915 # DTB hits | 932system.cpu1.dtb.hits 19761137 # DTB hits |
| 932system.cpu1.dtb.misses 3359 # DTB misses | 933system.cpu1.dtb.misses 3359 # DTB misses |
| 933system.cpu1.dtb.accesses 19761274 # DTB accesses | 934system.cpu1.dtb.accesses 19764496 # DTB accesses |
| 934system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 935system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 936system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 937system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 938system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 939system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 940system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 941system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 947system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 948system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 949system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 950system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 951system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 952system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 953system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 954system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 935system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 936system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 937system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 938system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 939system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 940system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 941system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 942system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 948system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 949system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 950system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 951system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 952system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 953system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 954system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 955system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 955system.cpu1.itb.inst_hits 53664371 # ITB inst hits | 956system.cpu1.itb.inst_hits 53671662 # ITB inst hits |
| 956system.cpu1.itb.inst_misses 1734 # ITB inst misses 957system.cpu1.itb.read_hits 0 # DTB read hits 958system.cpu1.itb.read_misses 0 # DTB read misses 959system.cpu1.itb.write_hits 0 # DTB write hits 960system.cpu1.itb.write_misses 0 # DTB write misses 961system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 962system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 963system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 964system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 965system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 966system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 967system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 968system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 969system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 970system.cpu1.itb.read_accesses 0 # DTB read accesses 971system.cpu1.itb.write_accesses 0 # DTB write accesses | 957system.cpu1.itb.inst_misses 1734 # ITB inst misses 958system.cpu1.itb.read_hits 0 # DTB read hits 959system.cpu1.itb.read_misses 0 # DTB read misses 960system.cpu1.itb.write_hits 0 # DTB write hits 961system.cpu1.itb.write_misses 0 # DTB write misses 962system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 963system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 964system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 965system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 966system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 967system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 968system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 969system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 970system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 971system.cpu1.itb.read_accesses 0 # DTB read accesses 972system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 972system.cpu1.itb.inst_accesses 53666105 # ITB inst accesses 973system.cpu1.itb.hits 53664371 # DTB hits | 973system.cpu1.itb.inst_accesses 53673396 # ITB inst accesses 974system.cpu1.itb.hits 53671662 # DTB hits |
| 974system.cpu1.itb.misses 1734 # DTB misses | 975system.cpu1.itb.misses 1734 # DTB misses |
| 975system.cpu1.itb.accesses 53666105 # DTB accesses 976system.cpu1.numCycles 5605295863 # number of cpu cycles simulated | 976system.cpu1.itb.accesses 53673396 # DTB accesses 977system.cpu1.numCycles 5605296302 # number of cpu cycles simulated |
| 977system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 978system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 978system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 979system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 979system.cpu1.committedInsts 51394160 # Number of instructions committed 980system.cpu1.committedOps 63338742 # Number of ops (including micro ops) committed 981system.cpu1.num_int_alu_accesses 56976202 # Number of integer alu accesses | 980system.cpu1.committedInsts 51401401 # Number of instructions committed 981system.cpu1.committedOps 63347692 # Number of ops (including micro ops) committed 982system.cpu1.num_int_alu_accesses 56984315 # Number of integer alu accesses |
| 982system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses | 983system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses |
| 983system.cpu1.num_func_calls 9170283 # number of times a function call or return occured 984system.cpu1.num_conditional_control_insts 5966381 # number of instructions that are conditional controls 985system.cpu1.num_int_insts 56976202 # number of integer instructions | 984system.cpu1.num_func_calls 9170855 # number of times a function call or return occured 985system.cpu1.num_conditional_control_insts 5967102 # number of instructions that are conditional controls 986system.cpu1.num_int_insts 56984315 # number of integer instructions |
| 986system.cpu1.num_fp_insts 1792 # number of float instructions | 987system.cpu1.num_fp_insts 1792 # number of float instructions |
| 987system.cpu1.num_int_register_reads 110660301 # number of times the integer registers were read 988system.cpu1.num_int_register_writes 41292600 # number of times the integer registers were written | 988system.cpu1.num_int_register_reads 110674840 # number of times the integer registers were read 989system.cpu1.num_int_register_writes 41298430 # number of times the integer registers were written |
| 989system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 990system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written | 990system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 991system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written |
| 991system.cpu1.num_cc_register_reads 196241872 # number of times the CC registers were read 992system.cpu1.num_cc_register_writes 18891627 # number of times the CC registers were written 993system.cpu1.num_mem_refs 20022980 # number of memory refs 994system.cpu1.num_load_insts 12287666 # Number of load instructions 995system.cpu1.num_store_insts 7735314 # Number of store instructions 996system.cpu1.num_idle_cycles 5539691262.121797 # Number of idle cycles 997system.cpu1.num_busy_cycles 65604600.878203 # Number of busy cycles 998system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles 999system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles 1000system.cpu1.Branches 15216192 # Number of branches fetched | 992system.cpu1.num_cc_register_reads 196268898 # number of times the CC registers were read 993system.cpu1.num_cc_register_writes 18894414 # number of times the CC registers were written 994system.cpu1.num_mem_refs 20026390 # number of memory refs 995system.cpu1.num_load_insts 12289548 # Number of load instructions 996system.cpu1.num_store_insts 7736842 # Number of store instructions 997system.cpu1.num_idle_cycles 5539682707.595543 # Number of idle cycles 998system.cpu1.num_busy_cycles 65613594.404457 # Number of busy cycles 999system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 1000system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 1001system.cpu1.Branches 15217497 # Number of branches fetched |
| 1001system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction | 1002system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction |
| 1002system.cpu1.op_class::IntAlu 45395839 69.36% 69.36% # Class of executed instruction 1003system.cpu1.op_class::IntMult 28345 0.04% 69.40% # Class of executed instruction | 1003system.cpu1.op_class::IntAlu 45401373 69.36% 69.36% # Class of executed instruction 1004system.cpu1.op_class::IntMult 28395 0.04% 69.40% # Class of executed instruction |
| 1004system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 1005system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 1006system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 1007system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 1008system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 1009system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 1010system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 1011system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 1019system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 1020system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 1021system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 1022system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 1023system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 1024system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 1025system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 1026system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction | 1005system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 1006system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 1007system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 1008system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 1009system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 1010system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 1011system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 1012system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 1020system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 1021system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 1022system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 1023system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 1024system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 1025system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 1026system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 1027system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction |
| 1027system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction | 1028system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction |
| 1028system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 1029system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 1030system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction | 1029system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 1030system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 1031system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction |
| 1031system.cpu1.op_class::MemRead 12287666 18.77% 88.18% # Class of executed instruction 1032system.cpu1.op_class::MemWrite 7735314 11.82% 100.00% # Class of executed instruction | 1032system.cpu1.op_class::MemRead 12289548 18.77% 88.18% # Class of executed instruction 1033system.cpu1.op_class::MemWrite 7736842 11.82% 100.00% # Class of executed instruction |
| 1033system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1034system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1034system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1035system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 1035system.cpu1.op_class::total 65450545 # Class of executed instruction | 1036system.cpu1.op_class::total 65459543 # Class of executed instruction |
| 1036system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1037system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1037system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed 1038system.cpu1.icache.tags.replacements 523179 # number of replacements 1039system.cpu1.icache.tags.tagsinuse 499.711075 # Cycle average of tags in use 1040system.cpu1.icache.tags.total_refs 53141770 # Total number of references to valid blocks. 1041system.cpu1.icache.tags.sampled_refs 523691 # Sample count of references to valid blocks. 1042system.cpu1.icache.tags.avg_refs 101.475431 # Average number of references to valid blocks. 1043system.cpu1.icache.tags.warmup_cycle 76931405000 # Cycle when the warmup percentage was hit. 1044system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711075 # Average occupied blocks per requestor | 1038system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 1039system.cpu1.icache.tags.replacements 523402 # number of replacements 1040system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use 1041system.cpu1.icache.tags.total_refs 53148838 # Total number of references to valid blocks. 1042system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks. 1043system.cpu1.icache.tags.avg_refs 101.445730 # Average number of references to valid blocks. 1044system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 1045system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor |
| 1045system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 1046system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 1047system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1048system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 1049system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 1050system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1046system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 1047system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 1048system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1049system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 1050system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 1051system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1051system.cpu1.icache.tags.tag_accesses 107854613 # Number of tag accesses 1052system.cpu1.icache.tags.data_accesses 107854613 # Number of data accesses 1053system.cpu1.icache.ReadReq_hits::cpu1.inst 53141770 # number of ReadReq hits 1054system.cpu1.icache.ReadReq_hits::total 53141770 # number of ReadReq hits 1055system.cpu1.icache.demand_hits::cpu1.inst 53141770 # number of demand (read+write) hits 1056system.cpu1.icache.demand_hits::total 53141770 # number of demand (read+write) hits 1057system.cpu1.icache.overall_hits::cpu1.inst 53141770 # number of overall hits 1058system.cpu1.icache.overall_hits::total 53141770 # number of overall hits 1059system.cpu1.icache.ReadReq_misses::cpu1.inst 523691 # number of ReadReq misses 1060system.cpu1.icache.ReadReq_misses::total 523691 # number of ReadReq misses 1061system.cpu1.icache.demand_misses::cpu1.inst 523691 # number of demand (read+write) misses 1062system.cpu1.icache.demand_misses::total 523691 # number of demand (read+write) misses 1063system.cpu1.icache.overall_misses::cpu1.inst 523691 # number of overall misses 1064system.cpu1.icache.overall_misses::total 523691 # number of overall misses 1065system.cpu1.icache.ReadReq_accesses::cpu1.inst 53665461 # number of ReadReq accesses(hits+misses) 1066system.cpu1.icache.ReadReq_accesses::total 53665461 # number of ReadReq accesses(hits+misses) 1067system.cpu1.icache.demand_accesses::cpu1.inst 53665461 # number of demand (read+write) accesses 1068system.cpu1.icache.demand_accesses::total 53665461 # number of demand (read+write) accesses 1069system.cpu1.icache.overall_accesses::cpu1.inst 53665461 # number of overall (read+write) accesses 1070system.cpu1.icache.overall_accesses::total 53665461 # number of overall (read+write) accesses 1071system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses 1072system.cpu1.icache.ReadReq_miss_rate::total 0.009758 # miss rate for ReadReq accesses 1073system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses 1074system.cpu1.icache.demand_miss_rate::total 0.009758 # miss rate for demand accesses 1075system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses 1076system.cpu1.icache.overall_miss_rate::total 0.009758 # miss rate for overall accesses | 1052system.cpu1.icache.tags.tag_accesses 107869418 # Number of tag accesses 1053system.cpu1.icache.tags.data_accesses 107869418 # Number of data accesses 1054system.cpu1.icache.ReadReq_hits::cpu1.inst 53148838 # number of ReadReq hits 1055system.cpu1.icache.ReadReq_hits::total 53148838 # number of ReadReq hits 1056system.cpu1.icache.demand_hits::cpu1.inst 53148838 # number of demand (read+write) hits 1057system.cpu1.icache.demand_hits::total 53148838 # number of demand (read+write) hits 1058system.cpu1.icache.overall_hits::cpu1.inst 53148838 # number of overall hits 1059system.cpu1.icache.overall_hits::total 53148838 # number of overall hits 1060system.cpu1.icache.ReadReq_misses::cpu1.inst 523914 # number of ReadReq misses 1061system.cpu1.icache.ReadReq_misses::total 523914 # number of ReadReq misses 1062system.cpu1.icache.demand_misses::cpu1.inst 523914 # number of demand (read+write) misses 1063system.cpu1.icache.demand_misses::total 523914 # number of demand (read+write) misses 1064system.cpu1.icache.overall_misses::cpu1.inst 523914 # number of overall misses 1065system.cpu1.icache.overall_misses::total 523914 # number of overall misses 1066system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672752 # number of ReadReq accesses(hits+misses) 1067system.cpu1.icache.ReadReq_accesses::total 53672752 # number of ReadReq accesses(hits+misses) 1068system.cpu1.icache.demand_accesses::cpu1.inst 53672752 # number of demand (read+write) accesses 1069system.cpu1.icache.demand_accesses::total 53672752 # number of demand (read+write) accesses 1070system.cpu1.icache.overall_accesses::cpu1.inst 53672752 # number of overall (read+write) accesses 1071system.cpu1.icache.overall_accesses::total 53672752 # number of overall (read+write) accesses 1072system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 1073system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 1074system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 1075system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 1076system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 1077system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses |
| 1077system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1078system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1080system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1082system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1083system.cpu1.icache.fast_writes 0 # number of fast writes performed 1084system.cpu1.icache.cache_copies 0 # number of cache copies performed 1085system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1086system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 1087system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 1088system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 1089system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 1090system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1091system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 1092system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1093system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 1094system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1078system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1079system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1081system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1082system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1083system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1084system.cpu1.icache.fast_writes 0 # number of fast writes performed 1085system.cpu1.icache.cache_copies 0 # number of cache copies performed 1086system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1087system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 1088system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 1089system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 1090system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 1091system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1092system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 1093system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1094system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 1095system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1095system.cpu1.l2cache.tags.replacements 48552 # number of replacements 1096system.cpu1.l2cache.tags.tagsinuse 15311.760536 # Cycle average of tags in use 1097system.cpu1.l2cache.tags.total_refs 716558 # Total number of references to valid blocks. 1098system.cpu1.l2cache.tags.sampled_refs 63379 # Sample count of references to valid blocks. 1099system.cpu1.l2cache.tags.avg_refs 11.305922 # Average number of references to valid blocks. | 1096system.cpu1.l2cache.tags.replacements 48605 # number of replacements 1097system.cpu1.l2cache.tags.tagsinuse 15302.416394 # Cycle average of tags in use 1098system.cpu1.l2cache.tags.total_refs 716648 # Total number of references to valid blocks. 1099system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. 1100system.cpu1.l2cache.tags.avg_refs 11.297716 # Average number of references to valid blocks. |
| 1100system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1101system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1101system.cpu1.l2cache.tags.occ_blocks::writebacks 8243.045220 # Average occupied blocks per requestor 1102system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.958358 # Average occupied blocks per requestor 1103system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015688 # Average occupied blocks per requestor 1104system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3303.816337 # Average occupied blocks per requestor 1105system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.924934 # Average occupied blocks per requestor 1106system.cpu1.l2cache.tags.occ_percent::writebacks 0.503116 # Average percentage of cache occupancy 1107system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy 1108system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 1109system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201649 # Average percentage of cache occupancy 1110system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229488 # Average percentage of cache occupancy 1111system.cpu1.l2cache.tags.occ_percent::total 0.934556 # Average percentage of cache occupancy 1112system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id 1113system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14809 # Occupied blocks per task id | 1102system.cpu1.l2cache.tags.occ_blocks::writebacks 8289.635884 # Average occupied blocks per requestor 1103system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.959660 # Average occupied blocks per requestor 1104system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.032491 # Average occupied blocks per requestor 1105system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3282.997092 # Average occupied blocks per requestor 1106system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3722.791267 # Average occupied blocks per requestor 1107system.cpu1.l2cache.tags.occ_percent::writebacks 0.505959 # Average percentage of cache occupancy 1108system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000303 # Average percentage of cache occupancy 1109system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 1110system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200378 # Average percentage of cache occupancy 1111system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227221 # Average percentage of cache occupancy 1112system.cpu1.l2cache.tags.occ_percent::total 0.933985 # Average percentage of cache occupancy 1113system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id 1114system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id |
| 1114system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id | 1115system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id |
| 1115system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 1116system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1117system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 540 # Occupied blocks per task id 1118system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9336 # Occupied blocks per task id 1119system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4933 # Occupied blocks per task id 1120system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id 1121system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903870 # Percentage of cache occupancy per task id 1122system.cpu1.l2cache.tags.tag_accesses 15206583 # Number of tag accesses 1123system.cpu1.l2cache.tags.data_accesses 15206583 # Number of data accesses 1124system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3143 # number of ReadReq hits 1125system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1725 # number of ReadReq hits 1126system.cpu1.l2cache.ReadReq_hits::cpu1.inst 509849 # number of ReadReq hits 1127system.cpu1.l2cache.ReadReq_hits::cpu1.data 99406 # number of ReadReq hits 1128system.cpu1.l2cache.ReadReq_hits::total 614123 # number of ReadReq hits 1129system.cpu1.l2cache.Writeback_hits::writebacks 120669 # number of Writeback hits 1130system.cpu1.l2cache.Writeback_hits::total 120669 # number of Writeback hits 1131system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits 1132system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits 1133system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19820 # number of ReadExReq hits 1134system.cpu1.l2cache.ReadExReq_hits::total 19820 # number of ReadExReq hits 1135system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3143 # number of demand (read+write) hits 1136system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1725 # number of demand (read+write) hits 1137system.cpu1.l2cache.demand_hits::cpu1.inst 509849 # number of demand (read+write) hits 1138system.cpu1.l2cache.demand_hits::cpu1.data 119226 # number of demand (read+write) hits 1139system.cpu1.l2cache.demand_hits::total 633943 # number of demand (read+write) hits 1140system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3143 # number of overall hits 1141system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1725 # number of overall hits 1142system.cpu1.l2cache.overall_hits::cpu1.inst 509849 # number of overall hits 1143system.cpu1.l2cache.overall_hits::cpu1.data 119226 # number of overall hits 1144system.cpu1.l2cache.overall_hits::total 633943 # number of overall hits 1145system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses 1146system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses 1147system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13842 # number of ReadReq misses 1148system.cpu1.l2cache.ReadReq_misses::cpu1.data 73217 # number of ReadReq misses 1149system.cpu1.l2cache.ReadReq_misses::total 87678 # number of ReadReq misses 1150system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28845 # number of UpgradeReq misses 1151system.cpu1.l2cache.UpgradeReq_misses::total 28845 # number of UpgradeReq misses 1152system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22527 # number of SCUpgradeReq misses 1153system.cpu1.l2cache.SCUpgradeReq_misses::total 22527 # number of SCUpgradeReq misses 1154system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43793 # number of ReadExReq misses 1155system.cpu1.l2cache.ReadExReq_misses::total 43793 # number of ReadExReq misses 1156system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses 1157system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses 1158system.cpu1.l2cache.demand_misses::cpu1.inst 13842 # number of demand (read+write) misses 1159system.cpu1.l2cache.demand_misses::cpu1.data 117010 # number of demand (read+write) misses 1160system.cpu1.l2cache.demand_misses::total 131471 # number of demand (read+write) misses 1161system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses 1162system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses 1163system.cpu1.l2cache.overall_misses::cpu1.inst 13842 # number of overall misses 1164system.cpu1.l2cache.overall_misses::cpu1.data 117010 # number of overall misses 1165system.cpu1.l2cache.overall_misses::total 131471 # number of overall misses 1166system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3491 # number of ReadReq accesses(hits+misses) 1167system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) 1168system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523691 # number of ReadReq accesses(hits+misses) 1169system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172623 # number of ReadReq accesses(hits+misses) 1170system.cpu1.l2cache.ReadReq_accesses::total 701801 # number of ReadReq accesses(hits+misses) 1171system.cpu1.l2cache.Writeback_accesses::writebacks 120669 # number of Writeback accesses(hits+misses) 1172system.cpu1.l2cache.Writeback_accesses::total 120669 # number of Writeback accesses(hits+misses) 1173system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28853 # number of UpgradeReq accesses(hits+misses) 1174system.cpu1.l2cache.UpgradeReq_accesses::total 28853 # number of UpgradeReq accesses(hits+misses) 1175system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22527 # number of SCUpgradeReq accesses(hits+misses) 1176system.cpu1.l2cache.SCUpgradeReq_accesses::total 22527 # number of SCUpgradeReq accesses(hits+misses) 1177system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63613 # number of ReadExReq accesses(hits+misses) 1178system.cpu1.l2cache.ReadExReq_accesses::total 63613 # number of ReadExReq accesses(hits+misses) 1179system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3491 # number of demand (read+write) accesses 1180system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses 1181system.cpu1.l2cache.demand_accesses::cpu1.inst 523691 # number of demand (read+write) accesses 1182system.cpu1.l2cache.demand_accesses::cpu1.data 236236 # number of demand (read+write) accesses 1183system.cpu1.l2cache.demand_accesses::total 765414 # number of demand (read+write) accesses 1184system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3491 # number of overall (read+write) accesses 1185system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses 1186system.cpu1.l2cache.overall_accesses::cpu1.inst 523691 # number of overall (read+write) accesses 1187system.cpu1.l2cache.overall_accesses::cpu1.data 236236 # number of overall (read+write) accesses 1188system.cpu1.l2cache.overall_accesses::total 765414 # number of overall (read+write) accesses 1189system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for ReadReq accesses 1190system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135772 # miss rate for ReadReq accesses 1191system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026432 # miss rate for ReadReq accesses 1192system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424144 # miss rate for ReadReq accesses 1193system.cpu1.l2cache.ReadReq_miss_rate::total 0.124933 # miss rate for ReadReq accesses 1194system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses 1195system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses | 1116system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 1117system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id 1118system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 551 # Occupied blocks per task id 1119system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9351 # Occupied blocks per task id 1120system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4901 # Occupied blocks per task id 1121system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id 1122system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903503 # Percentage of cache occupancy per task id 1123system.cpu1.l2cache.tags.tag_accesses 15213580 # Number of tag accesses 1124system.cpu1.l2cache.tags.data_accesses 15213580 # Number of data accesses 1125system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3243 # number of ReadReq hits 1126system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1759 # number of ReadReq hits 1127system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510095 # number of ReadReq hits 1128system.cpu1.l2cache.ReadReq_hits::cpu1.data 99336 # number of ReadReq hits 1129system.cpu1.l2cache.ReadReq_hits::total 614433 # number of ReadReq hits 1130system.cpu1.l2cache.Writeback_hits::writebacks 120654 # number of Writeback hits 1131system.cpu1.l2cache.Writeback_hits::total 120654 # number of Writeback hits 1132system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits 1133system.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits 1134system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19759 # number of ReadExReq hits 1135system.cpu1.l2cache.ReadExReq_hits::total 19759 # number of ReadExReq hits 1136system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3243 # number of demand (read+write) hits 1137system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1759 # number of demand (read+write) hits 1138system.cpu1.l2cache.demand_hits::cpu1.inst 510095 # number of demand (read+write) hits 1139system.cpu1.l2cache.demand_hits::cpu1.data 119095 # number of demand (read+write) hits 1140system.cpu1.l2cache.demand_hits::total 634192 # number of demand (read+write) hits 1141system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3243 # number of overall hits 1142system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1759 # number of overall hits 1143system.cpu1.l2cache.overall_hits::cpu1.inst 510095 # number of overall hits 1144system.cpu1.l2cache.overall_hits::cpu1.data 119095 # number of overall hits 1145system.cpu1.l2cache.overall_hits::total 634192 # number of overall hits 1146system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 343 # number of ReadReq misses 1147system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses 1148system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13819 # number of ReadReq misses 1149system.cpu1.l2cache.ReadReq_misses::cpu1.data 73339 # number of ReadReq misses 1150system.cpu1.l2cache.ReadReq_misses::total 87768 # number of ReadReq misses 1151system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28855 # number of UpgradeReq misses 1152system.cpu1.l2cache.UpgradeReq_misses::total 28855 # number of UpgradeReq misses 1153system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22557 # number of SCUpgradeReq misses 1154system.cpu1.l2cache.SCUpgradeReq_misses::total 22557 # number of SCUpgradeReq misses 1155system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43856 # number of ReadExReq misses 1156system.cpu1.l2cache.ReadExReq_misses::total 43856 # number of ReadExReq misses 1157system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 343 # number of demand (read+write) misses 1158system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses 1159system.cpu1.l2cache.demand_misses::cpu1.inst 13819 # number of demand (read+write) misses 1160system.cpu1.l2cache.demand_misses::cpu1.data 117195 # number of demand (read+write) misses 1161system.cpu1.l2cache.demand_misses::total 131624 # number of demand (read+write) misses 1162system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 343 # number of overall misses 1163system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses 1164system.cpu1.l2cache.overall_misses::cpu1.inst 13819 # number of overall misses 1165system.cpu1.l2cache.overall_misses::cpu1.data 117195 # number of overall misses 1166system.cpu1.l2cache.overall_misses::total 131624 # number of overall misses 1167system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3586 # number of ReadReq accesses(hits+misses) 1168system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2026 # number of ReadReq accesses(hits+misses) 1169system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523914 # number of ReadReq accesses(hits+misses) 1170system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172675 # number of ReadReq accesses(hits+misses) 1171system.cpu1.l2cache.ReadReq_accesses::total 702201 # number of ReadReq accesses(hits+misses) 1172system.cpu1.l2cache.Writeback_accesses::writebacks 120654 # number of Writeback accesses(hits+misses) 1173system.cpu1.l2cache.Writeback_accesses::total 120654 # number of Writeback accesses(hits+misses) 1174system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28862 # number of UpgradeReq accesses(hits+misses) 1175system.cpu1.l2cache.UpgradeReq_accesses::total 28862 # number of UpgradeReq accesses(hits+misses) 1176system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22557 # number of SCUpgradeReq accesses(hits+misses) 1177system.cpu1.l2cache.SCUpgradeReq_accesses::total 22557 # number of SCUpgradeReq accesses(hits+misses) 1178system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 1179system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 1180system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3586 # number of demand (read+write) accesses 1181system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2026 # number of demand (read+write) accesses 1182system.cpu1.l2cache.demand_accesses::cpu1.inst 523914 # number of demand (read+write) accesses 1183system.cpu1.l2cache.demand_accesses::cpu1.data 236290 # number of demand (read+write) accesses 1184system.cpu1.l2cache.demand_accesses::total 765816 # number of demand (read+write) accesses 1185system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3586 # number of overall (read+write) accesses 1186system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2026 # number of overall (read+write) accesses 1187system.cpu1.l2cache.overall_accesses::cpu1.inst 523914 # number of overall (read+write) accesses 1188system.cpu1.l2cache.overall_accesses::cpu1.data 236290 # number of overall (read+write) accesses 1189system.cpu1.l2cache.overall_accesses::total 765816 # number of overall (read+write) accesses 1190system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for ReadReq accesses 1191system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.131787 # miss rate for ReadReq accesses 1192system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026376 # miss rate for ReadReq accesses 1193system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424723 # miss rate for ReadReq accesses 1194system.cpu1.l2cache.ReadReq_miss_rate::total 0.124990 # miss rate for ReadReq accesses 1195system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses 1196system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses |
| 1196system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1197system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1197system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1198system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1198system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688428 # miss rate for ReadExReq accesses 1199system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688428 # miss rate for ReadExReq accesses 1200system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for demand accesses 1201system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135772 # miss rate for demand accesses 1202system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026432 # miss rate for demand accesses 1203system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495310 # miss rate for demand accesses 1204system.cpu1.l2cache.demand_miss_rate::total 0.171765 # miss rate for demand accesses 1205system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for overall accesses 1206system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135772 # miss rate for overall accesses 1207system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026432 # miss rate for overall accesses 1208system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495310 # miss rate for overall accesses 1209system.cpu1.l2cache.overall_miss_rate::total 0.171765 # miss rate for overall accesses | 1199system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689397 # miss rate for ReadExReq accesses 1200system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689397 # miss rate for ReadExReq accesses 1201system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for demand accesses 1202system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.131787 # miss rate for demand accesses 1203system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026376 # miss rate for demand accesses 1204system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495980 # miss rate for demand accesses 1205system.cpu1.l2cache.demand_miss_rate::total 0.171874 # miss rate for demand accesses 1206system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.095650 # miss rate for overall accesses 1207system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.131787 # miss rate for overall accesses 1208system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026376 # miss rate for overall accesses 1209system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495980 # miss rate for overall accesses 1210system.cpu1.l2cache.overall_miss_rate::total 0.171874 # miss rate for overall accesses |
| 1210system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1211system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1212system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1213system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1214system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1215system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1216system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1217system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1211system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1212system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1213system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1214system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1215system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1216system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1217system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1218system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1218system.cpu1.l2cache.writebacks::writebacks 33034 # number of writebacks 1219system.cpu1.l2cache.writebacks::total 33034 # number of writebacks | 1219system.cpu1.l2cache.writebacks::writebacks 32966 # number of writebacks 1220system.cpu1.l2cache.writebacks::total 32966 # number of writebacks |
| 1220system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1221system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1221system.cpu1.dcache.tags.replacements 191901 # number of replacements 1222system.cpu1.dcache.tags.tagsinuse 472.757627 # Cycle average of tags in use 1223system.cpu1.dcache.tags.total_refs 19500351 # Total number of references to valid blocks. 1224system.cpu1.dcache.tags.sampled_refs 192255 # Sample count of references to valid blocks. 1225system.cpu1.dcache.tags.avg_refs 101.429617 # Average number of references to valid blocks. 1226system.cpu1.dcache.tags.warmup_cycle 105851562500 # Cycle when the warmup percentage was hit. 1227system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757627 # Average occupied blocks per requestor 1228system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy 1229system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy | 1222system.cpu1.dcache.tags.replacements 191947 # number of replacements 1223system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use 1224system.cpu1.dcache.tags.total_refs 19503515 # Total number of references to valid blocks. 1225system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks. 1226system.cpu1.dcache.tags.avg_refs 101.421807 # Average number of references to valid blocks. 1227system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 1228system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor 1229system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 1230system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy |
| 1230system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 1231system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 1232system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 1233system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id | 1231system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 1232system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 1233system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 1234system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id |
| 1234system.cpu1.dcache.tags.tag_accesses 39745522 # Number of tag accesses 1235system.cpu1.dcache.tags.data_accesses 39745522 # Number of data accesses 1236system.cpu1.dcache.ReadReq_hits::cpu1.data 11856979 # number of ReadReq hits 1237system.cpu1.dcache.ReadReq_hits::total 11856979 # number of ReadReq hits 1238system.cpu1.dcache.WriteReq_hits::cpu1.data 7396120 # number of WriteReq hits 1239system.cpu1.dcache.WriteReq_hits::total 7396120 # number of WriteReq hits 1240system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50084 # number of SoftPFReq hits 1241system.cpu1.dcache.SoftPFReq_hits::total 50084 # number of SoftPFReq hits 1242system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91418 # number of LoadLockedReq hits 1243system.cpu1.dcache.LoadLockedReq_hits::total 91418 # number of LoadLockedReq hits 1244system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72426 # number of StoreCondReq hits 1245system.cpu1.dcache.StoreCondReq_hits::total 72426 # number of StoreCondReq hits 1246system.cpu1.dcache.demand_hits::cpu1.data 19253099 # number of demand (read+write) hits 1247system.cpu1.dcache.demand_hits::total 19253099 # number of demand (read+write) hits 1248system.cpu1.dcache.overall_hits::cpu1.data 19303183 # number of overall hits 1249system.cpu1.dcache.overall_hits::total 19303183 # number of overall hits 1250system.cpu1.dcache.ReadReq_misses::cpu1.data 136590 # number of ReadReq misses 1251system.cpu1.dcache.ReadReq_misses::total 136590 # number of ReadReq misses 1252system.cpu1.dcache.WriteReq_misses::cpu1.data 92466 # number of WriteReq misses 1253system.cpu1.dcache.WriteReq_misses::total 92466 # number of WriteReq misses 1254system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30716 # number of SoftPFReq misses 1255system.cpu1.dcache.SoftPFReq_misses::total 30716 # number of SoftPFReq misses 1256system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5317 # number of LoadLockedReq misses 1257system.cpu1.dcache.LoadLockedReq_misses::total 5317 # number of LoadLockedReq misses 1258system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22527 # number of StoreCondReq misses 1259system.cpu1.dcache.StoreCondReq_misses::total 22527 # number of StoreCondReq misses 1260system.cpu1.dcache.demand_misses::cpu1.data 229056 # number of demand (read+write) misses 1261system.cpu1.dcache.demand_misses::total 229056 # number of demand (read+write) misses 1262system.cpu1.dcache.overall_misses::cpu1.data 259772 # number of overall misses 1263system.cpu1.dcache.overall_misses::total 259772 # number of overall misses 1264system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993569 # number of ReadReq accesses(hits+misses) 1265system.cpu1.dcache.ReadReq_accesses::total 11993569 # number of ReadReq accesses(hits+misses) 1266system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488586 # number of WriteReq accesses(hits+misses) 1267system.cpu1.dcache.WriteReq_accesses::total 7488586 # number of WriteReq accesses(hits+misses) 1268system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) 1269system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) 1270system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96735 # number of LoadLockedReq accesses(hits+misses) 1271system.cpu1.dcache.LoadLockedReq_accesses::total 96735 # number of LoadLockedReq accesses(hits+misses) 1272system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94953 # number of StoreCondReq accesses(hits+misses) 1273system.cpu1.dcache.StoreCondReq_accesses::total 94953 # number of StoreCondReq accesses(hits+misses) 1274system.cpu1.dcache.demand_accesses::cpu1.data 19482155 # number of demand (read+write) accesses 1275system.cpu1.dcache.demand_accesses::total 19482155 # number of demand (read+write) accesses 1276system.cpu1.dcache.overall_accesses::cpu1.data 19562955 # number of overall (read+write) accesses 1277system.cpu1.dcache.overall_accesses::total 19562955 # number of overall (read+write) accesses 1278system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011389 # miss rate for ReadReq accesses 1279system.cpu1.dcache.ReadReq_miss_rate::total 0.011389 # miss rate for ReadReq accesses 1280system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses 1281system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses 1282system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380149 # miss rate for SoftPFReq accesses 1283system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380149 # miss rate for SoftPFReq accesses 1284system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054965 # miss rate for LoadLockedReq accesses 1285system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054965 # miss rate for LoadLockedReq accesses 1286system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237244 # miss rate for StoreCondReq accesses 1287system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237244 # miss rate for StoreCondReq accesses 1288system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 1289system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 1290system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 1291system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses | 1235system.cpu1.dcache.tags.tag_accesses 39752012 # Number of tag accesses 1236system.cpu1.dcache.tags.data_accesses 39752012 # Number of data accesses 1237system.cpu1.dcache.ReadReq_hits::cpu1.data 11858696 # number of ReadReq hits 1238system.cpu1.dcache.ReadReq_hits::total 11858696 # number of ReadReq hits 1239system.cpu1.dcache.WriteReq_hits::cpu1.data 7397487 # number of WriteReq hits 1240system.cpu1.dcache.WriteReq_hits::total 7397487 # number of WriteReq hits 1241system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 1242system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits 1243system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 1244system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 1245system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72422 # number of StoreCondReq hits 1246system.cpu1.dcache.StoreCondReq_hits::total 72422 # number of StoreCondReq hits 1247system.cpu1.dcache.demand_hits::cpu1.data 19256183 # number of demand (read+write) hits 1248system.cpu1.dcache.demand_hits::total 19256183 # number of demand (read+write) hits 1249system.cpu1.dcache.overall_hits::cpu1.data 19306283 # number of overall hits 1250system.cpu1.dcache.overall_hits::total 19306283 # number of overall hits 1251system.cpu1.dcache.ReadReq_misses::cpu1.data 136639 # number of ReadReq misses 1252system.cpu1.dcache.ReadReq_misses::total 136639 # number of ReadReq misses 1253system.cpu1.dcache.WriteReq_misses::cpu1.data 92477 # number of WriteReq misses 1254system.cpu1.dcache.WriteReq_misses::total 92477 # number of WriteReq misses 1255system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses 1256system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses 1257system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 1258system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 1259system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22557 # number of StoreCondReq misses 1260system.cpu1.dcache.StoreCondReq_misses::total 22557 # number of StoreCondReq misses 1261system.cpu1.dcache.demand_misses::cpu1.data 229116 # number of demand (read+write) misses 1262system.cpu1.dcache.demand_misses::total 229116 # number of demand (read+write) misses 1263system.cpu1.dcache.overall_misses::cpu1.data 259834 # number of overall misses 1264system.cpu1.dcache.overall_misses::total 259834 # number of overall misses 1265system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995335 # number of ReadReq accesses(hits+misses) 1266system.cpu1.dcache.ReadReq_accesses::total 11995335 # number of ReadReq accesses(hits+misses) 1267system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489964 # number of WriteReq accesses(hits+misses) 1268system.cpu1.dcache.WriteReq_accesses::total 7489964 # number of WriteReq accesses(hits+misses) 1269system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 1270system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 1271system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 1272system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 1273system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 1274system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 1275system.cpu1.dcache.demand_accesses::cpu1.data 19485299 # number of demand (read+write) accesses 1276system.cpu1.dcache.demand_accesses::total 19485299 # number of demand (read+write) accesses 1277system.cpu1.dcache.overall_accesses::cpu1.data 19566117 # number of overall (read+write) accesses 1278system.cpu1.dcache.overall_accesses::total 19566117 # number of overall (read+write) accesses 1279system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses 1280system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 1281system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012347 # miss rate for WriteReq accesses 1282system.cpu1.dcache.WriteReq_miss_rate::total 0.012347 # miss rate for WriteReq accesses 1283system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses 1284system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses 1285system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 1286system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 1287system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237495 # miss rate for StoreCondReq accesses 1288system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237495 # miss rate for StoreCondReq accesses 1289system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses 1290system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses 1291system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses 1292system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses |
| 1292system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1293system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1294system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1295system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1296system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1297system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1298system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1299system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1293system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1294system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1295system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1296system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1297system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1298system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1299system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1300system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1300system.cpu1.dcache.writebacks::writebacks 120669 # number of writebacks 1301system.cpu1.dcache.writebacks::total 120669 # number of writebacks | 1301system.cpu1.dcache.writebacks::writebacks 120654 # number of writebacks 1302system.cpu1.dcache.writebacks::total 120654 # number of writebacks |
| 1302system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1303system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1303system.cpu1.toL2Bus.trans_dist::ReadReq 709063 # Transaction distribution 1304system.cpu1.toL2Bus.trans_dist::ReadResp 709063 # Transaction distribution 1305system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution 1306system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution 1307system.cpu1.toL2Bus.trans_dist::Writeback 120669 # Transaction distribution 1308system.cpu1.toL2Bus.trans_dist::UpgradeReq 28853 # Transaction distribution 1309system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22527 # Transaction distribution 1310system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution 1311system.cpu1.toL2Bus.trans_dist::ReadExReq 63613 # Transaction distribution 1312system.cpu1.toL2Bus.trans_dist::ReadExResp 63613 # Transaction distribution 1313system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1047738 # Packet count per connected master and slave (bytes) 1314system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707355 # Packet count per connected master and slave (bytes) | 1304system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution 1305system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution 1306system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 1307system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 1308system.cpu1.toL2Bus.trans_dist::Writeback 120654 # Transaction distribution 1309system.cpu1.toL2Bus.trans_dist::UpgradeReq 28862 # Transaction distribution 1310system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22557 # Transaction distribution 1311system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution 1312system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 1313system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 1314system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes) 1315system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707532 # Packet count per connected master and slave (bytes) |
| 1315system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1316system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) | 1316system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1317system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) |
| 1317system.cpu1.toL2Bus.pkt_count::total 1773789 # Packet count per connected master and slave (bytes) 1318system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33516936 # Cumulative packet size per connected master and slave (bytes) 1319system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22861090 # Cumulative packet size per connected master and slave (bytes) | 1318system.cpu1.toL2Bus.pkt_count::total 1774410 # Packet count per connected master and slave (bytes) 1319system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes) 1320system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22863598 # Cumulative packet size per connected master and slave (bytes) |
| 1320system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1321system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) | 1321system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1322system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) |
| 1322system.cpu1.toL2Bus.pkt_size::total 56415418 # Cumulative packet size per connected master and slave (bytes) 1323system.cpu1.toL2Bus.snoops 499577 # Total snoops (count) 1324system.cpu1.toL2Bus.snoop_fanout::samples 1371208 # Request fanout histogram 1325system.cpu1.toL2Bus.snoop_fanout::mean 5.313508 # Request fanout histogram 1326system.cpu1.toL2Bus.snoop_fanout::stdev 0.463919 # Request fanout histogram | 1323system.cpu1.toL2Bus.pkt_size::total 56432194 # Cumulative packet size per connected master and slave (bytes) 1324system.cpu1.toL2Bus.snoops 499552 # Total snoops (count) 1325system.cpu1.toL2Bus.snoop_fanout::samples 1371519 # Request fanout histogram 1326system.cpu1.toL2Bus.snoop_fanout::mean 5.313444 # Request fanout histogram 1327system.cpu1.toL2Bus.snoop_fanout::stdev 0.463893 # Request fanout histogram |
| 1327system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1328system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1329system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1330system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1331system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1332system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1328system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1329system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1330system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1331system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1332system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1333system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1333system.cpu1.toL2Bus.snoop_fanout::5 941324 68.65% 68.65% # Request fanout histogram 1334system.cpu1.toL2Bus.snoop_fanout::6 429884 31.35% 100.00% # Request fanout histogram | 1334system.cpu1.toL2Bus.snoop_fanout::5 941625 68.66% 68.66% # Request fanout histogram 1335system.cpu1.toL2Bus.snoop_fanout::6 429894 31.34% 100.00% # Request fanout histogram |
| 1335system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1336system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1337system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1336system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1337system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1338system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1338system.cpu1.toL2Bus.snoop_fanout::total 1371208 # Request fanout histogram | 1339system.cpu1.toL2Bus.snoop_fanout::total 1371519 # Request fanout histogram |
| 1339system.iocache.tags.replacements 36442 # number of replacements | 1340system.iocache.tags.replacements 36442 # number of replacements |
| 1340system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use | 1341system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use |
| 1341system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1342system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1343system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1342system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1343system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1344system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1344system.iocache.tags.warmup_cycle 246641119509 # Cycle when the warmup percentage was hit. 1345system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor | 1345system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 1346system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor |
| 1346system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1347system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 1348system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1349system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1350system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1351system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1352system.iocache.tags.data_accesses 328284 # Number of data accesses 1353system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits --- 32 unchanged lines hidden --- | 1347system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1348system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 1349system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1350system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1351system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1352system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1353system.iocache.tags.data_accesses 328284 # Number of data accesses 1354system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits --- 32 unchanged lines hidden --- |