| stats.txt (10409:8c80b91944c5) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.900830 # Number of seconds simulated 4sim_ticks 900829868000 # Number of ticks simulated 5final_tick 900829868000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.802882 # Number of seconds simulated 4sim_ticks 2802882496500 # Number of ticks simulated 5final_tick 2802882496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1355321 # Simulator instruction rate (inst/s) 8host_op_rate 1632835 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19839612971 # Simulator tick rate (ticks/s) 10host_mem_usage 467260 # Number of bytes of host memory used 11host_seconds 45.41 # Real time elapsed on the host 12sim_insts 61539136 # Number of instructions simulated 13sim_ops 74139862 # Number of ops (including micro ops) simulated | 7host_inst_rate 1330236 # Simulator instruction rate (inst/s) 8host_op_rate 1620871 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25395755903 # Simulator tick rate (ticks/s) 10host_mem_usage 564312 # Number of bytes of host memory used 11host_seconds 110.37 # Real time elapsed on the host 12sim_insts 146815698 # Number of instructions simulated 13sim_ops 178892459 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory | 16system.realview.nvmem.bytes_read::cpu0.inst 24 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 52 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 76 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 24 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 52 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 76 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 6 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 19 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 27 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 19 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 19 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 27 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory |
| 36system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory | 36system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory |
| 37system.physmem.bytes_read::cpu0.inst 468620 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 6508860 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.inst 266564 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.data 2938616 # Number of bytes read from this memory 41system.physmem.bytes_read::total 49504452 # Number of bytes read from this memory 42system.physmem.bytes_inst_read::cpu0.inst 468620 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::cpu1.inst 266564 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::total 735184 # Number of instructions bytes read from this memory 45system.physmem.bytes_written::writebacks 3365568 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory | 37system.physmem.bytes_read::cpu0.inst 1117476 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 9458684 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.inst 149780 # Number of bytes read from this memory 41system.physmem.bytes_read::cpu1.data 1082912 # Number of bytes read from this memory 42system.physmem.bytes_read::total 11810580 # Number of bytes read from this memory 43system.physmem.bytes_inst_read::cpu0.inst 1117476 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::cpu1.inst 149780 # Number of instructions bytes read from this memory 45system.physmem.bytes_inst_read::total 1267256 # Number of instructions bytes read from this memory 46system.physmem.bytes_written::writebacks 6081216 # Number of bytes written to this memory 47system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 48system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory |
| 47system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory | 49system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory |
| 48system.physmem.bytes_written::total 6392656 # Number of bytes written to this memory 49system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory | 50system.physmem.bytes_written::total 8417296 # Number of bytes written to this memory 51system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory |
| 51system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory | 53system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory |
| 52system.physmem.num_reads::cpu0.inst 13550 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.data 101760 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.inst 4256 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.data 45934 # Number of read requests responded to by this memory 56system.physmem.num_reads::total 5080703 # Number of read requests responded to by this memory 57system.physmem.num_writes::writebacks 52587 # Number of write requests responded to by this memory 58system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory | 54system.physmem.num_reads::cpu0.inst 25914 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu0.data 148317 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu1.inst 2495 # Number of read requests responded to by this memory 58system.physmem.num_reads::cpu1.data 16944 # Number of read requests responded to by this memory 59system.physmem.num_reads::total 193697 # Number of read requests responded to by this memory 60system.physmem.num_writes::writebacks 95019 # Number of write requests responded to by this memory 61system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 62system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory |
| 59system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory | 63system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory |
| 60system.physmem.num_writes::total 809359 # Number of write requests responded to by this memory 61system.physmem.bw_read::realview.clcd 43650418 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu0.dtb.walker 71 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu0.itb.walker 142 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.inst 520209 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.data 7225404 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu1.inst 295909 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu1.data 3262121 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::total 54954275 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_inst_read::cpu0.inst 520209 # Instruction read bandwidth from this memory (bytes/s) 70system.physmem.bw_inst_read::cpu1.inst 295909 # Instruction read bandwidth from this memory (bytes/s) 71system.physmem.bw_inst_read::total 816119 # Instruction read bandwidth from this memory (bytes/s) 72system.physmem.bw_write::writebacks 3736075 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_write::cpu0.data 3360288 # Write bandwidth from this memory (bytes/s) 74system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) 75system.physmem.bw_write::total 7096408 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_total::writebacks 3736075 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.clcd 43650418 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.dtb.walker 71 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.itb.walker 142 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu0.inst 520209 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu0.data 10585693 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.inst 295909 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.data 3262165 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::total 62050682 # Total bandwidth to/from this memory (bytes/s) 85system.membus.trans_dist::ReadReq 6129610 # Transaction distribution 86system.membus.trans_dist::ReadResp 6129610 # Transaction distribution 87system.membus.trans_dist::WriteReq 767040 # Transaction distribution 88system.membus.trans_dist::WriteResp 767040 # Transaction distribution 89system.membus.trans_dist::Writeback 52587 # Transaction distribution 90system.membus.trans_dist::UpgradeReq 37380 # Transaction distribution 91system.membus.trans_dist::SCUpgradeReq 20039 # Transaction distribution 92system.membus.trans_dist::UpgradeResp 14449 # Transaction distribution 93system.membus.trans_dist::ReadExReq 163617 # Transaction distribution 94system.membus.trans_dist::ReadExResp 136674 # Transaction distribution 95system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382414 # Packet count per connected master and slave (bytes) 96system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 97system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8564 # Packet count per connected master and slave (bytes) 98system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 99system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 682 # Packet count per connected master and slave (bytes) 100system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1995948 # Packet count per connected master and slave (bytes) 101system.membus.pkt_count_system.l2c.mem_side::total 4387646 # Packet count per connected master and slave (bytes) 102system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 9830400 # Packet count per connected master and slave (bytes) 103system.membus.pkt_count_system.iocache.mem_side::total 9830400 # Packet count per connected master and slave (bytes) 104system.membus.pkt_count::total 14218046 # Packet count per connected master and slave (bytes) 105system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2389580 # Cumulative packet size per connected master and slave (bytes) 106system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 107system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 17128 # Cumulative packet size per connected master and slave (bytes) 108system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 109system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1364 # Cumulative packet size per connected master and slave (bytes) 110system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16575508 # Cumulative packet size per connected master and slave (bytes) 111system.membus.pkt_size_system.l2c.mem_side::total 18983656 # Cumulative packet size per connected master and slave (bytes) 112system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 39321600 # Cumulative packet size per connected master and slave (bytes) 113system.membus.pkt_size_system.iocache.mem_side::total 39321600 # Cumulative packet size per connected master and slave (bytes) 114system.membus.pkt_size::total 58305256 # Cumulative packet size per connected master and slave (bytes) | 64system.physmem.num_writes::total 135679 # Number of write requests responded to by this memory 65system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu0.inst 398688 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu0.data 3374627 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu1.inst 53438 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::cpu1.data 386357 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_read::total 4213726 # Total read bandwidth from this memory (bytes/s) 74system.physmem.bw_inst_read::cpu0.inst 398688 # Instruction read bandwidth from this memory (bytes/s) 75system.physmem.bw_inst_read::cpu1.inst 53438 # Instruction read bandwidth from this memory (bytes/s) 76system.physmem.bw_inst_read::total 452126 # Instruction read bandwidth from this memory (bytes/s) 77system.physmem.bw_write::writebacks 2169629 # Write bandwidth from this memory (bytes/s) 78system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) 80system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 81system.physmem.bw_write::total 3003086 # Write bandwidth from this memory (bytes/s) 82system.physmem.bw_total::writebacks 2169629 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::cpu0.inst 398688 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu0.data 3380944 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu1.inst 53438 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::cpu1.data 386371 # Total bandwidth to/from this memory (bytes/s) 91system.physmem.bw_total::total 7216812 # Total bandwidth to/from this memory (bytes/s) 92system.membus.trans_dist::ReadReq 75963 # Transaction distribution 93system.membus.trans_dist::ReadResp 75963 # Transaction distribution 94system.membus.trans_dist::WriteReq 30903 # Transaction distribution 95system.membus.trans_dist::WriteResp 30903 # Transaction distribution 96system.membus.trans_dist::Writeback 95019 # Transaction distribution 97system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 98system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 99system.membus.trans_dist::UpgradeReq 60332 # Transaction distribution 100system.membus.trans_dist::SCUpgradeReq 40886 # Transaction distribution 101system.membus.trans_dist::UpgradeResp 15607 # Transaction distribution 102system.membus.trans_dist::ReadExReq 196321 # Transaction distribution 103system.membus.trans_dist::ReadExResp 152216 # Transaction distribution 104system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) 105system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) 106system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) 107system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652185 # Packet count per connected master and slave (bytes) 108system.membus.pkt_count_system.l2c.mem_side::total 773609 # Packet count per connected master and slave (bytes) 109system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes) 110system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes) 111system.membus.pkt_count::total 846561 # Packet count per connected master and slave (bytes) 112system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) 113system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 76 # Cumulative packet size per connected master and slave (bytes) 114system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) 115system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17908580 # Cumulative packet size per connected master and slave (bytes) 116system.membus.pkt_size_system.l2c.mem_side::total 18098400 # Cumulative packet size per connected master and slave (bytes) 117system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes) 118system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes) 119system.membus.pkt_size::total 20432864 # Cumulative packet size per connected master and slave (bytes) |
| 115system.membus.snoops 0 # Total snoops (count) | 120system.membus.snoops 0 # Total snoops (count) |
| 116system.membus.snoop_fanout::samples 295628 # Request fanout histogram | 121system.membus.snoop_fanout::samples 460731 # Request fanout histogram |
| 117system.membus.snoop_fanout::mean 1 # Request fanout histogram 118system.membus.snoop_fanout::stdev 0 # Request fanout histogram 119system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 120system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 122system.membus.snoop_fanout::mean 1 # Request fanout histogram 123system.membus.snoop_fanout::stdev 0 # Request fanout histogram 124system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 125system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 121system.membus.snoop_fanout::1 295628 100.00% 100.00% # Request fanout histogram | 126system.membus.snoop_fanout::1 460731 100.00% 100.00% # Request fanout histogram |
| 122system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 123system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 124system.membus.snoop_fanout::min_value 1 # Request fanout histogram 125system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 127system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 128system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 129system.membus.snoop_fanout::min_value 1 # Request fanout histogram 130system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 126system.membus.snoop_fanout::total 295628 # Request fanout histogram | 131system.membus.snoop_fanout::total 460731 # Request fanout histogram |
| 127system.cpu_clk_domain.clock 500 # Clock period in ticks | 132system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 128system.l2c.tags.replacements 60014 # number of replacements 129system.l2c.tags.tagsinuse 50124.590156 # Cycle average of tags in use 130system.l2c.tags.total_refs 136044 # Total number of references to valid blocks. 131system.l2c.tags.sampled_refs 120331 # Sample count of references to valid blocks. 132system.l2c.tags.avg_refs 1.130581 # Average number of references to valid blocks. | 133system.l2c.tags.replacements 107723 # number of replacements 134system.l2c.tags.tagsinuse 62123.921751 # Cycle average of tags in use 135system.l2c.tags.total_refs 208051 # Total number of references to valid blocks. 136system.l2c.tags.sampled_refs 168144 # Sample count of references to valid blocks. 137system.l2c.tags.avg_refs 1.237338 # Average number of references to valid blocks. |
| 133system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 138system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 134system.l2c.tags.occ_blocks::writebacks 37074.868959 # Average occupied blocks per requestor 135system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.077014 # Average occupied blocks per requestor 136system.l2c.tags.occ_blocks::cpu0.itb.walker 1.053163 # Average occupied blocks per requestor 137system.l2c.tags.occ_blocks::cpu0.inst 4876.195614 # Average occupied blocks per requestor 138system.l2c.tags.occ_blocks::cpu0.data 5801.198822 # Average occupied blocks per requestor 139system.l2c.tags.occ_blocks::cpu1.inst 1684.572168 # Average occupied blocks per requestor 140system.l2c.tags.occ_blocks::cpu1.data 686.624416 # Average occupied blocks per requestor 141system.l2c.tags.occ_percent::writebacks 0.565718 # Average percentage of cache occupancy 142system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000001 # Average percentage of cache occupancy 143system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 144system.l2c.tags.occ_percent::cpu0.inst 0.074405 # Average percentage of cache occupancy 145system.l2c.tags.occ_percent::cpu0.data 0.088519 # Average percentage of cache occupancy 146system.l2c.tags.occ_percent::cpu1.inst 0.025705 # Average percentage of cache occupancy 147system.l2c.tags.occ_percent::cpu1.data 0.010477 # Average percentage of cache occupancy 148system.l2c.tags.occ_percent::total 0.764841 # Average percentage of cache occupancy 149system.l2c.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id 150system.l2c.tags.occ_task_id_blocks::1024 60314 # Occupied blocks per task id 151system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 152system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 153system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id 154system.l2c.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id 155system.l2c.tags.age_task_id_blocks_1024::2 1748 # Occupied blocks per task id 156system.l2c.tags.age_task_id_blocks_1024::3 13321 # Occupied blocks per task id 157system.l2c.tags.age_task_id_blocks_1024::4 45151 # Occupied blocks per task id 158system.l2c.tags.occ_task_id_percent::1023 0.000046 # Percentage of cache occupancy per task id 159system.l2c.tags.occ_task_id_percent::1024 0.920319 # Percentage of cache occupancy per task id 160system.l2c.tags.tag_accesses 3837449 # Number of tag accesses 161system.l2c.tags.data_accesses 3837449 # Number of data accesses 162system.l2c.ReadReq_hits::cpu0.dtb.walker 59 # number of ReadReq hits 163system.l2c.ReadReq_hits::cpu0.itb.walker 32 # number of ReadReq hits 164system.l2c.ReadReq_hits::cpu0.inst 12381 # number of ReadReq hits 165system.l2c.ReadReq_hits::cpu0.data 37925 # number of ReadReq hits 166system.l2c.ReadReq_hits::cpu1.dtb.walker 68 # number of ReadReq hits 167system.l2c.ReadReq_hits::cpu1.itb.walker 43 # number of ReadReq hits 168system.l2c.ReadReq_hits::cpu1.inst 18539 # number of ReadReq hits 169system.l2c.ReadReq_hits::cpu1.data 11807 # number of ReadReq hits 170system.l2c.ReadReq_hits::total 80854 # number of ReadReq hits 171system.l2c.Writeback_hits::writebacks 175673 # number of Writeback hits 172system.l2c.Writeback_hits::total 175673 # number of Writeback hits 173system.l2c.UpgradeReq_hits::cpu0.data 221 # number of UpgradeReq hits 174system.l2c.UpgradeReq_hits::cpu1.data 174 # number of UpgradeReq hits 175system.l2c.UpgradeReq_hits::total 395 # number of UpgradeReq hits 176system.l2c.SCUpgradeReq_hits::cpu0.data 20 # number of SCUpgradeReq hits 177system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits 178system.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits 179system.l2c.ReadExReq_hits::cpu0.data 7332 # number of ReadExReq hits 180system.l2c.ReadExReq_hits::cpu1.data 6046 # number of ReadExReq hits 181system.l2c.ReadExReq_hits::total 13378 # number of ReadExReq hits 182system.l2c.demand_hits::cpu0.dtb.walker 59 # number of demand (read+write) hits 183system.l2c.demand_hits::cpu0.itb.walker 32 # number of demand (read+write) hits 184system.l2c.demand_hits::cpu0.inst 12381 # number of demand (read+write) hits 185system.l2c.demand_hits::cpu0.data 45257 # number of demand (read+write) hits 186system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits 187system.l2c.demand_hits::cpu1.itb.walker 43 # number of demand (read+write) hits 188system.l2c.demand_hits::cpu1.inst 18539 # number of demand (read+write) hits 189system.l2c.demand_hits::cpu1.data 17853 # number of demand (read+write) hits 190system.l2c.demand_hits::total 94232 # number of demand (read+write) hits 191system.l2c.overall_hits::cpu0.dtb.walker 59 # number of overall hits 192system.l2c.overall_hits::cpu0.itb.walker 32 # number of overall hits 193system.l2c.overall_hits::cpu0.inst 12381 # number of overall hits 194system.l2c.overall_hits::cpu0.data 45257 # number of overall hits 195system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits 196system.l2c.overall_hits::cpu1.itb.walker 43 # number of overall hits 197system.l2c.overall_hits::cpu1.inst 18539 # number of overall hits 198system.l2c.overall_hits::cpu1.data 17853 # number of overall hits 199system.l2c.overall_hits::total 94232 # number of overall hits 200system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses | 139system.l2c.tags.occ_blocks::writebacks 48622.171138 # Average occupied blocks per requestor 140system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.975943 # Average occupied blocks per requestor 141system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor 142system.l2c.tags.occ_blocks::cpu0.inst 7348.709599 # Average occupied blocks per requestor 143system.l2c.tags.occ_blocks::cpu0.data 3778.182164 # Average occupied blocks per requestor 144system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823425 # Average occupied blocks per requestor 145system.l2c.tags.occ_blocks::cpu1.inst 1628.255131 # Average occupied blocks per requestor 146system.l2c.tags.occ_blocks::cpu1.data 741.773959 # Average occupied blocks per requestor 147system.l2c.tags.occ_percent::writebacks 0.741915 # Average percentage of cache occupancy 148system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy 149system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 150system.l2c.tags.occ_percent::cpu0.inst 0.112132 # Average percentage of cache occupancy 151system.l2c.tags.occ_percent::cpu0.data 0.057650 # Average percentage of cache occupancy 152system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy 153system.l2c.tags.occ_percent::cpu1.inst 0.024845 # Average percentage of cache occupancy 154system.l2c.tags.occ_percent::cpu1.data 0.011319 # Average percentage of cache occupancy 155system.l2c.tags.occ_percent::total 0.947936 # Average percentage of cache occupancy 156system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 157system.l2c.tags.occ_task_id_blocks::1024 60415 # Occupied blocks per task id 158system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 159system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 160system.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id 161system.l2c.tags.age_task_id_blocks_1024::2 1884 # Occupied blocks per task id 162system.l2c.tags.age_task_id_blocks_1024::3 13069 # Occupied blocks per task id 163system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id 164system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 165system.l2c.tags.occ_task_id_percent::1024 0.921860 # Percentage of cache occupancy per task id 166system.l2c.tags.tag_accesses 4905185 # Number of tag accesses 167system.l2c.tags.data_accesses 4905185 # Number of data accesses 168system.l2c.ReadReq_hits::cpu0.dtb.walker 79 # number of ReadReq hits 169system.l2c.ReadReq_hits::cpu0.itb.walker 74 # number of ReadReq hits 170system.l2c.ReadReq_hits::cpu0.inst 28057 # number of ReadReq hits 171system.l2c.ReadReq_hits::cpu0.data 75985 # number of ReadReq hits 172system.l2c.ReadReq_hits::cpu1.dtb.walker 42 # number of ReadReq hits 173system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits 174system.l2c.ReadReq_hits::cpu1.inst 11512 # number of ReadReq hits 175system.l2c.ReadReq_hits::cpu1.data 11347 # number of ReadReq hits 176system.l2c.ReadReq_hits::total 127129 # number of ReadReq hits 177system.l2c.Writeback_hits::writebacks 225966 # number of Writeback hits 178system.l2c.Writeback_hits::total 225966 # number of Writeback hits 179system.l2c.UpgradeReq_hits::cpu0.data 512 # number of UpgradeReq hits 180system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits 181system.l2c.UpgradeReq_hits::total 577 # number of UpgradeReq hits 182system.l2c.SCUpgradeReq_hits::cpu0.data 56 # number of SCUpgradeReq hits 183system.l2c.SCUpgradeReq_hits::cpu1.data 11 # number of SCUpgradeReq hits 184system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits 185system.l2c.ReadExReq_hits::cpu0.data 13971 # number of ReadExReq hits 186system.l2c.ReadExReq_hits::cpu1.data 3083 # number of ReadExReq hits 187system.l2c.ReadExReq_hits::total 17054 # number of ReadExReq hits 188system.l2c.demand_hits::cpu0.dtb.walker 79 # number of demand (read+write) hits 189system.l2c.demand_hits::cpu0.itb.walker 74 # number of demand (read+write) hits 190system.l2c.demand_hits::cpu0.inst 28057 # number of demand (read+write) hits 191system.l2c.demand_hits::cpu0.data 89956 # number of demand (read+write) hits 192system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits 193system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits 194system.l2c.demand_hits::cpu1.inst 11512 # number of demand (read+write) hits 195system.l2c.demand_hits::cpu1.data 14430 # number of demand (read+write) hits 196system.l2c.demand_hits::total 144183 # number of demand (read+write) hits 197system.l2c.overall_hits::cpu0.dtb.walker 79 # number of overall hits 198system.l2c.overall_hits::cpu0.itb.walker 74 # number of overall hits 199system.l2c.overall_hits::cpu0.inst 28057 # number of overall hits 200system.l2c.overall_hits::cpu0.data 89956 # number of overall hits 201system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits 202system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits 203system.l2c.overall_hits::cpu1.inst 11512 # number of overall hits 204system.l2c.overall_hits::cpu1.data 14430 # number of overall hits 205system.l2c.overall_hits::total 144183 # number of overall hits 206system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses |
| 201system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses | 207system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses |
| 202system.l2c.ReadReq_misses::cpu0.inst 6907 # number of ReadReq misses 203system.l2c.ReadReq_misses::cpu0.data 9458 # number of ReadReq misses 204system.l2c.ReadReq_misses::cpu1.inst 4159 # number of ReadReq misses 205system.l2c.ReadReq_misses::cpu1.data 1478 # number of ReadReq misses 206system.l2c.ReadReq_misses::total 22005 # number of ReadReq misses 207system.l2c.UpgradeReq_misses::cpu0.data 5858 # number of UpgradeReq misses 208system.l2c.UpgradeReq_misses::cpu1.data 6485 # number of UpgradeReq misses 209system.l2c.UpgradeReq_misses::total 12343 # number of UpgradeReq misses 210system.l2c.SCUpgradeReq_misses::cpu0.data 694 # number of SCUpgradeReq misses 211system.l2c.SCUpgradeReq_misses::cpu1.data 773 # number of SCUpgradeReq misses 212system.l2c.SCUpgradeReq_misses::total 1467 # number of SCUpgradeReq misses 213system.l2c.ReadExReq_misses::cpu0.data 92836 # number of ReadExReq misses 214system.l2c.ReadExReq_misses::cpu1.data 44477 # number of ReadExReq misses 215system.l2c.ReadExReq_misses::total 137313 # number of ReadExReq misses 216system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses | 208system.l2c.ReadReq_misses::cpu0.inst 16897 # number of ReadReq misses 209system.l2c.ReadReq_misses::cpu0.data 11316 # number of ReadReq misses 210system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses 211system.l2c.ReadReq_misses::cpu1.inst 2330 # number of ReadReq misses 212system.l2c.ReadReq_misses::cpu1.data 1142 # number of ReadReq misses 213system.l2c.ReadReq_misses::total 31697 # number of ReadReq misses 214system.l2c.UpgradeReq_misses::cpu0.data 9967 # number of UpgradeReq misses 215system.l2c.UpgradeReq_misses::cpu1.data 3302 # number of UpgradeReq misses 216system.l2c.UpgradeReq_misses::total 13269 # number of UpgradeReq misses 217system.l2c.SCUpgradeReq_misses::cpu0.data 763 # number of SCUpgradeReq misses 218system.l2c.SCUpgradeReq_misses::cpu1.data 1181 # number of SCUpgradeReq misses 219system.l2c.SCUpgradeReq_misses::total 1944 # number of SCUpgradeReq misses 220system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses 221system.l2c.ReadExReq_misses::cpu1.data 15814 # number of ReadExReq misses 222system.l2c.ReadExReq_misses::total 152610 # number of ReadExReq misses 223system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses |
| 217system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses | 224system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses |
| 218system.l2c.demand_misses::cpu0.inst 6907 # number of demand (read+write) misses 219system.l2c.demand_misses::cpu0.data 102294 # number of demand (read+write) misses 220system.l2c.demand_misses::cpu1.inst 4159 # number of demand (read+write) misses 221system.l2c.demand_misses::cpu1.data 45955 # number of demand (read+write) misses 222system.l2c.demand_misses::total 159318 # number of demand (read+write) misses 223system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses | 225system.l2c.demand_misses::cpu0.inst 16897 # number of demand (read+write) misses 226system.l2c.demand_misses::cpu0.data 148112 # number of demand (read+write) misses 227system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses 228system.l2c.demand_misses::cpu1.inst 2330 # number of demand (read+write) misses 229system.l2c.demand_misses::cpu1.data 16956 # number of demand (read+write) misses 230system.l2c.demand_misses::total 184307 # number of demand (read+write) misses 231system.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses |
| 224system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses | 232system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses |
| 225system.l2c.overall_misses::cpu0.inst 6907 # number of overall misses 226system.l2c.overall_misses::cpu0.data 102294 # number of overall misses 227system.l2c.overall_misses::cpu1.inst 4159 # number of overall misses 228system.l2c.overall_misses::cpu1.data 45955 # number of overall misses 229system.l2c.overall_misses::total 159318 # number of overall misses 230system.l2c.ReadReq_accesses::cpu0.dtb.walker 60 # number of ReadReq accesses(hits+misses) 231system.l2c.ReadReq_accesses::cpu0.itb.walker 34 # number of ReadReq accesses(hits+misses) 232system.l2c.ReadReq_accesses::cpu0.inst 19288 # number of ReadReq accesses(hits+misses) 233system.l2c.ReadReq_accesses::cpu0.data 47383 # number of ReadReq accesses(hits+misses) 234system.l2c.ReadReq_accesses::cpu1.dtb.walker 68 # number of ReadReq accesses(hits+misses) 235system.l2c.ReadReq_accesses::cpu1.itb.walker 43 # number of ReadReq accesses(hits+misses) 236system.l2c.ReadReq_accesses::cpu1.inst 22698 # number of ReadReq accesses(hits+misses) 237system.l2c.ReadReq_accesses::cpu1.data 13285 # number of ReadReq accesses(hits+misses) 238system.l2c.ReadReq_accesses::total 102859 # number of ReadReq accesses(hits+misses) 239system.l2c.Writeback_accesses::writebacks 175673 # number of Writeback accesses(hits+misses) 240system.l2c.Writeback_accesses::total 175673 # number of Writeback accesses(hits+misses) 241system.l2c.UpgradeReq_accesses::cpu0.data 6079 # number of UpgradeReq accesses(hits+misses) 242system.l2c.UpgradeReq_accesses::cpu1.data 6659 # number of UpgradeReq accesses(hits+misses) 243system.l2c.UpgradeReq_accesses::total 12738 # number of UpgradeReq accesses(hits+misses) 244system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses) 245system.l2c.SCUpgradeReq_accesses::cpu1.data 793 # number of SCUpgradeReq accesses(hits+misses) 246system.l2c.SCUpgradeReq_accesses::total 1507 # number of SCUpgradeReq accesses(hits+misses) 247system.l2c.ReadExReq_accesses::cpu0.data 100168 # number of ReadExReq accesses(hits+misses) 248system.l2c.ReadExReq_accesses::cpu1.data 50523 # number of ReadExReq accesses(hits+misses) 249system.l2c.ReadExReq_accesses::total 150691 # number of ReadExReq accesses(hits+misses) 250system.l2c.demand_accesses::cpu0.dtb.walker 60 # number of demand (read+write) accesses 251system.l2c.demand_accesses::cpu0.itb.walker 34 # number of demand (read+write) accesses 252system.l2c.demand_accesses::cpu0.inst 19288 # number of demand (read+write) accesses 253system.l2c.demand_accesses::cpu0.data 147551 # number of demand (read+write) accesses 254system.l2c.demand_accesses::cpu1.dtb.walker 68 # number of demand (read+write) accesses 255system.l2c.demand_accesses::cpu1.itb.walker 43 # number of demand (read+write) accesses 256system.l2c.demand_accesses::cpu1.inst 22698 # number of demand (read+write) accesses 257system.l2c.demand_accesses::cpu1.data 63808 # number of demand (read+write) accesses 258system.l2c.demand_accesses::total 253550 # number of demand (read+write) accesses 259system.l2c.overall_accesses::cpu0.dtb.walker 60 # number of overall (read+write) accesses 260system.l2c.overall_accesses::cpu0.itb.walker 34 # number of overall (read+write) accesses 261system.l2c.overall_accesses::cpu0.inst 19288 # number of overall (read+write) accesses 262system.l2c.overall_accesses::cpu0.data 147551 # number of overall (read+write) accesses 263system.l2c.overall_accesses::cpu1.dtb.walker 68 # number of overall (read+write) accesses 264system.l2c.overall_accesses::cpu1.itb.walker 43 # number of overall (read+write) accesses 265system.l2c.overall_accesses::cpu1.inst 22698 # number of overall (read+write) accesses 266system.l2c.overall_accesses::cpu1.data 63808 # number of overall (read+write) accesses 267system.l2c.overall_accesses::total 253550 # number of overall (read+write) accesses 268system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for ReadReq accesses 269system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.058824 # miss rate for ReadReq accesses 270system.l2c.ReadReq_miss_rate::cpu0.inst 0.358098 # miss rate for ReadReq accesses 271system.l2c.ReadReq_miss_rate::cpu0.data 0.199607 # miss rate for ReadReq accesses 272system.l2c.ReadReq_miss_rate::cpu1.inst 0.183232 # miss rate for ReadReq accesses 273system.l2c.ReadReq_miss_rate::cpu1.data 0.111253 # miss rate for ReadReq accesses 274system.l2c.ReadReq_miss_rate::total 0.213934 # miss rate for ReadReq accesses 275system.l2c.UpgradeReq_miss_rate::cpu0.data 0.963645 # miss rate for UpgradeReq accesses 276system.l2c.UpgradeReq_miss_rate::cpu1.data 0.973870 # miss rate for UpgradeReq accesses 277system.l2c.UpgradeReq_miss_rate::total 0.968990 # miss rate for UpgradeReq accesses 278system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.971989 # miss rate for SCUpgradeReq accesses 279system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974779 # miss rate for SCUpgradeReq accesses 280system.l2c.SCUpgradeReq_miss_rate::total 0.973457 # miss rate for SCUpgradeReq accesses 281system.l2c.ReadExReq_miss_rate::cpu0.data 0.926803 # miss rate for ReadExReq accesses 282system.l2c.ReadExReq_miss_rate::cpu1.data 0.880332 # miss rate for ReadExReq accesses 283system.l2c.ReadExReq_miss_rate::total 0.911222 # miss rate for ReadExReq accesses 284system.l2c.demand_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for demand accesses 285system.l2c.demand_miss_rate::cpu0.itb.walker 0.058824 # miss rate for demand accesses 286system.l2c.demand_miss_rate::cpu0.inst 0.358098 # miss rate for demand accesses 287system.l2c.demand_miss_rate::cpu0.data 0.693279 # miss rate for demand accesses 288system.l2c.demand_miss_rate::cpu1.inst 0.183232 # miss rate for demand accesses 289system.l2c.demand_miss_rate::cpu1.data 0.720207 # miss rate for demand accesses 290system.l2c.demand_miss_rate::total 0.628349 # miss rate for demand accesses 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu0.itb.walker 0.058824 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu0.inst 0.358098 # miss rate for overall accesses 294system.l2c.overall_miss_rate::cpu0.data 0.693279 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.inst 0.183232 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.data 0.720207 # miss rate for overall accesses 297system.l2c.overall_miss_rate::total 0.628349 # miss rate for overall accesses | 233system.l2c.overall_misses::cpu0.inst 16897 # number of overall misses 234system.l2c.overall_misses::cpu0.data 148112 # number of overall misses 235system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses 236system.l2c.overall_misses::cpu1.inst 2330 # number of overall misses 237system.l2c.overall_misses::cpu1.data 16956 # number of overall misses 238system.l2c.overall_misses::total 184307 # number of overall misses 239system.l2c.ReadReq_accesses::cpu0.dtb.walker 87 # number of ReadReq accesses(hits+misses) 240system.l2c.ReadReq_accesses::cpu0.itb.walker 76 # number of ReadReq accesses(hits+misses) 241system.l2c.ReadReq_accesses::cpu0.inst 44954 # number of ReadReq accesses(hits+misses) 242system.l2c.ReadReq_accesses::cpu0.data 87301 # number of ReadReq accesses(hits+misses) 243system.l2c.ReadReq_accesses::cpu1.dtb.walker 44 # number of ReadReq accesses(hits+misses) 244system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses) 245system.l2c.ReadReq_accesses::cpu1.inst 13842 # number of ReadReq accesses(hits+misses) 246system.l2c.ReadReq_accesses::cpu1.data 12489 # number of ReadReq accesses(hits+misses) 247system.l2c.ReadReq_accesses::total 158826 # number of ReadReq accesses(hits+misses) 248system.l2c.Writeback_accesses::writebacks 225966 # number of Writeback accesses(hits+misses) 249system.l2c.Writeback_accesses::total 225966 # number of Writeback accesses(hits+misses) 250system.l2c.UpgradeReq_accesses::cpu0.data 10479 # number of UpgradeReq accesses(hits+misses) 251system.l2c.UpgradeReq_accesses::cpu1.data 3367 # number of UpgradeReq accesses(hits+misses) 252system.l2c.UpgradeReq_accesses::total 13846 # number of UpgradeReq accesses(hits+misses) 253system.l2c.SCUpgradeReq_accesses::cpu0.data 819 # number of SCUpgradeReq accesses(hits+misses) 254system.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) 255system.l2c.SCUpgradeReq_accesses::total 2011 # number of SCUpgradeReq accesses(hits+misses) 256system.l2c.ReadExReq_accesses::cpu0.data 150767 # number of ReadExReq accesses(hits+misses) 257system.l2c.ReadExReq_accesses::cpu1.data 18897 # number of ReadExReq accesses(hits+misses) 258system.l2c.ReadExReq_accesses::total 169664 # number of ReadExReq accesses(hits+misses) 259system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses 260system.l2c.demand_accesses::cpu0.itb.walker 76 # number of demand (read+write) accesses 261system.l2c.demand_accesses::cpu0.inst 44954 # number of demand (read+write) accesses 262system.l2c.demand_accesses::cpu0.data 238068 # number of demand (read+write) accesses 263system.l2c.demand_accesses::cpu1.dtb.walker 44 # number of demand (read+write) accesses 264system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses 265system.l2c.demand_accesses::cpu1.inst 13842 # number of demand (read+write) accesses 266system.l2c.demand_accesses::cpu1.data 31386 # number of demand (read+write) accesses 267system.l2c.demand_accesses::total 328490 # number of demand (read+write) accesses 268system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses 269system.l2c.overall_accesses::cpu0.itb.walker 76 # number of overall (read+write) accesses 270system.l2c.overall_accesses::cpu0.inst 44954 # number of overall (read+write) accesses 271system.l2c.overall_accesses::cpu0.data 238068 # number of overall (read+write) accesses 272system.l2c.overall_accesses::cpu1.dtb.walker 44 # number of overall (read+write) accesses 273system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses 274system.l2c.overall_accesses::cpu1.inst 13842 # number of overall (read+write) accesses 275system.l2c.overall_accesses::cpu1.data 31386 # number of overall (read+write) accesses 276system.l2c.overall_accesses::total 328490 # number of overall (read+write) accesses 277system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for ReadReq accesses 278system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.026316 # miss rate for ReadReq accesses 279system.l2c.ReadReq_miss_rate::cpu0.inst 0.375873 # miss rate for ReadReq accesses 280system.l2c.ReadReq_miss_rate::cpu0.data 0.129621 # miss rate for ReadReq accesses 281system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for ReadReq accesses 282system.l2c.ReadReq_miss_rate::cpu1.inst 0.168328 # miss rate for ReadReq accesses 283system.l2c.ReadReq_miss_rate::cpu1.data 0.091440 # miss rate for ReadReq accesses 284system.l2c.ReadReq_miss_rate::total 0.199571 # miss rate for ReadReq accesses 285system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951140 # miss rate for UpgradeReq accesses 286system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980695 # miss rate for UpgradeReq accesses 287system.l2c.UpgradeReq_miss_rate::total 0.958327 # miss rate for UpgradeReq accesses 288system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.931624 # miss rate for SCUpgradeReq accesses 289system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.990772 # miss rate for SCUpgradeReq accesses 290system.l2c.SCUpgradeReq_miss_rate::total 0.966683 # miss rate for SCUpgradeReq accesses 291system.l2c.ReadExReq_miss_rate::cpu0.data 0.907334 # miss rate for ReadExReq accesses 292system.l2c.ReadExReq_miss_rate::cpu1.data 0.836852 # miss rate for ReadExReq accesses 293system.l2c.ReadExReq_miss_rate::total 0.899484 # miss rate for ReadExReq accesses 294system.l2c.demand_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for demand accesses 295system.l2c.demand_miss_rate::cpu0.itb.walker 0.026316 # miss rate for demand accesses 296system.l2c.demand_miss_rate::cpu0.inst 0.375873 # miss rate for demand accesses 297system.l2c.demand_miss_rate::cpu0.data 0.622142 # miss rate for demand accesses 298system.l2c.demand_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for demand accesses 299system.l2c.demand_miss_rate::cpu1.inst 0.168328 # miss rate for demand accesses 300system.l2c.demand_miss_rate::cpu1.data 0.540241 # miss rate for demand accesses 301system.l2c.demand_miss_rate::total 0.561073 # miss rate for demand accesses 302system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses 303system.l2c.overall_miss_rate::cpu0.itb.walker 0.026316 # miss rate for overall accesses 304system.l2c.overall_miss_rate::cpu0.inst 0.375873 # miss rate for overall accesses 305system.l2c.overall_miss_rate::cpu0.data 0.622142 # miss rate for overall accesses 306system.l2c.overall_miss_rate::cpu1.dtb.walker 0.045455 # miss rate for overall accesses 307system.l2c.overall_miss_rate::cpu1.inst 0.168328 # miss rate for overall accesses 308system.l2c.overall_miss_rate::cpu1.data 0.540241 # miss rate for overall accesses 309system.l2c.overall_miss_rate::total 0.561073 # miss rate for overall accesses |
| 298system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 299system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 300system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 301system.l2c.blocked::no_targets 0 # number of cycles access was blocked 302system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 303system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 304system.l2c.fast_writes 0 # number of fast writes performed 305system.l2c.cache_copies 0 # number of cache copies performed | 310system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 311system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 312system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 313system.l2c.blocked::no_targets 0 # number of cycles access was blocked 314system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 315system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 316system.l2c.fast_writes 0 # number of fast writes performed 317system.l2c.cache_copies 0 # number of cache copies performed |
| 306system.l2c.writebacks::writebacks 52587 # number of writebacks 307system.l2c.writebacks::total 52587 # number of writebacks | 318system.l2c.writebacks::writebacks 95019 # number of writebacks 319system.l2c.writebacks::total 95019 # number of writebacks |
| 308system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 320system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 321system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 322system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 323system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 324system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 325system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 326system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 327system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 328system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 329system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 330system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 331system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 332system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 333system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 334system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 335system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 336system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 337system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 338system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 339system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 340system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 341system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 342system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 343system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 344system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 345system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 346system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 347system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 348system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 349system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 350system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 351system.realview.ethernet.droppedPackets 0 # number of packets dropped |
|
| 309system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). | 352system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). |
| 310system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 311system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 312system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 313system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 314system.cf0.dma_write_txs 0 # Number of DMA write transactions. 315system.toL2Bus.trans_dist::ReadReq 1357667 # Transaction distribution 316system.toL2Bus.trans_dist::ReadResp 1357667 # Transaction distribution 317system.toL2Bus.trans_dist::WriteReq 767040 # Transaction distribution 318system.toL2Bus.trans_dist::WriteResp 767040 # Transaction distribution 319system.toL2Bus.trans_dist::Writeback 175673 # Transaction distribution 320system.toL2Bus.trans_dist::UpgradeReq 37136 # Transaction distribution 321system.toL2Bus.trans_dist::SCUpgradeReq 20079 # Transaction distribution 322system.toL2Bus.trans_dist::UpgradeResp 57215 # Transaction distribution 323system.toL2Bus.trans_dist::ReadExReq 177634 # Transaction distribution 324system.toL2Bus.trans_dist::ReadExResp 177634 # Transaction distribution 325system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2263595 # Packet count per connected master and slave (bytes) 326system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2631190 # Packet count per connected master and slave (bytes) 327system.toL2Bus.pkt_count::total 4894785 # Packet count per connected master and slave (bytes) 328system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 23563666 # Cumulative packet size per connected master and slave (bytes) 329system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15087382 # Cumulative packet size per connected master and slave (bytes) 330system.toL2Bus.pkt_size::total 38651048 # Cumulative packet size per connected master and slave (bytes) 331system.toL2Bus.snoops 0 # Total snoops (count) 332system.toL2Bus.snoop_fanout::samples 575784 # Request fanout histogram 333system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 334system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 353system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 354system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 355system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 356system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 357system.cf0.dma_write_txs 631 # Number of DMA write transactions. 358system.toL2Bus.trans_dist::ReadReq 305028 # Transaction distribution 359system.toL2Bus.trans_dist::ReadResp 305028 # Transaction distribution 360system.toL2Bus.trans_dist::WriteReq 30903 # Transaction distribution 361system.toL2Bus.trans_dist::WriteResp 30903 # Transaction distribution 362system.toL2Bus.trans_dist::Writeback 225966 # Transaction distribution 363system.toL2Bus.trans_dist::UpgradeReq 60515 # Transaction distribution 364system.toL2Bus.trans_dist::SCUpgradeReq 40953 # Transaction distribution 365system.toL2Bus.trans_dist::UpgradeResp 101468 # Transaction distribution 366system.toL2Bus.trans_dist::ReadExReq 213769 # Transaction distribution 367system.toL2Bus.trans_dist::ReadExResp 213769 # Transaction distribution 368system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117772 # Packet count per connected master and slave (bytes) 369system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410530 # Packet count per connected master and slave (bytes) 370system.toL2Bus.pkt_count::total 1528302 # Packet count per connected master and slave (bytes) 371system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34667382 # Cumulative packet size per connected master and slave (bytes) 372system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10427306 # Cumulative packet size per connected master and slave (bytes) 373system.toL2Bus.pkt_size::total 45094688 # Cumulative packet size per connected master and slave (bytes) 374system.toL2Bus.snoops 36713 # Total snoops (count) 375system.toL2Bus.snoop_fanout::samples 838693 # Request fanout histogram 376system.toL2Bus.snoop_fanout::mean 1.043491 # Request fanout histogram 377system.toL2Bus.snoop_fanout::stdev 0.203961 # Request fanout histogram |
| 335system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 336system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 378system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 379system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 337system.toL2Bus.snoop_fanout::1 575784 100.00% 100.00% # Request fanout histogram 338system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram | 380system.toL2Bus.snoop_fanout::1 802217 95.65% 95.65% # Request fanout histogram 381system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram |
| 339system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 340system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 382system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 383system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram |
| 341system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 342system.toL2Bus.snoop_fanout::total 575784 # Request fanout histogram 343system.iobus.trans_dist::ReadReq 6098452 # Transaction distribution 344system.iobus.trans_dist::ReadResp 6098452 # Transaction distribution 345system.iobus.trans_dist::WriteReq 7955 # Transaction distribution 346system.iobus.trans_dist::WriteResp 7955 # Transaction distribution 347system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30522 # Packet count per connected master and slave (bytes) 348system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7906 # Packet count per connected master and slave (bytes) | 384system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 385system.toL2Bus.snoop_fanout::total 838693 # Request fanout histogram 386system.iobus.trans_dist::ReadReq 31002 # Transaction distribution 387system.iobus.trans_dist::ReadResp 31002 # Transaction distribution 388system.iobus.trans_dist::WriteReq 59433 # Transaction distribution 389system.iobus.trans_dist::WriteResp 23209 # Transaction distribution 390system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 391system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) 392system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) |
| 349system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) | 393system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) |
| 350system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 684 # Packet count per connected master and slave (bytes) 351system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) | 394system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) |
| 352system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) | 395system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) |
| 353system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 488 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) | 396system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 397system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) |
| 356system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) | 398system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 399system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 400system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 359system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 360system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) | 401system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) |
| 361system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) | 402system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 362system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 363system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 364system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 365system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 366system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) | |
| 367system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) | 403system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 404system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 405system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) |
|
| 368system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) | 406system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 369system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 370system.iobus.pkt_count_system.bridge.master::total 2382414 # Packet count per connected master and slave (bytes) 371system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 9830400 # Packet count per connected master and slave (bytes) 372system.iobus.pkt_count_system.realview.clcd.dma::total 9830400 # Packet count per connected master and slave (bytes) 373system.iobus.pkt_count::total 12212814 # Packet count per connected master and slave (bytes) 374system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40294 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15812 # Cumulative packet size per connected master and slave (bytes) | 407system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 408system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 409system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 410system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 411system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 412system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) 413system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 414system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 415system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) 416system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) 417system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) |
| 376system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) | 418system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) |
| 377system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1368 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) | 419system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) |
| 379system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) | 420system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) |
| 380system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 268 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 421system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 422system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) |
| 383system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 423system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 424system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 425system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 386system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 387system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) | 426system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) |
| 388system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 427system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 389system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 390system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 392system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 393system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | |
| 394system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 428system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 429system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 430system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) |
|
| 395system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 431system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 396system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 397system.iobus.pkt_size_system.bridge.master::total 2389580 # Cumulative packet size per connected master and slave (bytes) 398system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 39321600 # Cumulative packet size per connected master and slave (bytes) 399system.iobus.pkt_size_system.realview.clcd.dma::total 39321600 # Cumulative packet size per connected master and slave (bytes) 400system.iobus.pkt_size::total 41711180 # Cumulative packet size per connected master and slave (bytes) | 432system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 433system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 434system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 435system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 436system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 437system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) 438system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 439system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 440system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) |
| 401system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 402system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 403system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 404system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 405system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 406system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 416system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 417system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 418system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 419system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 420system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 421system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 422system.cpu0.dtb.inst_hits 0 # ITB inst hits 423system.cpu0.dtb.inst_misses 0 # ITB inst misses | 441system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 442system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 443system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 444system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 445system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 446system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 447system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 448system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 456system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 457system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 458system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 459system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 460system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 461system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 462system.cpu0.dtb.inst_hits 0 # ITB inst hits 463system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 424system.cpu0.dtb.read_hits 7391828 # DTB read hits 425system.cpu0.dtb.read_misses 1916 # DTB read misses 426system.cpu0.dtb.write_hits 6659769 # DTB write hits 427system.cpu0.dtb.write_misses 1130 # DTB write misses 428system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 429system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 430system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 431system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 432system.cpu0.dtb.flush_entries 1223 # Number of entries that have been flushed from TLB | 464system.cpu0.dtb.read_hits 20338466 # DTB read hits 465system.cpu0.dtb.read_misses 6871 # DTB read misses 466system.cpu0.dtb.write_hits 16389914 # DTB write hits 467system.cpu0.dtb.write_misses 1093 # DTB write misses 468system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 469system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 470system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 471system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 472system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB |
| 433system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 473system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 434system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch | 474system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch |
| 435system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 475system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 436system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions 437system.cpu0.dtb.read_accesses 7393744 # DTB read accesses 438system.cpu0.dtb.write_accesses 6660899 # DTB write accesses | 476system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 477system.cpu0.dtb.read_accesses 20345337 # DTB read accesses 478system.cpu0.dtb.write_accesses 16391007 # DTB write accesses |
| 439system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 479system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 440system.cpu0.dtb.hits 14051597 # DTB hits 441system.cpu0.dtb.misses 3046 # DTB misses 442system.cpu0.dtb.accesses 14054643 # DTB accesses | 480system.cpu0.dtb.hits 36728380 # DTB hits 481system.cpu0.dtb.misses 7964 # DTB misses 482system.cpu0.dtb.accesses 36736344 # DTB accesses |
| 443system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 444system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 445system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 446system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 447system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 448system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 449system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 450system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 456system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 457system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 459system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 460system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 461system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 462system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 463system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 483system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 484system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 485system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 486system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 487system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 488system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 489system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 496system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 497system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 498system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 499system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 500system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 501system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 502system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 503system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 464system.cpu0.itb.inst_hits 37936653 # ITB inst hits 465system.cpu0.itb.inst_misses 1207 # ITB inst misses | 504system.cpu0.itb.inst_hits 97433991 # ITB inst hits 505system.cpu0.itb.inst_misses 3358 # ITB inst misses |
| 466system.cpu0.itb.read_hits 0 # DTB read hits 467system.cpu0.itb.read_misses 0 # DTB read misses 468system.cpu0.itb.write_hits 0 # DTB write hits 469system.cpu0.itb.write_misses 0 # DTB write misses | 506system.cpu0.itb.read_hits 0 # DTB read hits 507system.cpu0.itb.read_misses 0 # DTB read misses 508system.cpu0.itb.write_hits 0 # DTB write hits 509system.cpu0.itb.write_misses 0 # DTB write misses |
| 470system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 471system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 472system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 474system.cpu0.itb.flush_entries 848 # Number of entries that have been flushed from TLB | 510system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 511system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 512system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 513system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 514system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB |
| 475system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 476system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 477system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 479system.cpu0.itb.read_accesses 0 # DTB read accesses 480system.cpu0.itb.write_accesses 0 # DTB write accesses | 515system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 516system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 517system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 518system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 519system.cpu0.itb.read_accesses 0 # DTB read accesses 520system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 481system.cpu0.itb.inst_accesses 37937860 # ITB inst accesses 482system.cpu0.itb.hits 37936653 # DTB hits 483system.cpu0.itb.misses 1207 # DTB misses 484system.cpu0.itb.accesses 37937860 # DTB accesses 485system.cpu0.numCycles 1801220958 # number of cpu cycles simulated | 521system.cpu0.itb.inst_accesses 97437349 # ITB inst accesses 522system.cpu0.itb.hits 97433991 # DTB hits 523system.cpu0.itb.misses 3358 # DTB misses 524system.cpu0.itb.accesses 97437349 # DTB accesses 525system.cpu0.numCycles 5605766965 # number of cpu cycles simulated |
| 486system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 487system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 526system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 527system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 488system.cpu0.committedInsts 37699441 # Number of instructions committed 489system.cpu0.committedOps 44947195 # Number of ops (including micro ops) committed 490system.cpu0.num_int_alu_accesses 39864660 # Number of integer alu accesses 491system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses 492system.cpu0.num_func_calls 1205511 # number of times a function call or return occured 493system.cpu0.num_conditional_control_insts 4698026 # number of instructions that are conditional controls 494system.cpu0.num_int_insts 39864660 # number of integer instructions 495system.cpu0.num_fp_insts 4171 # number of float instructions 496system.cpu0.num_int_register_reads 70364659 # number of times the integer registers were read 497system.cpu0.num_int_register_writes 26109079 # number of times the integer registers were written 498system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read 499system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written 500system.cpu0.num_cc_register_reads 134799783 # number of times the CC registers were read 501system.cpu0.num_cc_register_writes 18388749 # number of times the CC registers were written 502system.cpu0.num_mem_refs 14597797 # number of memory refs 503system.cpu0.num_load_insts 7571468 # Number of load instructions 504system.cpu0.num_store_insts 7026329 # Number of store instructions 505system.cpu0.num_idle_cycles 1756040520.255098 # Number of idle cycles 506system.cpu0.num_busy_cycles 45180437.744902 # Number of busy cycles 507system.cpu0.not_idle_fraction 0.025083 # Percentage of non-idle cycles 508system.cpu0.idle_fraction 0.974917 # Percentage of idle cycles 509system.cpu0.Branches 6054439 # Number of branches fetched 510system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction 511system.cpu0.op_class::IntAlu 30339474 67.42% 67.45% # Class of executed instruction 512system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction 513system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction 514system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction 515system.cpu0.op_class::FloatCmp 0 0.00% 67.56% # Class of executed instruction 516system.cpu0.op_class::FloatCvt 0 0.00% 67.56% # Class of executed instruction 517system.cpu0.op_class::FloatMult 0 0.00% 67.56% # Class of executed instruction 518system.cpu0.op_class::FloatDiv 0 0.00% 67.56% # Class of executed instruction 519system.cpu0.op_class::FloatSqrt 0 0.00% 67.56% # Class of executed instruction 520system.cpu0.op_class::SimdAdd 0 0.00% 67.56% # Class of executed instruction 521system.cpu0.op_class::SimdAddAcc 0 0.00% 67.56% # Class of executed instruction 522system.cpu0.op_class::SimdAlu 0 0.00% 67.56% # Class of executed instruction 523system.cpu0.op_class::SimdCmp 0 0.00% 67.56% # Class of executed instruction 524system.cpu0.op_class::SimdCvt 0 0.00% 67.56% # Class of executed instruction 525system.cpu0.op_class::SimdMisc 0 0.00% 67.56% # Class of executed instruction 526system.cpu0.op_class::SimdMult 0 0.00% 67.56% # Class of executed instruction 527system.cpu0.op_class::SimdMultAcc 0 0.00% 67.56% # Class of executed instruction 528system.cpu0.op_class::SimdShift 0 0.00% 67.56% # Class of executed instruction 529system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.56% # Class of executed instruction 530system.cpu0.op_class::SimdSqrt 0 0.00% 67.56% # Class of executed instruction 531system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.56% # Class of executed instruction 532system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.56% # Class of executed instruction 533system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.56% # Class of executed instruction 534system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.56% # Class of executed instruction 535system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.56% # Class of executed instruction 536system.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Class of executed instruction 537system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction 538system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction 539system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction 540system.cpu0.op_class::MemRead 7571468 16.82% 84.39% # Class of executed instruction 541system.cpu0.op_class::MemWrite 7026329 15.61% 100.00% # Class of executed instruction | 528system.cpu0.committedInsts 95421538 # Number of instructions committed 529system.cpu0.committedOps 115553717 # Number of ops (including micro ops) committed 530system.cpu0.num_int_alu_accesses 100756647 # Number of integer alu accesses 531system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 532system.cpu0.num_func_calls 7999979 # number of times a function call or return occured 533system.cpu0.num_conditional_control_insts 13203645 # number of instructions that are conditional controls 534system.cpu0.num_int_insts 100756647 # number of integer instructions 535system.cpu0.num_fp_insts 9755 # number of float instructions 536system.cpu0.num_int_register_reads 182446507 # number of times the integer registers were read 537system.cpu0.num_int_register_writes 69131058 # number of times the integer registers were written 538system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 539system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 540system.cpu0.num_cc_register_reads 349951369 # number of times the CC registers were read 541system.cpu0.num_cc_register_writes 44905035 # number of times the CC registers were written 542system.cpu0.num_mem_refs 37871263 # number of memory refs 543system.cpu0.num_load_insts 20596038 # Number of load instructions 544system.cpu0.num_store_insts 17275225 # Number of store instructions 545system.cpu0.num_idle_cycles 5488189135.402444 # Number of idle cycles 546system.cpu0.num_busy_cycles 117577829.597556 # Number of busy cycles 547system.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles 548system.cpu0.idle_fraction 0.979026 # Percentage of idle cycles 549system.cpu0.Branches 21940727 # Number of branches fetched 550system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 551system.cpu0.op_class::IntAlu 78883166 67.49% 67.50% # Class of executed instruction 552system.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction 553system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 554system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 555system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 556system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 557system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 558system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 559system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 560system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 561system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 562system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 563system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 564system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 565system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 566system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 567system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 568system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 569system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 570system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 571system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 572system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 573system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 574system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 575system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 576system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 577system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 578system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 579system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 580system.cpu0.op_class::MemRead 20596038 17.62% 85.22% # Class of executed instruction 581system.cpu0.op_class::MemWrite 17275225 14.78% 100.00% # Class of executed instruction |
| 542system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 543system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 582system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 583system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 544system.cpu0.op_class::total 45002955 # Class of executed instruction | 584system.cpu0.op_class::total 116875407 # Class of executed instruction |
| 545system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 585system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 546system.cpu0.kern.inst.quiesce 42789 # number of quiesce instructions executed 547system.cpu0.icache.tags.replacements 346148 # number of replacements 548system.cpu0.icache.tags.tagsinuse 511.428315 # Cycle average of tags in use 549system.cpu0.icache.tags.total_refs 37590948 # Total number of references to valid blocks. 550system.cpu0.icache.tags.sampled_refs 346660 # Sample count of references to valid blocks. 551system.cpu0.icache.tags.avg_refs 108.437512 # Average number of references to valid blocks. 552system.cpu0.icache.tags.warmup_cycle 4521683000 # Cycle when the warmup percentage was hit. 553system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.428315 # Average occupied blocks per requestor 554system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998883 # Average percentage of cache occupancy 555system.cpu0.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy | 586system.cpu0.kern.inst.quiesce 1971 # number of quiesce instructions executed 587system.cpu0.icache.tags.replacements 1109428 # number of replacements 588system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 589system.cpu0.icache.tags.total_refs 96326384 # Total number of references to valid blocks. 590system.cpu0.icache.tags.sampled_refs 1109940 # Sample count of references to valid blocks. 591system.cpu0.icache.tags.avg_refs 86.785217 # Average number of references to valid blocks. 592system.cpu0.icache.tags.warmup_cycle 6345717500 # Cycle when the warmup percentage was hit. 593system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 594system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 595system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy |
| 556system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 596system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 557system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id | 597system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 598system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 599system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id |
| 558system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 600system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 559system.cpu0.icache.tags.tag_accesses 76221879 # Number of tag accesses 560system.cpu0.icache.tags.data_accesses 76221879 # Number of data accesses 561system.cpu0.icache.ReadReq_hits::cpu0.inst 37590948 # number of ReadReq hits 562system.cpu0.icache.ReadReq_hits::total 37590948 # number of ReadReq hits 563system.cpu0.icache.demand_hits::cpu0.inst 37590948 # number of demand (read+write) hits 564system.cpu0.icache.demand_hits::total 37590948 # number of demand (read+write) hits 565system.cpu0.icache.overall_hits::cpu0.inst 37590948 # number of overall hits 566system.cpu0.icache.overall_hits::total 37590948 # number of overall hits 567system.cpu0.icache.ReadReq_misses::cpu0.inst 346661 # number of ReadReq misses 568system.cpu0.icache.ReadReq_misses::total 346661 # number of ReadReq misses 569system.cpu0.icache.demand_misses::cpu0.inst 346661 # number of demand (read+write) misses 570system.cpu0.icache.demand_misses::total 346661 # number of demand (read+write) misses 571system.cpu0.icache.overall_misses::cpu0.inst 346661 # number of overall misses 572system.cpu0.icache.overall_misses::total 346661 # number of overall misses 573system.cpu0.icache.ReadReq_accesses::cpu0.inst 37937609 # number of ReadReq accesses(hits+misses) 574system.cpu0.icache.ReadReq_accesses::total 37937609 # number of ReadReq accesses(hits+misses) 575system.cpu0.icache.demand_accesses::cpu0.inst 37937609 # number of demand (read+write) accesses 576system.cpu0.icache.demand_accesses::total 37937609 # number of demand (read+write) accesses 577system.cpu0.icache.overall_accesses::cpu0.inst 37937609 # number of overall (read+write) accesses 578system.cpu0.icache.overall_accesses::total 37937609 # number of overall (read+write) accesses 579system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009138 # miss rate for ReadReq accesses 580system.cpu0.icache.ReadReq_miss_rate::total 0.009138 # miss rate for ReadReq accesses 581system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009138 # miss rate for demand accesses 582system.cpu0.icache.demand_miss_rate::total 0.009138 # miss rate for demand accesses 583system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009138 # miss rate for overall accesses 584system.cpu0.icache.overall_miss_rate::total 0.009138 # miss rate for overall accesses | 601system.cpu0.icache.tags.tag_accesses 195982615 # Number of tag accesses 602system.cpu0.icache.tags.data_accesses 195982615 # Number of data accesses 603system.cpu0.icache.ReadReq_hits::cpu0.inst 96326384 # number of ReadReq hits 604system.cpu0.icache.ReadReq_hits::total 96326384 # number of ReadReq hits 605system.cpu0.icache.demand_hits::cpu0.inst 96326384 # number of demand (read+write) hits 606system.cpu0.icache.demand_hits::total 96326384 # number of demand (read+write) hits 607system.cpu0.icache.overall_hits::cpu0.inst 96326384 # number of overall hits 608system.cpu0.icache.overall_hits::total 96326384 # number of overall hits 609system.cpu0.icache.ReadReq_misses::cpu0.inst 1109949 # number of ReadReq misses 610system.cpu0.icache.ReadReq_misses::total 1109949 # number of ReadReq misses 611system.cpu0.icache.demand_misses::cpu0.inst 1109949 # number of demand (read+write) misses 612system.cpu0.icache.demand_misses::total 1109949 # number of demand (read+write) misses 613system.cpu0.icache.overall_misses::cpu0.inst 1109949 # number of overall misses 614system.cpu0.icache.overall_misses::total 1109949 # number of overall misses 615system.cpu0.icache.ReadReq_accesses::cpu0.inst 97436333 # number of ReadReq accesses(hits+misses) 616system.cpu0.icache.ReadReq_accesses::total 97436333 # number of ReadReq accesses(hits+misses) 617system.cpu0.icache.demand_accesses::cpu0.inst 97436333 # number of demand (read+write) accesses 618system.cpu0.icache.demand_accesses::total 97436333 # number of demand (read+write) accesses 619system.cpu0.icache.overall_accesses::cpu0.inst 97436333 # number of overall (read+write) accesses 620system.cpu0.icache.overall_accesses::total 97436333 # number of overall (read+write) accesses 621system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011392 # miss rate for ReadReq accesses 622system.cpu0.icache.ReadReq_miss_rate::total 0.011392 # miss rate for ReadReq accesses 623system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011392 # miss rate for demand accesses 624system.cpu0.icache.demand_miss_rate::total 0.011392 # miss rate for demand accesses 625system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011392 # miss rate for overall accesses 626system.cpu0.icache.overall_miss_rate::total 0.011392 # miss rate for overall accesses |
| 585system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 586system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 587system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 588system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 589system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 590system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 591system.cpu0.icache.fast_writes 0 # number of fast writes performed 592system.cpu0.icache.cache_copies 0 # number of cache copies performed 593system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 594system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 595system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 596system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 597system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 598system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 599system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 600system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 601system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 602system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 627system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 628system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 629system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 630system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 631system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 632system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 633system.cpu0.icache.fast_writes 0 # number of fast writes performed 634system.cpu0.icache.cache_copies 0 # number of cache copies performed 635system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 636system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 637system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 638system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 639system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 640system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 641system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 642system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 643system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 644system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 603system.cpu0.l2cache.tags.replacements 133971 # number of replacements 604system.cpu0.l2cache.tags.tagsinuse 15179.385733 # Cycle average of tags in use 605system.cpu0.l2cache.tags.total_refs 737408 # Total number of references to valid blocks. 606system.cpu0.l2cache.tags.sampled_refs 149269 # Sample count of references to valid blocks. 607system.cpu0.l2cache.tags.avg_refs 4.940128 # Average number of references to valid blocks. 608system.cpu0.l2cache.tags.warmup_cycle 992860000 # Cycle when the warmup percentage was hit. 609system.cpu0.l2cache.tags.occ_blocks::writebacks 7074.912262 # Average occupied blocks per requestor 610system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 8.111336 # Average occupied blocks per requestor 611system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.268775 # Average occupied blocks per requestor 612system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3357.655544 # Average occupied blocks per requestor 613system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4738.437815 # Average occupied blocks per requestor 614system.cpu0.l2cache.tags.occ_percent::writebacks 0.431818 # Average percentage of cache occupancy 615system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000495 # Average percentage of cache occupancy 616system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 617system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.204935 # Average percentage of cache occupancy 618system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.289211 # Average percentage of cache occupancy 619system.cpu0.l2cache.tags.occ_percent::total 0.926476 # Average percentage of cache occupancy 620system.cpu0.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id 621system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15278 # Occupied blocks per task id 622system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 623system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id 624system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 625system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3216 # Occupied blocks per task id 626system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5292 # Occupied blocks per task id 627system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 6770 # Occupied blocks per task id 628system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id 629system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.932495 # Percentage of cache occupancy per task id 630system.cpu0.l2cache.tags.tag_accesses 17962499 # Number of tag accesses 631system.cpu0.l2cache.tags.data_accesses 17962499 # Number of data accesses 632system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4364 # number of ReadReq hits 633system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 1619 # number of ReadReq hits 634system.cpu0.l2cache.ReadReq_hits::cpu0.inst 326789 # number of ReadReq hits 635system.cpu0.l2cache.ReadReq_hits::cpu0.data 179454 # number of ReadReq hits 636system.cpu0.l2cache.ReadReq_hits::total 512226 # number of ReadReq hits 637system.cpu0.l2cache.Writeback_hits::writebacks 323282 # number of Writeback hits 638system.cpu0.l2cache.Writeback_hits::total 323282 # number of Writeback hits 639system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 640system.cpu0.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits 641system.cpu0.l2cache.ReadExReq_hits::cpu0.data 38112 # number of ReadExReq hits 642system.cpu0.l2cache.ReadExReq_hits::total 38112 # number of ReadExReq hits 643system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4364 # number of demand (read+write) hits 644system.cpu0.l2cache.demand_hits::cpu0.itb.walker 1619 # number of demand (read+write) hits 645system.cpu0.l2cache.demand_hits::cpu0.inst 326789 # number of demand (read+write) hits 646system.cpu0.l2cache.demand_hits::cpu0.data 217566 # number of demand (read+write) hits 647system.cpu0.l2cache.demand_hits::total 550338 # number of demand (read+write) hits 648system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4364 # number of overall hits 649system.cpu0.l2cache.overall_hits::cpu0.itb.walker 1619 # number of overall hits 650system.cpu0.l2cache.overall_hits::cpu0.inst 326789 # number of overall hits 651system.cpu0.l2cache.overall_hits::cpu0.data 217566 # number of overall hits 652system.cpu0.l2cache.overall_hits::total 550338 # number of overall hits 653system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 89 # number of ReadReq misses 654system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 56 # number of ReadReq misses 655system.cpu0.l2cache.ReadReq_misses::cpu0.inst 19767 # number of ReadReq misses 656system.cpu0.l2cache.ReadReq_misses::cpu0.data 70654 # number of ReadReq misses 657system.cpu0.l2cache.ReadReq_misses::total 90566 # number of ReadReq misses 658system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 12767 # number of UpgradeReq misses 659system.cpu0.l2cache.UpgradeReq_misses::total 12767 # number of UpgradeReq misses 660system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 8852 # number of SCUpgradeReq misses 661system.cpu0.l2cache.SCUpgradeReq_misses::total 8852 # number of SCUpgradeReq misses 662system.cpu0.l2cache.ReadExReq_misses::cpu0.data 114761 # number of ReadExReq misses 663system.cpu0.l2cache.ReadExReq_misses::total 114761 # number of ReadExReq misses 664system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 89 # number of demand (read+write) misses 665system.cpu0.l2cache.demand_misses::cpu0.itb.walker 56 # number of demand (read+write) misses 666system.cpu0.l2cache.demand_misses::cpu0.inst 19767 # number of demand (read+write) misses 667system.cpu0.l2cache.demand_misses::cpu0.data 185415 # number of demand (read+write) misses 668system.cpu0.l2cache.demand_misses::total 205327 # number of demand (read+write) misses 669system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 89 # number of overall misses 670system.cpu0.l2cache.overall_misses::cpu0.itb.walker 56 # number of overall misses 671system.cpu0.l2cache.overall_misses::cpu0.inst 19767 # number of overall misses 672system.cpu0.l2cache.overall_misses::cpu0.data 185415 # number of overall misses 673system.cpu0.l2cache.overall_misses::total 205327 # number of overall misses 674system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 4453 # number of ReadReq accesses(hits+misses) 675system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 1675 # number of ReadReq accesses(hits+misses) 676system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 346556 # number of ReadReq accesses(hits+misses) 677system.cpu0.l2cache.ReadReq_accesses::cpu0.data 250108 # number of ReadReq accesses(hits+misses) 678system.cpu0.l2cache.ReadReq_accesses::total 602792 # number of ReadReq accesses(hits+misses) 679system.cpu0.l2cache.Writeback_accesses::writebacks 323282 # number of Writeback accesses(hits+misses) 680system.cpu0.l2cache.Writeback_accesses::total 323282 # number of Writeback accesses(hits+misses) 681system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 12769 # number of UpgradeReq accesses(hits+misses) 682system.cpu0.l2cache.UpgradeReq_accesses::total 12769 # number of UpgradeReq accesses(hits+misses) 683system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 8852 # number of SCUpgradeReq accesses(hits+misses) 684system.cpu0.l2cache.SCUpgradeReq_accesses::total 8852 # number of SCUpgradeReq accesses(hits+misses) 685system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 152873 # number of ReadExReq accesses(hits+misses) 686system.cpu0.l2cache.ReadExReq_accesses::total 152873 # number of ReadExReq accesses(hits+misses) 687system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 4453 # number of demand (read+write) accesses 688system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 1675 # number of demand (read+write) accesses 689system.cpu0.l2cache.demand_accesses::cpu0.inst 346556 # number of demand (read+write) accesses 690system.cpu0.l2cache.demand_accesses::cpu0.data 402981 # number of demand (read+write) accesses 691system.cpu0.l2cache.demand_accesses::total 755665 # number of demand (read+write) accesses 692system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 4453 # number of overall (read+write) accesses 693system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 1675 # number of overall (read+write) accesses 694system.cpu0.l2cache.overall_accesses::cpu0.inst 346556 # number of overall (read+write) accesses 695system.cpu0.l2cache.overall_accesses::cpu0.data 402981 # number of overall (read+write) accesses 696system.cpu0.l2cache.overall_accesses::total 755665 # number of overall (read+write) accesses 697system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for ReadReq accesses 698system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.033433 # miss rate for ReadReq accesses 699system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.057038 # miss rate for ReadReq accesses 700system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.282494 # miss rate for ReadReq accesses 701system.cpu0.l2cache.ReadReq_miss_rate::total 0.150244 # miss rate for ReadReq accesses 702system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999843 # miss rate for UpgradeReq accesses 703system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999843 # miss rate for UpgradeReq accesses | 645system.cpu0.l2cache.tags.replacements 252470 # number of replacements 646system.cpu0.l2cache.tags.tagsinuse 16140.899010 # Cycle average of tags in use 647system.cpu0.l2cache.tags.total_refs 1809063 # Total number of references to valid blocks. 648system.cpu0.l2cache.tags.sampled_refs 268660 # Sample count of references to valid blocks. 649system.cpu0.l2cache.tags.avg_refs 6.733652 # Average number of references to valid blocks. 650system.cpu0.l2cache.tags.warmup_cycle 1814551000 # Cycle when the warmup percentage was hit. 651system.cpu0.l2cache.tags.occ_blocks::writebacks 8130.897895 # Average occupied blocks per requestor 652system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.403919 # Average occupied blocks per requestor 653system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.095149 # Average occupied blocks per requestor 654system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4678.277611 # Average occupied blocks per requestor 655system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3330.224436 # Average occupied blocks per requestor 656system.cpu0.l2cache.tags.occ_percent::writebacks 0.496271 # Average percentage of cache occupancy 657system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000086 # Average percentage of cache occupancy 658system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy 659system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.285539 # Average percentage of cache occupancy 660system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.203261 # Average percentage of cache occupancy 661system.cpu0.l2cache.tags.occ_percent::total 0.985162 # Average percentage of cache occupancy 662system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id 663system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id 664system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 665system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 666system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 667system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 668system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id 669system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5558 # Occupied blocks per task id 670system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7600 # Occupied blocks per task id 671system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2662 # Occupied blocks per task id 672system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id 673system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id 674system.cpu0.l2cache.tags.tag_accesses 39435786 # Number of tag accesses 675system.cpu0.l2cache.tags.data_accesses 39435786 # Number of data accesses 676system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7516 # number of ReadReq hits 677system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3210 # number of ReadReq hits 678system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1064995 # number of ReadReq hits 679system.cpu0.l2cache.ReadReq_hits::cpu0.data 352145 # number of ReadReq hits 680system.cpu0.l2cache.ReadReq_hits::total 1427866 # number of ReadReq hits 681system.cpu0.l2cache.Writeback_hits::writebacks 511188 # number of Writeback hits 682system.cpu0.l2cache.Writeback_hits::total 511188 # number of Writeback hits 683system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits 684system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits 685system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94088 # number of ReadExReq hits 686system.cpu0.l2cache.ReadExReq_hits::total 94088 # number of ReadExReq hits 687system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7516 # number of demand (read+write) hits 688system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3210 # number of demand (read+write) hits 689system.cpu0.l2cache.demand_hits::cpu0.inst 1064995 # number of demand (read+write) hits 690system.cpu0.l2cache.demand_hits::cpu0.data 446233 # number of demand (read+write) hits 691system.cpu0.l2cache.demand_hits::total 1521954 # number of demand (read+write) hits 692system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7516 # number of overall hits 693system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3210 # number of overall hits 694system.cpu0.l2cache.overall_hits::cpu0.inst 1064995 # number of overall hits 695system.cpu0.l2cache.overall_hits::cpu0.data 446233 # number of overall hits 696system.cpu0.l2cache.overall_hits::total 1521954 # number of overall hits 697system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses 698system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 135 # number of ReadReq misses 699system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44954 # number of ReadReq misses 700system.cpu0.l2cache.ReadReq_misses::cpu0.data 128031 # number of ReadReq misses 701system.cpu0.l2cache.ReadReq_misses::total 173336 # number of ReadReq misses 702system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26217 # number of UpgradeReq misses 703system.cpu0.l2cache.UpgradeReq_misses::total 26217 # number of UpgradeReq misses 704system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18426 # number of SCUpgradeReq misses 705system.cpu0.l2cache.SCUpgradeReq_misses::total 18426 # number of SCUpgradeReq misses 706system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175429 # number of ReadExReq misses 707system.cpu0.l2cache.ReadExReq_misses::total 175429 # number of ReadExReq misses 708system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses 709system.cpu0.l2cache.demand_misses::cpu0.itb.walker 135 # number of demand (read+write) misses 710system.cpu0.l2cache.demand_misses::cpu0.inst 44954 # number of demand (read+write) misses 711system.cpu0.l2cache.demand_misses::cpu0.data 303460 # number of demand (read+write) misses 712system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses 713system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses 714system.cpu0.l2cache.overall_misses::cpu0.itb.walker 135 # number of overall misses 715system.cpu0.l2cache.overall_misses::cpu0.inst 44954 # number of overall misses 716system.cpu0.l2cache.overall_misses::cpu0.data 303460 # number of overall misses 717system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses 718system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7732 # number of ReadReq accesses(hits+misses) 719system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3345 # number of ReadReq accesses(hits+misses) 720system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1109949 # number of ReadReq accesses(hits+misses) 721system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480176 # number of ReadReq accesses(hits+misses) 722system.cpu0.l2cache.ReadReq_accesses::total 1601202 # number of ReadReq accesses(hits+misses) 723system.cpu0.l2cache.Writeback_accesses::writebacks 511188 # number of Writeback accesses(hits+misses) 724system.cpu0.l2cache.Writeback_accesses::total 511188 # number of Writeback accesses(hits+misses) 725system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26234 # number of UpgradeReq accesses(hits+misses) 726system.cpu0.l2cache.UpgradeReq_accesses::total 26234 # number of UpgradeReq accesses(hits+misses) 727system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18426 # number of SCUpgradeReq accesses(hits+misses) 728system.cpu0.l2cache.SCUpgradeReq_accesses::total 18426 # number of SCUpgradeReq accesses(hits+misses) 729system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) 730system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) 731system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7732 # number of demand (read+write) accesses 732system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3345 # number of demand (read+write) accesses 733system.cpu0.l2cache.demand_accesses::cpu0.inst 1109949 # number of demand (read+write) accesses 734system.cpu0.l2cache.demand_accesses::cpu0.data 749693 # number of demand (read+write) accesses 735system.cpu0.l2cache.demand_accesses::total 1870719 # number of demand (read+write) accesses 736system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7732 # number of overall (read+write) accesses 737system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3345 # number of overall (read+write) accesses 738system.cpu0.l2cache.overall_accesses::cpu0.inst 1109949 # number of overall (read+write) accesses 739system.cpu0.l2cache.overall_accesses::cpu0.data 749693 # number of overall (read+write) accesses 740system.cpu0.l2cache.overall_accesses::total 1870719 # number of overall (read+write) accesses 741system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for ReadReq accesses 742system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.040359 # miss rate for ReadReq accesses 743system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040501 # miss rate for ReadReq accesses 744system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266633 # miss rate for ReadReq accesses 745system.cpu0.l2cache.ReadReq_miss_rate::total 0.108254 # miss rate for ReadReq accesses 746system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses 747system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses |
| 704system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 705system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 748system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 749system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 706system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.750695 # miss rate for ReadExReq accesses 707system.cpu0.l2cache.ReadExReq_miss_rate::total 0.750695 # miss rate for ReadExReq accesses 708system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for demand accesses 709system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.033433 # miss rate for demand accesses 710system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.057038 # miss rate for demand accesses 711system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.460109 # miss rate for demand accesses 712system.cpu0.l2cache.demand_miss_rate::total 0.271717 # miss rate for demand accesses 713system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for overall accesses 714system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.033433 # miss rate for overall accesses 715system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.057038 # miss rate for overall accesses 716system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.460109 # miss rate for overall accesses 717system.cpu0.l2cache.overall_miss_rate::total 0.271717 # miss rate for overall accesses | 750system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650901 # miss rate for ReadExReq accesses 751system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650901 # miss rate for ReadExReq accesses 752system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for demand accesses 753system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.040359 # miss rate for demand accesses 754system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040501 # miss rate for demand accesses 755system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404779 # miss rate for demand accesses 756system.cpu0.l2cache.demand_miss_rate::total 0.186434 # miss rate for demand accesses 757system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027936 # miss rate for overall accesses 758system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.040359 # miss rate for overall accesses 759system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040501 # miss rate for overall accesses 760system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404779 # miss rate for overall accesses 761system.cpu0.l2cache.overall_miss_rate::total 0.186434 # miss rate for overall accesses |
| 718system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 719system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 721system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 723system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 725system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 762system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 763system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 764system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 765system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 766system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 767system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 768system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 769system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 726system.cpu0.l2cache.writebacks::writebacks 114351 # number of writebacks 727system.cpu0.l2cache.writebacks::total 114351 # number of writebacks | 770system.cpu0.l2cache.writebacks::writebacks 192932 # number of writebacks 771system.cpu0.l2cache.writebacks::total 192932 # number of writebacks |
| 728system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 772system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 729system.cpu0.dcache.tags.replacements 371621 # number of replacements 730system.cpu0.dcache.tags.tagsinuse 458.751149 # Cycle average of tags in use 731system.cpu0.dcache.tags.total_refs 12812322 # Total number of references to valid blocks. 732system.cpu0.dcache.tags.sampled_refs 371931 # Sample count of references to valid blocks. 733system.cpu0.dcache.tags.avg_refs 34.448115 # Average number of references to valid blocks. 734system.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit. 735system.cpu0.dcache.tags.occ_blocks::cpu0.data 458.751149 # Average occupied blocks per requestor 736system.cpu0.dcache.tags.occ_percent::cpu0.data 0.895998 # Average percentage of cache occupancy 737system.cpu0.dcache.tags.occ_percent::total 0.895998 # Average percentage of cache occupancy 738system.cpu0.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id 739system.cpu0.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 740system.cpu0.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id 741system.cpu0.dcache.tags.tag_accesses 26837769 # Number of tag accesses 742system.cpu0.dcache.tags.data_accesses 26837769 # Number of data accesses 743system.cpu0.dcache.ReadReq_hits::cpu0.data 6854480 # number of ReadReq hits 744system.cpu0.dcache.ReadReq_hits::total 6854480 # number of ReadReq hits 745system.cpu0.dcache.WriteReq_hits::cpu0.data 5591690 # number of WriteReq hits 746system.cpu0.dcache.WriteReq_hits::total 5591690 # number of WriteReq hits 747system.cpu0.dcache.SoftPFReq_hits::cpu0.data 77211 # number of SoftPFReq hits 748system.cpu0.dcache.SoftPFReq_hits::total 77211 # number of SoftPFReq hits 749system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 134223 # number of LoadLockedReq hits 750system.cpu0.dcache.LoadLockedReq_hits::total 134223 # number of LoadLockedReq hits 751system.cpu0.dcache.StoreCondReq_hits::cpu0.data 135188 # number of StoreCondReq hits 752system.cpu0.dcache.StoreCondReq_hits::total 135188 # number of StoreCondReq hits 753system.cpu0.dcache.demand_hits::cpu0.data 12446170 # number of demand (read+write) hits 754system.cpu0.dcache.demand_hits::total 12446170 # number of demand (read+write) hits 755system.cpu0.dcache.overall_hits::cpu0.data 12523381 # number of overall hits 756system.cpu0.dcache.overall_hits::total 12523381 # number of overall hits 757system.cpu0.dcache.ReadReq_misses::cpu0.data 187851 # number of ReadReq misses 758system.cpu0.dcache.ReadReq_misses::total 187851 # number of ReadReq misses 759system.cpu0.dcache.WriteReq_misses::cpu0.data 165642 # number of WriteReq misses 760system.cpu0.dcache.WriteReq_misses::total 165642 # number of WriteReq misses 761system.cpu0.dcache.SoftPFReq_misses::cpu0.data 51876 # number of SoftPFReq misses 762system.cpu0.dcache.SoftPFReq_misses::total 51876 # number of SoftPFReq misses 763system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10381 # number of LoadLockedReq misses 764system.cpu0.dcache.LoadLockedReq_misses::total 10381 # number of LoadLockedReq misses 765system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8852 # number of StoreCondReq misses 766system.cpu0.dcache.StoreCondReq_misses::total 8852 # number of StoreCondReq misses 767system.cpu0.dcache.demand_misses::cpu0.data 353493 # number of demand (read+write) misses 768system.cpu0.dcache.demand_misses::total 353493 # number of demand (read+write) misses 769system.cpu0.dcache.overall_misses::cpu0.data 405369 # number of overall misses 770system.cpu0.dcache.overall_misses::total 405369 # number of overall misses 771system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042331 # number of ReadReq accesses(hits+misses) 772system.cpu0.dcache.ReadReq_accesses::total 7042331 # number of ReadReq accesses(hits+misses) 773system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757332 # number of WriteReq accesses(hits+misses) 774system.cpu0.dcache.WriteReq_accesses::total 5757332 # number of WriteReq accesses(hits+misses) 775system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) 776system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) 777system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144604 # number of LoadLockedReq accesses(hits+misses) 778system.cpu0.dcache.LoadLockedReq_accesses::total 144604 # number of LoadLockedReq accesses(hits+misses) 779system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144040 # number of StoreCondReq accesses(hits+misses) 780system.cpu0.dcache.StoreCondReq_accesses::total 144040 # number of StoreCondReq accesses(hits+misses) 781system.cpu0.dcache.demand_accesses::cpu0.data 12799663 # number of demand (read+write) accesses 782system.cpu0.dcache.demand_accesses::total 12799663 # number of demand (read+write) accesses 783system.cpu0.dcache.overall_accesses::cpu0.data 12928750 # number of overall (read+write) accesses 784system.cpu0.dcache.overall_accesses::total 12928750 # number of overall (read+write) accesses 785system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026675 # miss rate for ReadReq accesses 786system.cpu0.dcache.ReadReq_miss_rate::total 0.026675 # miss rate for ReadReq accesses 787system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028771 # miss rate for WriteReq accesses 788system.cpu0.dcache.WriteReq_miss_rate::total 0.028771 # miss rate for WriteReq accesses 789system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.401869 # miss rate for SoftPFReq accesses 790system.cpu0.dcache.SoftPFReq_miss_rate::total 0.401869 # miss rate for SoftPFReq accesses 791system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.071789 # miss rate for LoadLockedReq accesses 792system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.071789 # miss rate for LoadLockedReq accesses 793system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061455 # miss rate for StoreCondReq accesses 794system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061455 # miss rate for StoreCondReq accesses 795system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027617 # miss rate for demand accesses 796system.cpu0.dcache.demand_miss_rate::total 0.027617 # miss rate for demand accesses 797system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031354 # miss rate for overall accesses 798system.cpu0.dcache.overall_miss_rate::total 0.031354 # miss rate for overall accesses | 773system.cpu0.dcache.tags.replacements 693475 # number of replacements 774system.cpu0.dcache.tags.tagsinuse 494.745909 # Cycle average of tags in use 775system.cpu0.dcache.tags.total_refs 35929913 # Total number of references to valid blocks. 776system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. 777system.cpu0.dcache.tags.avg_refs 51.773179 # Average number of references to valid blocks. 778system.cpu0.dcache.tags.warmup_cycle 23662000 # Cycle when the warmup percentage was hit. 779system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.745909 # Average occupied blocks per requestor 780system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966301 # Average percentage of cache occupancy 781system.cpu0.dcache.tags.occ_percent::total 0.966301 # Average percentage of cache occupancy 782system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 783system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 784system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 785system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 786system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 787system.cpu0.dcache.tags.tag_accesses 74108905 # Number of tag accesses 788system.cpu0.dcache.tags.data_accesses 74108905 # Number of data accesses 789system.cpu0.dcache.ReadReq_hits::cpu0.data 19107323 # number of ReadReq hits 790system.cpu0.dcache.ReadReq_hits::total 19107323 # number of ReadReq hits 791system.cpu0.dcache.WriteReq_hits::cpu0.data 15689235 # number of WriteReq hits 792system.cpu0.dcache.WriteReq_hits::total 15689235 # number of WriteReq hits 793system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346054 # number of SoftPFReq hits 794system.cpu0.dcache.SoftPFReq_hits::total 346054 # number of SoftPFReq hits 795system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379605 # number of LoadLockedReq hits 796system.cpu0.dcache.LoadLockedReq_hits::total 379605 # number of LoadLockedReq hits 797system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363036 # number of StoreCondReq hits 798system.cpu0.dcache.StoreCondReq_hits::total 363036 # number of StoreCondReq hits 799system.cpu0.dcache.demand_hits::cpu0.data 34796558 # number of demand (read+write) hits 800system.cpu0.dcache.demand_hits::total 34796558 # number of demand (read+write) hits 801system.cpu0.dcache.overall_hits::cpu0.data 35142612 # number of overall hits 802system.cpu0.dcache.overall_hits::total 35142612 # number of overall hits 803system.cpu0.dcache.ReadReq_misses::cpu0.data 373110 # number of ReadReq misses 804system.cpu0.dcache.ReadReq_misses::total 373110 # number of ReadReq misses 805system.cpu0.dcache.WriteReq_misses::cpu0.data 295751 # number of WriteReq misses 806system.cpu0.dcache.WriteReq_misses::total 295751 # number of WriteReq misses 807system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100324 # number of SoftPFReq misses 808system.cpu0.dcache.SoftPFReq_misses::total 100324 # number of SoftPFReq misses 809system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 810system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 811system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18426 # number of StoreCondReq misses 812system.cpu0.dcache.StoreCondReq_misses::total 18426 # number of StoreCondReq misses 813system.cpu0.dcache.demand_misses::cpu0.data 668861 # number of demand (read+write) misses 814system.cpu0.dcache.demand_misses::total 668861 # number of demand (read+write) misses 815system.cpu0.dcache.overall_misses::cpu0.data 769185 # number of overall misses 816system.cpu0.dcache.overall_misses::total 769185 # number of overall misses 817system.cpu0.dcache.ReadReq_accesses::cpu0.data 19480433 # number of ReadReq accesses(hits+misses) 818system.cpu0.dcache.ReadReq_accesses::total 19480433 # number of ReadReq accesses(hits+misses) 819system.cpu0.dcache.WriteReq_accesses::cpu0.data 15984986 # number of WriteReq accesses(hits+misses) 820system.cpu0.dcache.WriteReq_accesses::total 15984986 # number of WriteReq accesses(hits+misses) 821system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446378 # number of SoftPFReq accesses(hits+misses) 822system.cpu0.dcache.SoftPFReq_accesses::total 446378 # number of SoftPFReq accesses(hits+misses) 823system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386347 # number of LoadLockedReq accesses(hits+misses) 824system.cpu0.dcache.LoadLockedReq_accesses::total 386347 # number of LoadLockedReq accesses(hits+misses) 825system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381462 # number of StoreCondReq accesses(hits+misses) 826system.cpu0.dcache.StoreCondReq_accesses::total 381462 # number of StoreCondReq accesses(hits+misses) 827system.cpu0.dcache.demand_accesses::cpu0.data 35465419 # number of demand (read+write) accesses 828system.cpu0.dcache.demand_accesses::total 35465419 # number of demand (read+write) accesses 829system.cpu0.dcache.overall_accesses::cpu0.data 35911797 # number of overall (read+write) accesses 830system.cpu0.dcache.overall_accesses::total 35911797 # number of overall (read+write) accesses 831system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019153 # miss rate for ReadReq accesses 832system.cpu0.dcache.ReadReq_miss_rate::total 0.019153 # miss rate for ReadReq accesses 833system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses 834system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses 835system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224751 # miss rate for SoftPFReq accesses 836system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224751 # miss rate for SoftPFReq accesses 837system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017451 # miss rate for LoadLockedReq accesses 838system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017451 # miss rate for LoadLockedReq accesses 839system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048304 # miss rate for StoreCondReq accesses 840system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048304 # miss rate for StoreCondReq accesses 841system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018860 # miss rate for demand accesses 842system.cpu0.dcache.demand_miss_rate::total 0.018860 # miss rate for demand accesses 843system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021419 # miss rate for overall accesses 844system.cpu0.dcache.overall_miss_rate::total 0.021419 # miss rate for overall accesses |
| 799system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 800system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 801system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 802system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 803system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 804system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 805system.cpu0.dcache.fast_writes 0 # number of fast writes performed 806system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 845system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 846system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 847system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 848system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 849system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 850system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 851system.cpu0.dcache.fast_writes 0 # number of fast writes performed 852system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 807system.cpu0.dcache.writebacks::writebacks 323282 # number of writebacks 808system.cpu0.dcache.writebacks::total 323282 # number of writebacks | 853system.cpu0.dcache.writebacks::writebacks 511188 # number of writebacks 854system.cpu0.dcache.writebacks::total 511188 # number of writebacks |
| 809system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 855system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 810system.cpu0.toL2Bus.trans_dist::ReadReq 689270 # Transaction distribution 811system.cpu0.toL2Bus.trans_dist::ReadResp 689270 # Transaction distribution 812system.cpu0.toL2Bus.trans_dist::WriteReq 763494 # Transaction distribution 813system.cpu0.toL2Bus.trans_dist::WriteResp 763494 # Transaction distribution 814system.cpu0.toL2Bus.trans_dist::Writeback 323282 # Transaction distribution 815system.cpu0.toL2Bus.trans_dist::UpgradeReq 12769 # Transaction distribution 816system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 8852 # Transaction distribution 817system.cpu0.toL2Bus.trans_dist::UpgradeResp 21621 # Transaction distribution 818system.cpu0.toL2Bus.trans_dist::ReadExReq 152873 # Transaction distribution 819system.cpu0.toL2Bus.trans_dist::ReadExResp 152873 # Transaction distribution 820system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 706618 # Packet count per connected master and slave (bytes) 821system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2854542 # Packet count per connected master and slave (bytes) 822system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 4790 # Packet count per connected master and slave (bytes) 823system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 11848 # Packet count per connected master and slave (bytes) 824system.cpu0.toL2Bus.pkt_count::total 3577798 # Packet count per connected master and slave (bytes) 825system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 22212896 # Cumulative packet size per connected master and slave (bytes) 826system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 49695730 # Cumulative packet size per connected master and slave (bytes) 827system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9580 # Cumulative packet size per connected master and slave (bytes) 828system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23696 # Cumulative packet size per connected master and slave (bytes) 829system.cpu0.toL2Bus.pkt_size::total 71941902 # Cumulative packet size per connected master and slave (bytes) 830system.cpu0.toL2Bus.snoops 229047 # Total snoops (count) 831system.cpu0.toL2Bus.snoop_fanout::samples 1276029 # Request fanout histogram 832system.cpu0.toL2Bus.snoop_fanout::mean 5.135706 # Request fanout histogram 833system.cpu0.toL2Bus.snoop_fanout::stdev 0.342476 # Request fanout histogram | 856system.cpu0.toL2Bus.trans_dist::ReadReq 1651550 # Transaction distribution 857system.cpu0.toL2Bus.trans_dist::ReadResp 1651550 # Transaction distribution 858system.cpu0.toL2Bus.trans_dist::WriteReq 28399 # Transaction distribution 859system.cpu0.toL2Bus.trans_dist::WriteResp 28399 # Transaction distribution 860system.cpu0.toL2Bus.trans_dist::Writeback 511188 # Transaction distribution 861system.cpu0.toL2Bus.trans_dist::UpgradeReq 26234 # Transaction distribution 862system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18426 # Transaction distribution 863system.cpu0.toL2Bus.trans_dist::UpgradeResp 44660 # Transaction distribution 864system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution 865system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution 866system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2237944 # Packet count per connected master and slave (bytes) 867system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2219872 # Packet count per connected master and slave (bytes) 868system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 869system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 870system.cpu0.toL2Bus.pkt_count::total 4499440 # Packet count per connected master and slave (bytes) 871system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71072828 # Cumulative packet size per connected master and slave (bytes) 872system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887162 # Cumulative packet size per connected master and slave (bytes) 873system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 874system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 875system.cpu0.toL2Bus.pkt_size::total 152043238 # Cumulative packet size per connected master and slave (bytes) 876system.cpu0.toL2Bus.snoops 321922 # Total snoops (count) 877system.cpu0.toL2Bus.snoop_fanout::samples 2655621 # Request fanout histogram 878system.cpu0.toL2Bus.snoop_fanout::mean 5.082587 # Request fanout histogram 879system.cpu0.toL2Bus.snoop_fanout::stdev 0.275257 # Request fanout histogram |
| 834system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 835system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 836system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 837system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 838system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 839system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 880system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 881system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 882system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 883system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 884system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 885system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 840system.cpu0.toL2Bus.snoop_fanout::5 1102864 86.43% 86.43% # Request fanout histogram 841system.cpu0.toL2Bus.snoop_fanout::6 173165 13.57% 100.00% # Request fanout histogram | 886system.cpu0.toL2Bus.snoop_fanout::5 2436302 91.74% 91.74% # Request fanout histogram 887system.cpu0.toL2Bus.snoop_fanout::6 219319 8.26% 100.00% # Request fanout histogram |
| 842system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 843system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 844system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 888system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 889system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 890system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 845system.cpu0.toL2Bus.snoop_fanout::total 1276029 # Request fanout histogram | 891system.cpu0.toL2Bus.snoop_fanout::total 2655621 # Request fanout histogram |
| 846system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 847system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 848system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 849system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 850system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 851system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 852system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 853system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 861system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 862system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 863system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 864system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 865system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 866system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 867system.cpu1.dtb.inst_hits 0 # ITB inst hits 868system.cpu1.dtb.inst_misses 0 # ITB inst misses | 892system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 893system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 894system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 895system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 896system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 897system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 898system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 899system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 907system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 908system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 909system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 910system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 911system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 912system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 913system.cpu1.dtb.inst_hits 0 # ITB inst hits 914system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 869system.cpu1.dtb.read_hits 6029083 # DTB read hits 870system.cpu1.dtb.read_misses 5405 # DTB read misses 871system.cpu1.dtb.write_hits 4781968 # DTB write hits 872system.cpu1.dtb.write_misses 1104 # DTB write misses 873system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 874system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 875system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 876system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 877system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB | 915system.cpu1.dtb.read_hits 12172110 # DTB read hits 916system.cpu1.dtb.read_misses 2853 # DTB read misses 917system.cpu1.dtb.write_hits 7585805 # DTB write hits 918system.cpu1.dtb.write_misses 506 # DTB write misses 919system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 920system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 921system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 922system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 923system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB |
| 878system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 924system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 879system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch | 925system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch |
| 880system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 926system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 881system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions 882system.cpu1.dtb.read_accesses 6034488 # DTB read accesses 883system.cpu1.dtb.write_accesses 4783072 # DTB write accesses | 927system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 928system.cpu1.dtb.read_accesses 12174963 # DTB read accesses 929system.cpu1.dtb.write_accesses 7586311 # DTB write accesses |
| 884system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 930system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 885system.cpu1.dtb.hits 10811051 # DTB hits 886system.cpu1.dtb.misses 6509 # DTB misses 887system.cpu1.dtb.accesses 10817560 # DTB accesses | 931system.cpu1.dtb.hits 19757915 # DTB hits 932system.cpu1.dtb.misses 3359 # DTB misses 933system.cpu1.dtb.accesses 19761274 # DTB accesses |
| 888system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 889system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 890system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 891system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 892system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 893system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 894system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 895system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 901system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 902system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 903system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 904system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 905system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 906system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 907system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 908system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 934system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 935system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 936system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 937system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 938system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 939system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 940system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 941system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 947system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 948system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 949system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 950system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 951system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 952system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 953system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 954system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 909system.cpu1.itb.inst_hits 24627232 # ITB inst hits 910system.cpu1.itb.inst_misses 3166 # ITB inst misses | 955system.cpu1.itb.inst_hits 53664371 # ITB inst hits 956system.cpu1.itb.inst_misses 1734 # ITB inst misses |
| 911system.cpu1.itb.read_hits 0 # DTB read hits 912system.cpu1.itb.read_misses 0 # DTB read misses 913system.cpu1.itb.write_hits 0 # DTB write hits 914system.cpu1.itb.write_misses 0 # DTB write misses | 957system.cpu1.itb.read_hits 0 # DTB read hits 958system.cpu1.itb.read_misses 0 # DTB read misses 959system.cpu1.itb.write_hits 0 # DTB write hits 960system.cpu1.itb.write_misses 0 # DTB write misses |
| 915system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 916system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 917system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 918system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 919system.cpu1.itb.flush_entries 1581 # Number of entries that have been flushed from TLB | 961system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 962system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 963system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 964system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 965system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB |
| 920system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 921system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 922system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 923system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 924system.cpu1.itb.read_accesses 0 # DTB read accesses 925system.cpu1.itb.write_accesses 0 # DTB write accesses | 966system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 967system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 968system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 969system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 970system.cpu1.itb.read_accesses 0 # DTB read accesses 971system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 926system.cpu1.itb.inst_accesses 24630398 # ITB inst accesses 927system.cpu1.itb.hits 24627232 # DTB hits 928system.cpu1.itb.misses 3166 # DTB misses 929system.cpu1.itb.accesses 24630398 # DTB accesses 930system.cpu1.numCycles 1801708036 # number of cpu cycles simulated | 972system.cpu1.itb.inst_accesses 53666105 # ITB inst accesses 973system.cpu1.itb.hits 53664371 # DTB hits 974system.cpu1.itb.misses 1734 # DTB misses 975system.cpu1.itb.accesses 53666105 # DTB accesses 976system.cpu1.numCycles 5605295863 # number of cpu cycles simulated |
| 931system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 932system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 977system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 978system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 933system.cpu1.committedInsts 23839695 # Number of instructions committed 934system.cpu1.committedOps 29192667 # Number of ops (including micro ops) committed 935system.cpu1.num_int_alu_accesses 25548618 # Number of integer alu accesses 936system.cpu1.num_fp_alu_accesses 5779 # Number of float alu accesses 937system.cpu1.num_func_calls 987959 # number of times a function call or return occured 938system.cpu1.num_conditional_control_insts 2987443 # number of instructions that are conditional controls 939system.cpu1.num_int_insts 25548618 # number of integer instructions 940system.cpu1.num_fp_insts 5779 # number of float instructions 941system.cpu1.num_int_register_reads 48280801 # number of times the integer registers were read 942system.cpu1.num_int_register_writes 17496069 # number of times the integer registers were written 943system.cpu1.num_fp_register_reads 3771 # number of times the floating registers were read 944system.cpu1.num_fp_register_writes 2012 # number of times the floating registers were written 945system.cpu1.num_cc_register_reads 86968126 # number of times the CC registers were read 946system.cpu1.num_cc_register_writes 11050847 # number of times the CC registers were written 947system.cpu1.num_mem_refs 11166773 # number of memory refs 948system.cpu1.num_load_insts 6206724 # Number of load instructions 949system.cpu1.num_store_insts 4960049 # Number of store instructions 950system.cpu1.num_idle_cycles 1771724648.110516 # Number of idle cycles 951system.cpu1.num_busy_cycles 29983387.889484 # Number of busy cycles 952system.cpu1.not_idle_fraction 0.016642 # Percentage of non-idle cycles 953system.cpu1.idle_fraction 0.983358 # Percentage of idle cycles 954system.cpu1.Branches 4459767 # Number of branches fetched 955system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction 956system.cpu1.op_class::IntAlu 18047467 61.65% 61.71% # Class of executed instruction 957system.cpu1.op_class::IntMult 40427 0.14% 61.85% # Class of executed instruction 958system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction 959system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction 960system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction 961system.cpu1.op_class::FloatCvt 0 0.00% 61.85% # Class of executed instruction 962system.cpu1.op_class::FloatMult 0 0.00% 61.85% # Class of executed instruction 963system.cpu1.op_class::FloatDiv 0 0.00% 61.85% # Class of executed instruction 964system.cpu1.op_class::FloatSqrt 0 0.00% 61.85% # Class of executed instruction 965system.cpu1.op_class::SimdAdd 0 0.00% 61.85% # Class of executed instruction 966system.cpu1.op_class::SimdAddAcc 0 0.00% 61.85% # Class of executed instruction 967system.cpu1.op_class::SimdAlu 0 0.00% 61.85% # Class of executed instruction 968system.cpu1.op_class::SimdCmp 0 0.00% 61.85% # Class of executed instruction 969system.cpu1.op_class::SimdCvt 0 0.00% 61.85% # Class of executed instruction 970system.cpu1.op_class::SimdMisc 0 0.00% 61.85% # Class of executed instruction 971system.cpu1.op_class::SimdMult 0 0.00% 61.85% # Class of executed instruction 972system.cpu1.op_class::SimdMultAcc 0 0.00% 61.85% # Class of executed instruction 973system.cpu1.op_class::SimdShift 0 0.00% 61.85% # Class of executed instruction 974system.cpu1.op_class::SimdShiftAcc 0 0.00% 61.85% # Class of executed instruction 975system.cpu1.op_class::SimdSqrt 0 0.00% 61.85% # Class of executed instruction 976system.cpu1.op_class::SimdFloatAdd 0 0.00% 61.85% # Class of executed instruction 977system.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Class of executed instruction 978system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction 979system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction 980system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction 981system.cpu1.op_class::SimdFloatMisc 1550 0.01% 61.85% # Class of executed instruction 982system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction 983system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction 984system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction 985system.cpu1.op_class::MemRead 6206724 21.20% 83.06% # Class of executed instruction 986system.cpu1.op_class::MemWrite 4960049 16.94% 100.00% # Class of executed instruction | 979system.cpu1.committedInsts 51394160 # Number of instructions committed 980system.cpu1.committedOps 63338742 # Number of ops (including micro ops) committed 981system.cpu1.num_int_alu_accesses 56976202 # Number of integer alu accesses 982system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 983system.cpu1.num_func_calls 9170283 # number of times a function call or return occured 984system.cpu1.num_conditional_control_insts 5966381 # number of instructions that are conditional controls 985system.cpu1.num_int_insts 56976202 # number of integer instructions 986system.cpu1.num_fp_insts 1792 # number of float instructions 987system.cpu1.num_int_register_reads 110660301 # number of times the integer registers were read 988system.cpu1.num_int_register_writes 41292600 # number of times the integer registers were written 989system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 990system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 991system.cpu1.num_cc_register_reads 196241872 # number of times the CC registers were read 992system.cpu1.num_cc_register_writes 18891627 # number of times the CC registers were written 993system.cpu1.num_mem_refs 20022980 # number of memory refs 994system.cpu1.num_load_insts 12287666 # Number of load instructions 995system.cpu1.num_store_insts 7735314 # Number of store instructions 996system.cpu1.num_idle_cycles 5539691262.121797 # Number of idle cycles 997system.cpu1.num_busy_cycles 65604600.878203 # Number of busy cycles 998system.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles 999system.cpu1.idle_fraction 0.988296 # Percentage of idle cycles 1000system.cpu1.Branches 15216192 # Number of branches fetched 1001system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 1002system.cpu1.op_class::IntAlu 45395839 69.36% 69.36% # Class of executed instruction 1003system.cpu1.op_class::IntMult 28345 0.04% 69.40% # Class of executed instruction 1004system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 1005system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 1006system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 1007system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 1008system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 1009system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 1010system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 1011system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 1012system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 1013system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 1014system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 1015system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 1016system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 1017system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 1018system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 1019system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 1020system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 1021system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 1022system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 1023system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 1024system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 1025system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 1026system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 1027system.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction 1028system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 1029system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 1030system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 1031system.cpu1.op_class::MemRead 12287666 18.77% 88.18% # Class of executed instruction 1032system.cpu1.op_class::MemWrite 7735314 11.82% 100.00% # Class of executed instruction |
| 987system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 988system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 1033system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1034system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 989system.cpu1.op_class::total 29271769 # Class of executed instruction | 1035system.cpu1.op_class::total 65450545 # Class of executed instruction |
| 990system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1036system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 991system.cpu1.kern.inst.quiesce 48299 # number of quiesce instructions executed 992system.cpu1.icache.tags.replacements 398154 # number of replacements 993system.cpu1.icache.tags.tagsinuse 474.812776 # Cycle average of tags in use 994system.cpu1.icache.tags.total_refs 24230251 # Total number of references to valid blocks. 995system.cpu1.icache.tags.sampled_refs 398666 # Sample count of references to valid blocks. 996system.cpu1.icache.tags.avg_refs 60.778323 # Average number of references to valid blocks. 997system.cpu1.icache.tags.warmup_cycle 103932913000 # Cycle when the warmup percentage was hit. 998system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.812776 # Average occupied blocks per requestor 999system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927369 # Average percentage of cache occupancy 1000system.cpu1.icache.tags.occ_percent::total 0.927369 # Average percentage of cache occupancy | 1037system.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed 1038system.cpu1.icache.tags.replacements 523179 # number of replacements 1039system.cpu1.icache.tags.tagsinuse 499.711075 # Cycle average of tags in use 1040system.cpu1.icache.tags.total_refs 53141770 # Total number of references to valid blocks. 1041system.cpu1.icache.tags.sampled_refs 523691 # Sample count of references to valid blocks. 1042system.cpu1.icache.tags.avg_refs 101.475431 # Average number of references to valid blocks. 1043system.cpu1.icache.tags.warmup_cycle 76931405000 # Cycle when the warmup percentage was hit. 1044system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711075 # Average occupied blocks per requestor 1045system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 1046system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy |
| 1001system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1047system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1002system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id 1003system.cpu1.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 1004system.cpu1.icache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id 1005system.cpu1.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id | 1048system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 1049system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id |
| 1006system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1050system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1007system.cpu1.icache.tags.tag_accesses 49656500 # Number of tag accesses 1008system.cpu1.icache.tags.data_accesses 49656500 # Number of data accesses 1009system.cpu1.icache.ReadReq_hits::cpu1.inst 24230251 # number of ReadReq hits 1010system.cpu1.icache.ReadReq_hits::total 24230251 # number of ReadReq hits 1011system.cpu1.icache.demand_hits::cpu1.inst 24230251 # number of demand (read+write) hits 1012system.cpu1.icache.demand_hits::total 24230251 # number of demand (read+write) hits 1013system.cpu1.icache.overall_hits::cpu1.inst 24230251 # number of overall hits 1014system.cpu1.icache.overall_hits::total 24230251 # number of overall hits 1015system.cpu1.icache.ReadReq_misses::cpu1.inst 398666 # number of ReadReq misses 1016system.cpu1.icache.ReadReq_misses::total 398666 # number of ReadReq misses 1017system.cpu1.icache.demand_misses::cpu1.inst 398666 # number of demand (read+write) misses 1018system.cpu1.icache.demand_misses::total 398666 # number of demand (read+write) misses 1019system.cpu1.icache.overall_misses::cpu1.inst 398666 # number of overall misses 1020system.cpu1.icache.overall_misses::total 398666 # number of overall misses 1021system.cpu1.icache.ReadReq_accesses::cpu1.inst 24628917 # number of ReadReq accesses(hits+misses) 1022system.cpu1.icache.ReadReq_accesses::total 24628917 # number of ReadReq accesses(hits+misses) 1023system.cpu1.icache.demand_accesses::cpu1.inst 24628917 # number of demand (read+write) accesses 1024system.cpu1.icache.demand_accesses::total 24628917 # number of demand (read+write) accesses 1025system.cpu1.icache.overall_accesses::cpu1.inst 24628917 # number of overall (read+write) accesses 1026system.cpu1.icache.overall_accesses::total 24628917 # number of overall (read+write) accesses 1027system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016187 # miss rate for ReadReq accesses 1028system.cpu1.icache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses 1029system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016187 # miss rate for demand accesses 1030system.cpu1.icache.demand_miss_rate::total 0.016187 # miss rate for demand accesses 1031system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016187 # miss rate for overall accesses 1032system.cpu1.icache.overall_miss_rate::total 0.016187 # miss rate for overall accesses | 1051system.cpu1.icache.tags.tag_accesses 107854613 # Number of tag accesses 1052system.cpu1.icache.tags.data_accesses 107854613 # Number of data accesses 1053system.cpu1.icache.ReadReq_hits::cpu1.inst 53141770 # number of ReadReq hits 1054system.cpu1.icache.ReadReq_hits::total 53141770 # number of ReadReq hits 1055system.cpu1.icache.demand_hits::cpu1.inst 53141770 # number of demand (read+write) hits 1056system.cpu1.icache.demand_hits::total 53141770 # number of demand (read+write) hits 1057system.cpu1.icache.overall_hits::cpu1.inst 53141770 # number of overall hits 1058system.cpu1.icache.overall_hits::total 53141770 # number of overall hits 1059system.cpu1.icache.ReadReq_misses::cpu1.inst 523691 # number of ReadReq misses 1060system.cpu1.icache.ReadReq_misses::total 523691 # number of ReadReq misses 1061system.cpu1.icache.demand_misses::cpu1.inst 523691 # number of demand (read+write) misses 1062system.cpu1.icache.demand_misses::total 523691 # number of demand (read+write) misses 1063system.cpu1.icache.overall_misses::cpu1.inst 523691 # number of overall misses 1064system.cpu1.icache.overall_misses::total 523691 # number of overall misses 1065system.cpu1.icache.ReadReq_accesses::cpu1.inst 53665461 # number of ReadReq accesses(hits+misses) 1066system.cpu1.icache.ReadReq_accesses::total 53665461 # number of ReadReq accesses(hits+misses) 1067system.cpu1.icache.demand_accesses::cpu1.inst 53665461 # number of demand (read+write) accesses 1068system.cpu1.icache.demand_accesses::total 53665461 # number of demand (read+write) accesses 1069system.cpu1.icache.overall_accesses::cpu1.inst 53665461 # number of overall (read+write) accesses 1070system.cpu1.icache.overall_accesses::total 53665461 # number of overall (read+write) accesses 1071system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009758 # miss rate for ReadReq accesses 1072system.cpu1.icache.ReadReq_miss_rate::total 0.009758 # miss rate for ReadReq accesses 1073system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009758 # miss rate for demand accesses 1074system.cpu1.icache.demand_miss_rate::total 0.009758 # miss rate for demand accesses 1075system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009758 # miss rate for overall accesses 1076system.cpu1.icache.overall_miss_rate::total 0.009758 # miss rate for overall accesses |
| 1033system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1034system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1035system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1036system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1037system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1038system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1039system.cpu1.icache.fast_writes 0 # number of fast writes performed 1040system.cpu1.icache.cache_copies 0 # number of cache copies performed 1041system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1042system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 1043system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 1044system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 1045system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 1046system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1047system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 1048system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1049system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 1050system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 1077system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1078system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1080system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1082system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1083system.cpu1.icache.fast_writes 0 # number of fast writes performed 1084system.cpu1.icache.cache_copies 0 # number of cache copies performed 1085system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1086system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 1087system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 1088system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 1089system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 1090system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1091system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 1092system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1093system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 1094system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| 1051system.cpu1.l2cache.tags.replacements 88565 # number of replacements 1052system.cpu1.l2cache.tags.tagsinuse 12390.036216 # Cycle average of tags in use 1053system.cpu1.l2cache.tags.total_refs 691452 # Total number of references to valid blocks. 1054system.cpu1.l2cache.tags.sampled_refs 104644 # Sample count of references to valid blocks. 1055system.cpu1.l2cache.tags.avg_refs 6.607660 # Average number of references to valid blocks. 1056system.cpu1.l2cache.tags.warmup_cycle 876305009500 # Cycle when the warmup percentage was hit. 1057system.cpu1.l2cache.tags.occ_blocks::writebacks 6229.071421 # Average occupied blocks per requestor 1058system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 8.886003 # Average occupied blocks per requestor 1059system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.649559 # Average occupied blocks per requestor 1060system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3323.104999 # Average occupied blocks per requestor 1061system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2826.324234 # Average occupied blocks per requestor 1062system.cpu1.l2cache.tags.occ_percent::writebacks 0.380192 # Average percentage of cache occupancy 1063system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000542 # Average percentage of cache occupancy 1064system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000162 # Average percentage of cache occupancy 1065system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.202826 # Average percentage of cache occupancy 1066system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.172505 # Average percentage of cache occupancy 1067system.cpu1.l2cache.tags.occ_percent::total 0.756228 # Average percentage of cache occupancy 1068system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1069system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id 1070system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1071system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 1072system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1073system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 1074system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id 1075system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id 1076system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9480 # Occupied blocks per task id 1077system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2833 # Occupied blocks per task id 1078system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 1079system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id 1080system.cpu1.l2cache.tags.tag_accesses 15740589 # Number of tag accesses 1081system.cpu1.l2cache.tags.data_accesses 15740589 # Number of data accesses 1082system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5896 # number of ReadReq hits 1083system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2700 # number of ReadReq hits 1084system.cpu1.l2cache.ReadReq_hits::cpu1.inst 375664 # number of ReadReq hits 1085system.cpu1.l2cache.ReadReq_hits::cpu1.data 151551 # number of ReadReq hits 1086system.cpu1.l2cache.ReadReq_hits::total 535811 # number of ReadReq hits 1087system.cpu1.l2cache.Writeback_hits::writebacks 209707 # number of Writeback hits 1088system.cpu1.l2cache.Writeback_hits::total 209707 # number of Writeback hits 1089system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 21 # number of UpgradeReq hits 1090system.cpu1.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits 1091system.cpu1.l2cache.ReadExReq_hits::cpu1.data 48287 # number of ReadExReq hits 1092system.cpu1.l2cache.ReadExReq_hits::total 48287 # number of ReadExReq hits 1093system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5896 # number of demand (read+write) hits 1094system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2700 # number of demand (read+write) hits 1095system.cpu1.l2cache.demand_hits::cpu1.inst 375664 # number of demand (read+write) hits 1096system.cpu1.l2cache.demand_hits::cpu1.data 199838 # number of demand (read+write) hits 1097system.cpu1.l2cache.demand_hits::total 584098 # number of demand (read+write) hits 1098system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5896 # number of overall hits 1099system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2700 # number of overall hits 1100system.cpu1.l2cache.overall_hits::cpu1.inst 375664 # number of overall hits 1101system.cpu1.l2cache.overall_hits::cpu1.data 199838 # number of overall hits 1102system.cpu1.l2cache.overall_hits::total 584098 # number of overall hits 1103system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 349 # number of ReadReq misses 1104system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 263 # number of ReadReq misses 1105system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22734 # number of ReadReq misses 1106system.cpu1.l2cache.ReadReq_misses::cpu1.data 51350 # number of ReadReq misses 1107system.cpu1.l2cache.ReadReq_misses::total 74696 # number of ReadReq misses 1108system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 18752 # number of UpgradeReq misses 1109system.cpu1.l2cache.UpgradeReq_misses::total 18752 # number of UpgradeReq misses 1110system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 11227 # number of SCUpgradeReq misses 1111system.cpu1.l2cache.SCUpgradeReq_misses::total 11227 # number of SCUpgradeReq misses 1112system.cpu1.l2cache.ReadExReq_misses::cpu1.data 68490 # number of ReadExReq misses 1113system.cpu1.l2cache.ReadExReq_misses::total 68490 # number of ReadExReq misses 1114system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 349 # number of demand (read+write) misses 1115system.cpu1.l2cache.demand_misses::cpu1.itb.walker 263 # number of demand (read+write) misses 1116system.cpu1.l2cache.demand_misses::cpu1.inst 22734 # number of demand (read+write) misses 1117system.cpu1.l2cache.demand_misses::cpu1.data 119840 # number of demand (read+write) misses 1118system.cpu1.l2cache.demand_misses::total 143186 # number of demand (read+write) misses 1119system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 349 # number of overall misses 1120system.cpu1.l2cache.overall_misses::cpu1.itb.walker 263 # number of overall misses 1121system.cpu1.l2cache.overall_misses::cpu1.inst 22734 # number of overall misses 1122system.cpu1.l2cache.overall_misses::cpu1.data 119840 # number of overall misses 1123system.cpu1.l2cache.overall_misses::total 143186 # number of overall misses 1124system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6245 # number of ReadReq accesses(hits+misses) 1125system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2963 # number of ReadReq accesses(hits+misses) 1126system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 398398 # number of ReadReq accesses(hits+misses) 1127system.cpu1.l2cache.ReadReq_accesses::cpu1.data 202901 # number of ReadReq accesses(hits+misses) 1128system.cpu1.l2cache.ReadReq_accesses::total 610507 # number of ReadReq accesses(hits+misses) 1129system.cpu1.l2cache.Writeback_accesses::writebacks 209707 # number of Writeback accesses(hits+misses) 1130system.cpu1.l2cache.Writeback_accesses::total 209707 # number of Writeback accesses(hits+misses) 1131system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 18773 # number of UpgradeReq accesses(hits+misses) 1132system.cpu1.l2cache.UpgradeReq_accesses::total 18773 # number of UpgradeReq accesses(hits+misses) 1133system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 11227 # number of SCUpgradeReq accesses(hits+misses) 1134system.cpu1.l2cache.SCUpgradeReq_accesses::total 11227 # number of SCUpgradeReq accesses(hits+misses) 1135system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 116777 # number of ReadExReq accesses(hits+misses) 1136system.cpu1.l2cache.ReadExReq_accesses::total 116777 # number of ReadExReq accesses(hits+misses) 1137system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6245 # number of demand (read+write) accesses 1138system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2963 # number of demand (read+write) accesses 1139system.cpu1.l2cache.demand_accesses::cpu1.inst 398398 # number of demand (read+write) accesses 1140system.cpu1.l2cache.demand_accesses::cpu1.data 319678 # number of demand (read+write) accesses 1141system.cpu1.l2cache.demand_accesses::total 727284 # number of demand (read+write) accesses 1142system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6245 # number of overall (read+write) accesses 1143system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2963 # number of overall (read+write) accesses 1144system.cpu1.l2cache.overall_accesses::cpu1.inst 398398 # number of overall (read+write) accesses 1145system.cpu1.l2cache.overall_accesses::cpu1.data 319678 # number of overall (read+write) accesses 1146system.cpu1.l2cache.overall_accesses::total 727284 # number of overall (read+write) accesses 1147system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for ReadReq accesses 1148system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.088761 # miss rate for ReadReq accesses 1149system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.057064 # miss rate for ReadReq accesses 1150system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.253079 # miss rate for ReadReq accesses 1151system.cpu1.l2cache.ReadReq_miss_rate::total 0.122351 # miss rate for ReadReq accesses 1152system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998881 # miss rate for UpgradeReq accesses 1153system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998881 # miss rate for UpgradeReq accesses | 1095system.cpu1.l2cache.tags.replacements 48552 # number of replacements 1096system.cpu1.l2cache.tags.tagsinuse 15311.760536 # Cycle average of tags in use 1097system.cpu1.l2cache.tags.total_refs 716558 # Total number of references to valid blocks. 1098system.cpu1.l2cache.tags.sampled_refs 63379 # Sample count of references to valid blocks. 1099system.cpu1.l2cache.tags.avg_refs 11.305922 # Average number of references to valid blocks. 1100system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1101system.cpu1.l2cache.tags.occ_blocks::writebacks 8243.045220 # Average occupied blocks per requestor 1102system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.958358 # Average occupied blocks per requestor 1103system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015688 # Average occupied blocks per requestor 1104system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3303.816337 # Average occupied blocks per requestor 1105system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.924934 # Average occupied blocks per requestor 1106system.cpu1.l2cache.tags.occ_percent::writebacks 0.503116 # Average percentage of cache occupancy 1107system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000181 # Average percentage of cache occupancy 1108system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 1109system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201649 # Average percentage of cache occupancy 1110system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229488 # Average percentage of cache occupancy 1111system.cpu1.l2cache.tags.occ_percent::total 0.934556 # Average percentage of cache occupancy 1112system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id 1113system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14809 # Occupied blocks per task id 1114system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 1115system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 1116system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1117system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 540 # Occupied blocks per task id 1118system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9336 # Occupied blocks per task id 1119system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4933 # Occupied blocks per task id 1120system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id 1121system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903870 # Percentage of cache occupancy per task id 1122system.cpu1.l2cache.tags.tag_accesses 15206583 # Number of tag accesses 1123system.cpu1.l2cache.tags.data_accesses 15206583 # Number of data accesses 1124system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3143 # number of ReadReq hits 1125system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1725 # number of ReadReq hits 1126system.cpu1.l2cache.ReadReq_hits::cpu1.inst 509849 # number of ReadReq hits 1127system.cpu1.l2cache.ReadReq_hits::cpu1.data 99406 # number of ReadReq hits 1128system.cpu1.l2cache.ReadReq_hits::total 614123 # number of ReadReq hits 1129system.cpu1.l2cache.Writeback_hits::writebacks 120669 # number of Writeback hits 1130system.cpu1.l2cache.Writeback_hits::total 120669 # number of Writeback hits 1131system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits 1132system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits 1133system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19820 # number of ReadExReq hits 1134system.cpu1.l2cache.ReadExReq_hits::total 19820 # number of ReadExReq hits 1135system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3143 # number of demand (read+write) hits 1136system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1725 # number of demand (read+write) hits 1137system.cpu1.l2cache.demand_hits::cpu1.inst 509849 # number of demand (read+write) hits 1138system.cpu1.l2cache.demand_hits::cpu1.data 119226 # number of demand (read+write) hits 1139system.cpu1.l2cache.demand_hits::total 633943 # number of demand (read+write) hits 1140system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3143 # number of overall hits 1141system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1725 # number of overall hits 1142system.cpu1.l2cache.overall_hits::cpu1.inst 509849 # number of overall hits 1143system.cpu1.l2cache.overall_hits::cpu1.data 119226 # number of overall hits 1144system.cpu1.l2cache.overall_hits::total 633943 # number of overall hits 1145system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 348 # number of ReadReq misses 1146system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses 1147system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13842 # number of ReadReq misses 1148system.cpu1.l2cache.ReadReq_misses::cpu1.data 73217 # number of ReadReq misses 1149system.cpu1.l2cache.ReadReq_misses::total 87678 # number of ReadReq misses 1150system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28845 # number of UpgradeReq misses 1151system.cpu1.l2cache.UpgradeReq_misses::total 28845 # number of UpgradeReq misses 1152system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22527 # number of SCUpgradeReq misses 1153system.cpu1.l2cache.SCUpgradeReq_misses::total 22527 # number of SCUpgradeReq misses 1154system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43793 # number of ReadExReq misses 1155system.cpu1.l2cache.ReadExReq_misses::total 43793 # number of ReadExReq misses 1156system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 348 # number of demand (read+write) misses 1157system.cpu1.l2cache.demand_misses::cpu1.itb.walker 271 # number of demand (read+write) misses 1158system.cpu1.l2cache.demand_misses::cpu1.inst 13842 # number of demand (read+write) misses 1159system.cpu1.l2cache.demand_misses::cpu1.data 117010 # number of demand (read+write) misses 1160system.cpu1.l2cache.demand_misses::total 131471 # number of demand (read+write) misses 1161system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 348 # number of overall misses 1162system.cpu1.l2cache.overall_misses::cpu1.itb.walker 271 # number of overall misses 1163system.cpu1.l2cache.overall_misses::cpu1.inst 13842 # number of overall misses 1164system.cpu1.l2cache.overall_misses::cpu1.data 117010 # number of overall misses 1165system.cpu1.l2cache.overall_misses::total 131471 # number of overall misses 1166system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3491 # number of ReadReq accesses(hits+misses) 1167system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) 1168system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523691 # number of ReadReq accesses(hits+misses) 1169system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172623 # number of ReadReq accesses(hits+misses) 1170system.cpu1.l2cache.ReadReq_accesses::total 701801 # number of ReadReq accesses(hits+misses) 1171system.cpu1.l2cache.Writeback_accesses::writebacks 120669 # number of Writeback accesses(hits+misses) 1172system.cpu1.l2cache.Writeback_accesses::total 120669 # number of Writeback accesses(hits+misses) 1173system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28853 # number of UpgradeReq accesses(hits+misses) 1174system.cpu1.l2cache.UpgradeReq_accesses::total 28853 # number of UpgradeReq accesses(hits+misses) 1175system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22527 # number of SCUpgradeReq accesses(hits+misses) 1176system.cpu1.l2cache.SCUpgradeReq_accesses::total 22527 # number of SCUpgradeReq accesses(hits+misses) 1177system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63613 # number of ReadExReq accesses(hits+misses) 1178system.cpu1.l2cache.ReadExReq_accesses::total 63613 # number of ReadExReq accesses(hits+misses) 1179system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3491 # number of demand (read+write) accesses 1180system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1996 # number of demand (read+write) accesses 1181system.cpu1.l2cache.demand_accesses::cpu1.inst 523691 # number of demand (read+write) accesses 1182system.cpu1.l2cache.demand_accesses::cpu1.data 236236 # number of demand (read+write) accesses 1183system.cpu1.l2cache.demand_accesses::total 765414 # number of demand (read+write) accesses 1184system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3491 # number of overall (read+write) accesses 1185system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 # number of overall (read+write) accesses 1186system.cpu1.l2cache.overall_accesses::cpu1.inst 523691 # number of overall (read+write) accesses 1187system.cpu1.l2cache.overall_accesses::cpu1.data 236236 # number of overall (read+write) accesses 1188system.cpu1.l2cache.overall_accesses::total 765414 # number of overall (read+write) accesses 1189system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for ReadReq accesses 1190system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.135772 # miss rate for ReadReq accesses 1191system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026432 # miss rate for ReadReq accesses 1192system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424144 # miss rate for ReadReq accesses 1193system.cpu1.l2cache.ReadReq_miss_rate::total 0.124933 # miss rate for ReadReq accesses 1194system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses 1195system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses |
| 1154system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1155system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses | 1196system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1197system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 1156system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.586502 # miss rate for ReadExReq accesses 1157system.cpu1.l2cache.ReadExReq_miss_rate::total 0.586502 # miss rate for ReadExReq accesses 1158system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for demand accesses 1159system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.088761 # miss rate for demand accesses 1160system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.057064 # miss rate for demand accesses 1161system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.374877 # miss rate for demand accesses 1162system.cpu1.l2cache.demand_miss_rate::total 0.196878 # miss rate for demand accesses 1163system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for overall accesses 1164system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.088761 # miss rate for overall accesses 1165system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.057064 # miss rate for overall accesses 1166system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.374877 # miss rate for overall accesses 1167system.cpu1.l2cache.overall_miss_rate::total 0.196878 # miss rate for overall accesses | 1198system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688428 # miss rate for ReadExReq accesses 1199system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688428 # miss rate for ReadExReq accesses 1200system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for demand accesses 1201system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.135772 # miss rate for demand accesses 1202system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026432 # miss rate for demand accesses 1203system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495310 # miss rate for demand accesses 1204system.cpu1.l2cache.demand_miss_rate::total 0.171765 # miss rate for demand accesses 1205system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.099685 # miss rate for overall accesses 1206system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.135772 # miss rate for overall accesses 1207system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026432 # miss rate for overall accesses 1208system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495310 # miss rate for overall accesses 1209system.cpu1.l2cache.overall_miss_rate::total 0.171765 # miss rate for overall accesses |
| 1168system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1169system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1170system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1171system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1172system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1173system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1174system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1175system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 1210system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1211system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1212system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1213system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1214system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1215system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1216system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1217system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 1176system.cpu1.l2cache.writebacks::writebacks 61322 # number of writebacks 1177system.cpu1.l2cache.writebacks::total 61322 # number of writebacks | 1218system.cpu1.l2cache.writebacks::writebacks 33034 # number of writebacks 1219system.cpu1.l2cache.writebacks::total 33034 # number of writebacks |
| 1178system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1220system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1179system.cpu1.dcache.tags.replacements 299305 # number of replacements 1180system.cpu1.dcache.tags.tagsinuse 464.628152 # Cycle average of tags in use 1181system.cpu1.dcache.tags.total_refs 9384005 # Total number of references to valid blocks. 1182system.cpu1.dcache.tags.sampled_refs 299817 # Sample count of references to valid blocks. 1183system.cpu1.dcache.tags.avg_refs 31.299109 # Average number of references to valid blocks. 1184system.cpu1.dcache.tags.warmup_cycle 94422670000 # Cycle when the warmup percentage was hit. 1185system.cpu1.dcache.tags.occ_blocks::cpu1.data 464.628152 # Average occupied blocks per requestor 1186system.cpu1.dcache.tags.occ_percent::cpu1.data 0.907477 # Average percentage of cache occupancy 1187system.cpu1.dcache.tags.occ_percent::total 0.907477 # Average percentage of cache occupancy 1188system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1189system.cpu1.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 1190system.cpu1.dcache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 1191system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id 1192system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1193system.cpu1.dcache.tags.tag_accesses 19727044 # Number of tag accesses 1194system.cpu1.dcache.tags.data_accesses 19727044 # Number of data accesses 1195system.cpu1.dcache.ReadReq_hits::cpu1.data 4592285 # number of ReadReq hits 1196system.cpu1.dcache.ReadReq_hits::total 4592285 # number of ReadReq hits 1197system.cpu1.dcache.WriteReq_hits::cpu1.data 4538287 # number of WriteReq hits 1198system.cpu1.dcache.WriteReq_hits::total 4538287 # number of WriteReq hits 1199system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35329 # number of SoftPFReq hits 1200system.cpu1.dcache.SoftPFReq_hits::total 35329 # number of SoftPFReq hits 1201system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94231 # number of LoadLockedReq hits 1202system.cpu1.dcache.LoadLockedReq_hits::total 94231 # number of LoadLockedReq hits 1203system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93873 # number of StoreCondReq hits 1204system.cpu1.dcache.StoreCondReq_hits::total 93873 # number of StoreCondReq hits 1205system.cpu1.dcache.demand_hits::cpu1.data 9130572 # number of demand (read+write) hits 1206system.cpu1.dcache.demand_hits::total 9130572 # number of demand (read+write) hits 1207system.cpu1.dcache.overall_hits::cpu1.data 9165901 # number of overall hits 1208system.cpu1.dcache.overall_hits::total 9165901 # number of overall hits 1209system.cpu1.dcache.ReadReq_misses::cpu1.data 163656 # number of ReadReq misses 1210system.cpu1.dcache.ReadReq_misses::total 163656 # number of ReadReq misses 1211system.cpu1.dcache.WriteReq_misses::cpu1.data 135550 # number of WriteReq misses 1212system.cpu1.dcache.WriteReq_misses::total 135550 # number of WriteReq misses 1213system.cpu1.dcache.SoftPFReq_misses::cpu1.data 28044 # number of SoftPFReq misses 1214system.cpu1.dcache.SoftPFReq_misses::total 28044 # number of SoftPFReq misses 1215system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11201 # number of LoadLockedReq misses 1216system.cpu1.dcache.LoadLockedReq_misses::total 11201 # number of LoadLockedReq misses 1217system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11227 # number of StoreCondReq misses 1218system.cpu1.dcache.StoreCondReq_misses::total 11227 # number of StoreCondReq misses 1219system.cpu1.dcache.demand_misses::cpu1.data 299206 # number of demand (read+write) misses 1220system.cpu1.dcache.demand_misses::total 299206 # number of demand (read+write) misses 1221system.cpu1.dcache.overall_misses::cpu1.data 327250 # number of overall misses 1222system.cpu1.dcache.overall_misses::total 327250 # number of overall misses 1223system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755941 # number of ReadReq accesses(hits+misses) 1224system.cpu1.dcache.ReadReq_accesses::total 4755941 # number of ReadReq accesses(hits+misses) 1225system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673837 # number of WriteReq accesses(hits+misses) 1226system.cpu1.dcache.WriteReq_accesses::total 4673837 # number of WriteReq accesses(hits+misses) 1227system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) 1228system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) 1229system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105432 # number of LoadLockedReq accesses(hits+misses) 1230system.cpu1.dcache.LoadLockedReq_accesses::total 105432 # number of LoadLockedReq accesses(hits+misses) 1231system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105100 # number of StoreCondReq accesses(hits+misses) 1232system.cpu1.dcache.StoreCondReq_accesses::total 105100 # number of StoreCondReq accesses(hits+misses) 1233system.cpu1.dcache.demand_accesses::cpu1.data 9429778 # number of demand (read+write) accesses 1234system.cpu1.dcache.demand_accesses::total 9429778 # number of demand (read+write) accesses 1235system.cpu1.dcache.overall_accesses::cpu1.data 9493151 # number of overall (read+write) accesses 1236system.cpu1.dcache.overall_accesses::total 9493151 # number of overall (read+write) accesses 1237system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034411 # miss rate for ReadReq accesses 1238system.cpu1.dcache.ReadReq_miss_rate::total 0.034411 # miss rate for ReadReq accesses 1239system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029002 # miss rate for WriteReq accesses 1240system.cpu1.dcache.WriteReq_miss_rate::total 0.029002 # miss rate for WriteReq accesses 1241system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.442523 # miss rate for SoftPFReq accesses 1242system.cpu1.dcache.SoftPFReq_miss_rate::total 0.442523 # miss rate for SoftPFReq accesses 1243system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106239 # miss rate for LoadLockedReq accesses 1244system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106239 # miss rate for LoadLockedReq accesses 1245system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106822 # miss rate for StoreCondReq accesses 1246system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106822 # miss rate for StoreCondReq accesses 1247system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031730 # miss rate for demand accesses 1248system.cpu1.dcache.demand_miss_rate::total 0.031730 # miss rate for demand accesses 1249system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034472 # miss rate for overall accesses 1250system.cpu1.dcache.overall_miss_rate::total 0.034472 # miss rate for overall accesses | 1221system.cpu1.dcache.tags.replacements 191901 # number of replacements 1222system.cpu1.dcache.tags.tagsinuse 472.757627 # Cycle average of tags in use 1223system.cpu1.dcache.tags.total_refs 19500351 # Total number of references to valid blocks. 1224system.cpu1.dcache.tags.sampled_refs 192255 # Sample count of references to valid blocks. 1225system.cpu1.dcache.tags.avg_refs 101.429617 # Average number of references to valid blocks. 1226system.cpu1.dcache.tags.warmup_cycle 105851562500 # Cycle when the warmup percentage was hit. 1227system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757627 # Average occupied blocks per requestor 1228system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy 1229system.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy 1230system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 1231system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 1232system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 1233system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 1234system.cpu1.dcache.tags.tag_accesses 39745522 # Number of tag accesses 1235system.cpu1.dcache.tags.data_accesses 39745522 # Number of data accesses 1236system.cpu1.dcache.ReadReq_hits::cpu1.data 11856979 # number of ReadReq hits 1237system.cpu1.dcache.ReadReq_hits::total 11856979 # number of ReadReq hits 1238system.cpu1.dcache.WriteReq_hits::cpu1.data 7396120 # number of WriteReq hits 1239system.cpu1.dcache.WriteReq_hits::total 7396120 # number of WriteReq hits 1240system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50084 # number of SoftPFReq hits 1241system.cpu1.dcache.SoftPFReq_hits::total 50084 # number of SoftPFReq hits 1242system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91418 # number of LoadLockedReq hits 1243system.cpu1.dcache.LoadLockedReq_hits::total 91418 # number of LoadLockedReq hits 1244system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72426 # number of StoreCondReq hits 1245system.cpu1.dcache.StoreCondReq_hits::total 72426 # number of StoreCondReq hits 1246system.cpu1.dcache.demand_hits::cpu1.data 19253099 # number of demand (read+write) hits 1247system.cpu1.dcache.demand_hits::total 19253099 # number of demand (read+write) hits 1248system.cpu1.dcache.overall_hits::cpu1.data 19303183 # number of overall hits 1249system.cpu1.dcache.overall_hits::total 19303183 # number of overall hits 1250system.cpu1.dcache.ReadReq_misses::cpu1.data 136590 # number of ReadReq misses 1251system.cpu1.dcache.ReadReq_misses::total 136590 # number of ReadReq misses 1252system.cpu1.dcache.WriteReq_misses::cpu1.data 92466 # number of WriteReq misses 1253system.cpu1.dcache.WriteReq_misses::total 92466 # number of WriteReq misses 1254system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30716 # number of SoftPFReq misses 1255system.cpu1.dcache.SoftPFReq_misses::total 30716 # number of SoftPFReq misses 1256system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5317 # number of LoadLockedReq misses 1257system.cpu1.dcache.LoadLockedReq_misses::total 5317 # number of LoadLockedReq misses 1258system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22527 # number of StoreCondReq misses 1259system.cpu1.dcache.StoreCondReq_misses::total 22527 # number of StoreCondReq misses 1260system.cpu1.dcache.demand_misses::cpu1.data 229056 # number of demand (read+write) misses 1261system.cpu1.dcache.demand_misses::total 229056 # number of demand (read+write) misses 1262system.cpu1.dcache.overall_misses::cpu1.data 259772 # number of overall misses 1263system.cpu1.dcache.overall_misses::total 259772 # number of overall misses 1264system.cpu1.dcache.ReadReq_accesses::cpu1.data 11993569 # number of ReadReq accesses(hits+misses) 1265system.cpu1.dcache.ReadReq_accesses::total 11993569 # number of ReadReq accesses(hits+misses) 1266system.cpu1.dcache.WriteReq_accesses::cpu1.data 7488586 # number of WriteReq accesses(hits+misses) 1267system.cpu1.dcache.WriteReq_accesses::total 7488586 # number of WriteReq accesses(hits+misses) 1268system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80800 # number of SoftPFReq accesses(hits+misses) 1269system.cpu1.dcache.SoftPFReq_accesses::total 80800 # number of SoftPFReq accesses(hits+misses) 1270system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96735 # number of LoadLockedReq accesses(hits+misses) 1271system.cpu1.dcache.LoadLockedReq_accesses::total 96735 # number of LoadLockedReq accesses(hits+misses) 1272system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94953 # number of StoreCondReq accesses(hits+misses) 1273system.cpu1.dcache.StoreCondReq_accesses::total 94953 # number of StoreCondReq accesses(hits+misses) 1274system.cpu1.dcache.demand_accesses::cpu1.data 19482155 # number of demand (read+write) accesses 1275system.cpu1.dcache.demand_accesses::total 19482155 # number of demand (read+write) accesses 1276system.cpu1.dcache.overall_accesses::cpu1.data 19562955 # number of overall (read+write) accesses 1277system.cpu1.dcache.overall_accesses::total 19562955 # number of overall (read+write) accesses 1278system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011389 # miss rate for ReadReq accesses 1279system.cpu1.dcache.ReadReq_miss_rate::total 0.011389 # miss rate for ReadReq accesses 1280system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses 1281system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses 1282system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380149 # miss rate for SoftPFReq accesses 1283system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380149 # miss rate for SoftPFReq accesses 1284system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054965 # miss rate for LoadLockedReq accesses 1285system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054965 # miss rate for LoadLockedReq accesses 1286system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237244 # miss rate for StoreCondReq accesses 1287system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237244 # miss rate for StoreCondReq accesses 1288system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 1289system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 1290system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 1291system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses |
| 1251system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1252system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1253system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1254system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1255system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1256system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1257system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1258system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1292system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1293system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1294system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1295system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1296system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1297system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1298system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1299system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1259system.cpu1.dcache.writebacks::writebacks 209707 # number of writebacks 1260system.cpu1.dcache.writebacks::total 209707 # number of writebacks | 1300system.cpu1.dcache.writebacks::writebacks 120669 # number of writebacks 1301system.cpu1.dcache.writebacks::total 120669 # number of writebacks |
| 1261system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1302system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1262system.cpu1.toL2Bus.trans_dist::ReadReq 1728836 # Transaction distribution 1263system.cpu1.toL2Bus.trans_dist::ReadResp 1728836 # Transaction distribution 1264system.cpu1.toL2Bus.trans_dist::WriteReq 3546 # Transaction distribution 1265system.cpu1.toL2Bus.trans_dist::WriteResp 3546 # Transaction distribution 1266system.cpu1.toL2Bus.trans_dist::Writeback 209707 # Transaction distribution 1267system.cpu1.toL2Bus.trans_dist::UpgradeReq 18773 # Transaction distribution 1268system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 11227 # Transaction distribution 1269system.cpu1.toL2Bus.trans_dist::UpgradeResp 30000 # Transaction distribution 1270system.cpu1.toL2Bus.trans_dist::ReadExReq 116777 # Transaction distribution 1271system.cpu1.toL2Bus.trans_dist::ReadExResp 116777 # Transaction distribution 1272system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797550 # Packet count per connected master and slave (bytes) 1273system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 3132383 # Packet count per connected master and slave (bytes) 1274system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12644 # Packet count per connected master and slave (bytes) 1275system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25448 # Packet count per connected master and slave (bytes) 1276system.cpu1.toL2Bus.pkt_count::total 3968025 # Packet count per connected master and slave (bytes) 1277system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25515060 # Cumulative packet size per connected master and slave (bytes) 1278system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36101346 # Cumulative packet size per connected master and slave (bytes) 1279system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25288 # Cumulative packet size per connected master and slave (bytes) 1280system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50896 # Cumulative packet size per connected master and slave (bytes) 1281system.cpu1.toL2Bus.pkt_size::total 61692590 # Cumulative packet size per connected master and slave (bytes) 1282system.cpu1.toL2Bus.snoops 259574 # Total snoops (count) 1283system.cpu1.toL2Bus.snoop_fanout::samples 1204043 # Request fanout histogram 1284system.cpu1.toL2Bus.snoop_fanout::mean 5.188487 # Request fanout histogram 1285system.cpu1.toL2Bus.snoop_fanout::stdev 0.391100 # Request fanout histogram | 1303system.cpu1.toL2Bus.trans_dist::ReadReq 709063 # Transaction distribution 1304system.cpu1.toL2Bus.trans_dist::ReadResp 709063 # Transaction distribution 1305system.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution 1306system.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution 1307system.cpu1.toL2Bus.trans_dist::Writeback 120669 # Transaction distribution 1308system.cpu1.toL2Bus.trans_dist::UpgradeReq 28853 # Transaction distribution 1309system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22527 # Transaction distribution 1310system.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution 1311system.cpu1.toL2Bus.trans_dist::ReadExReq 63613 # Transaction distribution 1312system.cpu1.toL2Bus.trans_dist::ReadExResp 63613 # Transaction distribution 1313system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1047738 # Packet count per connected master and slave (bytes) 1314system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707355 # Packet count per connected master and slave (bytes) 1315system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1316system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 1317system.cpu1.toL2Bus.pkt_count::total 1773789 # Packet count per connected master and slave (bytes) 1318system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33516936 # Cumulative packet size per connected master and slave (bytes) 1319system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22861090 # Cumulative packet size per connected master and slave (bytes) 1320system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1321system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 1322system.cpu1.toL2Bus.pkt_size::total 56415418 # Cumulative packet size per connected master and slave (bytes) 1323system.cpu1.toL2Bus.snoops 499577 # Total snoops (count) 1324system.cpu1.toL2Bus.snoop_fanout::samples 1371208 # Request fanout histogram 1325system.cpu1.toL2Bus.snoop_fanout::mean 5.313508 # Request fanout histogram 1326system.cpu1.toL2Bus.snoop_fanout::stdev 0.463919 # Request fanout histogram |
| 1286system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1287system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1288system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1289system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1290system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1291system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 1327system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1328system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1329system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1330system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1331system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1332system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 1292system.cpu1.toL2Bus.snoop_fanout::5 977097 81.15% 81.15% # Request fanout histogram 1293system.cpu1.toL2Bus.snoop_fanout::6 226946 18.85% 100.00% # Request fanout histogram | 1333system.cpu1.toL2Bus.snoop_fanout::5 941324 68.65% 68.65% # Request fanout histogram 1334system.cpu1.toL2Bus.snoop_fanout::6 429884 31.35% 100.00% # Request fanout histogram |
| 1294system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1295system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1296system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram | 1335system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1336system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1337system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram |
| 1297system.cpu1.toL2Bus.snoop_fanout::total 1204043 # Request fanout histogram 1298system.iocache.tags.replacements 0 # number of replacements 1299system.iocache.tags.tagsinuse 0 # Cycle average of tags in use | 1338system.cpu1.toL2Bus.snoop_fanout::total 1371208 # Request fanout histogram 1339system.iocache.tags.replacements 36442 # number of replacements 1340system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use |
| 1300system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1341system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1301system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1302system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1303system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1304system.iocache.tags.tag_accesses 0 # Number of tag accesses 1305system.iocache.tags.data_accesses 0 # Number of data accesses | 1342system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1343system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1344system.iocache.tags.warmup_cycle 246641119509 # Cycle when the warmup percentage was hit. 1345system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor 1346system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1347system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 1348system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1349system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1350system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1351system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1352system.iocache.tags.data_accesses 328284 # Number of data accesses 1353system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1354system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1355system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1356system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1357system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 1358system.iocache.demand_misses::total 252 # number of demand (read+write) misses 1359system.iocache.overall_misses::realview.ide 252 # number of overall misses 1360system.iocache.overall_misses::total 252 # number of overall misses 1361system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1362system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1363system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1364system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1365system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 1366system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 1367system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 1368system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 1369system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1370system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1371system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1372system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1373system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1374system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1306system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1307system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1308system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1309system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1310system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1311system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1375system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1376system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1377system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1378system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1379system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1380system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1312system.iocache.fast_writes 0 # number of fast writes performed | 1381system.iocache.fast_writes 36224 # number of fast writes performed |
| 1313system.iocache.cache_copies 0 # number of cache copies performed 1314system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1315 1316---------- End Simulation Statistics ---------- | 1382system.iocache.cache_copies 0 # number of cache copies performed 1383system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1384 1385---------- End Simulation Statistics ---------- |