| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.900855 # Number of seconds simulated 4sim_ticks 900854787500 # Number of ticks simulated 5final_tick 900854787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.900830 # Number of seconds simulated 4sim_ticks 900829868000 # Number of ticks simulated 5final_tick 900829868000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 875862 # Simulator instruction rate (inst/s) 8host_op_rate 1055198 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12821864647 # Simulator tick rate (ticks/s) 10host_mem_usage 433912 # Number of bytes of host memory used 11host_seconds 70.26 # Real time elapsed on the host 12sim_insts 61537412 # Number of instructions simulated 13sim_ops 74137396 # Number of ops (including micro ops) simulated | 7host_inst_rate 1355321 # Simulator instruction rate (inst/s) 8host_op_rate 1632835 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 19839612971 # Simulator tick rate (ticks/s) 10host_mem_usage 467260 # Number of bytes of host memory used 11host_seconds 45.41 # Real time elapsed on the host 12sim_insts 61539136 # Number of instructions simulated 13sim_ops 74139862 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 460108 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 6580092 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 258564 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 2992120 # Number of bytes read from this memory 23system.physmem.bytes_read::total 49612932 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 460108 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 258564 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 718672 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 4174784 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 30system.physmem.bytes_written::total 7201872 # Number of bytes written to this memory 31system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.inst 13417 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.data 102873 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 4131 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 46770 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 5082398 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 65231 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 822003 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43649210 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 284 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 213 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 510746 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 7304276 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.inst 287021 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.data 3321423 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::total 55073173 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu0.inst 510746 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu1.inst 287021 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 797767 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_write::writebacks 4634247 # Write bandwidth from this memory (bytes/s) 55system.physmem.bw_write::cpu0.data 3360195 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::total 7994487 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_total::writebacks 4634247 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::realview.clcd 43649210 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu0.dtb.walker 284 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.itb.walker 213 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.inst 510746 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.data 10664471 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu1.inst 287021 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.data 3321468 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::total 63067661 # Total bandwidth to/from this memory (bytes/s) | |
| 67system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 68system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 69system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 70system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 71system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 72system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 73system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 74system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 75system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 76system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 77system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 78system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 83system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 84system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) | 16system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 17system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 18system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 19system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 20system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 21system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 22system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 23system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 24system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 25system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 30system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 31system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 32system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 33system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) |
| 85system.membus.throughput 65740815 # Throughput (bytes/s) 86system.membus.data_through_bus 59222928 # Total data (bytes) 87system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 34system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu0.inst 468620 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu0.data 6508860 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.inst 266564 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.data 2938616 # Number of bytes read from this memory 41system.physmem.bytes_read::total 49504452 # Number of bytes read from this memory 42system.physmem.bytes_inst_read::cpu0.inst 468620 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::cpu1.inst 266564 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::total 735184 # Number of instructions bytes read from this memory 45system.physmem.bytes_written::writebacks 3365568 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory 47system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 48system.physmem.bytes_written::total 6392656 # Number of bytes written to this memory 49system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.inst 13550 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.data 101760 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.inst 4256 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.data 45934 # Number of read requests responded to by this memory 56system.physmem.num_reads::total 5080703 # Number of read requests responded to by this memory 57system.physmem.num_writes::writebacks 52587 # Number of write requests responded to by this memory 58system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory 59system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 60system.physmem.num_writes::total 809359 # Number of write requests responded to by this memory 61system.physmem.bw_read::realview.clcd 43650418 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu0.dtb.walker 71 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu0.itb.walker 142 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.inst 520209 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.data 7225404 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu1.inst 295909 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu1.data 3262121 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::total 54954275 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_inst_read::cpu0.inst 520209 # Instruction read bandwidth from this memory (bytes/s) 70system.physmem.bw_inst_read::cpu1.inst 295909 # Instruction read bandwidth from this memory (bytes/s) 71system.physmem.bw_inst_read::total 816119 # Instruction read bandwidth from this memory (bytes/s) 72system.physmem.bw_write::writebacks 3736075 # Write bandwidth from this memory (bytes/s) 73system.physmem.bw_write::cpu0.data 3360288 # Write bandwidth from this memory (bytes/s) 74system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) 75system.physmem.bw_write::total 7096408 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_total::writebacks 3736075 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.clcd 43650418 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu0.dtb.walker 71 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.itb.walker 142 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu0.inst 520209 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu0.data 10585693 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu1.inst 295909 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.data 3262165 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::total 62050682 # Total bandwidth to/from this memory (bytes/s) 85system.membus.trans_dist::ReadReq 6129610 # Transaction distribution 86system.membus.trans_dist::ReadResp 6129610 # Transaction distribution 87system.membus.trans_dist::WriteReq 767040 # Transaction distribution 88system.membus.trans_dist::WriteResp 767040 # Transaction distribution 89system.membus.trans_dist::Writeback 52587 # Transaction distribution 90system.membus.trans_dist::UpgradeReq 37380 # Transaction distribution 91system.membus.trans_dist::SCUpgradeReq 20039 # Transaction distribution 92system.membus.trans_dist::UpgradeResp 14449 # Transaction distribution 93system.membus.trans_dist::ReadExReq 163617 # Transaction distribution 94system.membus.trans_dist::ReadExResp 136674 # Transaction distribution 95system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382414 # Packet count per connected master and slave (bytes) 96system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 97system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8564 # Packet count per connected master and slave (bytes) 98system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) 99system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 682 # Packet count per connected master and slave (bytes) 100system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1995948 # Packet count per connected master and slave (bytes) 101system.membus.pkt_count_system.l2c.mem_side::total 4387646 # Packet count per connected master and slave (bytes) 102system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 9830400 # Packet count per connected master and slave (bytes) 103system.membus.pkt_count_system.iocache.mem_side::total 9830400 # Packet count per connected master and slave (bytes) 104system.membus.pkt_count::total 14218046 # Packet count per connected master and slave (bytes) 105system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2389580 # Cumulative packet size per connected master and slave (bytes) 106system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 107system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 17128 # Cumulative packet size per connected master and slave (bytes) 108system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) 109system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1364 # Cumulative packet size per connected master and slave (bytes) 110system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16575508 # Cumulative packet size per connected master and slave (bytes) 111system.membus.pkt_size_system.l2c.mem_side::total 18983656 # Cumulative packet size per connected master and slave (bytes) 112system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 39321600 # Cumulative packet size per connected master and slave (bytes) 113system.membus.pkt_size_system.iocache.mem_side::total 39321600 # Cumulative packet size per connected master and slave (bytes) 114system.membus.pkt_size::total 58305256 # Cumulative packet size per connected master and slave (bytes) 115system.membus.snoops 0 # Total snoops (count) 116system.membus.snoop_fanout::samples 295628 # Request fanout histogram 117system.membus.snoop_fanout::mean 1 # Request fanout histogram 118system.membus.snoop_fanout::stdev 0 # Request fanout histogram 119system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 120system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 121system.membus.snoop_fanout::1 295628 100.00% 100.00% # Request fanout histogram 122system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 123system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 124system.membus.snoop_fanout::min_value 1 # Request fanout histogram 125system.membus.snoop_fanout::max_value 1 # Request fanout histogram 126system.membus.snoop_fanout::total 295628 # Request fanout histogram |
| 88system.cpu_clk_domain.clock 500 # Clock period in ticks | 127system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 89system.l2c.tags.replacements 70256 # number of replacements 90system.l2c.tags.tagsinuse 51491.506872 # Cycle average of tags in use 91system.l2c.tags.total_refs 1633923 # Total number of references to valid blocks. 92system.l2c.tags.sampled_refs 135467 # Sample count of references to valid blocks. 93system.l2c.tags.avg_refs 12.061410 # Average number of references to valid blocks. | 128system.l2c.tags.replacements 60014 # number of replacements 129system.l2c.tags.tagsinuse 50124.590156 # Cycle average of tags in use 130system.l2c.tags.total_refs 136044 # Total number of references to valid blocks. 131system.l2c.tags.sampled_refs 120331 # Sample count of references to valid blocks. 132system.l2c.tags.avg_refs 1.130581 # Average number of references to valid blocks. |
| 94system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 133system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 95system.l2c.tags.occ_blocks::writebacks 39155.338647 # Average occupied blocks per requestor 96system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.673377 # Average occupied blocks per requestor 97system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001056 # Average occupied blocks per requestor 98system.l2c.tags.occ_blocks::cpu0.inst 4830.605577 # Average occupied blocks per requestor 99system.l2c.tags.occ_blocks::cpu0.data 5154.208952 # Average occupied blocks per requestor 100system.l2c.tags.occ_blocks::cpu1.inst 1696.649192 # Average occupied blocks per requestor 101system.l2c.tags.occ_blocks::cpu1.data 652.030072 # Average occupied blocks per requestor 102system.l2c.tags.occ_percent::writebacks 0.597463 # Average percentage of cache occupancy 103system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy 104system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 105system.l2c.tags.occ_percent::cpu0.inst 0.073709 # Average percentage of cache occupancy 106system.l2c.tags.occ_percent::cpu0.data 0.078647 # Average percentage of cache occupancy 107system.l2c.tags.occ_percent::cpu1.inst 0.025889 # Average percentage of cache occupancy 108system.l2c.tags.occ_percent::cpu1.data 0.009949 # Average percentage of cache occupancy 109system.l2c.tags.occ_percent::total 0.785698 # Average percentage of cache occupancy 110system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id 111system.l2c.tags.occ_task_id_blocks::1024 65207 # Occupied blocks per task id 112system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 113system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 114system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 115system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id 116system.l2c.tags.age_task_id_blocks_1024::2 3953 # Occupied blocks per task id 117system.l2c.tags.age_task_id_blocks_1024::3 12685 # Occupied blocks per task id 118system.l2c.tags.age_task_id_blocks_1024::4 48286 # Occupied blocks per task id 119system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id 120system.l2c.tags.occ_task_id_percent::1024 0.994980 # Percentage of cache occupancy per task id 121system.l2c.tags.tag_accesses 16963603 # Number of tag accesses 122system.l2c.tags.data_accesses 16963603 # Number of data accesses 123system.l2c.ReadReq_hits::cpu0.dtb.walker 4298 # number of ReadReq hits 124system.l2c.ReadReq_hits::cpu0.itb.walker 1596 # number of ReadReq hits 125system.l2c.ReadReq_hits::cpu0.inst 413244 # number of ReadReq hits 126system.l2c.ReadReq_hits::cpu0.data 202837 # number of ReadReq hits 127system.l2c.ReadReq_hits::cpu1.dtb.walker 4578 # number of ReadReq hits 128system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits 129system.l2c.ReadReq_hits::cpu1.inst 438543 # number of ReadReq hits 130system.l2c.ReadReq_hits::cpu1.data 146503 # number of ReadReq hits 131system.l2c.ReadReq_hits::total 1213542 # number of ReadReq hits 132system.l2c.Writeback_hits::writebacks 571726 # number of Writeback hits 133system.l2c.Writeback_hits::total 571726 # number of Writeback hits 134system.l2c.UpgradeReq_hits::cpu0.data 1266 # number of UpgradeReq hits 135system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits 136system.l2c.UpgradeReq_hits::total 1663 # number of UpgradeReq hits 137system.l2c.SCUpgradeReq_hits::cpu0.data 238 # number of SCUpgradeReq hits 138system.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits 139system.l2c.SCUpgradeReq_hits::total 276 # number of SCUpgradeReq hits 140system.l2c.ReadExReq_hits::cpu0.data 51499 # number of ReadExReq hits 141system.l2c.ReadExReq_hits::cpu1.data 57148 # number of ReadExReq hits 142system.l2c.ReadExReq_hits::total 108647 # number of ReadExReq hits 143system.l2c.demand_hits::cpu0.dtb.walker 4298 # number of demand (read+write) hits 144system.l2c.demand_hits::cpu0.itb.walker 1596 # number of demand (read+write) hits 145system.l2c.demand_hits::cpu0.inst 413244 # number of demand (read+write) hits 146system.l2c.demand_hits::cpu0.data 254336 # number of demand (read+write) hits 147system.l2c.demand_hits::cpu1.dtb.walker 4578 # number of demand (read+write) hits 148system.l2c.demand_hits::cpu1.itb.walker 1943 # number of demand (read+write) hits 149system.l2c.demand_hits::cpu1.inst 438543 # number of demand (read+write) hits 150system.l2c.demand_hits::cpu1.data 203651 # number of demand (read+write) hits 151system.l2c.demand_hits::total 1322189 # number of demand (read+write) hits 152system.l2c.overall_hits::cpu0.dtb.walker 4298 # number of overall hits 153system.l2c.overall_hits::cpu0.itb.walker 1596 # number of overall hits 154system.l2c.overall_hits::cpu0.inst 413244 # number of overall hits 155system.l2c.overall_hits::cpu0.data 254336 # number of overall hits 156system.l2c.overall_hits::cpu1.dtb.walker 4578 # number of overall hits 157system.l2c.overall_hits::cpu1.itb.walker 1943 # number of overall hits 158system.l2c.overall_hits::cpu1.inst 438543 # number of overall hits 159system.l2c.overall_hits::cpu1.data 203651 # number of overall hits 160system.l2c.overall_hits::total 1322189 # number of overall hits 161system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses 162system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 163system.l2c.ReadReq_misses::cpu0.inst 6774 # number of ReadReq misses 164system.l2c.ReadReq_misses::cpu0.data 9699 # number of ReadReq misses 165system.l2c.ReadReq_misses::cpu1.inst 4034 # number of ReadReq misses 166system.l2c.ReadReq_misses::cpu1.data 1828 # number of ReadReq misses 167system.l2c.ReadReq_misses::total 22342 # number of ReadReq misses 168system.l2c.UpgradeReq_misses::cpu0.data 2906 # number of UpgradeReq misses 169system.l2c.UpgradeReq_misses::cpu1.data 5033 # number of UpgradeReq misses 170system.l2c.UpgradeReq_misses::total 7939 # number of UpgradeReq misses 171system.l2c.SCUpgradeReq_misses::cpu0.data 414 # number of SCUpgradeReq misses 172system.l2c.SCUpgradeReq_misses::cpu1.data 662 # number of SCUpgradeReq misses 173system.l2c.SCUpgradeReq_misses::total 1076 # number of SCUpgradeReq misses 174system.l2c.ReadExReq_misses::cpu0.data 94027 # number of ReadExReq misses 175system.l2c.ReadExReq_misses::cpu1.data 46518 # number of ReadExReq misses 176system.l2c.ReadExReq_misses::total 140545 # number of ReadExReq misses 177system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses 178system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 179system.l2c.demand_misses::cpu0.inst 6774 # number of demand (read+write) misses 180system.l2c.demand_misses::cpu0.data 103726 # number of demand (read+write) misses 181system.l2c.demand_misses::cpu1.inst 4034 # number of demand (read+write) misses 182system.l2c.demand_misses::cpu1.data 48346 # number of demand (read+write) misses 183system.l2c.demand_misses::total 162887 # number of demand (read+write) misses 184system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses 185system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 186system.l2c.overall_misses::cpu0.inst 6774 # number of overall misses 187system.l2c.overall_misses::cpu0.data 103726 # number of overall misses 188system.l2c.overall_misses::cpu1.inst 4034 # number of overall misses 189system.l2c.overall_misses::cpu1.data 48346 # number of overall misses 190system.l2c.overall_misses::total 162887 # number of overall misses 191system.l2c.ReadReq_accesses::cpu0.dtb.walker 4302 # number of ReadReq accesses(hits+misses) 192system.l2c.ReadReq_accesses::cpu0.itb.walker 1599 # number of ReadReq accesses(hits+misses) 193system.l2c.ReadReq_accesses::cpu0.inst 420018 # number of ReadReq accesses(hits+misses) 194system.l2c.ReadReq_accesses::cpu0.data 212536 # number of ReadReq accesses(hits+misses) 195system.l2c.ReadReq_accesses::cpu1.dtb.walker 4578 # number of ReadReq accesses(hits+misses) 196system.l2c.ReadReq_accesses::cpu1.itb.walker 1943 # number of ReadReq accesses(hits+misses) 197system.l2c.ReadReq_accesses::cpu1.inst 442577 # number of ReadReq accesses(hits+misses) 198system.l2c.ReadReq_accesses::cpu1.data 148331 # number of ReadReq accesses(hits+misses) 199system.l2c.ReadReq_accesses::total 1235884 # number of ReadReq accesses(hits+misses) 200system.l2c.Writeback_accesses::writebacks 571726 # number of Writeback accesses(hits+misses) 201system.l2c.Writeback_accesses::total 571726 # number of Writeback accesses(hits+misses) 202system.l2c.UpgradeReq_accesses::cpu0.data 4172 # number of UpgradeReq accesses(hits+misses) 203system.l2c.UpgradeReq_accesses::cpu1.data 5430 # number of UpgradeReq accesses(hits+misses) 204system.l2c.UpgradeReq_accesses::total 9602 # number of UpgradeReq accesses(hits+misses) 205system.l2c.SCUpgradeReq_accesses::cpu0.data 652 # number of SCUpgradeReq accesses(hits+misses) 206system.l2c.SCUpgradeReq_accesses::cpu1.data 700 # number of SCUpgradeReq accesses(hits+misses) 207system.l2c.SCUpgradeReq_accesses::total 1352 # number of SCUpgradeReq accesses(hits+misses) 208system.l2c.ReadExReq_accesses::cpu0.data 145526 # number of ReadExReq accesses(hits+misses) 209system.l2c.ReadExReq_accesses::cpu1.data 103666 # number of ReadExReq accesses(hits+misses) 210system.l2c.ReadExReq_accesses::total 249192 # number of ReadExReq accesses(hits+misses) 211system.l2c.demand_accesses::cpu0.dtb.walker 4302 # number of demand (read+write) accesses 212system.l2c.demand_accesses::cpu0.itb.walker 1599 # number of demand (read+write) accesses 213system.l2c.demand_accesses::cpu0.inst 420018 # number of demand (read+write) accesses 214system.l2c.demand_accesses::cpu0.data 358062 # number of demand (read+write) accesses 215system.l2c.demand_accesses::cpu1.dtb.walker 4578 # number of demand (read+write) accesses 216system.l2c.demand_accesses::cpu1.itb.walker 1943 # number of demand (read+write) accesses 217system.l2c.demand_accesses::cpu1.inst 442577 # number of demand (read+write) accesses 218system.l2c.demand_accesses::cpu1.data 251997 # number of demand (read+write) accesses 219system.l2c.demand_accesses::total 1485076 # number of demand (read+write) accesses 220system.l2c.overall_accesses::cpu0.dtb.walker 4302 # number of overall (read+write) accesses 221system.l2c.overall_accesses::cpu0.itb.walker 1599 # number of overall (read+write) accesses 222system.l2c.overall_accesses::cpu0.inst 420018 # number of overall (read+write) accesses 223system.l2c.overall_accesses::cpu0.data 358062 # number of overall (read+write) accesses 224system.l2c.overall_accesses::cpu1.dtb.walker 4578 # number of overall (read+write) accesses 225system.l2c.overall_accesses::cpu1.itb.walker 1943 # number of overall (read+write) accesses 226system.l2c.overall_accesses::cpu1.inst 442577 # number of overall (read+write) accesses 227system.l2c.overall_accesses::cpu1.data 251997 # number of overall (read+write) accesses 228system.l2c.overall_accesses::total 1485076 # number of overall (read+write) accesses 229system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for ReadReq accesses 230system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001876 # miss rate for ReadReq accesses 231system.l2c.ReadReq_miss_rate::cpu0.inst 0.016128 # miss rate for ReadReq accesses 232system.l2c.ReadReq_miss_rate::cpu0.data 0.045635 # miss rate for ReadReq accesses 233system.l2c.ReadReq_miss_rate::cpu1.inst 0.009115 # miss rate for ReadReq accesses 234system.l2c.ReadReq_miss_rate::cpu1.data 0.012324 # miss rate for ReadReq accesses 235system.l2c.ReadReq_miss_rate::total 0.018078 # miss rate for ReadReq accesses 236system.l2c.UpgradeReq_miss_rate::cpu0.data 0.696548 # miss rate for UpgradeReq accesses 237system.l2c.UpgradeReq_miss_rate::cpu1.data 0.926888 # miss rate for UpgradeReq accesses 238system.l2c.UpgradeReq_miss_rate::total 0.826807 # miss rate for UpgradeReq accesses 239system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.634969 # miss rate for SCUpgradeReq accesses 240system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.945714 # miss rate for SCUpgradeReq accesses 241system.l2c.SCUpgradeReq_miss_rate::total 0.795858 # miss rate for SCUpgradeReq accesses 242system.l2c.ReadExReq_miss_rate::cpu0.data 0.646118 # miss rate for ReadExReq accesses 243system.l2c.ReadExReq_miss_rate::cpu1.data 0.448730 # miss rate for ReadExReq accesses 244system.l2c.ReadExReq_miss_rate::total 0.564003 # miss rate for ReadExReq accesses 245system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for demand accesses 246system.l2c.demand_miss_rate::cpu0.itb.walker 0.001876 # miss rate for demand accesses 247system.l2c.demand_miss_rate::cpu0.inst 0.016128 # miss rate for demand accesses 248system.l2c.demand_miss_rate::cpu0.data 0.289687 # miss rate for demand accesses 249system.l2c.demand_miss_rate::cpu1.inst 0.009115 # miss rate for demand accesses 250system.l2c.demand_miss_rate::cpu1.data 0.191851 # miss rate for demand accesses 251system.l2c.demand_miss_rate::total 0.109683 # miss rate for demand accesses 252system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000930 # miss rate for overall accesses 253system.l2c.overall_miss_rate::cpu0.itb.walker 0.001876 # miss rate for overall accesses 254system.l2c.overall_miss_rate::cpu0.inst 0.016128 # miss rate for overall accesses 255system.l2c.overall_miss_rate::cpu0.data 0.289687 # miss rate for overall accesses 256system.l2c.overall_miss_rate::cpu1.inst 0.009115 # miss rate for overall accesses 257system.l2c.overall_miss_rate::cpu1.data 0.191851 # miss rate for overall accesses 258system.l2c.overall_miss_rate::total 0.109683 # miss rate for overall accesses | 134system.l2c.tags.occ_blocks::writebacks 37074.868959 # Average occupied blocks per requestor 135system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.077014 # Average occupied blocks per requestor 136system.l2c.tags.occ_blocks::cpu0.itb.walker 1.053163 # Average occupied blocks per requestor 137system.l2c.tags.occ_blocks::cpu0.inst 4876.195614 # Average occupied blocks per requestor 138system.l2c.tags.occ_blocks::cpu0.data 5801.198822 # Average occupied blocks per requestor 139system.l2c.tags.occ_blocks::cpu1.inst 1684.572168 # Average occupied blocks per requestor 140system.l2c.tags.occ_blocks::cpu1.data 686.624416 # Average occupied blocks per requestor 141system.l2c.tags.occ_percent::writebacks 0.565718 # Average percentage of cache occupancy 142system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000001 # Average percentage of cache occupancy 143system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 144system.l2c.tags.occ_percent::cpu0.inst 0.074405 # Average percentage of cache occupancy 145system.l2c.tags.occ_percent::cpu0.data 0.088519 # Average percentage of cache occupancy 146system.l2c.tags.occ_percent::cpu1.inst 0.025705 # Average percentage of cache occupancy 147system.l2c.tags.occ_percent::cpu1.data 0.010477 # Average percentage of cache occupancy 148system.l2c.tags.occ_percent::total 0.764841 # Average percentage of cache occupancy 149system.l2c.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id 150system.l2c.tags.occ_task_id_blocks::1024 60314 # Occupied blocks per task id 151system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 152system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 153system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id 154system.l2c.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id 155system.l2c.tags.age_task_id_blocks_1024::2 1748 # Occupied blocks per task id 156system.l2c.tags.age_task_id_blocks_1024::3 13321 # Occupied blocks per task id 157system.l2c.tags.age_task_id_blocks_1024::4 45151 # Occupied blocks per task id 158system.l2c.tags.occ_task_id_percent::1023 0.000046 # Percentage of cache occupancy per task id 159system.l2c.tags.occ_task_id_percent::1024 0.920319 # Percentage of cache occupancy per task id 160system.l2c.tags.tag_accesses 3837449 # Number of tag accesses 161system.l2c.tags.data_accesses 3837449 # Number of data accesses 162system.l2c.ReadReq_hits::cpu0.dtb.walker 59 # number of ReadReq hits 163system.l2c.ReadReq_hits::cpu0.itb.walker 32 # number of ReadReq hits 164system.l2c.ReadReq_hits::cpu0.inst 12381 # number of ReadReq hits 165system.l2c.ReadReq_hits::cpu0.data 37925 # number of ReadReq hits 166system.l2c.ReadReq_hits::cpu1.dtb.walker 68 # number of ReadReq hits 167system.l2c.ReadReq_hits::cpu1.itb.walker 43 # number of ReadReq hits 168system.l2c.ReadReq_hits::cpu1.inst 18539 # number of ReadReq hits 169system.l2c.ReadReq_hits::cpu1.data 11807 # number of ReadReq hits 170system.l2c.ReadReq_hits::total 80854 # number of ReadReq hits 171system.l2c.Writeback_hits::writebacks 175673 # number of Writeback hits 172system.l2c.Writeback_hits::total 175673 # number of Writeback hits 173system.l2c.UpgradeReq_hits::cpu0.data 221 # number of UpgradeReq hits 174system.l2c.UpgradeReq_hits::cpu1.data 174 # number of UpgradeReq hits 175system.l2c.UpgradeReq_hits::total 395 # number of UpgradeReq hits 176system.l2c.SCUpgradeReq_hits::cpu0.data 20 # number of SCUpgradeReq hits 177system.l2c.SCUpgradeReq_hits::cpu1.data 20 # number of SCUpgradeReq hits 178system.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits 179system.l2c.ReadExReq_hits::cpu0.data 7332 # number of ReadExReq hits 180system.l2c.ReadExReq_hits::cpu1.data 6046 # number of ReadExReq hits 181system.l2c.ReadExReq_hits::total 13378 # number of ReadExReq hits 182system.l2c.demand_hits::cpu0.dtb.walker 59 # number of demand (read+write) hits 183system.l2c.demand_hits::cpu0.itb.walker 32 # number of demand (read+write) hits 184system.l2c.demand_hits::cpu0.inst 12381 # number of demand (read+write) hits 185system.l2c.demand_hits::cpu0.data 45257 # number of demand (read+write) hits 186system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits 187system.l2c.demand_hits::cpu1.itb.walker 43 # number of demand (read+write) hits 188system.l2c.demand_hits::cpu1.inst 18539 # number of demand (read+write) hits 189system.l2c.demand_hits::cpu1.data 17853 # number of demand (read+write) hits 190system.l2c.demand_hits::total 94232 # number of demand (read+write) hits 191system.l2c.overall_hits::cpu0.dtb.walker 59 # number of overall hits 192system.l2c.overall_hits::cpu0.itb.walker 32 # number of overall hits 193system.l2c.overall_hits::cpu0.inst 12381 # number of overall hits 194system.l2c.overall_hits::cpu0.data 45257 # number of overall hits 195system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits 196system.l2c.overall_hits::cpu1.itb.walker 43 # number of overall hits 197system.l2c.overall_hits::cpu1.inst 18539 # number of overall hits 198system.l2c.overall_hits::cpu1.data 17853 # number of overall hits 199system.l2c.overall_hits::total 94232 # number of overall hits 200system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 201system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 202system.l2c.ReadReq_misses::cpu0.inst 6907 # number of ReadReq misses 203system.l2c.ReadReq_misses::cpu0.data 9458 # number of ReadReq misses 204system.l2c.ReadReq_misses::cpu1.inst 4159 # number of ReadReq misses 205system.l2c.ReadReq_misses::cpu1.data 1478 # number of ReadReq misses 206system.l2c.ReadReq_misses::total 22005 # number of ReadReq misses 207system.l2c.UpgradeReq_misses::cpu0.data 5858 # number of UpgradeReq misses 208system.l2c.UpgradeReq_misses::cpu1.data 6485 # number of UpgradeReq misses 209system.l2c.UpgradeReq_misses::total 12343 # number of UpgradeReq misses 210system.l2c.SCUpgradeReq_misses::cpu0.data 694 # number of SCUpgradeReq misses 211system.l2c.SCUpgradeReq_misses::cpu1.data 773 # number of SCUpgradeReq misses 212system.l2c.SCUpgradeReq_misses::total 1467 # number of SCUpgradeReq misses 213system.l2c.ReadExReq_misses::cpu0.data 92836 # number of ReadExReq misses 214system.l2c.ReadExReq_misses::cpu1.data 44477 # number of ReadExReq misses 215system.l2c.ReadExReq_misses::total 137313 # number of ReadExReq misses 216system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 217system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 218system.l2c.demand_misses::cpu0.inst 6907 # number of demand (read+write) misses 219system.l2c.demand_misses::cpu0.data 102294 # number of demand (read+write) misses 220system.l2c.demand_misses::cpu1.inst 4159 # number of demand (read+write) misses 221system.l2c.demand_misses::cpu1.data 45955 # number of demand (read+write) misses 222system.l2c.demand_misses::total 159318 # number of demand (read+write) misses 223system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 224system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 225system.l2c.overall_misses::cpu0.inst 6907 # number of overall misses 226system.l2c.overall_misses::cpu0.data 102294 # number of overall misses 227system.l2c.overall_misses::cpu1.inst 4159 # number of overall misses 228system.l2c.overall_misses::cpu1.data 45955 # number of overall misses 229system.l2c.overall_misses::total 159318 # number of overall misses 230system.l2c.ReadReq_accesses::cpu0.dtb.walker 60 # number of ReadReq accesses(hits+misses) 231system.l2c.ReadReq_accesses::cpu0.itb.walker 34 # number of ReadReq accesses(hits+misses) 232system.l2c.ReadReq_accesses::cpu0.inst 19288 # number of ReadReq accesses(hits+misses) 233system.l2c.ReadReq_accesses::cpu0.data 47383 # number of ReadReq accesses(hits+misses) 234system.l2c.ReadReq_accesses::cpu1.dtb.walker 68 # number of ReadReq accesses(hits+misses) 235system.l2c.ReadReq_accesses::cpu1.itb.walker 43 # number of ReadReq accesses(hits+misses) 236system.l2c.ReadReq_accesses::cpu1.inst 22698 # number of ReadReq accesses(hits+misses) 237system.l2c.ReadReq_accesses::cpu1.data 13285 # number of ReadReq accesses(hits+misses) 238system.l2c.ReadReq_accesses::total 102859 # number of ReadReq accesses(hits+misses) 239system.l2c.Writeback_accesses::writebacks 175673 # number of Writeback accesses(hits+misses) 240system.l2c.Writeback_accesses::total 175673 # number of Writeback accesses(hits+misses) 241system.l2c.UpgradeReq_accesses::cpu0.data 6079 # number of UpgradeReq accesses(hits+misses) 242system.l2c.UpgradeReq_accesses::cpu1.data 6659 # number of UpgradeReq accesses(hits+misses) 243system.l2c.UpgradeReq_accesses::total 12738 # number of UpgradeReq accesses(hits+misses) 244system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses) 245system.l2c.SCUpgradeReq_accesses::cpu1.data 793 # number of SCUpgradeReq accesses(hits+misses) 246system.l2c.SCUpgradeReq_accesses::total 1507 # number of SCUpgradeReq accesses(hits+misses) 247system.l2c.ReadExReq_accesses::cpu0.data 100168 # number of ReadExReq accesses(hits+misses) 248system.l2c.ReadExReq_accesses::cpu1.data 50523 # number of ReadExReq accesses(hits+misses) 249system.l2c.ReadExReq_accesses::total 150691 # number of ReadExReq accesses(hits+misses) 250system.l2c.demand_accesses::cpu0.dtb.walker 60 # number of demand (read+write) accesses 251system.l2c.demand_accesses::cpu0.itb.walker 34 # number of demand (read+write) accesses 252system.l2c.demand_accesses::cpu0.inst 19288 # number of demand (read+write) accesses 253system.l2c.demand_accesses::cpu0.data 147551 # number of demand (read+write) accesses 254system.l2c.demand_accesses::cpu1.dtb.walker 68 # number of demand (read+write) accesses 255system.l2c.demand_accesses::cpu1.itb.walker 43 # number of demand (read+write) accesses 256system.l2c.demand_accesses::cpu1.inst 22698 # number of demand (read+write) accesses 257system.l2c.demand_accesses::cpu1.data 63808 # number of demand (read+write) accesses 258system.l2c.demand_accesses::total 253550 # number of demand (read+write) accesses 259system.l2c.overall_accesses::cpu0.dtb.walker 60 # number of overall (read+write) accesses 260system.l2c.overall_accesses::cpu0.itb.walker 34 # number of overall (read+write) accesses 261system.l2c.overall_accesses::cpu0.inst 19288 # number of overall (read+write) accesses 262system.l2c.overall_accesses::cpu0.data 147551 # number of overall (read+write) accesses 263system.l2c.overall_accesses::cpu1.dtb.walker 68 # number of overall (read+write) accesses 264system.l2c.overall_accesses::cpu1.itb.walker 43 # number of overall (read+write) accesses 265system.l2c.overall_accesses::cpu1.inst 22698 # number of overall (read+write) accesses 266system.l2c.overall_accesses::cpu1.data 63808 # number of overall (read+write) accesses 267system.l2c.overall_accesses::total 253550 # number of overall (read+write) accesses 268system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for ReadReq accesses 269system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.058824 # miss rate for ReadReq accesses 270system.l2c.ReadReq_miss_rate::cpu0.inst 0.358098 # miss rate for ReadReq accesses 271system.l2c.ReadReq_miss_rate::cpu0.data 0.199607 # miss rate for ReadReq accesses 272system.l2c.ReadReq_miss_rate::cpu1.inst 0.183232 # miss rate for ReadReq accesses 273system.l2c.ReadReq_miss_rate::cpu1.data 0.111253 # miss rate for ReadReq accesses 274system.l2c.ReadReq_miss_rate::total 0.213934 # miss rate for ReadReq accesses 275system.l2c.UpgradeReq_miss_rate::cpu0.data 0.963645 # miss rate for UpgradeReq accesses 276system.l2c.UpgradeReq_miss_rate::cpu1.data 0.973870 # miss rate for UpgradeReq accesses 277system.l2c.UpgradeReq_miss_rate::total 0.968990 # miss rate for UpgradeReq accesses 278system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.971989 # miss rate for SCUpgradeReq accesses 279system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974779 # miss rate for SCUpgradeReq accesses 280system.l2c.SCUpgradeReq_miss_rate::total 0.973457 # miss rate for SCUpgradeReq accesses 281system.l2c.ReadExReq_miss_rate::cpu0.data 0.926803 # miss rate for ReadExReq accesses 282system.l2c.ReadExReq_miss_rate::cpu1.data 0.880332 # miss rate for ReadExReq accesses 283system.l2c.ReadExReq_miss_rate::total 0.911222 # miss rate for ReadExReq accesses 284system.l2c.demand_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for demand accesses 285system.l2c.demand_miss_rate::cpu0.itb.walker 0.058824 # miss rate for demand accesses 286system.l2c.demand_miss_rate::cpu0.inst 0.358098 # miss rate for demand accesses 287system.l2c.demand_miss_rate::cpu0.data 0.693279 # miss rate for demand accesses 288system.l2c.demand_miss_rate::cpu1.inst 0.183232 # miss rate for demand accesses 289system.l2c.demand_miss_rate::cpu1.data 0.720207 # miss rate for demand accesses 290system.l2c.demand_miss_rate::total 0.628349 # miss rate for demand accesses 291system.l2c.overall_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for overall accesses 292system.l2c.overall_miss_rate::cpu0.itb.walker 0.058824 # miss rate for overall accesses 293system.l2c.overall_miss_rate::cpu0.inst 0.358098 # miss rate for overall accesses 294system.l2c.overall_miss_rate::cpu0.data 0.693279 # miss rate for overall accesses 295system.l2c.overall_miss_rate::cpu1.inst 0.183232 # miss rate for overall accesses 296system.l2c.overall_miss_rate::cpu1.data 0.720207 # miss rate for overall accesses 297system.l2c.overall_miss_rate::total 0.628349 # miss rate for overall accesses |
| 259system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 260system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 261system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 262system.l2c.blocked::no_targets 0 # number of cycles access was blocked 263system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 264system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 265system.l2c.fast_writes 0 # number of fast writes performed 266system.l2c.cache_copies 0 # number of cache copies performed | 298system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 299system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 300system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 301system.l2c.blocked::no_targets 0 # number of cycles access was blocked 302system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 303system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 304system.l2c.fast_writes 0 # number of fast writes performed 305system.l2c.cache_copies 0 # number of cache copies performed |
| 267system.l2c.writebacks::writebacks 65231 # number of writebacks 268system.l2c.writebacks::total 65231 # number of writebacks | 306system.l2c.writebacks::writebacks 52587 # number of writebacks 307system.l2c.writebacks::total 52587 # number of writebacks |
| 269system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 270system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 271system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 272system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 273system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 274system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 275system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 308system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 309system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 310system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 311system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 312system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 313system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 314system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 276system.toL2Bus.throughput 156214740 # Throughput (bytes/s) 277system.toL2Bus.data_through_bus 140726796 # Total data (bytes) 278system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 279system.iobus.throughput 46301771 # Throughput (bytes/s) 280system.iobus.data_through_bus 41711172 # Total data (bytes) | 315system.toL2Bus.trans_dist::ReadReq 1357667 # Transaction distribution 316system.toL2Bus.trans_dist::ReadResp 1357667 # Transaction distribution 317system.toL2Bus.trans_dist::WriteReq 767040 # Transaction distribution 318system.toL2Bus.trans_dist::WriteResp 767040 # Transaction distribution 319system.toL2Bus.trans_dist::Writeback 175673 # Transaction distribution 320system.toL2Bus.trans_dist::UpgradeReq 37136 # Transaction distribution 321system.toL2Bus.trans_dist::SCUpgradeReq 20079 # Transaction distribution 322system.toL2Bus.trans_dist::UpgradeResp 57215 # Transaction distribution 323system.toL2Bus.trans_dist::ReadExReq 177634 # Transaction distribution 324system.toL2Bus.trans_dist::ReadExResp 177634 # Transaction distribution 325system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2263595 # Packet count per connected master and slave (bytes) 326system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2631190 # Packet count per connected master and slave (bytes) 327system.toL2Bus.pkt_count::total 4894785 # Packet count per connected master and slave (bytes) 328system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 23563666 # Cumulative packet size per connected master and slave (bytes) 329system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15087382 # Cumulative packet size per connected master and slave (bytes) 330system.toL2Bus.pkt_size::total 38651048 # Cumulative packet size per connected master and slave (bytes) 331system.toL2Bus.snoops 0 # Total snoops (count) 332system.toL2Bus.snoop_fanout::samples 575784 # Request fanout histogram 333system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 334system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 335system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 336system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 337system.toL2Bus.snoop_fanout::1 575784 100.00% 100.00% # Request fanout histogram 338system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 339system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 340system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 341system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 342system.toL2Bus.snoop_fanout::total 575784 # Request fanout histogram 343system.iobus.trans_dist::ReadReq 6098452 # Transaction distribution 344system.iobus.trans_dist::ReadResp 6098452 # Transaction distribution 345system.iobus.trans_dist::WriteReq 7955 # Transaction distribution 346system.iobus.trans_dist::WriteResp 7955 # Transaction distribution 347system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30522 # Packet count per connected master and slave (bytes) 348system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7906 # Packet count per connected master and slave (bytes) 349system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 350system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 684 # Packet count per connected master and slave (bytes) 351system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 352system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 353system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 488 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 356system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 359system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 360system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 361system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 363system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 364system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 365system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 366system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 367system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 368system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 369system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 370system.iobus.pkt_count_system.bridge.master::total 2382414 # Packet count per connected master and slave (bytes) 371system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 9830400 # Packet count per connected master and slave (bytes) 372system.iobus.pkt_count_system.realview.clcd.dma::total 9830400 # Packet count per connected master and slave (bytes) 373system.iobus.pkt_count::total 12212814 # Packet count per connected master and slave (bytes) 374system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40294 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15812 # Cumulative packet size per connected master and slave (bytes) 376system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 377system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1368 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 379system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 380system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 268 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 382system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 383system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 384system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 385system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 386system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 387system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 388system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 389system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 390system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 391system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 392system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 393system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 394system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 395system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 396system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 397system.iobus.pkt_size_system.bridge.master::total 2389580 # Cumulative packet size per connected master and slave (bytes) 398system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 39321600 # Cumulative packet size per connected master and slave (bytes) 399system.iobus.pkt_size_system.realview.clcd.dma::total 39321600 # Cumulative packet size per connected master and slave (bytes) 400system.iobus.pkt_size::total 41711180 # Cumulative packet size per connected master and slave (bytes) |
| 281system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 282system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 283system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 284system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 285system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 286system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 287system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 288system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 296system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 297system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 298system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 299system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 300system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 301system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 302system.cpu0.dtb.inst_hits 0 # ITB inst hits 303system.cpu0.dtb.inst_misses 0 # ITB inst misses | 401system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 402system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 403system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 404system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 405system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 406system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 416system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 417system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 418system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 419system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 420system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 421system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 422system.cpu0.dtb.inst_hits 0 # ITB inst hits 423system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 304system.cpu0.dtb.read_hits 7391669 # DTB read hits 305system.cpu0.dtb.read_misses 1915 # DTB read misses 306system.cpu0.dtb.write_hits 6659638 # DTB write hits | 424system.cpu0.dtb.read_hits 7391828 # DTB read hits 425system.cpu0.dtb.read_misses 1916 # DTB read misses 426system.cpu0.dtb.write_hits 6659769 # DTB write hits |
| 307system.cpu0.dtb.write_misses 1130 # DTB write misses 308system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 309system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 310system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 311system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 312system.cpu0.dtb.flush_entries 1223 # Number of entries that have been flushed from TLB 313system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 314system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch 315system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 316system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions | 427system.cpu0.dtb.write_misses 1130 # DTB write misses 428system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 429system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 430system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 431system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 432system.cpu0.dtb.flush_entries 1223 # Number of entries that have been flushed from TLB 433system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 434system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch 435system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 436system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions |
| 317system.cpu0.dtb.read_accesses 7393584 # DTB read accesses 318system.cpu0.dtb.write_accesses 6660768 # DTB write accesses | 437system.cpu0.dtb.read_accesses 7393744 # DTB read accesses 438system.cpu0.dtb.write_accesses 6660899 # DTB write accesses |
| 319system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 439system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 320system.cpu0.dtb.hits 14051307 # DTB hits 321system.cpu0.dtb.misses 3045 # DTB misses 322system.cpu0.dtb.accesses 14054352 # DTB accesses | 440system.cpu0.dtb.hits 14051597 # DTB hits 441system.cpu0.dtb.misses 3046 # DTB misses 442system.cpu0.dtb.accesses 14054643 # DTB accesses |
| 323system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 324system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 325system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 326system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 327system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 328system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 329system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 330system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 336system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 337system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 338system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 339system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 340system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 341system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 342system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 343system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 443system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 444system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 445system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 446system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 447system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 448system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 449system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 450system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 456system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 457system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 458system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 459system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 460system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 461system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 462system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 463system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 344system.cpu0.itb.inst_hits 37936012 # ITB inst hits | 464system.cpu0.itb.inst_hits 37936653 # ITB inst hits |
| 345system.cpu0.itb.inst_misses 1207 # ITB inst misses 346system.cpu0.itb.read_hits 0 # DTB read hits 347system.cpu0.itb.read_misses 0 # DTB read misses 348system.cpu0.itb.write_hits 0 # DTB write hits 349system.cpu0.itb.write_misses 0 # DTB write misses 350system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 351system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 352system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 353system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 354system.cpu0.itb.flush_entries 848 # Number of entries that have been flushed from TLB 355system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 356system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 357system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 358system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 359system.cpu0.itb.read_accesses 0 # DTB read accesses 360system.cpu0.itb.write_accesses 0 # DTB write accesses | 465system.cpu0.itb.inst_misses 1207 # ITB inst misses 466system.cpu0.itb.read_hits 0 # DTB read hits 467system.cpu0.itb.read_misses 0 # DTB read misses 468system.cpu0.itb.write_hits 0 # DTB write hits 469system.cpu0.itb.write_misses 0 # DTB write misses 470system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 471system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 472system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 474system.cpu0.itb.flush_entries 848 # Number of entries that have been flushed from TLB 475system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 476system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 477system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 479system.cpu0.itb.read_accesses 0 # DTB read accesses 480system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 361system.cpu0.itb.inst_accesses 37937219 # ITB inst accesses 362system.cpu0.itb.hits 37936012 # DTB hits | 481system.cpu0.itb.inst_accesses 37937860 # ITB inst accesses 482system.cpu0.itb.hits 37936653 # DTB hits |
| 363system.cpu0.itb.misses 1207 # DTB misses | 483system.cpu0.itb.misses 1207 # DTB misses |
| 364system.cpu0.itb.accesses 37937219 # DTB accesses 365system.cpu0.numCycles 1801227301 # number of cpu cycles simulated | 484system.cpu0.itb.accesses 37937860 # DTB accesses 485system.cpu0.numCycles 1801220958 # number of cpu cycles simulated |
| 366system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 367system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 486system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 487system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 368system.cpu0.committedInsts 37698803 # Number of instructions committed 369system.cpu0.committedOps 44946380 # Number of ops (including micro ops) committed 370system.cpu0.num_int_alu_accesses 39863943 # Number of integer alu accesses | 488system.cpu0.committedInsts 37699441 # Number of instructions committed 489system.cpu0.committedOps 44947195 # Number of ops (including micro ops) committed 490system.cpu0.num_int_alu_accesses 39864660 # Number of integer alu accesses |
| 371system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses | 491system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses |
| 372system.cpu0.num_func_calls 1205467 # number of times a function call or return occured 373system.cpu0.num_conditional_control_insts 4697957 # number of instructions that are conditional controls 374system.cpu0.num_int_insts 39863943 # number of integer instructions | 492system.cpu0.num_func_calls 1205511 # number of times a function call or return occured 493system.cpu0.num_conditional_control_insts 4698026 # number of instructions that are conditional controls 494system.cpu0.num_int_insts 39864660 # number of integer instructions |
| 375system.cpu0.num_fp_insts 4171 # number of float instructions | 495system.cpu0.num_fp_insts 4171 # number of float instructions |
| 376system.cpu0.num_int_register_reads 70363299 # number of times the integer registers were read 377system.cpu0.num_int_register_writes 26108579 # number of times the integer registers were written | 496system.cpu0.num_int_register_reads 70364659 # number of times the integer registers were read 497system.cpu0.num_int_register_writes 26109079 # number of times the integer registers were written |
| 378system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read 379system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written | 498system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read 499system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written |
| 380system.cpu0.num_cc_register_reads 134797325 # number of times the CC registers were read 381system.cpu0.num_cc_register_writes 18388517 # number of times the CC registers were written 382system.cpu0.num_mem_refs 14597479 # number of memory refs 383system.cpu0.num_load_insts 7571296 # Number of load instructions 384system.cpu0.num_store_insts 7026183 # Number of store instructions 385system.cpu0.num_idle_cycles 1756006001.161348 # Number of idle cycles 386system.cpu0.num_busy_cycles 45221299.838652 # Number of busy cycles 387system.cpu0.not_idle_fraction 0.025106 # Percentage of non-idle cycles 388system.cpu0.idle_fraction 0.974894 # Percentage of idle cycles 389system.cpu0.Branches 6054325 # Number of branches fetched | 500system.cpu0.num_cc_register_reads 134799783 # number of times the CC registers were read 501system.cpu0.num_cc_register_writes 18388749 # number of times the CC registers were written 502system.cpu0.num_mem_refs 14597797 # number of memory refs 503system.cpu0.num_load_insts 7571468 # Number of load instructions 504system.cpu0.num_store_insts 7026329 # Number of store instructions 505system.cpu0.num_idle_cycles 1756040520.255098 # Number of idle cycles 506system.cpu0.num_busy_cycles 45180437.744902 # Number of busy cycles 507system.cpu0.not_idle_fraction 0.025083 # Percentage of non-idle cycles 508system.cpu0.idle_fraction 0.974917 # Percentage of idle cycles 509system.cpu0.Branches 6054439 # Number of branches fetched |
| 390system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction | 510system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction |
| 391system.cpu0.op_class::IntAlu 30338974 67.42% 67.45% # Class of executed instruction | 511system.cpu0.op_class::IntAlu 30339474 67.42% 67.45% # Class of executed instruction |
| 392system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction 393system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction 394system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction 395system.cpu0.op_class::FloatCmp 0 0.00% 67.56% # Class of executed instruction 396system.cpu0.op_class::FloatCvt 0 0.00% 67.56% # Class of executed instruction 397system.cpu0.op_class::FloatMult 0 0.00% 67.56% # Class of executed instruction 398system.cpu0.op_class::FloatDiv 0 0.00% 67.56% # Class of executed instruction 399system.cpu0.op_class::FloatSqrt 0 0.00% 67.56% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 412system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.56% # Class of executed instruction 413system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.56% # Class of executed instruction 414system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.56% # Class of executed instruction 415system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.56% # Class of executed instruction 416system.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Class of executed instruction 417system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction 418system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction 419system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction | 512system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction 513system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction 514system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction 515system.cpu0.op_class::FloatCmp 0 0.00% 67.56% # Class of executed instruction 516system.cpu0.op_class::FloatCvt 0 0.00% 67.56% # Class of executed instruction 517system.cpu0.op_class::FloatMult 0 0.00% 67.56% # Class of executed instruction 518system.cpu0.op_class::FloatDiv 0 0.00% 67.56% # Class of executed instruction 519system.cpu0.op_class::FloatSqrt 0 0.00% 67.56% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 532system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.56% # Class of executed instruction 533system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.56% # Class of executed instruction 534system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.56% # Class of executed instruction 535system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.56% # Class of executed instruction 536system.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Class of executed instruction 537system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction 538system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction 539system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction |
| 420system.cpu0.op_class::MemRead 7571296 16.82% 84.39% # Class of executed instruction 421system.cpu0.op_class::MemWrite 7026183 15.61% 100.00% # Class of executed instruction | 540system.cpu0.op_class::MemRead 7571468 16.82% 84.39% # Class of executed instruction 541system.cpu0.op_class::MemWrite 7026329 15.61% 100.00% # Class of executed instruction |
| 422system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 423system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 542system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 543system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 424system.cpu0.op_class::total 45002137 # Class of executed instruction | 544system.cpu0.op_class::total 45002955 # Class of executed instruction |
| 425system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 545system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 426system.cpu0.kern.inst.quiesce 42773 # number of quiesce instructions executed 427system.cpu0.icache.tags.replacements 419775 # number of replacements 428system.cpu0.icache.tags.tagsinuse 511.035896 # Cycle average of tags in use 429system.cpu0.icache.tags.total_refs 37516680 # Total number of references to valid blocks. 430system.cpu0.icache.tags.sampled_refs 420287 # Sample count of references to valid blocks. 431system.cpu0.icache.tags.avg_refs 89.264431 # Average number of references to valid blocks. 432system.cpu0.icache.tags.warmup_cycle 64363581500 # Cycle when the warmup percentage was hit. 433system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.035896 # Average occupied blocks per requestor 434system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998117 # Average percentage of cache occupancy 435system.cpu0.icache.tags.occ_percent::total 0.998117 # Average percentage of cache occupancy | 546system.cpu0.kern.inst.quiesce 42789 # number of quiesce instructions executed 547system.cpu0.icache.tags.replacements 346148 # number of replacements 548system.cpu0.icache.tags.tagsinuse 511.428315 # Cycle average of tags in use 549system.cpu0.icache.tags.total_refs 37590948 # Total number of references to valid blocks. 550system.cpu0.icache.tags.sampled_refs 346660 # Sample count of references to valid blocks. 551system.cpu0.icache.tags.avg_refs 108.437512 # Average number of references to valid blocks. 552system.cpu0.icache.tags.warmup_cycle 4521683000 # Cycle when the warmup percentage was hit. 553system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.428315 # Average occupied blocks per requestor 554system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998883 # Average percentage of cache occupancy 555system.cpu0.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy |
| 436system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 556system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 437system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id 438system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id | 557system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id |
| 439system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 558system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 440system.cpu0.icache.tags.tag_accesses 38357256 # Number of tag accesses 441system.cpu0.icache.tags.data_accesses 38357256 # Number of data accesses 442system.cpu0.icache.ReadReq_hits::cpu0.inst 37516680 # number of ReadReq hits 443system.cpu0.icache.ReadReq_hits::total 37516680 # number of ReadReq hits 444system.cpu0.icache.demand_hits::cpu0.inst 37516680 # number of demand (read+write) hits 445system.cpu0.icache.demand_hits::total 37516680 # number of demand (read+write) hits 446system.cpu0.icache.overall_hits::cpu0.inst 37516680 # number of overall hits 447system.cpu0.icache.overall_hits::total 37516680 # number of overall hits 448system.cpu0.icache.ReadReq_misses::cpu0.inst 420288 # number of ReadReq misses 449system.cpu0.icache.ReadReq_misses::total 420288 # number of ReadReq misses 450system.cpu0.icache.demand_misses::cpu0.inst 420288 # number of demand (read+write) misses 451system.cpu0.icache.demand_misses::total 420288 # number of demand (read+write) misses 452system.cpu0.icache.overall_misses::cpu0.inst 420288 # number of overall misses 453system.cpu0.icache.overall_misses::total 420288 # number of overall misses 454system.cpu0.icache.ReadReq_accesses::cpu0.inst 37936968 # number of ReadReq accesses(hits+misses) 455system.cpu0.icache.ReadReq_accesses::total 37936968 # number of ReadReq accesses(hits+misses) 456system.cpu0.icache.demand_accesses::cpu0.inst 37936968 # number of demand (read+write) accesses 457system.cpu0.icache.demand_accesses::total 37936968 # number of demand (read+write) accesses 458system.cpu0.icache.overall_accesses::cpu0.inst 37936968 # number of overall (read+write) accesses 459system.cpu0.icache.overall_accesses::total 37936968 # number of overall (read+write) accesses 460system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011079 # miss rate for ReadReq accesses 461system.cpu0.icache.ReadReq_miss_rate::total 0.011079 # miss rate for ReadReq accesses 462system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011079 # miss rate for demand accesses 463system.cpu0.icache.demand_miss_rate::total 0.011079 # miss rate for demand accesses 464system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011079 # miss rate for overall accesses 465system.cpu0.icache.overall_miss_rate::total 0.011079 # miss rate for overall accesses | 559system.cpu0.icache.tags.tag_accesses 76221879 # Number of tag accesses 560system.cpu0.icache.tags.data_accesses 76221879 # Number of data accesses 561system.cpu0.icache.ReadReq_hits::cpu0.inst 37590948 # number of ReadReq hits 562system.cpu0.icache.ReadReq_hits::total 37590948 # number of ReadReq hits 563system.cpu0.icache.demand_hits::cpu0.inst 37590948 # number of demand (read+write) hits 564system.cpu0.icache.demand_hits::total 37590948 # number of demand (read+write) hits 565system.cpu0.icache.overall_hits::cpu0.inst 37590948 # number of overall hits 566system.cpu0.icache.overall_hits::total 37590948 # number of overall hits 567system.cpu0.icache.ReadReq_misses::cpu0.inst 346661 # number of ReadReq misses 568system.cpu0.icache.ReadReq_misses::total 346661 # number of ReadReq misses 569system.cpu0.icache.demand_misses::cpu0.inst 346661 # number of demand (read+write) misses 570system.cpu0.icache.demand_misses::total 346661 # number of demand (read+write) misses 571system.cpu0.icache.overall_misses::cpu0.inst 346661 # number of overall misses 572system.cpu0.icache.overall_misses::total 346661 # number of overall misses 573system.cpu0.icache.ReadReq_accesses::cpu0.inst 37937609 # number of ReadReq accesses(hits+misses) 574system.cpu0.icache.ReadReq_accesses::total 37937609 # number of ReadReq accesses(hits+misses) 575system.cpu0.icache.demand_accesses::cpu0.inst 37937609 # number of demand (read+write) accesses 576system.cpu0.icache.demand_accesses::total 37937609 # number of demand (read+write) accesses 577system.cpu0.icache.overall_accesses::cpu0.inst 37937609 # number of overall (read+write) accesses 578system.cpu0.icache.overall_accesses::total 37937609 # number of overall (read+write) accesses 579system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009138 # miss rate for ReadReq accesses 580system.cpu0.icache.ReadReq_miss_rate::total 0.009138 # miss rate for ReadReq accesses 581system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009138 # miss rate for demand accesses 582system.cpu0.icache.demand_miss_rate::total 0.009138 # miss rate for demand accesses 583system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009138 # miss rate for overall accesses 584system.cpu0.icache.overall_miss_rate::total 0.009138 # miss rate for overall accesses |
| 466system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 467system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 468system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 469system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 470system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 471system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 472system.cpu0.icache.fast_writes 0 # number of fast writes performed 473system.cpu0.icache.cache_copies 0 # number of cache copies performed 474system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 585system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 586system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 587system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 588system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 589system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 590system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 591system.cpu0.icache.fast_writes 0 # number of fast writes performed 592system.cpu0.icache.cache_copies 0 # number of cache copies performed 593system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 475system.cpu0.dcache.tags.replacements 348431 # number of replacements 476system.cpu0.dcache.tags.tagsinuse 471.119339 # Cycle average of tags in use 477system.cpu0.dcache.tags.total_refs 12834011 # Total number of references to valid blocks. 478system.cpu0.dcache.tags.sampled_refs 348738 # Sample count of references to valid blocks. 479system.cpu0.dcache.tags.avg_refs 36.801298 # Average number of references to valid blocks. | 594system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 595system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 596system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 597system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 598system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 599system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 600system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 601system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 602system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 603system.cpu0.l2cache.tags.replacements 133971 # number of replacements 604system.cpu0.l2cache.tags.tagsinuse 15179.385733 # Cycle average of tags in use 605system.cpu0.l2cache.tags.total_refs 737408 # Total number of references to valid blocks. 606system.cpu0.l2cache.tags.sampled_refs 149269 # Sample count of references to valid blocks. 607system.cpu0.l2cache.tags.avg_refs 4.940128 # Average number of references to valid blocks. 608system.cpu0.l2cache.tags.warmup_cycle 992860000 # Cycle when the warmup percentage was hit. 609system.cpu0.l2cache.tags.occ_blocks::writebacks 7074.912262 # Average occupied blocks per requestor 610system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 8.111336 # Average occupied blocks per requestor 611system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.268775 # Average occupied blocks per requestor 612system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3357.655544 # Average occupied blocks per requestor 613system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4738.437815 # Average occupied blocks per requestor 614system.cpu0.l2cache.tags.occ_percent::writebacks 0.431818 # Average percentage of cache occupancy 615system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000495 # Average percentage of cache occupancy 616system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy 617system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.204935 # Average percentage of cache occupancy 618system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.289211 # Average percentage of cache occupancy 619system.cpu0.l2cache.tags.occ_percent::total 0.926476 # Average percentage of cache occupancy 620system.cpu0.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id 621system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15278 # Occupied blocks per task id 622system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 623system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id 624system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 625system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3216 # Occupied blocks per task id 626system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5292 # Occupied blocks per task id 627system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 6770 # Occupied blocks per task id 628system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id 629system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.932495 # Percentage of cache occupancy per task id 630system.cpu0.l2cache.tags.tag_accesses 17962499 # Number of tag accesses 631system.cpu0.l2cache.tags.data_accesses 17962499 # Number of data accesses 632system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4364 # number of ReadReq hits 633system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 1619 # number of ReadReq hits 634system.cpu0.l2cache.ReadReq_hits::cpu0.inst 326789 # number of ReadReq hits 635system.cpu0.l2cache.ReadReq_hits::cpu0.data 179454 # number of ReadReq hits 636system.cpu0.l2cache.ReadReq_hits::total 512226 # number of ReadReq hits 637system.cpu0.l2cache.Writeback_hits::writebacks 323282 # number of Writeback hits 638system.cpu0.l2cache.Writeback_hits::total 323282 # number of Writeback hits 639system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits 640system.cpu0.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits 641system.cpu0.l2cache.ReadExReq_hits::cpu0.data 38112 # number of ReadExReq hits 642system.cpu0.l2cache.ReadExReq_hits::total 38112 # number of ReadExReq hits 643system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4364 # number of demand (read+write) hits 644system.cpu0.l2cache.demand_hits::cpu0.itb.walker 1619 # number of demand (read+write) hits 645system.cpu0.l2cache.demand_hits::cpu0.inst 326789 # number of demand (read+write) hits 646system.cpu0.l2cache.demand_hits::cpu0.data 217566 # number of demand (read+write) hits 647system.cpu0.l2cache.demand_hits::total 550338 # number of demand (read+write) hits 648system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4364 # number of overall hits 649system.cpu0.l2cache.overall_hits::cpu0.itb.walker 1619 # number of overall hits 650system.cpu0.l2cache.overall_hits::cpu0.inst 326789 # number of overall hits 651system.cpu0.l2cache.overall_hits::cpu0.data 217566 # number of overall hits 652system.cpu0.l2cache.overall_hits::total 550338 # number of overall hits 653system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 89 # number of ReadReq misses 654system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 56 # number of ReadReq misses 655system.cpu0.l2cache.ReadReq_misses::cpu0.inst 19767 # number of ReadReq misses 656system.cpu0.l2cache.ReadReq_misses::cpu0.data 70654 # number of ReadReq misses 657system.cpu0.l2cache.ReadReq_misses::total 90566 # number of ReadReq misses 658system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 12767 # number of UpgradeReq misses 659system.cpu0.l2cache.UpgradeReq_misses::total 12767 # number of UpgradeReq misses 660system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 8852 # number of SCUpgradeReq misses 661system.cpu0.l2cache.SCUpgradeReq_misses::total 8852 # number of SCUpgradeReq misses 662system.cpu0.l2cache.ReadExReq_misses::cpu0.data 114761 # number of ReadExReq misses 663system.cpu0.l2cache.ReadExReq_misses::total 114761 # number of ReadExReq misses 664system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 89 # number of demand (read+write) misses 665system.cpu0.l2cache.demand_misses::cpu0.itb.walker 56 # number of demand (read+write) misses 666system.cpu0.l2cache.demand_misses::cpu0.inst 19767 # number of demand (read+write) misses 667system.cpu0.l2cache.demand_misses::cpu0.data 185415 # number of demand (read+write) misses 668system.cpu0.l2cache.demand_misses::total 205327 # number of demand (read+write) misses 669system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 89 # number of overall misses 670system.cpu0.l2cache.overall_misses::cpu0.itb.walker 56 # number of overall misses 671system.cpu0.l2cache.overall_misses::cpu0.inst 19767 # number of overall misses 672system.cpu0.l2cache.overall_misses::cpu0.data 185415 # number of overall misses 673system.cpu0.l2cache.overall_misses::total 205327 # number of overall misses 674system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 4453 # number of ReadReq accesses(hits+misses) 675system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 1675 # number of ReadReq accesses(hits+misses) 676system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 346556 # number of ReadReq accesses(hits+misses) 677system.cpu0.l2cache.ReadReq_accesses::cpu0.data 250108 # number of ReadReq accesses(hits+misses) 678system.cpu0.l2cache.ReadReq_accesses::total 602792 # number of ReadReq accesses(hits+misses) 679system.cpu0.l2cache.Writeback_accesses::writebacks 323282 # number of Writeback accesses(hits+misses) 680system.cpu0.l2cache.Writeback_accesses::total 323282 # number of Writeback accesses(hits+misses) 681system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 12769 # number of UpgradeReq accesses(hits+misses) 682system.cpu0.l2cache.UpgradeReq_accesses::total 12769 # number of UpgradeReq accesses(hits+misses) 683system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 8852 # number of SCUpgradeReq accesses(hits+misses) 684system.cpu0.l2cache.SCUpgradeReq_accesses::total 8852 # number of SCUpgradeReq accesses(hits+misses) 685system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 152873 # number of ReadExReq accesses(hits+misses) 686system.cpu0.l2cache.ReadExReq_accesses::total 152873 # number of ReadExReq accesses(hits+misses) 687system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 4453 # number of demand (read+write) accesses 688system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 1675 # number of demand (read+write) accesses 689system.cpu0.l2cache.demand_accesses::cpu0.inst 346556 # number of demand (read+write) accesses 690system.cpu0.l2cache.demand_accesses::cpu0.data 402981 # number of demand (read+write) accesses 691system.cpu0.l2cache.demand_accesses::total 755665 # number of demand (read+write) accesses 692system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 4453 # number of overall (read+write) accesses 693system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 1675 # number of overall (read+write) accesses 694system.cpu0.l2cache.overall_accesses::cpu0.inst 346556 # number of overall (read+write) accesses 695system.cpu0.l2cache.overall_accesses::cpu0.data 402981 # number of overall (read+write) accesses 696system.cpu0.l2cache.overall_accesses::total 755665 # number of overall (read+write) accesses 697system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for ReadReq accesses 698system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.033433 # miss rate for ReadReq accesses 699system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.057038 # miss rate for ReadReq accesses 700system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.282494 # miss rate for ReadReq accesses 701system.cpu0.l2cache.ReadReq_miss_rate::total 0.150244 # miss rate for ReadReq accesses 702system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999843 # miss rate for UpgradeReq accesses 703system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999843 # miss rate for UpgradeReq accesses 704system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 705system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 706system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.750695 # miss rate for ReadExReq accesses 707system.cpu0.l2cache.ReadExReq_miss_rate::total 0.750695 # miss rate for ReadExReq accesses 708system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for demand accesses 709system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.033433 # miss rate for demand accesses 710system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.057038 # miss rate for demand accesses 711system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.460109 # miss rate for demand accesses 712system.cpu0.l2cache.demand_miss_rate::total 0.271717 # miss rate for demand accesses 713system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for overall accesses 714system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.033433 # miss rate for overall accesses 715system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.057038 # miss rate for overall accesses 716system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.460109 # miss rate for overall accesses 717system.cpu0.l2cache.overall_miss_rate::total 0.271717 # miss rate for overall accesses 718system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 719system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 721system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 723system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 725system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 726system.cpu0.l2cache.writebacks::writebacks 114351 # number of writebacks 727system.cpu0.l2cache.writebacks::total 114351 # number of writebacks 728system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 729system.cpu0.dcache.tags.replacements 371621 # number of replacements 730system.cpu0.dcache.tags.tagsinuse 458.751149 # Cycle average of tags in use 731system.cpu0.dcache.tags.total_refs 12812322 # Total number of references to valid blocks. 732system.cpu0.dcache.tags.sampled_refs 371931 # Sample count of references to valid blocks. 733system.cpu0.dcache.tags.avg_refs 34.448115 # Average number of references to valid blocks. |
| 480system.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit. | 734system.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit. |
| 481system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.119339 # Average occupied blocks per requestor 482system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920155 # Average percentage of cache occupancy 483system.cpu0.dcache.tags.occ_percent::total 0.920155 # Average percentage of cache occupancy 484system.cpu0.dcache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 485system.cpu0.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id 486system.cpu0.dcache.tags.occ_task_id_percent::1024 0.599609 # Percentage of cache occupancy per task id 487system.cpu0.dcache.tags.tag_accesses 53249455 # Number of tag accesses 488system.cpu0.dcache.tags.data_accesses 53249455 # Number of data accesses 489system.cpu0.dcache.ReadReq_hits::cpu0.data 6868875 # number of ReadReq hits 490system.cpu0.dcache.ReadReq_hits::total 6868875 # number of ReadReq hits 491system.cpu0.dcache.WriteReq_hits::cpu0.data 5598061 # number of WriteReq hits 492system.cpu0.dcache.WriteReq_hits::total 5598061 # number of WriteReq hits 493system.cpu0.dcache.SoftPFReq_hits::cpu0.data 78744 # number of SoftPFReq hits 494system.cpu0.dcache.SoftPFReq_hits::total 78744 # number of SoftPFReq hits 495system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135195 # number of LoadLockedReq hits 496system.cpu0.dcache.LoadLockedReq_hits::total 135195 # number of LoadLockedReq hits 497system.cpu0.dcache.StoreCondReq_hits::cpu0.data 136387 # number of StoreCondReq hits 498system.cpu0.dcache.StoreCondReq_hits::total 136387 # number of StoreCondReq hits 499system.cpu0.dcache.demand_hits::cpu0.data 12466936 # number of demand (read+write) hits 500system.cpu0.dcache.demand_hits::total 12466936 # number of demand (read+write) hits 501system.cpu0.dcache.overall_hits::cpu0.data 12545680 # number of overall hits 502system.cpu0.dcache.overall_hits::total 12545680 # number of overall hits 503system.cpu0.dcache.ReadReq_misses::cpu0.data 173318 # number of ReadReq misses 504system.cpu0.dcache.ReadReq_misses::total 173318 # number of ReadReq misses 505system.cpu0.dcache.WriteReq_misses::cpu0.data 159147 # number of WriteReq misses 506system.cpu0.dcache.WriteReq_misses::total 159147 # number of WriteReq misses 507system.cpu0.dcache.SoftPFReq_misses::cpu0.data 50343 # number of SoftPFReq misses 508system.cpu0.dcache.SoftPFReq_misses::total 50343 # number of SoftPFReq misses 509system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9388 # number of LoadLockedReq misses 510system.cpu0.dcache.LoadLockedReq_misses::total 9388 # number of LoadLockedReq misses 511system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7646 # number of StoreCondReq misses 512system.cpu0.dcache.StoreCondReq_misses::total 7646 # number of StoreCondReq misses 513system.cpu0.dcache.demand_misses::cpu0.data 332465 # number of demand (read+write) misses 514system.cpu0.dcache.demand_misses::total 332465 # number of demand (read+write) misses 515system.cpu0.dcache.overall_misses::cpu0.data 382808 # number of overall misses 516system.cpu0.dcache.overall_misses::total 382808 # number of overall misses 517system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042193 # number of ReadReq accesses(hits+misses) 518system.cpu0.dcache.ReadReq_accesses::total 7042193 # number of ReadReq accesses(hits+misses) 519system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757208 # number of WriteReq accesses(hits+misses) 520system.cpu0.dcache.WriteReq_accesses::total 5757208 # number of WriteReq accesses(hits+misses) | 735system.cpu0.dcache.tags.occ_blocks::cpu0.data 458.751149 # Average occupied blocks per requestor 736system.cpu0.dcache.tags.occ_percent::cpu0.data 0.895998 # Average percentage of cache occupancy 737system.cpu0.dcache.tags.occ_percent::total 0.895998 # Average percentage of cache occupancy 738system.cpu0.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id 739system.cpu0.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 740system.cpu0.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id 741system.cpu0.dcache.tags.tag_accesses 26837769 # Number of tag accesses 742system.cpu0.dcache.tags.data_accesses 26837769 # Number of data accesses 743system.cpu0.dcache.ReadReq_hits::cpu0.data 6854480 # number of ReadReq hits 744system.cpu0.dcache.ReadReq_hits::total 6854480 # number of ReadReq hits 745system.cpu0.dcache.WriteReq_hits::cpu0.data 5591690 # number of WriteReq hits 746system.cpu0.dcache.WriteReq_hits::total 5591690 # number of WriteReq hits 747system.cpu0.dcache.SoftPFReq_hits::cpu0.data 77211 # number of SoftPFReq hits 748system.cpu0.dcache.SoftPFReq_hits::total 77211 # number of SoftPFReq hits 749system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 134223 # number of LoadLockedReq hits 750system.cpu0.dcache.LoadLockedReq_hits::total 134223 # number of LoadLockedReq hits 751system.cpu0.dcache.StoreCondReq_hits::cpu0.data 135188 # number of StoreCondReq hits 752system.cpu0.dcache.StoreCondReq_hits::total 135188 # number of StoreCondReq hits 753system.cpu0.dcache.demand_hits::cpu0.data 12446170 # number of demand (read+write) hits 754system.cpu0.dcache.demand_hits::total 12446170 # number of demand (read+write) hits 755system.cpu0.dcache.overall_hits::cpu0.data 12523381 # number of overall hits 756system.cpu0.dcache.overall_hits::total 12523381 # number of overall hits 757system.cpu0.dcache.ReadReq_misses::cpu0.data 187851 # number of ReadReq misses 758system.cpu0.dcache.ReadReq_misses::total 187851 # number of ReadReq misses 759system.cpu0.dcache.WriteReq_misses::cpu0.data 165642 # number of WriteReq misses 760system.cpu0.dcache.WriteReq_misses::total 165642 # number of WriteReq misses 761system.cpu0.dcache.SoftPFReq_misses::cpu0.data 51876 # number of SoftPFReq misses 762system.cpu0.dcache.SoftPFReq_misses::total 51876 # number of SoftPFReq misses 763system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10381 # number of LoadLockedReq misses 764system.cpu0.dcache.LoadLockedReq_misses::total 10381 # number of LoadLockedReq misses 765system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8852 # number of StoreCondReq misses 766system.cpu0.dcache.StoreCondReq_misses::total 8852 # number of StoreCondReq misses 767system.cpu0.dcache.demand_misses::cpu0.data 353493 # number of demand (read+write) misses 768system.cpu0.dcache.demand_misses::total 353493 # number of demand (read+write) misses 769system.cpu0.dcache.overall_misses::cpu0.data 405369 # number of overall misses 770system.cpu0.dcache.overall_misses::total 405369 # number of overall misses 771system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042331 # number of ReadReq accesses(hits+misses) 772system.cpu0.dcache.ReadReq_accesses::total 7042331 # number of ReadReq accesses(hits+misses) 773system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757332 # number of WriteReq accesses(hits+misses) 774system.cpu0.dcache.WriteReq_accesses::total 5757332 # number of WriteReq accesses(hits+misses) |
| 521system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) 522system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) | 775system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) 776system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) |
| 523system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144583 # number of LoadLockedReq accesses(hits+misses) 524system.cpu0.dcache.LoadLockedReq_accesses::total 144583 # number of LoadLockedReq accesses(hits+misses) 525system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144033 # number of StoreCondReq accesses(hits+misses) 526system.cpu0.dcache.StoreCondReq_accesses::total 144033 # number of StoreCondReq accesses(hits+misses) 527system.cpu0.dcache.demand_accesses::cpu0.data 12799401 # number of demand (read+write) accesses 528system.cpu0.dcache.demand_accesses::total 12799401 # number of demand (read+write) accesses 529system.cpu0.dcache.overall_accesses::cpu0.data 12928488 # number of overall (read+write) accesses 530system.cpu0.dcache.overall_accesses::total 12928488 # number of overall (read+write) accesses 531system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.024611 # miss rate for ReadReq accesses 532system.cpu0.dcache.ReadReq_miss_rate::total 0.024611 # miss rate for ReadReq accesses 533system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027643 # miss rate for WriteReq accesses 534system.cpu0.dcache.WriteReq_miss_rate::total 0.027643 # miss rate for WriteReq accesses 535system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389993 # miss rate for SoftPFReq accesses 536system.cpu0.dcache.SoftPFReq_miss_rate::total 0.389993 # miss rate for SoftPFReq accesses 537system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064932 # miss rate for LoadLockedReq accesses 538system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064932 # miss rate for LoadLockedReq accesses 539system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053085 # miss rate for StoreCondReq accesses 540system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053085 # miss rate for StoreCondReq accesses 541system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025975 # miss rate for demand accesses 542system.cpu0.dcache.demand_miss_rate::total 0.025975 # miss rate for demand accesses 543system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029610 # miss rate for overall accesses 544system.cpu0.dcache.overall_miss_rate::total 0.029610 # miss rate for overall accesses | 777system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144604 # number of LoadLockedReq accesses(hits+misses) 778system.cpu0.dcache.LoadLockedReq_accesses::total 144604 # number of LoadLockedReq accesses(hits+misses) 779system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144040 # number of StoreCondReq accesses(hits+misses) 780system.cpu0.dcache.StoreCondReq_accesses::total 144040 # number of StoreCondReq accesses(hits+misses) 781system.cpu0.dcache.demand_accesses::cpu0.data 12799663 # number of demand (read+write) accesses 782system.cpu0.dcache.demand_accesses::total 12799663 # number of demand (read+write) accesses 783system.cpu0.dcache.overall_accesses::cpu0.data 12928750 # number of overall (read+write) accesses 784system.cpu0.dcache.overall_accesses::total 12928750 # number of overall (read+write) accesses 785system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026675 # miss rate for ReadReq accesses 786system.cpu0.dcache.ReadReq_miss_rate::total 0.026675 # miss rate for ReadReq accesses 787system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028771 # miss rate for WriteReq accesses 788system.cpu0.dcache.WriteReq_miss_rate::total 0.028771 # miss rate for WriteReq accesses 789system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.401869 # miss rate for SoftPFReq accesses 790system.cpu0.dcache.SoftPFReq_miss_rate::total 0.401869 # miss rate for SoftPFReq accesses 791system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.071789 # miss rate for LoadLockedReq accesses 792system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.071789 # miss rate for LoadLockedReq accesses 793system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061455 # miss rate for StoreCondReq accesses 794system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061455 # miss rate for StoreCondReq accesses 795system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027617 # miss rate for demand accesses 796system.cpu0.dcache.demand_miss_rate::total 0.027617 # miss rate for demand accesses 797system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031354 # miss rate for overall accesses 798system.cpu0.dcache.overall_miss_rate::total 0.031354 # miss rate for overall accesses |
| 545system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 546system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 549system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 550system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 551system.cpu0.dcache.fast_writes 0 # number of fast writes performed 552system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 799system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 800system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 801system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 802system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 803system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 804system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 805system.cpu0.dcache.fast_writes 0 # number of fast writes performed 806system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 553system.cpu0.dcache.writebacks::writebacks 321785 # number of writebacks 554system.cpu0.dcache.writebacks::total 321785 # number of writebacks | 807system.cpu0.dcache.writebacks::writebacks 323282 # number of writebacks 808system.cpu0.dcache.writebacks::total 323282 # number of writebacks |
| 555system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 809system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 810system.cpu0.toL2Bus.trans_dist::ReadReq 689270 # Transaction distribution 811system.cpu0.toL2Bus.trans_dist::ReadResp 689270 # Transaction distribution 812system.cpu0.toL2Bus.trans_dist::WriteReq 763494 # Transaction distribution 813system.cpu0.toL2Bus.trans_dist::WriteResp 763494 # Transaction distribution 814system.cpu0.toL2Bus.trans_dist::Writeback 323282 # Transaction distribution 815system.cpu0.toL2Bus.trans_dist::UpgradeReq 12769 # Transaction distribution 816system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 8852 # Transaction distribution 817system.cpu0.toL2Bus.trans_dist::UpgradeResp 21621 # Transaction distribution 818system.cpu0.toL2Bus.trans_dist::ReadExReq 152873 # Transaction distribution 819system.cpu0.toL2Bus.trans_dist::ReadExResp 152873 # Transaction distribution 820system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 706618 # Packet count per connected master and slave (bytes) 821system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2854542 # Packet count per connected master and slave (bytes) 822system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 4790 # Packet count per connected master and slave (bytes) 823system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 11848 # Packet count per connected master and slave (bytes) 824system.cpu0.toL2Bus.pkt_count::total 3577798 # Packet count per connected master and slave (bytes) 825system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 22212896 # Cumulative packet size per connected master and slave (bytes) 826system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 49695730 # Cumulative packet size per connected master and slave (bytes) 827system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9580 # Cumulative packet size per connected master and slave (bytes) 828system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23696 # Cumulative packet size per connected master and slave (bytes) 829system.cpu0.toL2Bus.pkt_size::total 71941902 # Cumulative packet size per connected master and slave (bytes) 830system.cpu0.toL2Bus.snoops 229047 # Total snoops (count) 831system.cpu0.toL2Bus.snoop_fanout::samples 1276029 # Request fanout histogram 832system.cpu0.toL2Bus.snoop_fanout::mean 5.135706 # Request fanout histogram 833system.cpu0.toL2Bus.snoop_fanout::stdev 0.342476 # Request fanout histogram 834system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 835system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 836system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 837system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 838system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 839system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 840system.cpu0.toL2Bus.snoop_fanout::5 1102864 86.43% 86.43% # Request fanout histogram 841system.cpu0.toL2Bus.snoop_fanout::6 173165 13.57% 100.00% # Request fanout histogram 842system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 843system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 844system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 845system.cpu0.toL2Bus.snoop_fanout::total 1276029 # Request fanout histogram |
|
| 556system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 557system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 558system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 559system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 560system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 561system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 562system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 563system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 571system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 572system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 573system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 574system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 575system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 576system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 577system.cpu1.dtb.inst_hits 0 # ITB inst hits 578system.cpu1.dtb.inst_misses 0 # ITB inst misses | 846system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 847system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 848system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 849system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 850system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 851system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 852system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 853system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 7 unchanged lines hidden (view full) --- 861system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 862system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 863system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 864system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 865system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 866system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 867system.cpu1.dtb.inst_hits 0 # ITB inst hits 868system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 579system.cpu1.dtb.read_hits 6028686 # DTB read hits 580system.cpu1.dtb.read_misses 5403 # DTB read misses 581system.cpu1.dtb.write_hits 4781604 # DTB write hits | 869system.cpu1.dtb.read_hits 6029083 # DTB read hits 870system.cpu1.dtb.read_misses 5405 # DTB read misses 871system.cpu1.dtb.write_hits 4781968 # DTB write hits |
| 582system.cpu1.dtb.write_misses 1104 # DTB write misses 583system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 584system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 585system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 586system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 587system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB 588system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 589system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch 590system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 591system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions | 872system.cpu1.dtb.write_misses 1104 # DTB write misses 873system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 874system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 875system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 876system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 877system.cpu1.dtb.flush_entries 2367 # Number of entries that have been flushed from TLB 878system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 879system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch 880system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 881system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions |
| 592system.cpu1.dtb.read_accesses 6034089 # DTB read accesses 593system.cpu1.dtb.write_accesses 4782708 # DTB write accesses | 882system.cpu1.dtb.read_accesses 6034488 # DTB read accesses 883system.cpu1.dtb.write_accesses 4783072 # DTB write accesses |
| 594system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 884system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 595system.cpu1.dtb.hits 10810290 # DTB hits 596system.cpu1.dtb.misses 6507 # DTB misses 597system.cpu1.dtb.accesses 10816797 # DTB accesses | 885system.cpu1.dtb.hits 10811051 # DTB hits 886system.cpu1.dtb.misses 6509 # DTB misses 887system.cpu1.dtb.accesses 10817560 # DTB accesses |
| 598system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 599system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 600system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 601system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 602system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 603system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 604system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 605system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 611system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 612system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 613system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 614system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 615system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 616system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 617system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 618system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 888system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 889system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 890system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 891system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 892system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 893system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 894system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 895system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 901system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 902system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 903system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 904system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 905system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 906system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 907system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 908system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 619system.cpu1.itb.inst_hits 24626141 # ITB inst hits | 909system.cpu1.itb.inst_hits 24627232 # ITB inst hits |
| 620system.cpu1.itb.inst_misses 3166 # ITB inst misses 621system.cpu1.itb.read_hits 0 # DTB read hits 622system.cpu1.itb.read_misses 0 # DTB read misses 623system.cpu1.itb.write_hits 0 # DTB write hits 624system.cpu1.itb.write_misses 0 # DTB write misses 625system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 626system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 627system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 628system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 629system.cpu1.itb.flush_entries 1581 # Number of entries that have been flushed from TLB 630system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 631system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 632system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 633system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 634system.cpu1.itb.read_accesses 0 # DTB read accesses 635system.cpu1.itb.write_accesses 0 # DTB write accesses | 910system.cpu1.itb.inst_misses 3166 # ITB inst misses 911system.cpu1.itb.read_hits 0 # DTB read hits 912system.cpu1.itb.read_misses 0 # DTB read misses 913system.cpu1.itb.write_hits 0 # DTB write hits 914system.cpu1.itb.write_misses 0 # DTB write misses 915system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 916system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 917system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 918system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 919system.cpu1.itb.flush_entries 1581 # Number of entries that have been flushed from TLB 920system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 921system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 922system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 923system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 924system.cpu1.itb.read_accesses 0 # DTB read accesses 925system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 636system.cpu1.itb.inst_accesses 24629307 # ITB inst accesses 637system.cpu1.itb.hits 24626141 # DTB hits | 926system.cpu1.itb.inst_accesses 24630398 # ITB inst accesses 927system.cpu1.itb.hits 24627232 # DTB hits |
| 638system.cpu1.itb.misses 3166 # DTB misses | 928system.cpu1.itb.misses 3166 # DTB misses |
| 639system.cpu1.itb.accesses 24629307 # DTB accesses 640system.cpu1.numCycles 1801709576 # number of cpu cycles simulated | 929system.cpu1.itb.accesses 24630398 # DTB accesses 930system.cpu1.numCycles 1801708036 # number of cpu cycles simulated |
| 641system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 642system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 931system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 932system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 643system.cpu1.committedInsts 23838609 # Number of instructions committed 644system.cpu1.committedOps 29191016 # Number of ops (including micro ops) committed 645system.cpu1.num_int_alu_accesses 25547086 # Number of integer alu accesses 646system.cpu1.num_fp_alu_accesses 5650 # Number of float alu accesses 647system.cpu1.num_func_calls 987842 # number of times a function call or return occured 648system.cpu1.num_conditional_control_insts 2987341 # number of instructions that are conditional controls 649system.cpu1.num_int_insts 25547086 # number of integer instructions 650system.cpu1.num_fp_insts 5650 # number of float instructions 651system.cpu1.num_int_register_reads 48277330 # number of times the integer registers were read 652system.cpu1.num_int_register_writes 17495174 # number of times the integer registers were written 653system.cpu1.num_fp_register_reads 3706 # number of times the floating registers were read 654system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written 655system.cpu1.num_cc_register_reads 86963152 # number of times the CC registers were read 656system.cpu1.num_cc_register_writes 11050350 # number of times the CC registers were written 657system.cpu1.num_mem_refs 11165955 # number of memory refs 658system.cpu1.num_load_insts 6206289 # Number of load instructions 659system.cpu1.num_store_insts 4959666 # Number of store instructions 660system.cpu1.num_idle_cycles 1771680344.893366 # Number of idle cycles 661system.cpu1.num_busy_cycles 30029231.106634 # Number of busy cycles 662system.cpu1.not_idle_fraction 0.016667 # Percentage of non-idle cycles 663system.cpu1.idle_fraction 0.983333 # Percentage of idle cycles 664system.cpu1.Branches 4459555 # Number of branches fetched | 933system.cpu1.committedInsts 23839695 # Number of instructions committed 934system.cpu1.committedOps 29192667 # Number of ops (including micro ops) committed 935system.cpu1.num_int_alu_accesses 25548618 # Number of integer alu accesses 936system.cpu1.num_fp_alu_accesses 5779 # Number of float alu accesses 937system.cpu1.num_func_calls 987959 # number of times a function call or return occured 938system.cpu1.num_conditional_control_insts 2987443 # number of instructions that are conditional controls 939system.cpu1.num_int_insts 25548618 # number of integer instructions 940system.cpu1.num_fp_insts 5779 # number of float instructions 941system.cpu1.num_int_register_reads 48280801 # number of times the integer registers were read 942system.cpu1.num_int_register_writes 17496069 # number of times the integer registers were written 943system.cpu1.num_fp_register_reads 3771 # number of times the floating registers were read 944system.cpu1.num_fp_register_writes 2012 # number of times the floating registers were written 945system.cpu1.num_cc_register_reads 86968126 # number of times the CC registers were read 946system.cpu1.num_cc_register_writes 11050847 # number of times the CC registers were written 947system.cpu1.num_mem_refs 11166773 # number of memory refs 948system.cpu1.num_load_insts 6206724 # Number of load instructions 949system.cpu1.num_store_insts 4960049 # Number of store instructions 950system.cpu1.num_idle_cycles 1771724648.110516 # Number of idle cycles 951system.cpu1.num_busy_cycles 29983387.889484 # Number of busy cycles 952system.cpu1.not_idle_fraction 0.016642 # Percentage of non-idle cycles 953system.cpu1.idle_fraction 0.983358 # Percentage of idle cycles 954system.cpu1.Branches 4459767 # Number of branches fetched |
| 665system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction | 955system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction |
| 666system.cpu1.op_class::IntAlu 18046643 61.66% 61.71% # Class of executed instruction 667system.cpu1.op_class::IntMult 40424 0.14% 61.85% # Class of executed instruction | 956system.cpu1.op_class::IntAlu 18047467 61.65% 61.71% # Class of executed instruction 957system.cpu1.op_class::IntMult 40427 0.14% 61.85% # Class of executed instruction |
| 668system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction 669system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction 670system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction 671system.cpu1.op_class::FloatCvt 0 0.00% 61.85% # Class of executed instruction 672system.cpu1.op_class::FloatMult 0 0.00% 61.85% # Class of executed instruction 673system.cpu1.op_class::FloatDiv 0 0.00% 61.85% # Class of executed instruction 674system.cpu1.op_class::FloatSqrt 0 0.00% 61.85% # Class of executed instruction 675system.cpu1.op_class::SimdAdd 0 0.00% 61.85% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 683system.cpu1.op_class::SimdShift 0 0.00% 61.85% # Class of executed instruction 684system.cpu1.op_class::SimdShiftAcc 0 0.00% 61.85% # Class of executed instruction 685system.cpu1.op_class::SimdSqrt 0 0.00% 61.85% # Class of executed instruction 686system.cpu1.op_class::SimdFloatAdd 0 0.00% 61.85% # Class of executed instruction 687system.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Class of executed instruction 688system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction 689system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction 690system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction | 958system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction 959system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction 960system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction 961system.cpu1.op_class::FloatCvt 0 0.00% 61.85% # Class of executed instruction 962system.cpu1.op_class::FloatMult 0 0.00% 61.85% # Class of executed instruction 963system.cpu1.op_class::FloatDiv 0 0.00% 61.85% # Class of executed instruction 964system.cpu1.op_class::FloatSqrt 0 0.00% 61.85% # Class of executed instruction 965system.cpu1.op_class::SimdAdd 0 0.00% 61.85% # Class of executed instruction --- 7 unchanged lines hidden (view full) --- 973system.cpu1.op_class::SimdShift 0 0.00% 61.85% # Class of executed instruction 974system.cpu1.op_class::SimdShiftAcc 0 0.00% 61.85% # Class of executed instruction 975system.cpu1.op_class::SimdSqrt 0 0.00% 61.85% # Class of executed instruction 976system.cpu1.op_class::SimdFloatAdd 0 0.00% 61.85% # Class of executed instruction 977system.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Class of executed instruction 978system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction 979system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction 980system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction |
| 691system.cpu1.op_class::SimdFloatMisc 1539 0.01% 61.85% # Class of executed instruction | 981system.cpu1.op_class::SimdFloatMisc 1550 0.01% 61.85% # Class of executed instruction |
| 692system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction 693system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction 694system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction | 982system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction 983system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction 984system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction |
| 695system.cpu1.op_class::MemRead 6206289 21.20% 83.06% # Class of executed instruction 696system.cpu1.op_class::MemWrite 4959666 16.94% 100.00% # Class of executed instruction | 985system.cpu1.op_class::MemRead 6206724 21.20% 83.06% # Class of executed instruction 986system.cpu1.op_class::MemWrite 4960049 16.94% 100.00% # Class of executed instruction |
| 697system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 698system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 987system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 988system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 699system.cpu1.op_class::total 29270113 # Class of executed instruction | 989system.cpu1.op_class::total 29271769 # Class of executed instruction |
| 700system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 990system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 701system.cpu1.kern.inst.quiesce 48301 # number of quiesce instructions executed 702system.cpu1.icache.tags.replacements 442993 # number of replacements 703system.cpu1.icache.tags.tagsinuse 472.644505 # Cycle average of tags in use 704system.cpu1.icache.tags.total_refs 24184321 # Total number of references to valid blocks. 705system.cpu1.icache.tags.sampled_refs 443505 # Sample count of references to valid blocks. 706system.cpu1.icache.tags.avg_refs 54.529985 # Average number of references to valid blocks. 707system.cpu1.icache.tags.warmup_cycle 254679414000 # Cycle when the warmup percentage was hit. 708system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.644505 # Average occupied blocks per requestor 709system.cpu1.icache.tags.occ_percent::cpu1.inst 0.923134 # Average percentage of cache occupancy 710system.cpu1.icache.tags.occ_percent::total 0.923134 # Average percentage of cache occupancy | 991system.cpu1.kern.inst.quiesce 48299 # number of quiesce instructions executed 992system.cpu1.icache.tags.replacements 398154 # number of replacements 993system.cpu1.icache.tags.tagsinuse 474.812776 # Cycle average of tags in use 994system.cpu1.icache.tags.total_refs 24230251 # Total number of references to valid blocks. 995system.cpu1.icache.tags.sampled_refs 398666 # Sample count of references to valid blocks. 996system.cpu1.icache.tags.avg_refs 60.778323 # Average number of references to valid blocks. 997system.cpu1.icache.tags.warmup_cycle 103932913000 # Cycle when the warmup percentage was hit. 998system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.812776 # Average occupied blocks per requestor 999system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927369 # Average percentage of cache occupancy 1000system.cpu1.icache.tags.occ_percent::total 0.927369 # Average percentage of cache occupancy |
| 711system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1001system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 712system.cpu1.icache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 713system.cpu1.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id 714system.cpu1.icache.tags.age_task_id_blocks_1024::2 257 # Occupied blocks per task id 715system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id | 1002system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id 1003system.cpu1.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id 1004system.cpu1.icache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id 1005system.cpu1.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id |
| 716system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1006system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 717system.cpu1.icache.tags.tag_accesses 25071331 # Number of tag accesses 718system.cpu1.icache.tags.data_accesses 25071331 # Number of data accesses 719system.cpu1.icache.ReadReq_hits::cpu1.inst 24184321 # number of ReadReq hits 720system.cpu1.icache.ReadReq_hits::total 24184321 # number of ReadReq hits 721system.cpu1.icache.demand_hits::cpu1.inst 24184321 # number of demand (read+write) hits 722system.cpu1.icache.demand_hits::total 24184321 # number of demand (read+write) hits 723system.cpu1.icache.overall_hits::cpu1.inst 24184321 # number of overall hits 724system.cpu1.icache.overall_hits::total 24184321 # number of overall hits 725system.cpu1.icache.ReadReq_misses::cpu1.inst 443505 # number of ReadReq misses 726system.cpu1.icache.ReadReq_misses::total 443505 # number of ReadReq misses 727system.cpu1.icache.demand_misses::cpu1.inst 443505 # number of demand (read+write) misses 728system.cpu1.icache.demand_misses::total 443505 # number of demand (read+write) misses 729system.cpu1.icache.overall_misses::cpu1.inst 443505 # number of overall misses 730system.cpu1.icache.overall_misses::total 443505 # number of overall misses 731system.cpu1.icache.ReadReq_accesses::cpu1.inst 24627826 # number of ReadReq accesses(hits+misses) 732system.cpu1.icache.ReadReq_accesses::total 24627826 # number of ReadReq accesses(hits+misses) 733system.cpu1.icache.demand_accesses::cpu1.inst 24627826 # number of demand (read+write) accesses 734system.cpu1.icache.demand_accesses::total 24627826 # number of demand (read+write) accesses 735system.cpu1.icache.overall_accesses::cpu1.inst 24627826 # number of overall (read+write) accesses 736system.cpu1.icache.overall_accesses::total 24627826 # number of overall (read+write) accesses 737system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018008 # miss rate for ReadReq accesses 738system.cpu1.icache.ReadReq_miss_rate::total 0.018008 # miss rate for ReadReq accesses 739system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018008 # miss rate for demand accesses 740system.cpu1.icache.demand_miss_rate::total 0.018008 # miss rate for demand accesses 741system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018008 # miss rate for overall accesses 742system.cpu1.icache.overall_miss_rate::total 0.018008 # miss rate for overall accesses | 1007system.cpu1.icache.tags.tag_accesses 49656500 # Number of tag accesses 1008system.cpu1.icache.tags.data_accesses 49656500 # Number of data accesses 1009system.cpu1.icache.ReadReq_hits::cpu1.inst 24230251 # number of ReadReq hits 1010system.cpu1.icache.ReadReq_hits::total 24230251 # number of ReadReq hits 1011system.cpu1.icache.demand_hits::cpu1.inst 24230251 # number of demand (read+write) hits 1012system.cpu1.icache.demand_hits::total 24230251 # number of demand (read+write) hits 1013system.cpu1.icache.overall_hits::cpu1.inst 24230251 # number of overall hits 1014system.cpu1.icache.overall_hits::total 24230251 # number of overall hits 1015system.cpu1.icache.ReadReq_misses::cpu1.inst 398666 # number of ReadReq misses 1016system.cpu1.icache.ReadReq_misses::total 398666 # number of ReadReq misses 1017system.cpu1.icache.demand_misses::cpu1.inst 398666 # number of demand (read+write) misses 1018system.cpu1.icache.demand_misses::total 398666 # number of demand (read+write) misses 1019system.cpu1.icache.overall_misses::cpu1.inst 398666 # number of overall misses 1020system.cpu1.icache.overall_misses::total 398666 # number of overall misses 1021system.cpu1.icache.ReadReq_accesses::cpu1.inst 24628917 # number of ReadReq accesses(hits+misses) 1022system.cpu1.icache.ReadReq_accesses::total 24628917 # number of ReadReq accesses(hits+misses) 1023system.cpu1.icache.demand_accesses::cpu1.inst 24628917 # number of demand (read+write) accesses 1024system.cpu1.icache.demand_accesses::total 24628917 # number of demand (read+write) accesses 1025system.cpu1.icache.overall_accesses::cpu1.inst 24628917 # number of overall (read+write) accesses 1026system.cpu1.icache.overall_accesses::total 24628917 # number of overall (read+write) accesses 1027system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016187 # miss rate for ReadReq accesses 1028system.cpu1.icache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses 1029system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016187 # miss rate for demand accesses 1030system.cpu1.icache.demand_miss_rate::total 0.016187 # miss rate for demand accesses 1031system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016187 # miss rate for overall accesses 1032system.cpu1.icache.overall_miss_rate::total 0.016187 # miss rate for overall accesses |
| 743system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 744system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 745system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 746system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 747system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 748system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 749system.cpu1.icache.fast_writes 0 # number of fast writes performed 750system.cpu1.icache.cache_copies 0 # number of cache copies performed 751system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1033system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1034system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1035system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1036system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1037system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1038system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1039system.cpu1.icache.fast_writes 0 # number of fast writes performed 1040system.cpu1.icache.cache_copies 0 # number of cache copies performed 1041system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 752system.cpu1.dcache.tags.replacements 274056 # number of replacements 753system.cpu1.dcache.tags.tagsinuse 468.122166 # Cycle average of tags in use 754system.cpu1.dcache.tags.total_refs 9407683 # Total number of references to valid blocks. 755system.cpu1.dcache.tags.sampled_refs 274568 # Sample count of references to valid blocks. 756system.cpu1.dcache.tags.avg_refs 34.263581 # Average number of references to valid blocks. 757system.cpu1.dcache.tags.warmup_cycle 94419429000 # Cycle when the warmup percentage was hit. 758system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.122166 # Average occupied blocks per requestor 759system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914301 # Average percentage of cache occupancy 760system.cpu1.dcache.tags.occ_percent::total 0.914301 # Average percentage of cache occupancy | 1042system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified 1043system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 1044system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 1045system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 1046system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1047system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 1048system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1049system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 1050system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1051system.cpu1.l2cache.tags.replacements 88565 # number of replacements 1052system.cpu1.l2cache.tags.tagsinuse 12390.036216 # Cycle average of tags in use 1053system.cpu1.l2cache.tags.total_refs 691452 # Total number of references to valid blocks. 1054system.cpu1.l2cache.tags.sampled_refs 104644 # Sample count of references to valid blocks. 1055system.cpu1.l2cache.tags.avg_refs 6.607660 # Average number of references to valid blocks. 1056system.cpu1.l2cache.tags.warmup_cycle 876305009500 # Cycle when the warmup percentage was hit. 1057system.cpu1.l2cache.tags.occ_blocks::writebacks 6229.071421 # Average occupied blocks per requestor 1058system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 8.886003 # Average occupied blocks per requestor 1059system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.649559 # Average occupied blocks per requestor 1060system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3323.104999 # Average occupied blocks per requestor 1061system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2826.324234 # Average occupied blocks per requestor 1062system.cpu1.l2cache.tags.occ_percent::writebacks 0.380192 # Average percentage of cache occupancy 1063system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000542 # Average percentage of cache occupancy 1064system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000162 # Average percentage of cache occupancy 1065system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.202826 # Average percentage of cache occupancy 1066system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.172505 # Average percentage of cache occupancy 1067system.cpu1.l2cache.tags.occ_percent::total 0.756228 # Average percentage of cache occupancy 1068system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 1069system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id 1070system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 1071system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 1072system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 1073system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 1074system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id 1075system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id 1076system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9480 # Occupied blocks per task id 1077system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2833 # Occupied blocks per task id 1078system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 1079system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id 1080system.cpu1.l2cache.tags.tag_accesses 15740589 # Number of tag accesses 1081system.cpu1.l2cache.tags.data_accesses 15740589 # Number of data accesses 1082system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5896 # number of ReadReq hits 1083system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2700 # number of ReadReq hits 1084system.cpu1.l2cache.ReadReq_hits::cpu1.inst 375664 # number of ReadReq hits 1085system.cpu1.l2cache.ReadReq_hits::cpu1.data 151551 # number of ReadReq hits 1086system.cpu1.l2cache.ReadReq_hits::total 535811 # number of ReadReq hits 1087system.cpu1.l2cache.Writeback_hits::writebacks 209707 # number of Writeback hits 1088system.cpu1.l2cache.Writeback_hits::total 209707 # number of Writeback hits 1089system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 21 # number of UpgradeReq hits 1090system.cpu1.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits 1091system.cpu1.l2cache.ReadExReq_hits::cpu1.data 48287 # number of ReadExReq hits 1092system.cpu1.l2cache.ReadExReq_hits::total 48287 # number of ReadExReq hits 1093system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5896 # number of demand (read+write) hits 1094system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2700 # number of demand (read+write) hits 1095system.cpu1.l2cache.demand_hits::cpu1.inst 375664 # number of demand (read+write) hits 1096system.cpu1.l2cache.demand_hits::cpu1.data 199838 # number of demand (read+write) hits 1097system.cpu1.l2cache.demand_hits::total 584098 # number of demand (read+write) hits 1098system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5896 # number of overall hits 1099system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2700 # number of overall hits 1100system.cpu1.l2cache.overall_hits::cpu1.inst 375664 # number of overall hits 1101system.cpu1.l2cache.overall_hits::cpu1.data 199838 # number of overall hits 1102system.cpu1.l2cache.overall_hits::total 584098 # number of overall hits 1103system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 349 # number of ReadReq misses 1104system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 263 # number of ReadReq misses 1105system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22734 # number of ReadReq misses 1106system.cpu1.l2cache.ReadReq_misses::cpu1.data 51350 # number of ReadReq misses 1107system.cpu1.l2cache.ReadReq_misses::total 74696 # number of ReadReq misses 1108system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 18752 # number of UpgradeReq misses 1109system.cpu1.l2cache.UpgradeReq_misses::total 18752 # number of UpgradeReq misses 1110system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 11227 # number of SCUpgradeReq misses 1111system.cpu1.l2cache.SCUpgradeReq_misses::total 11227 # number of SCUpgradeReq misses 1112system.cpu1.l2cache.ReadExReq_misses::cpu1.data 68490 # number of ReadExReq misses 1113system.cpu1.l2cache.ReadExReq_misses::total 68490 # number of ReadExReq misses 1114system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 349 # number of demand (read+write) misses 1115system.cpu1.l2cache.demand_misses::cpu1.itb.walker 263 # number of demand (read+write) misses 1116system.cpu1.l2cache.demand_misses::cpu1.inst 22734 # number of demand (read+write) misses 1117system.cpu1.l2cache.demand_misses::cpu1.data 119840 # number of demand (read+write) misses 1118system.cpu1.l2cache.demand_misses::total 143186 # number of demand (read+write) misses 1119system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 349 # number of overall misses 1120system.cpu1.l2cache.overall_misses::cpu1.itb.walker 263 # number of overall misses 1121system.cpu1.l2cache.overall_misses::cpu1.inst 22734 # number of overall misses 1122system.cpu1.l2cache.overall_misses::cpu1.data 119840 # number of overall misses 1123system.cpu1.l2cache.overall_misses::total 143186 # number of overall misses 1124system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6245 # number of ReadReq accesses(hits+misses) 1125system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2963 # number of ReadReq accesses(hits+misses) 1126system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 398398 # number of ReadReq accesses(hits+misses) 1127system.cpu1.l2cache.ReadReq_accesses::cpu1.data 202901 # number of ReadReq accesses(hits+misses) 1128system.cpu1.l2cache.ReadReq_accesses::total 610507 # number of ReadReq accesses(hits+misses) 1129system.cpu1.l2cache.Writeback_accesses::writebacks 209707 # number of Writeback accesses(hits+misses) 1130system.cpu1.l2cache.Writeback_accesses::total 209707 # number of Writeback accesses(hits+misses) 1131system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 18773 # number of UpgradeReq accesses(hits+misses) 1132system.cpu1.l2cache.UpgradeReq_accesses::total 18773 # number of UpgradeReq accesses(hits+misses) 1133system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 11227 # number of SCUpgradeReq accesses(hits+misses) 1134system.cpu1.l2cache.SCUpgradeReq_accesses::total 11227 # number of SCUpgradeReq accesses(hits+misses) 1135system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 116777 # number of ReadExReq accesses(hits+misses) 1136system.cpu1.l2cache.ReadExReq_accesses::total 116777 # number of ReadExReq accesses(hits+misses) 1137system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6245 # number of demand (read+write) accesses 1138system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2963 # number of demand (read+write) accesses 1139system.cpu1.l2cache.demand_accesses::cpu1.inst 398398 # number of demand (read+write) accesses 1140system.cpu1.l2cache.demand_accesses::cpu1.data 319678 # number of demand (read+write) accesses 1141system.cpu1.l2cache.demand_accesses::total 727284 # number of demand (read+write) accesses 1142system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6245 # number of overall (read+write) accesses 1143system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2963 # number of overall (read+write) accesses 1144system.cpu1.l2cache.overall_accesses::cpu1.inst 398398 # number of overall (read+write) accesses 1145system.cpu1.l2cache.overall_accesses::cpu1.data 319678 # number of overall (read+write) accesses 1146system.cpu1.l2cache.overall_accesses::total 727284 # number of overall (read+write) accesses 1147system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for ReadReq accesses 1148system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.088761 # miss rate for ReadReq accesses 1149system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.057064 # miss rate for ReadReq accesses 1150system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.253079 # miss rate for ReadReq accesses 1151system.cpu1.l2cache.ReadReq_miss_rate::total 0.122351 # miss rate for ReadReq accesses 1152system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998881 # miss rate for UpgradeReq accesses 1153system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998881 # miss rate for UpgradeReq accesses 1154system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1155system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1156system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.586502 # miss rate for ReadExReq accesses 1157system.cpu1.l2cache.ReadExReq_miss_rate::total 0.586502 # miss rate for ReadExReq accesses 1158system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for demand accesses 1159system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.088761 # miss rate for demand accesses 1160system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.057064 # miss rate for demand accesses 1161system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.374877 # miss rate for demand accesses 1162system.cpu1.l2cache.demand_miss_rate::total 0.196878 # miss rate for demand accesses 1163system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for overall accesses 1164system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.088761 # miss rate for overall accesses 1165system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.057064 # miss rate for overall accesses 1166system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.374877 # miss rate for overall accesses 1167system.cpu1.l2cache.overall_miss_rate::total 0.196878 # miss rate for overall accesses 1168system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1169system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1170system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1171system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1172system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1173system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1174system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1175system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1176system.cpu1.l2cache.writebacks::writebacks 61322 # number of writebacks 1177system.cpu1.l2cache.writebacks::total 61322 # number of writebacks 1178system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1179system.cpu1.dcache.tags.replacements 299305 # number of replacements 1180system.cpu1.dcache.tags.tagsinuse 464.628152 # Cycle average of tags in use 1181system.cpu1.dcache.tags.total_refs 9384005 # Total number of references to valid blocks. 1182system.cpu1.dcache.tags.sampled_refs 299817 # Sample count of references to valid blocks. 1183system.cpu1.dcache.tags.avg_refs 31.299109 # Average number of references to valid blocks. 1184system.cpu1.dcache.tags.warmup_cycle 94422670000 # Cycle when the warmup percentage was hit. 1185system.cpu1.dcache.tags.occ_blocks::cpu1.data 464.628152 # Average occupied blocks per requestor 1186system.cpu1.dcache.tags.occ_percent::cpu1.data 0.907477 # Average percentage of cache occupancy 1187system.cpu1.dcache.tags.occ_percent::total 0.907477 # Average percentage of cache occupancy |
| 761system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1188system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 762system.cpu1.dcache.tags.age_task_id_blocks_1024::0 322 # Occupied blocks per task id 763system.cpu1.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 764system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 765system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 1189system.cpu1.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 1190system.cpu1.dcache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 1191system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id |
| 766system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1192system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 767system.cpu1.dcache.tags.tag_accesses 39106907 # Number of tag accesses 768system.cpu1.dcache.tags.data_accesses 39106907 # Number of data accesses 769system.cpu1.dcache.ReadReq_hits::cpu1.data 4611957 # number of ReadReq hits 770system.cpu1.dcache.ReadReq_hits::total 4611957 # number of ReadReq hits 771system.cpu1.dcache.WriteReq_hits::cpu1.data 4543395 # number of WriteReq hits 772system.cpu1.dcache.WriteReq_hits::total 4543395 # number of WriteReq hits 773system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35603 # number of SoftPFReq hits 774system.cpu1.dcache.SoftPFReq_hits::total 35603 # number of SoftPFReq hits 775system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94939 # number of LoadLockedReq hits 776system.cpu1.dcache.LoadLockedReq_hits::total 94939 # number of LoadLockedReq hits 777system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95657 # number of StoreCondReq hits 778system.cpu1.dcache.StoreCondReq_hits::total 95657 # number of StoreCondReq hits 779system.cpu1.dcache.demand_hits::cpu1.data 9155352 # number of demand (read+write) hits 780system.cpu1.dcache.demand_hits::total 9155352 # number of demand (read+write) hits 781system.cpu1.dcache.overall_hits::cpu1.data 9190955 # number of overall hits 782system.cpu1.dcache.overall_hits::total 9190955 # number of overall hits 783system.cpu1.dcache.ReadReq_misses::cpu1.data 143554 # number of ReadReq misses 784system.cpu1.dcache.ReadReq_misses::total 143554 # number of ReadReq misses 785system.cpu1.dcache.WriteReq_misses::cpu1.data 130048 # number of WriteReq misses 786system.cpu1.dcache.WriteReq_misses::total 130048 # number of WriteReq misses 787system.cpu1.dcache.SoftPFReq_misses::cpu1.data 27770 # number of SoftPFReq misses 788system.cpu1.dcache.SoftPFReq_misses::total 27770 # number of SoftPFReq misses 789system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10527 # number of LoadLockedReq misses 790system.cpu1.dcache.LoadLockedReq_misses::total 10527 # number of LoadLockedReq misses 791system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9468 # number of StoreCondReq misses 792system.cpu1.dcache.StoreCondReq_misses::total 9468 # number of StoreCondReq misses 793system.cpu1.dcache.demand_misses::cpu1.data 273602 # number of demand (read+write) misses 794system.cpu1.dcache.demand_misses::total 273602 # number of demand (read+write) misses 795system.cpu1.dcache.overall_misses::cpu1.data 301372 # number of overall misses 796system.cpu1.dcache.overall_misses::total 301372 # number of overall misses 797system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755511 # number of ReadReq accesses(hits+misses) 798system.cpu1.dcache.ReadReq_accesses::total 4755511 # number of ReadReq accesses(hits+misses) 799system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673443 # number of WriteReq accesses(hits+misses) 800system.cpu1.dcache.WriteReq_accesses::total 4673443 # number of WriteReq accesses(hits+misses) | 1193system.cpu1.dcache.tags.tag_accesses 19727044 # Number of tag accesses 1194system.cpu1.dcache.tags.data_accesses 19727044 # Number of data accesses 1195system.cpu1.dcache.ReadReq_hits::cpu1.data 4592285 # number of ReadReq hits 1196system.cpu1.dcache.ReadReq_hits::total 4592285 # number of ReadReq hits 1197system.cpu1.dcache.WriteReq_hits::cpu1.data 4538287 # number of WriteReq hits 1198system.cpu1.dcache.WriteReq_hits::total 4538287 # number of WriteReq hits 1199system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35329 # number of SoftPFReq hits 1200system.cpu1.dcache.SoftPFReq_hits::total 35329 # number of SoftPFReq hits 1201system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94231 # number of LoadLockedReq hits 1202system.cpu1.dcache.LoadLockedReq_hits::total 94231 # number of LoadLockedReq hits 1203system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93873 # number of StoreCondReq hits 1204system.cpu1.dcache.StoreCondReq_hits::total 93873 # number of StoreCondReq hits 1205system.cpu1.dcache.demand_hits::cpu1.data 9130572 # number of demand (read+write) hits 1206system.cpu1.dcache.demand_hits::total 9130572 # number of demand (read+write) hits 1207system.cpu1.dcache.overall_hits::cpu1.data 9165901 # number of overall hits 1208system.cpu1.dcache.overall_hits::total 9165901 # number of overall hits 1209system.cpu1.dcache.ReadReq_misses::cpu1.data 163656 # number of ReadReq misses 1210system.cpu1.dcache.ReadReq_misses::total 163656 # number of ReadReq misses 1211system.cpu1.dcache.WriteReq_misses::cpu1.data 135550 # number of WriteReq misses 1212system.cpu1.dcache.WriteReq_misses::total 135550 # number of WriteReq misses 1213system.cpu1.dcache.SoftPFReq_misses::cpu1.data 28044 # number of SoftPFReq misses 1214system.cpu1.dcache.SoftPFReq_misses::total 28044 # number of SoftPFReq misses 1215system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11201 # number of LoadLockedReq misses 1216system.cpu1.dcache.LoadLockedReq_misses::total 11201 # number of LoadLockedReq misses 1217system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11227 # number of StoreCondReq misses 1218system.cpu1.dcache.StoreCondReq_misses::total 11227 # number of StoreCondReq misses 1219system.cpu1.dcache.demand_misses::cpu1.data 299206 # number of demand (read+write) misses 1220system.cpu1.dcache.demand_misses::total 299206 # number of demand (read+write) misses 1221system.cpu1.dcache.overall_misses::cpu1.data 327250 # number of overall misses 1222system.cpu1.dcache.overall_misses::total 327250 # number of overall misses 1223system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755941 # number of ReadReq accesses(hits+misses) 1224system.cpu1.dcache.ReadReq_accesses::total 4755941 # number of ReadReq accesses(hits+misses) 1225system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673837 # number of WriteReq accesses(hits+misses) 1226system.cpu1.dcache.WriteReq_accesses::total 4673837 # number of WriteReq accesses(hits+misses) |
| 801system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) 802system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) | 1227system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) 1228system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) |
| 803system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105466 # number of LoadLockedReq accesses(hits+misses) 804system.cpu1.dcache.LoadLockedReq_accesses::total 105466 # number of LoadLockedReq accesses(hits+misses) 805system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105125 # number of StoreCondReq accesses(hits+misses) 806system.cpu1.dcache.StoreCondReq_accesses::total 105125 # number of StoreCondReq accesses(hits+misses) 807system.cpu1.dcache.demand_accesses::cpu1.data 9428954 # number of demand (read+write) accesses 808system.cpu1.dcache.demand_accesses::total 9428954 # number of demand (read+write) accesses 809system.cpu1.dcache.overall_accesses::cpu1.data 9492327 # number of overall (read+write) accesses 810system.cpu1.dcache.overall_accesses::total 9492327 # number of overall (read+write) accesses 811system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.030187 # miss rate for ReadReq accesses 812system.cpu1.dcache.ReadReq_miss_rate::total 0.030187 # miss rate for ReadReq accesses 813system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027827 # miss rate for WriteReq accesses 814system.cpu1.dcache.WriteReq_miss_rate::total 0.027827 # miss rate for WriteReq accesses 815system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.438199 # miss rate for SoftPFReq accesses 816system.cpu1.dcache.SoftPFReq_miss_rate::total 0.438199 # miss rate for SoftPFReq accesses 817system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099814 # miss rate for LoadLockedReq accesses 818system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099814 # miss rate for LoadLockedReq accesses 819system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090064 # miss rate for StoreCondReq accesses 820system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090064 # miss rate for StoreCondReq accesses 821system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029017 # miss rate for demand accesses 822system.cpu1.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses 823system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031749 # miss rate for overall accesses 824system.cpu1.dcache.overall_miss_rate::total 0.031749 # miss rate for overall accesses | 1229system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105432 # number of LoadLockedReq accesses(hits+misses) 1230system.cpu1.dcache.LoadLockedReq_accesses::total 105432 # number of LoadLockedReq accesses(hits+misses) 1231system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105100 # number of StoreCondReq accesses(hits+misses) 1232system.cpu1.dcache.StoreCondReq_accesses::total 105100 # number of StoreCondReq accesses(hits+misses) 1233system.cpu1.dcache.demand_accesses::cpu1.data 9429778 # number of demand (read+write) accesses 1234system.cpu1.dcache.demand_accesses::total 9429778 # number of demand (read+write) accesses 1235system.cpu1.dcache.overall_accesses::cpu1.data 9493151 # number of overall (read+write) accesses 1236system.cpu1.dcache.overall_accesses::total 9493151 # number of overall (read+write) accesses 1237system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034411 # miss rate for ReadReq accesses 1238system.cpu1.dcache.ReadReq_miss_rate::total 0.034411 # miss rate for ReadReq accesses 1239system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029002 # miss rate for WriteReq accesses 1240system.cpu1.dcache.WriteReq_miss_rate::total 0.029002 # miss rate for WriteReq accesses 1241system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.442523 # miss rate for SoftPFReq accesses 1242system.cpu1.dcache.SoftPFReq_miss_rate::total 0.442523 # miss rate for SoftPFReq accesses 1243system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106239 # miss rate for LoadLockedReq accesses 1244system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106239 # miss rate for LoadLockedReq accesses 1245system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106822 # miss rate for StoreCondReq accesses 1246system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106822 # miss rate for StoreCondReq accesses 1247system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031730 # miss rate for demand accesses 1248system.cpu1.dcache.demand_miss_rate::total 0.031730 # miss rate for demand accesses 1249system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034472 # miss rate for overall accesses 1250system.cpu1.dcache.overall_miss_rate::total 0.034472 # miss rate for overall accesses |
| 825system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 826system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 827system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 828system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 829system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 830system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 831system.cpu1.dcache.fast_writes 0 # number of fast writes performed 832system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1251system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1252system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1253system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1254system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1255system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1256system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1257system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1258system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 833system.cpu1.dcache.writebacks::writebacks 249941 # number of writebacks 834system.cpu1.dcache.writebacks::total 249941 # number of writebacks | 1259system.cpu1.dcache.writebacks::writebacks 209707 # number of writebacks 1260system.cpu1.dcache.writebacks::total 209707 # number of writebacks |
| 835system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1261system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1262system.cpu1.toL2Bus.trans_dist::ReadReq 1728836 # Transaction distribution 1263system.cpu1.toL2Bus.trans_dist::ReadResp 1728836 # Transaction distribution 1264system.cpu1.toL2Bus.trans_dist::WriteReq 3546 # Transaction distribution 1265system.cpu1.toL2Bus.trans_dist::WriteResp 3546 # Transaction distribution 1266system.cpu1.toL2Bus.trans_dist::Writeback 209707 # Transaction distribution 1267system.cpu1.toL2Bus.trans_dist::UpgradeReq 18773 # Transaction distribution 1268system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 11227 # Transaction distribution 1269system.cpu1.toL2Bus.trans_dist::UpgradeResp 30000 # Transaction distribution 1270system.cpu1.toL2Bus.trans_dist::ReadExReq 116777 # Transaction distribution 1271system.cpu1.toL2Bus.trans_dist::ReadExResp 116777 # Transaction distribution 1272system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797550 # Packet count per connected master and slave (bytes) 1273system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 3132383 # Packet count per connected master and slave (bytes) 1274system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12644 # Packet count per connected master and slave (bytes) 1275system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25448 # Packet count per connected master and slave (bytes) 1276system.cpu1.toL2Bus.pkt_count::total 3968025 # Packet count per connected master and slave (bytes) 1277system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25515060 # Cumulative packet size per connected master and slave (bytes) 1278system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36101346 # Cumulative packet size per connected master and slave (bytes) 1279system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25288 # Cumulative packet size per connected master and slave (bytes) 1280system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50896 # Cumulative packet size per connected master and slave (bytes) 1281system.cpu1.toL2Bus.pkt_size::total 61692590 # Cumulative packet size per connected master and slave (bytes) 1282system.cpu1.toL2Bus.snoops 259574 # Total snoops (count) 1283system.cpu1.toL2Bus.snoop_fanout::samples 1204043 # Request fanout histogram 1284system.cpu1.toL2Bus.snoop_fanout::mean 5.188487 # Request fanout histogram 1285system.cpu1.toL2Bus.snoop_fanout::stdev 0.391100 # Request fanout histogram 1286system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1287system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1288system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1289system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1290system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1291system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1292system.cpu1.toL2Bus.snoop_fanout::5 977097 81.15% 81.15% # Request fanout histogram 1293system.cpu1.toL2Bus.snoop_fanout::6 226946 18.85% 100.00% # Request fanout histogram 1294system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1295system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1296system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1297system.cpu1.toL2Bus.snoop_fanout::total 1204043 # Request fanout histogram |
|
| 836system.iocache.tags.replacements 0 # number of replacements 837system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 838system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 839system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 840system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 841system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 842system.iocache.tags.tag_accesses 0 # Number of tag accesses 843system.iocache.tags.data_accesses 0 # Number of data accesses 844system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 845system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 846system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 847system.iocache.blocked::no_targets 0 # number of cycles access was blocked 848system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 849system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 850system.iocache.fast_writes 0 # number of fast writes performed 851system.iocache.cache_copies 0 # number of cache copies performed 852system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 853 854---------- End Simulation Statistics ---------- | 1298system.iocache.tags.replacements 0 # number of replacements 1299system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1300system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1301system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1302system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1303system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1304system.iocache.tags.tag_accesses 0 # Number of tag accesses 1305system.iocache.tags.data_accesses 0 # Number of data accesses 1306system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1307system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1308system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1309system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1310system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1311system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1312system.iocache.fast_writes 0 # number of fast writes performed 1313system.iocache.cache_copies 0 # number of cache copies performed 1314system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1315 1316---------- End Simulation Statistics ---------- |