| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882797500 # Number of ticks simulated 5final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1371763 # Simulator instruction rate (inst/s) 8host_op_rate 1671473 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26186322462 # Simulator tick rate (ticks/s) 10host_mem_usage 640448 # Number of bytes of host memory used 11host_seconds 107.04 # Real time elapsed on the host |
| 12sim_insts 146828219 # Number of instructions simulated 13sim_ops 178907974 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory 23system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 24system.physmem.bytes_read::total 11758444 # Number of bytes read from this memory --- 35 unchanged lines hidden (view full) --- 60system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s) |
| 68system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 69system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) |
| 87system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 88system.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 89system.bridge.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 90system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 91system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 92system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 93system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 94system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 95system.cf0.dma_write_txs 631 # Number of DMA write transactions. 96system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 97system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 98system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 119system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 127system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 128system.cpu0.dtb.walker.walks 7964 # Table walker walks requested 129system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 130system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 131system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 132system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 133system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 134system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 135system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 159system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 160system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 161system.cpu0.dtb.read_accesses 20346565 # DTB read accesses 162system.cpu0.dtb.write_accesses 16392097 # DTB write accesses 163system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 164system.cpu0.dtb.hits 36730698 # DTB hits 165system.cpu0.dtb.misses 7964 # DTB misses 166system.cpu0.dtb.accesses 36738662 # DTB accesses |
| 167system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 168system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 169system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 170system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 171system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 172system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 173system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 174system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 175system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 189system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 190system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 191system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 192system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 193system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 194system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 195system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 196system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 197system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 198system.cpu0.itb.walker.walks 3358 # Table walker walks requested 199system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 200system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 201system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 202system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 203system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 204system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 205system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 229system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 230system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu0.itb.read_accesses 0 # DTB read accesses 232system.cpu0.itb.write_accesses 0 # DTB write accesses 233system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses 234system.cpu0.itb.hits 97439155 # DTB hits 235system.cpu0.itb.misses 3358 # DTB misses 236system.cpu0.itb.accesses 97442513 # DTB accesses |
| 237system.cpu0.numPwrStateTransitions 3932 # Number of power state transitions 238system.cpu0.pwrStateClkGateDist::samples 1966 # Distribution of time spent in the clock gated state 239system.cpu0.pwrStateClkGateDist::mean 1395773493.506104 # Distribution of time spent in the clock gated state 240system.cpu0.pwrStateClkGateDist::stdev 23114974453.612934 # Distribution of time spent in the clock gated state 241system.cpu0.pwrStateClkGateDist::underflows 1154 58.70% 58.70% # Distribution of time spent in the clock gated state 242system.cpu0.pwrStateClkGateDist::1000-5e+10 806 41.00% 99.69% # Distribution of time spent in the clock gated state 243system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state 244system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state 245system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state 246system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 247system.cpu0.pwrStateClkGateDist::max_value 499983242180 # Distribution of time spent in the clock gated state 248system.cpu0.pwrStateClkGateDist::total 1966 # Distribution of time spent in the clock gated state 249system.cpu0.pwrStateResidencyTicks::ON 58792109267 # Cumulative time (in ticks) in various power states 250system.cpu0.pwrStateResidencyTicks::CLK_GATED 2744090688233 # Cumulative time (in ticks) in various power states |
| 251system.cpu0.numCycles 5605767562 # number of cpu cycles simulated 252system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 253system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 254system.cpu0.kern.inst.arm 0 # number of arm instructions executed 255system.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed 256system.cpu0.committedInsts 95426725 # Number of instructions committed 257system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed 258system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 305system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 306system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 307system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 308system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction 309system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction 310system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 311system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 312system.cpu0.op_class::total 116881836 # Class of executed instruction |
| 313system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 314system.cpu0.dcache.tags.replacements 693478 # number of replacements 315system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use 316system.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks. 317system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. 318system.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks. 319system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 320system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor 321system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 322system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 323system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 324system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 325system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 326system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 327system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 328system.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses 329system.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses |
| 330system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 331system.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits 332system.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits 333system.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits 334system.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits 335system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits 336system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits 337system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits 338system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits --- 48 unchanged lines hidden (view full) --- 387system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 388system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 389system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 390system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 391system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 392system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 393system.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks 394system.cpu0.dcache.writebacks::total 693478 # number of writebacks |
| 395system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 396system.cpu0.icache.tags.replacements 1109639 # number of replacements 397system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 398system.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks. 399system.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks. 400system.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks. 401system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 402system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 403system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 404system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 405system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 406system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 407system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 408system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 409system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 410system.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses 411system.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses |
| 412system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 413system.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits 414system.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits 415system.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits 416system.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits 417system.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits 418system.cpu0.icache.overall_hits::total 96331337 # number of overall hits 419system.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses 420system.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 437system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 438system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 439system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 440system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 441system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 442system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 443system.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks 444system.cpu0.icache.writebacks::total 1109639 # number of writebacks |
| 445system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 446system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 447system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 448system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 449system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 450system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 451system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 452system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 453system.cpu0.l2cache.tags.replacements 249747 # number of replacements 454system.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use 455system.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks. 456system.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks. 457system.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks. 458system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 459system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor 460system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor --- 11 unchanged lines hidden (view full) --- 472system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 473system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id 474system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id 475system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id 476system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 477system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id 478system.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses 479system.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses |
| 480system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 481system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits 482system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits 483system.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits 484system.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits 485system.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits 486system.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits 487system.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits 488system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits --- 94 unchanged lines hidden (view full) --- 583system.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks 584system.cpu0.l2cache.writebacks::total 193031 # number of writebacks 585system.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter. 586system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data. 587system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 588system.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter. 589system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 590system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 591system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 592system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 593system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution 594system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 595system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 596system.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution 597system.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution 598system.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution 599system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution --- 19 unchanged lines hidden (view full) --- 619system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 620system.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram 621system.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram 622system.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram 623system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 624system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 625system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 626system.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram |
| 627system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 628system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 629system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 630system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 631system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 632system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 649system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 650system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 651system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 652system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 653system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 654system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 655system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 656system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 657system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 658system.cpu1.dtb.walker.walks 3359 # Table walker walks requested 659system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 660system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 661system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 662system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 663system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 664system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 665system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 689system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 690system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 691system.cpu1.dtb.read_accesses 12176798 # DTB read accesses 692system.cpu1.dtb.write_accesses 7587727 # DTB write accesses 693system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 694system.cpu1.dtb.hits 19761166 # DTB hits 695system.cpu1.dtb.misses 3359 # DTB misses 696system.cpu1.dtb.accesses 19764525 # DTB accesses |
| 697system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 698system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 699system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 700system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 701system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 702system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 703system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 704system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 705system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 719system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 720system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 721system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 722system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 723system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 724system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 725system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 726system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 727system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 728system.cpu1.itb.walker.walks 1734 # Table walker walks requested 729system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 730system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 731system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 732system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 733system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 734system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 735system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution --- 23 unchanged lines hidden (view full) --- 759system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 760system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 761system.cpu1.itb.read_accesses 0 # DTB read accesses 762system.cpu1.itb.write_accesses 0 # DTB write accesses 763system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses 764system.cpu1.itb.hits 53671758 # DTB hits 765system.cpu1.itb.misses 1734 # DTB misses 766system.cpu1.itb.accesses 53673492 # DTB accesses |
| 767system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions 768system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state 769system.cpu1.pwrStateClkGateDist::mean 1011344723.290617 # Distribution of time spent in the clock gated state 770system.cpu1.pwrStateClkGateDist::stdev 25846310002.973743 # Distribution of time spent in the clock gated state 771system.cpu1.pwrStateClkGateDist::underflows 1957 71.45% 71.45% # Distribution of time spent in the clock gated state 772system.cpu1.pwrStateClkGateDist::1000-5e+10 777 28.37% 99.82% # Distribution of time spent in the clock gated state 773system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state 774system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 775system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 776system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 777system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 778system.cpu1.pwrStateClkGateDist::max_value 979984930372 # Distribution of time spent in the clock gated state 779system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state 780system.cpu1.pwrStateResidencyTicks::ON 32809600407 # Cumulative time (in ticks) in various power states 781system.cpu1.pwrStateResidencyTicks::CLK_GATED 2770073197093 # Cumulative time (in ticks) in various power states |
| 782system.cpu1.numCycles 5605296470 # number of cpu cycles simulated 783system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 784system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 785system.cpu1.kern.inst.arm 0 # number of arm instructions executed 786system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 787system.cpu1.committedInsts 51401494 # Number of instructions committed 788system.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed 789system.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses --- 46 unchanged lines hidden (view full) --- 836system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 837system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 838system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 839system.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction 840system.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction 841system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 842system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 843system.cpu1.op_class::total 65459659 # Class of executed instruction |
| 844system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 845system.cpu1.dcache.tags.replacements 191946 # number of replacements 846system.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use 847system.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks. 848system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. 849system.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks. 850system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 851system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor 852system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 853system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy 854system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 855system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 856system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 857system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 858system.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses 859system.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses |
| 860system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 861system.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits 862system.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits 863system.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits 864system.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits 865system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 866system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits 867system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 868system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits --- 48 unchanged lines hidden (view full) --- 917system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 918system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 919system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 920system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 921system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 922system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 923system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks 924system.cpu1.dcache.writebacks::total 191946 # number of writebacks |
| 925system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 926system.cpu1.icache.tags.replacements 523401 # number of replacements 927system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use 928system.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks. 929system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. 930system.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks. 931system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 932system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor 933system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 934system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 935system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 936system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 937system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 938system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 939system.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses 940system.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses |
| 941system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 942system.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits 943system.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits 944system.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits 945system.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits 946system.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits 947system.cpu1.icache.overall_hits::total 53148935 # number of overall hits 948system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses 949system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses --- 16 unchanged lines hidden (view full) --- 966system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 967system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 968system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 969system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 970system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 971system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 972system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks 973system.cpu1.icache.writebacks::total 523401 # number of writebacks |
| 974system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 975system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 976system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 977system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 978system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 979system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 980system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 981system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 982system.cpu1.l2cache.tags.replacements 47503 # number of replacements 983system.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use 984system.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks. 985system.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks. 986system.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks. 987system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 988system.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor 989system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor --- 9 unchanged lines hidden (view full) --- 999system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1000system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id 1001system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id 1002system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id 1003system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id 1004system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id 1005system.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses 1006system.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses |
| 1007system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1008system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits 1009system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits 1010system.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits 1011system.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits 1012system.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits 1013system.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits 1014system.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits 1015system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits --- 94 unchanged lines hidden (view full) --- 1110system.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks 1111system.cpu1.l2cache.writebacks::total 32790 # number of writebacks 1112system.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter. 1113system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1114system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1115system.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter. 1116system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1117system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1118system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1119system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution 1120system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution 1121system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 1122system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 1123system.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution 1124system.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution 1125system.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution 1126system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution --- 19 unchanged lines hidden (view full) --- 1146system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1147system.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram 1148system.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram 1149system.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram 1150system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1151system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1152system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1153system.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram |
| 1154system.iobus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1155system.iobus.trans_dist::ReadReq 30995 # Transaction distribution 1156system.iobus.trans_dist::ReadResp 30995 # Transaction distribution 1157system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1158system.iobus.trans_dist::WriteResp 59419 # Transaction distribution 1159system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 1160system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1161system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1162system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) --- 34 unchanged lines hidden (view full) --- 1197system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1198system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1199system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1200system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1201system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 1202system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1203system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1204system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) |
| 1205system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1206system.iocache.tags.replacements 36442 # number of replacements 1207system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use 1208system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1209system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1210system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1211system.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit. 1212system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor 1213system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 1214system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 1215system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1216system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1217system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1218system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1219system.iocache.tags.data_accesses 328284 # Number of data accesses |
| 1220system.iocache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1221system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1222system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1223system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1224system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1225system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 1226system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 1227system.iocache.overall_misses::realview.ide 36476 # number of overall misses 1228system.iocache.overall_misses::total 36476 # number of overall misses --- 16 unchanged lines hidden (view full) --- 1245system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1246system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1247system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1248system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1249system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1250system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1251system.iocache.writebacks::writebacks 36190 # number of writebacks 1252system.iocache.writebacks::total 36190 # number of writebacks |
| 1253system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1254system.l2c.tags.replacements 107745 # number of replacements 1255system.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use 1256system.l2c.tags.total_refs 243993 # Total number of references to valid blocks. 1257system.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks. 1258system.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks. 1259system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1260system.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor 1261system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor --- 17 unchanged lines hidden (view full) --- 1279system.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id 1280system.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id 1281system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id 1282system.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id 1283system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 1284system.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id 1285system.l2c.tags.tag_accesses 5181909 # Number of tag accesses 1286system.l2c.tags.data_accesses 5181909 # Number of data accesses |
| 1287system.l2c.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1288system.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits 1289system.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits 1290system.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits 1291system.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits 1292system.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits 1293system.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits 1294system.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits 1295system.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits --- 134 unchanged lines hidden (view full) --- 1430system.l2c.writebacks::writebacks 96240 # number of writebacks 1431system.l2c.writebacks::total 96240 # number of writebacks 1432system.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter. 1433system.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1434system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1435system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1436system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1437system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1438system.membus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1439system.membus.trans_dist::ReadReq 43996 # Transaction distribution 1440system.membus.trans_dist::ReadResp 75748 # Transaction distribution 1441system.membus.trans_dist::WriteReq 30846 # Transaction distribution 1442system.membus.trans_dist::WriteResp 30846 # Transaction distribution 1443system.membus.trans_dist::WritebackDirty 132430 # Transaction distribution 1444system.membus.trans_dist::CleanEvict 8725 # Transaction distribution 1445system.membus.trans_dist::UpgradeReq 60386 # Transaction distribution 1446system.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution --- 26 unchanged lines hidden (view full) --- 1473system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1474system.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram 1475system.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram 1476system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1477system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1478system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1479system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1480system.membus.snoop_fanout::total 537521 # Request fanout histogram |
| 1481system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1482system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1483system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1484system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1485system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1486system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1487system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1488system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1489system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1490system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1491system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1492system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1493system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 1494system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1495system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1496system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1497system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1498system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1499system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1500system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1501system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1502system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1503system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU --- 15 unchanged lines hidden (view full) --- 1519system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1520system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1521system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1522system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1523system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1524system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1525system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1526system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 1527system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1528system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1529system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1530system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1531system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1532system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1533system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1534system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1535system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1536system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1537system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 1538system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1539system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1540system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1541system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1542system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1543system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1544system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1545system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1546system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1547system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1548system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1549system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1550system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter. 1551system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1552system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1553system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter. 1554system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1555system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1556system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states |
| 1557system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 1558system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution 1559system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 1560system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 1561system.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution 1562system.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution 1563system.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution 1564system.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution --- 24 unchanged lines hidden --- |