1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802883 # Number of seconds simulated 4sim_ticks 2802882879000 # Number of ticks simulated 5final_tick 2802882879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 1338296 # Simulator instruction rate (inst/s) 8host_op_rate 1630694 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25547394462 # Simulator tick rate (ticks/s) 10host_mem_usage 592020 # Number of bytes of host memory used 11host_seconds 109.71 # Real time elapsed on the host |
12sim_insts 146828562 # Number of instructions simulated 13sim_ops 178908371 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1109732 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9413156 # Number of bytes read from this memory --- 340 unchanged lines hidden (view full) --- 360system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 361system.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 362system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
368system.cpu0.dcache.writebacks::writebacks 693475 # number of writebacks 369system.cpu0.dcache.writebacks::total 693475 # number of writebacks |
370system.cpu0.icache.tags.replacements 1109624 # number of replacements 371system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 372system.cpu0.icache.tags.total_refs 96331795 # Total number of references to valid blocks. 373system.cpu0.icache.tags.sampled_refs 1110136 # Sample count of references to valid blocks. 374system.cpu0.icache.tags.avg_refs 86.774769 # Average number of references to valid blocks. 375system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 376system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 377system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 408system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 409system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses 410system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 411system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 412system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 413system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 414system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 415system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
416system.cpu0.icache.writebacks::writebacks 1109624 # number of writebacks 417system.cpu0.icache.writebacks::total 1109624 # number of writebacks |
418system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 419system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 420system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 421system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 422system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 423system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 424system.cpu0.l2cache.tags.replacements 249486 # number of replacements 425system.cpu0.l2cache.tags.tagsinuse 16123.886747 # Cycle average of tags in use --- 118 unchanged lines hidden (view full) --- 544system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404291 # miss rate for overall accesses 545system.cpu0.l2cache.overall_miss_rate::total 0.184125 # miss rate for overall accesses 546system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 547system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 548system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 549system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 550system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 551system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
552system.cpu0.l2cache.writebacks::writebacks 193020 # number of writebacks 553system.cpu0.l2cache.writebacks::total 193020 # number of writebacks |
554system.cpu0.toL2Bus.snoop_filter.tot_requests 3720001 # Total number of requests made to the snoop filter. 555system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860202 # Number of requests hitting in the snoop filter with a single holder of the requested data. 556system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 557system.cpu0.toL2Bus.snoop_filter.tot_snoops 218277 # Total number of snoops made to the snoop filter. 558system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215192 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 559system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3085 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 560system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 561system.cpu0.toL2Bus.trans_dist::ReadResp 1651713 # Transaction distribution --- 300 unchanged lines hidden (view full) --- 862system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 863system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 864system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 865system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 866system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 867system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 868system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 869system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
870system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks 871system.cpu1.dcache.writebacks::total 191946 # number of writebacks |
872system.cpu1.icache.tags.replacements 523401 # number of replacements 873system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use 874system.cpu1.icache.tags.total_refs 53148863 # Total number of references to valid blocks. 875system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. 876system.cpu1.icache.tags.avg_refs 101.445971 # Average number of references to valid blocks. 877system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 878system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor 879system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy --- 29 unchanged lines hidden (view full) --- 909system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 910system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 911system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 912system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 913system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 914system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 915system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 916system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
917system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks 918system.cpu1.icache.writebacks::total 523401 # number of writebacks |
919system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 920system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 921system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 922system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 923system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 924system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 925system.cpu1.l2cache.tags.replacements 47378 # number of replacements 926system.cpu1.l2cache.tags.tagsinuse 15226.816500 # Cycle average of tags in use --- 117 unchanged lines hidden (view full) --- 1044system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496439 # miss rate for overall accesses 1045system.cpu1.l2cache.overall_miss_rate::total 0.171432 # miss rate for overall accesses 1046system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1047system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1048system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1049system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1050system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1051system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1052system.cpu1.l2cache.writebacks::writebacks 32706 # number of writebacks 1053system.cpu1.l2cache.writebacks::total 32706 # number of writebacks |
1054system.cpu1.toL2Bus.snoop_filter.tot_requests 1533509 # Total number of requests made to the snoop filter. 1055system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773310 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1056system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1057system.cpu1.toL2Bus.snoop_filter.tot_snoops 166217 # Total number of snoops made to the snoop filter. 1058system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164146 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1059system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2071 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1060system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution 1061system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution --- 93 unchanged lines hidden (view full) --- 1155system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1156system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1157system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1158system.iocache.tags.data_accesses 328284 # Number of data accesses 1159system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1160system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1161system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1162system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses |
1163system.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 1164system.iocache.demand_misses::total 36476 # number of demand (read+write) misses 1165system.iocache.overall_misses::realview.ide 36476 # number of overall misses 1166system.iocache.overall_misses::total 36476 # number of overall misses |
1167system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1168system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1169system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1170system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) |
1171system.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 1172system.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 1173system.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 1174system.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses |
1175system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1176system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1177system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1178system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1179system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1180system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1181system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1182system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1183system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1187system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1189system.iocache.writebacks::writebacks 36190 # number of writebacks 1190system.iocache.writebacks::total 36190 # number of writebacks |
1191system.l2c.tags.replacements 107729 # number of replacements 1192system.l2c.tags.tagsinuse 62410.633039 # Cycle average of tags in use 1193system.l2c.tags.total_refs 243914 # Total number of references to valid blocks. 1194system.l2c.tags.sampled_refs 168410 # Sample count of references to valid blocks. 1195system.l2c.tags.avg_refs 1.448334 # Average number of references to valid blocks. 1196system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1197system.l2c.tags.occ_blocks::writebacks 48132.772899 # Average occupied blocks per requestor 1198system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010469 # Average occupied blocks per requestor --- 159 unchanged lines hidden (view full) --- 1358system.l2c.overall_miss_rate::cpu1.data 0.534269 # miss rate for overall accesses 1359system.l2c.overall_miss_rate::total 0.565856 # miss rate for overall accesses 1360system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1361system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1362system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1363system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1364system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1365system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
1366system.l2c.writebacks::writebacks 96268 # number of writebacks 1367system.l2c.writebacks::total 96268 # number of writebacks |
1368system.membus.trans_dist::ReadReq 43996 # Transaction distribution 1369system.membus.trans_dist::ReadResp 75724 # Transaction distribution 1370system.membus.trans_dist::WriteReq 30846 # Transaction distribution 1371system.membus.trans_dist::WriteResp 30846 # Transaction distribution 1372system.membus.trans_dist::WritebackDirty 132458 # Transaction distribution 1373system.membus.trans_dist::CleanEvict 8718 # Transaction distribution 1374system.membus.trans_dist::UpgradeReq 60357 # Transaction distribution 1375system.membus.trans_dist::SCUpgradeReq 40887 # Transaction distribution --- 113 unchanged lines hidden --- |