Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt

Deleted Added

sdiff udiff text old ( 10628:c9b7e0c69f88 ) new ( 10726:8a20e2a1562d )

full compact

4,5c4,5
< sim_ticks 2802895103500 # Number of ticks simulated
< final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 2802894699500 # Number of ticks simulated
> final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 834307 # Simulator instruction rate (inst/s)
< host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 15926512431 # Simulator tick rate (ticks/s)
< host_mem_usage 572876 # Number of bytes of host memory used
< host_seconds 175.99 # Real time elapsed on the host
< sim_insts 146829031 # Number of instructions simulated
< sim_ops 178908942 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1337323 # Simulator instruction rate (inst/s)
> host_op_rate 1629508 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 25528979782 # Simulator tick rate (ticks/s)
> host_mem_usage 626168 # Number of bytes of host memory used
> host_seconds 109.79 # Real time elapsed on the host
> sim_insts 146828240 # Number of instructions simulated
> sim_ops 178908039 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu0.inst 1117604 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 9440956 # Number of bytes read from this memory
21,22c21,22
< system.physmem.bytes_read::cpu1.inst 152404 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 1082016 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu1.inst 152020 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 1081568 # Number of bytes read from this memory
24,28c24,28
< system.physmem.bytes_read::total 11794004 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 1117540 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 152404 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 1269944 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8387200 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 11793812 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 1117604 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 152020 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 1269624 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8390656 # Number of bytes written to this memory
31c31
< system.physmem.bytes_written::total 8404944 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8408400 # Number of bytes written to this memory
34,35c34,35
< system.physmem.num_reads::cpu0.inst 25915 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 148031 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu0.inst 25916 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 148040 # Number of read requests responded to by this memory
37,38c37,38
< system.physmem.num_reads::cpu1.inst 2536 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 16930 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu1.inst 2530 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 16923 # Number of read requests responded to by this memory
40,41c40,41
< system.physmem.num_reads::total 193438 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 131050 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 193435 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 131104 # Number of write requests responded to by this memory
44c44
< system.physmem.num_writes::total 135486 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 135540 # Number of write requests responded to by this memory
47,48c47,48
< system.physmem.bw_read::cpu0.inst 398709 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 3368082 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu0.inst 398732 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 3368288 # Total read bandwidth from this memory (bytes/s)
50,51c50,51
< system.physmem.bw_read::cpu1.inst 54374 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 386035 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu1.inst 54237 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 385875 # Total read bandwidth from this memory (bytes/s)
53,57c53,57
< system.physmem.bw_read::total 4207794 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 398709 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 54374 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 453083 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 2992335 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::total 4207726 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 398732 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 54237 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 452969 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2993568 # Write bandwidth from this memory (bytes/s)
60,61c60,61
< system.physmem.bw_write::total 2998665 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 2992335 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::total 2999899 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2993568 # Total bandwidth to/from this memory (bytes/s)
64,65c64,65
< system.physmem.bw_total::cpu0.inst 398709 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 3374398 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu0.inst 398732 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 3374604 # Total bandwidth to/from this memory (bytes/s)
67,68c67,68
< system.physmem.bw_total::cpu1.inst 54374 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 386049 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu1.inst 54237 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 385890 # Total bandwidth to/from this memory (bytes/s)
70c70
< system.physmem.bw_total::total 7206459 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::total 7207624 # Total bandwidth to/from this memory (bytes/s)
145c145
< system.cpu0.dtb.read_hits 20339962 # DTB read hits
---
> system.cpu0.dtb.read_hits 20339720 # DTB read hits
147c147
< system.cpu0.dtb.write_hits 16391171 # DTB write hits
---
> system.cpu0.dtb.write_hits 16391078 # DTB write hits
158,159c158,159
< system.cpu0.dtb.read_accesses 20346836 # DTB read accesses
< system.cpu0.dtb.write_accesses 16392264 # DTB write accesses
---
> system.cpu0.dtb.read_accesses 20346594 # DTB read accesses
> system.cpu0.dtb.write_accesses 16392171 # DTB write accesses
161c161
< system.cpu0.dtb.hits 36731133 # DTB hits
---
> system.cpu0.dtb.hits 36730798 # DTB hits
163c163
< system.cpu0.dtb.accesses 36739100 # DTB accesses
---
> system.cpu0.dtb.accesses 36738765 # DTB accesses
211c211
< system.cpu0.itb.inst_hits 97440315 # ITB inst hits
---
> system.cpu0.itb.inst_hits 97439331 # ITB inst hits
228,229c228,229
< system.cpu0.itb.inst_accesses 97443673 # ITB inst accesses
< system.cpu0.itb.hits 97440315 # DTB hits
---
> system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses
> system.cpu0.itb.hits 97439331 # DTB hits
231,232c231,232
< system.cpu0.itb.accesses 97443673 # DTB accesses
< system.cpu0.numCycles 5605792176 # number of cpu cycles simulated
---
> system.cpu0.itb.accesses 97442689 # DTB accesses
> system.cpu0.numCycles 5605791368 # number of cpu cycles simulated
235,237c235,237
< system.cpu0.committedInsts 95427853 # Number of instructions committed
< system.cpu0.committedOps 115561498 # Number of ops (including micro ops) committed
< system.cpu0.num_int_alu_accesses 100763618 # Number of integer alu accesses
---
> system.cpu0.committedInsts 95426926 # Number of instructions committed
> system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed
> system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses
239,241c239,241
< system.cpu0.num_func_calls 8000324 # number of times a function call or return occured
< system.cpu0.num_conditional_control_insts 13204344 # number of instructions that are conditional controls
< system.cpu0.num_int_insts 100763618 # number of integer instructions
---
> system.cpu0.num_func_calls 8000180 # number of times a function call or return occured
> system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls
> system.cpu0.num_int_insts 100762696 # number of integer instructions
243,244c243,244
< system.cpu0.num_int_register_reads 182459108 # number of times the integer registers were read
< system.cpu0.num_int_register_writes 69136203 # number of times the integer registers were written
---
> system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read
> system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written
247,253c247,253
< system.cpu0.num_cc_register_reads 349974767 # number of times the CC registers were read
< system.cpu0.num_cc_register_writes 44907843 # number of times the CC registers were written
< system.cpu0.num_mem_refs 37874145 # number of memory refs
< system.cpu0.num_load_insts 20597552 # Number of load instructions
< system.cpu0.num_store_insts 17276593 # Number of store instructions
< system.cpu0.num_idle_cycles 5488206556.246817 # Number of idle cycles
< system.cpu0.num_busy_cycles 117585619.753183 # Number of busy cycles
---
> system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read
> system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written
> system.cpu0.num_mem_refs 37873810 # number of memory refs
> system.cpu0.num_load_insts 20597310 # Number of load instructions
> system.cpu0.num_store_insts 17276500 # Number of store instructions
> system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles
> system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles
256c256
< system.cpu0.Branches 21941792 # Number of branches fetched
---
> system.cpu0.Branches 21941499 # Number of branches fetched
258c258
< system.cpu0.op_class::IntAlu 78888049 67.49% 67.50% # Class of executed instruction
---
> system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction
287,288c287,288
< system.cpu0.op_class::MemRead 20597552 17.62% 85.22% # Class of executed instruction
< system.cpu0.op_class::MemWrite 17276593 14.78% 100.00% # Class of executed instruction
---
> system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction
> system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction
291c291
< system.cpu0.op_class::total 116883193 # Class of executed instruction
---
> system.cpu0.op_class::total 116882065 # Class of executed instruction
294,298c294,298
< system.cpu0.dcache.tags.replacements 693476 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 494.853661 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 35932684 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 693988 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 51.777097 # Average number of references to valid blocks.
---
> system.cpu0.dcache.tags.replacements 693477 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 494.853657 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 35932369 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 693989 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 51.776569 # Average number of references to valid blocks.
300c300
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853661 # Average occupied blocks per requestor
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853657 # Average occupied blocks per requestor
308,313c308,313
< system.cpu0.dcache.tags.tag_accesses 74114402 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 74114402 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 19108775 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 19108775 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 15690454 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 15690454 # number of WriteReq hits
---
> system.cpu0.dcache.tags.tag_accesses 74113775 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 74113775 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 19108539 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 19108539 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 15690376 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 15690376 # number of WriteReq hits
318,327c318,327
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363052 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 363052 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 34799229 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 34799229 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 35145322 # number of overall hits
< system.cpu0.dcache.overall_hits::total 35145322 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 373098 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 373098 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 295765 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 295765 # number of WriteReq misses
---
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363049 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 363049 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 34798915 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 34798915 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 35145008 # number of overall hits
> system.cpu0.dcache.overall_hits::total 35145008 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 373099 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 373099 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 295764 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 295764 # number of WriteReq misses
332,333c332,333
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18433 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 18433 # number of StoreCondReq misses
---
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18436 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 18436 # number of StoreCondReq misses
338,341c338,341
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481873 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 19481873 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986219 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 15986219 # number of WriteReq accesses(hits+misses)
---
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481638 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 19481638 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986140 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 15986140 # number of WriteReq accesses(hits+misses)
348,351c348,351
< system.cpu0.dcache.demand_accesses::cpu0.data 35468092 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 35468092 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 35914506 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 35914506 # number of overall (read+write) accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 35467778 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 35467778 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses
360,361c360,361
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048319 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048319 # miss rate for StoreCondReq accesses
---
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048327 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048327 # miss rate for StoreCondReq accesses
374,375c374,375
< system.cpu0.dcache.writebacks::writebacks 511648 # number of writebacks
< system.cpu0.dcache.writebacks::total 511648 # number of writebacks
---
> system.cpu0.dcache.writebacks::writebacks 511896 # number of writebacks
> system.cpu0.dcache.writebacks::total 511896 # number of writebacks
377c377
< system.cpu0.icache.tags.replacements 1109742 # number of replacements
---
> system.cpu0.icache.tags.replacements 1109735 # number of replacements
379,381c379,381
< system.cpu0.icache.tags.total_refs 96332394 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 1110254 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 86.766086 # Average number of references to valid blocks.
---
> system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks.
391,410c391,410
< system.cpu0.icache.tags.tag_accesses 195995577 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 195995577 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 96332394 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 96332394 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 96332394 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 96332394 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 96332394 # number of overall hits
< system.cpu0.icache.overall_hits::total 96332394 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 1110263 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 1110263 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 1110263 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 1110263 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 1110263 # number of overall misses
< system.cpu0.icache.overall_misses::total 1110263 # number of overall misses
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 97442657 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 97442657 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 97442657 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 97442657 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 97442657 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 97442657 # number of overall (read+write) accesses
---
> system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits
> system.cpu0.icache.overall_hits::total 96331417 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses
> system.cpu0.icache.overall_misses::total 1110256 # number of overall misses
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses
432,436c432,436
< system.cpu0.l2cache.tags.replacements 252403 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks.
---
> system.cpu0.l2cache.tags.replacements 252330 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16129.294754 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 1810154 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 268529 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 6.741000 # Average number of references to valid blocks.
438,449c438,449
< system.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.086115 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.591048 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.325333 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.492437 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289831 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201985 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.984453 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_blocks::writebacks 8067.926153 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.192846 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.094111 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.670375 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.411269 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.492427 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289836 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201990 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.984454 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
451,459c451,459
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5587 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7674 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2571 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5555 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7641 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2632 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id
461,469c461,469
< system.cpu0.l2cache.tags.tag_accesses 39450391 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 39450391 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7605 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3248 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065251 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.data 352125 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 1428229 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 511648 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 511648 # number of Writeback hits
---
> system.cpu0.l2cache.tags.tag_accesses 39452382 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 39452382 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7540 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3225 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065497 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.data 351995 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 1428257 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 511896 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 511896 # number of Writeback hits
472,515c472,515
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94130 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 94130 # number of ReadExReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7605 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3248 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 1065251 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 446255 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 1522359 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7605 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3248 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 1065251 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 446255 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 1522359 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 134 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.inst 45012 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.data 128036 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 173407 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18433 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 18433 # number of SCUpgradeReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175387 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 175387 # number of ReadExReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 134 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 45012 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 303423 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 348794 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 134 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 45012 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 303423 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 348794 # number of overall misses
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7830 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3382 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110263 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480161 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 1601636 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 511648 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 511648 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18433 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 18433 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94089 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 94089 # number of ReadExReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7540 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3225 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 1065497 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 446084 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 1522346 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7540 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3225 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 1065497 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 446084 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 1522346 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 210 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44759 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.data 128167 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 173260 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26230 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 26230 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18436 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 18436 # number of SCUpgradeReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 210 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 44759 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 303595 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 348688 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 210 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 44759 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 303595 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 348688 # number of overall misses
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7750 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3349 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480162 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 1601517 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 511896 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 511896 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26247 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 26247 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18436 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 18436 # number of SCUpgradeReq accesses(hits+misses)
518,532c518,532
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7830 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3382 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 1110263 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 1871153 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7830 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3382 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 1110263 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 1871153 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039622 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040542 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266652 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.108269 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7750 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3349 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 749679 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 1871034 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7750 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3349 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 749679 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 1871034 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037026 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040314 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266924 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.108185 # miss rate for ReadReq accesses
537,548c537,548
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650746 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650746 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039622 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040542 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404738 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.186406 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039622 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040542 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404738 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.186406 # miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650898 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650898 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037026 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040314 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404967 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037026 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040314 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404967 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses
557,558c557,558
< system.cpu0.l2cache.writebacks::writebacks 192841 # number of writebacks
< system.cpu0.l2cache.writebacks::total 192841 # number of writebacks
---
> system.cpu0.l2cache.writebacks::writebacks 192974 # number of writebacks
> system.cpu0.l2cache.writebacks::total 192974 # number of writebacks
560,567c560,567
< system.cpu0.toL2Bus.trans_dist::ReadReq 1651853 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 1651853 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 511648 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18433 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 44681 # Transaction distribution
---
> system.cpu0.toL2Bus.trans_dist::ReadReq 1651840 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 1651840 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 28386 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 28386 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 511896 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 26247 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18436 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 44683 # Transaction distribution
570,571c570,571
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238570 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220344 # Packet count per connected master and slave (bytes)
---
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220556 # Packet count per connected master and slave (bytes)
574,576c574,576
< system.cpu0.toL2Bus.pkt_count::total 4500550 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092920 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80915642 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu0.toL2Bus.pkt_count::total 4500748 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80931536 # Cumulative packet size per connected master and slave (bytes)
579,583c579,583
< system.cpu0.toL2Bus.pkt_size::total 152091834 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 322042 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 2656528 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 5.082604 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.275283 # Request fanout histogram
---
> system.cpu0.toL2Bus.pkt_size::total 152107280 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 322019 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 2656743 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 3.082586 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.275256 # Request fanout histogram
588,591c588,589
< system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::3 2437332 91.74% 91.74% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::4 219411 8.26% 100.00% # Request fanout histogram
593,595c591,593
< system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::total 2656743 # Request fanout histogram
645c643
< system.cpu1.dtb.read_hits 12173884 # DTB read hits
---
> system.cpu1.dtb.read_hits 12173916 # DTB read hits
647c645
< system.cpu1.dtb.write_hits 7587193 # DTB write hits
---
> system.cpu1.dtb.write_hits 7587209 # DTB write hits
658,659c656,657
< system.cpu1.dtb.read_accesses 12176736 # DTB read accesses
< system.cpu1.dtb.write_accesses 7587699 # DTB write accesses
---
> system.cpu1.dtb.read_accesses 12176768 # DTB read accesses
> system.cpu1.dtb.write_accesses 7587715 # DTB write accesses
661c659
< system.cpu1.dtb.hits 19761077 # DTB hits
---
> system.cpu1.dtb.hits 19761125 # DTB hits
663c661
< system.cpu1.dtb.accesses 19764435 # DTB accesses
---
> system.cpu1.dtb.accesses 19764483 # DTB accesses
711c709
< system.cpu1.itb.inst_hits 53671431 # ITB inst hits
---
> system.cpu1.itb.inst_hits 53671575 # ITB inst hits
728,729c726,727
< system.cpu1.itb.inst_accesses 53673165 # ITB inst accesses
< system.cpu1.itb.hits 53671431 # DTB hits
---
> system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses
> system.cpu1.itb.hits 53671575 # DTB hits
731,732c729,730
< system.cpu1.itb.accesses 53673165 # DTB accesses
< system.cpu1.numCycles 5605321082 # number of cpu cycles simulated
---
> system.cpu1.itb.accesses 53673309 # DTB accesses
> system.cpu1.numCycles 5605320274 # number of cpu cycles simulated
735,737c733,735
< system.cpu1.committedInsts 51401178 # Number of instructions committed
< system.cpu1.committedOps 63347444 # Number of ops (including micro ops) committed
< system.cpu1.num_int_alu_accesses 56984089 # Number of integer alu accesses
---
> system.cpu1.committedInsts 51401314 # Number of instructions committed
> system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed
> system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses
739,741c737,739
< system.cpu1.num_func_calls 9170823 # number of times a function call or return occured
< system.cpu1.num_conditional_control_insts 5967084 # number of instructions that are conditional controls
< system.cpu1.num_int_insts 56984089 # number of integer instructions
---
> system.cpu1.num_func_calls 9170855 # number of times a function call or return occured
> system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls
> system.cpu1.num_int_insts 56984241 # number of integer instructions
743,744c741,742
< system.cpu1.num_int_register_reads 110674435 # number of times the integer registers were read
< system.cpu1.num_int_register_writes 41298241 # number of times the integer registers were written
---
> system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read
> system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written
747,753c745,751
< system.cpu1.num_cc_register_reads 196268127 # number of times the CC registers were read
< system.cpu1.num_cc_register_writes 18894317 # number of times the CC registers were written
< system.cpu1.num_mem_refs 20026333 # number of memory refs
< system.cpu1.num_load_insts 12289505 # Number of load instructions
< system.cpu1.num_store_insts 7736828 # Number of store instructions
< system.cpu1.num_idle_cycles 5539707743.549846 # Number of idle cycles
< system.cpu1.num_busy_cycles 65613338.450155 # Number of busy cycles
---
> system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read
> system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written
> system.cpu1.num_mem_refs 20026381 # number of memory refs
> system.cpu1.num_load_insts 12289537 # Number of load instructions
> system.cpu1.num_store_insts 7736844 # Number of store instructions
> system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles
> system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles
756c754
< system.cpu1.Branches 15217445 # Number of branches fetched
---
> system.cpu1.Branches 15217493 # Number of branches fetched
758c756
< system.cpu1.op_class::IntAlu 45401182 69.36% 69.36% # Class of executed instruction
---
> system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction
787,788c785,786
< system.cpu1.op_class::MemRead 12289505 18.77% 88.18% # Class of executed instruction
< system.cpu1.op_class::MemWrite 7736828 11.82% 100.00% # Class of executed instruction
---
> system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction
> system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction
791c789
< system.cpu1.op_class::total 65459288 # Class of executed instruction
---
> system.cpu1.op_class::total 65459464 # Class of executed instruction
795,796c793,794
< system.cpu1.dcache.tags.tagsinuse 472.735401 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 19503461 # Total number of references to valid blocks.
---
> system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks.
798c796
< system.cpu1.dcache.tags.avg_refs 101.426274 # Average number of references to valid blocks.
---
> system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks.
800c798
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735401 # Average occupied blocks per requestor
---
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor
807,812c805,810
< system.cpu1.dcache.tags.tag_accesses 39751883 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 39751883 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 11858662 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 11858662 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 7397475 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 7397475 # number of WriteReq hits
---
> system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 7397494 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 7397494 # number of WriteReq hits
817,822c815,820
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72435 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 72435 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 19256137 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 19256137 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 19306236 # number of overall hits
< system.cpu1.dcache.overall_hits::total 19306236 # number of overall hits
---
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72460 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 72460 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 19256188 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 19256188 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 19306287 # number of overall hits
> system.cpu1.dcache.overall_hits::total 19306287 # number of overall hits
825,826c823,824
< system.cpu1.dcache.WriteReq_misses::cpu1.data 92471 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 92471 # number of WriteReq misses
---
> system.cpu1.dcache.WriteReq_misses::cpu1.data 92468 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 92468 # number of WriteReq misses
831,840c829,838
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22544 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 22544 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 229101 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 229101 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 259820 # number of overall misses
< system.cpu1.dcache.overall_misses::total 259820 # number of overall misses
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995292 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 11995292 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489946 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 7489946 # number of WriteReq accesses(hits+misses)
---
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22519 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 22519 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 229098 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 229098 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses
> system.cpu1.dcache.overall_misses::total 259817 # number of overall misses
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses)
847,850c845,848
< system.cpu1.dcache.demand_accesses::cpu1.data 19485238 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 19485238 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 19566056 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 19566056 # number of overall (read+write) accesses
---
> system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses
859,862c857,860
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237358 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237358 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses
---
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237095 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237095 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
873,874c871,872
< system.cpu1.dcache.writebacks::writebacks 120709 # number of writebacks
< system.cpu1.dcache.writebacks::total 120709 # number of writebacks
---
> system.cpu1.dcache.writebacks::writebacks 120855 # number of writebacks
> system.cpu1.dcache.writebacks::total 120855 # number of writebacks
877,878c875,876
< system.cpu1.icache.tags.tagsinuse 499.711131 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 53148636 # Total number of references to valid blocks.
---
> system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks.
880c878
< system.cpu1.icache.tags.avg_refs 101.450960 # Average number of references to valid blocks.
---
> system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks.
882c880
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711131 # Average occupied blocks per requestor
---
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor
889,896c887,894
< system.cpu1.icache.tags.tag_accesses 107868927 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 107868927 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 53148636 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 53148636 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 53148636 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 53148636 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 53148636 # number of overall hits
< system.cpu1.icache.overall_hits::total 53148636 # number of overall hits
---
> system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits
> system.cpu1.icache.overall_hits::total 53148780 # number of overall hits
903,908c901,906
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672521 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 53672521 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 53672521 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 53672521 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 53672521 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 53672521 # number of overall (read+write) accesses
---
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses
930,934c928,932
< system.cpu1.l2cache.tags.replacements 48598 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.tags.replacements 48604 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 15305.333897 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 716708 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 11.298662 # Average number of references to valid blocks.
936,940c934,938
< system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030831 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.951411 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.465503 # Average occupied blocks per requestor
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809694 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.091002 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.023143 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.979607 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.430451 # Average occupied blocks per requestor
942,948c940,946
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200131 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225370 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.934164 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14799 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200133 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225368 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.934163 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14807 # Occupied blocks per task id
950,951c948,949
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
953,965c951,963
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9279 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4981 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903259 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 15211446 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 15211446 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3145 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1724 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510078 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.data 99331 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 614278 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 120709 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 120709 # number of Writeback hits
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9357 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4911 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903748 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 15213345 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 15213345 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3151 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1735 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510036 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.data 99375 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 614297 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 120855 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 120855 # number of Writeback hits
968,1000c966,998
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19802 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 19802 # number of ReadExReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3145 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1724 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 510078 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 119133 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 634080 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3145 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1724 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 510078 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 119133 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 634080 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13807 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.data 73336 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 87759 # number of ReadReq misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28847 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 28847 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22544 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 22544 # number of SCUpgradeReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43814 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 43814 # number of ReadExReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 13807 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 117150 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 13807 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 117150 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses
---
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19784 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 19784 # number of ReadExReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3151 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1735 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 510036 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 119159 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 634081 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3151 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1735 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 510036 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 119159 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 634081 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 261 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13849 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.data 73292 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 87740 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28844 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 28844 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22519 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 22519 # number of SCUpgradeReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43832 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 43832 # number of ReadExReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 261 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 13849 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 117124 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 131572 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 261 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 13849 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 117124 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 131572 # number of overall misses
1006,1011c1004,1009
< system.cpu1.l2cache.Writeback_accesses::writebacks 120709 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 120709 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28855 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 28855 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22544 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 22544 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu1.l2cache.Writeback_accesses::writebacks 120855 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 120855 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28852 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 28852 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22519 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 22519 # number of SCUpgradeReq accesses(hits+misses)
1024,1028c1022,1026
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136273 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026355 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424725 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.125006 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.130762 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026435 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424470 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.124979 # miss rate for ReadReq accesses
1033,1044c1031,1042
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688726 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688726 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136273 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026355 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495804 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.171844 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136273 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026355 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495804 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.171844 # miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689009 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689009 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.130762 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026435 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495694 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.171843 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.130762 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026435 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495694 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.171843 # miss rate for overall accesses
1053,1054c1051,1052
< system.cpu1.l2cache.writebacks::writebacks 32919 # number of writebacks
< system.cpu1.l2cache.writebacks::total 32919 # number of writebacks
---
> system.cpu1.l2cache.writebacks::writebacks 32977 # number of writebacks
> system.cpu1.l2cache.writebacks::total 32977 # number of writebacks
1060,1063c1058,1061
< system.cpu1.toL2Bus.trans_dist::Writeback 120709 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 28855 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22544 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 51399 # Transaction distribution
---
> system.cpu1.toL2Bus.trans_dist::Writeback 120855 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 28852 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22519 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 51371 # Transaction distribution
1067c1065
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707533 # Packet count per connected master and slave (bytes)
---
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707623 # Packet count per connected master and slave (bytes)
1070c1068
< system.cpu1.toL2Bus.pkt_count::total 1774351 # Packet count per connected master and slave (bytes)
---
> system.cpu1.toL2Bus.pkt_count::total 1774441 # Packet count per connected master and slave (bytes)
1072c1070
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866670 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22876014 # Cumulative packet size per connected master and slave (bytes)
1075,1079c1073,1077
< system.cpu1.toL2Bus.pkt_size::total 56433406 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 499587 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 1371557 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 5.313464 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.463901 # Request fanout histogram
---
> system.cpu1.toL2Bus.pkt_size::total 56442750 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 499492 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 1371571 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 3.313385 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.463870 # Request fanout histogram
1084,1087c1082,1083
< system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::5 941623 68.65% 68.65% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::6 429934 31.35% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::3 941741 68.66% 68.66% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::4 429830 31.34% 100.00% # Request fanout histogram
1089,1095c1085,1091
< system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::total 1371557 # Request fanout histogram
< system.iobus.trans_dist::ReadReq 31002 # Transaction distribution
< system.iobus.trans_dist::ReadResp 31002 # Transaction distribution
< system.iobus.trans_dist::WriteReq 59433 # Transaction distribution
< system.iobus.trans_dist::WriteResp 23209 # Transaction distribution
---
> system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::total 1371571 # Request fanout histogram
> system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
> system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
> system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
> system.iobus.trans_dist::WriteResp 23195 # Transaction distribution
1097c1093
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes)
1118c1114
< system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes)
1121,1122c1117,1118
< system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes)
1143c1139
< system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes)
1146c1142
< system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes)
1196,1200c1192,1196
< system.l2c.tags.replacements 107620 # number of replacements
< system.l2c.tags.tagsinuse 62052.354763 # Cycle average of tags in use
< system.l2c.tags.total_refs 207975 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 168018 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 1.237814 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 107683 # number of replacements
> system.l2c.tags.tagsinuse 62052.473518 # Cycle average of tags in use
> system.l2c.tags.total_refs 207875 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 168125 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 1.236431 # Average number of references to valid blocks.
1202,1203c1198,1199
< system.l2c.tags.occ_blocks::writebacks 48595.577563 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.970677 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::writebacks 48595.677496 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972785 # Average occupied blocks per requestor
1205,1206c1201,1202
< system.l2c.tags.occ_blocks::cpu0.inst 7329.733330 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 3756.722499 # Average occupied blocks per requestor
---
> system.l2c.tags.occ_blocks::cpu0.inst 7329.722723 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 3756.747244 # Average occupied blocks per requestor
1208,1210c1204,1206
< system.l2c.tags.occ_blocks::cpu1.inst 1654.519056 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 710.978017 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.741510 # Average percentage of cache occupancy
---
> system.l2c.tags.occ_blocks::cpu1.inst 1654.505866 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 710.993782 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.741511 # Average percentage of cache occupancy
1218,1268c1214,1264
< system.l2c.tags.occ_percent::total 0.946844 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 60392 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 1918 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 45390 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.921509 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 4903951 # Number of tag accesses
< system.l2c.tags.data_accesses 4903951 # Number of data accesses
< system.l2c.ReadReq_hits::cpu0.dtb.walker 85 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.itb.walker 75 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.inst 28112 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu0.data 75977 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.dtb.walker 41 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.itb.walker 36 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.inst 11436 # number of ReadReq hits
< system.l2c.ReadReq_hits::cpu1.data 11429 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 127191 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 225760 # number of Writeback hits
< system.l2c.Writeback_hits::total 225760 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 516 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 573 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 13918 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 3099 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 17017 # number of ReadExReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 85 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 28112 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 89895 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 41 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 11436 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 14528 # number of demand (read+write) hits
< system.l2c.demand_hits::total 144208 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 85 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 28112 # number of overall hits
< system.l2c.overall_hits::cpu0.data 89895 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 41 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 11436 # number of overall hits
< system.l2c.overall_hits::cpu1.data 14528 # number of overall hits
< system.l2c.overall_hits::total 144208 # number of overall hits
---
> system.l2c.tags.occ_percent::total 0.946846 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 60435 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 1875 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 13095 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.922165 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 4904261 # Number of tag accesses
> system.l2c.tags.data_accesses 4904261 # Number of data accesses
> system.l2c.ReadReq_hits::cpu0.dtb.walker 71 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.inst 27858 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu0.data 76068 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.dtb.walker 39 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.itb.walker 20 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.inst 11484 # number of ReadReq hits
> system.l2c.ReadReq_hits::cpu1.data 11410 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 127013 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 225951 # number of Writeback hits
> system.l2c.Writeback_hits::total 225951 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 487 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 552 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 64 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 13938 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 3112 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 17050 # number of ReadExReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 27858 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 90006 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 39 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 11484 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 14522 # number of demand (read+write) hits
> system.l2c.demand_hits::total 144063 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 27858 # number of overall hits
> system.l2c.overall_hits::cpu0.data 90006 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 39 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 11484 # number of overall hits
> system.l2c.overall_hits::cpu1.data 14522 # number of overall hits
> system.l2c.overall_hits::total 144063 # number of overall hits
1271,1272c1267,1268
< system.l2c.ReadReq_misses::cpu0.inst 16900 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu0.data 11311 # number of ReadReq misses
---
> system.l2c.ReadReq_misses::cpu0.inst 16901 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu0.data 11313 # number of ReadReq misses
1274,1285c1270,1281
< system.l2c.ReadReq_misses::cpu1.inst 2371 # number of ReadReq misses
< system.l2c.ReadReq_misses::cpu1.data 1120 # number of ReadReq misses
< system.l2c.ReadReq_misses::total 31713 # number of ReadReq misses
< system.l2c.UpgradeReq_misses::cpu0.data 9991 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 3299 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 13290 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 771 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 1177 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1948 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 15826 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 152622 # number of ReadExReq misses
---
> system.l2c.ReadReq_misses::cpu1.inst 2365 # number of ReadReq misses
> system.l2c.ReadReq_misses::cpu1.data 1118 # number of ReadReq misses
> system.l2c.ReadReq_misses::total 31708 # number of ReadReq misses
> system.l2c.UpgradeReq_misses::cpu0.data 10019 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 3288 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 13307 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 752 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1179 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1931 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 136795 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 15822 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 152617 # number of ReadExReq misses
1288,1289c1284,1285
< system.l2c.demand_misses::cpu0.inst 16900 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 148107 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu0.inst 16901 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 148108 # number of demand (read+write) misses
1291,1293c1287,1289
< system.l2c.demand_misses::cpu1.inst 2371 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 16946 # number of demand (read+write) misses
< system.l2c.demand_misses::total 184335 # number of demand (read+write) misses
---
> system.l2c.demand_misses::cpu1.inst 2365 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 16940 # number of demand (read+write) misses
> system.l2c.demand_misses::total 184325 # number of demand (read+write) misses
1296,1297c1292,1293
< system.l2c.overall_misses::cpu0.inst 16900 # number of overall misses
< system.l2c.overall_misses::cpu0.data 148107 # number of overall misses
---
> system.l2c.overall_misses::cpu0.inst 16901 # number of overall misses
> system.l2c.overall_misses::cpu0.data 148108 # number of overall misses
1299,1372c1295,1368
< system.l2c.overall_misses::cpu1.inst 2371 # number of overall misses
< system.l2c.overall_misses::cpu1.data 16946 # number of overall misses
< system.l2c.overall_misses::total 184335 # number of overall misses
< system.l2c.ReadReq_accesses::cpu0.dtb.walker 92 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.itb.walker 77 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.inst 45012 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu0.data 87288 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.dtb.walker 43 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.itb.walker 36 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.inst 13807 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::cpu1.data 12549 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 158904 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 225760 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 225760 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 10507 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 3356 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 823 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 2009 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 150714 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 18925 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 169639 # number of ReadExReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 92 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 45012 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 238002 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 13807 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 31474 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 328543 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 92 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 45012 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 238002 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 13807 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 31474 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 328543 # number of overall (read+write) accesses
< system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.inst 0.375455 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu0.data 0.129583 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.inst 0.171724 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::cpu1.data 0.089250 # miss rate for ReadReq accesses
< system.l2c.ReadReq_miss_rate::total 0.199573 # miss rate for ReadReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950890 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.983015 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.958667 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.936817 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992411 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.969637 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.907653 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.836248 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.899687 # miss rate for ReadExReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.375455 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.622293 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.171724 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.538413 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.561068 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.375455 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.622293 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.171724 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.538413 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.561068 # miss rate for overall accesses
---
> system.l2c.overall_misses::cpu1.inst 2365 # number of overall misses
> system.l2c.overall_misses::cpu1.data 16940 # number of overall misses
> system.l2c.overall_misses::total 184325 # number of overall misses
> system.l2c.ReadReq_accesses::cpu0.dtb.walker 78 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.inst 44759 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu0.data 87381 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.dtb.walker 41 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.itb.walker 20 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.inst 13849 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::cpu1.data 12528 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 158721 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 225951 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 225951 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 10506 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 3353 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 13859 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 816 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 1189 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 150733 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 18934 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 169667 # number of ReadExReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 78 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 44759 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 238114 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 13849 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 31462 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 328388 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 78 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 44759 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 238114 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 13849 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 31462 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 328388 # number of overall (read+write) accesses
> system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.inst 0.377600 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu0.data 0.129468 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.inst 0.170770 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::cpu1.data 0.089240 # miss rate for ReadReq accesses
> system.l2c.ReadReq_miss_rate::total 0.199772 # miss rate for ReadReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.953646 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980614 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.960170 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921569 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.991590 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.963092 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.907532 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.835640 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.899509 # miss rate for ReadExReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.377600 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.622005 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.170770 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.538427 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.561302 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.377600 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.622005 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.170770 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.538427 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.561302 # miss rate for overall accesses
1381,1382c1377,1378
< system.l2c.writebacks::writebacks 94860 # number of writebacks
< system.l2c.writebacks::total 94860 # number of writebacks
---
> system.l2c.writebacks::writebacks 94914 # number of writebacks
> system.l2c.writebacks::total 94914 # number of writebacks
1384,1388c1380,1384
< system.membus.trans_dist::ReadReq 75978 # Transaction distribution
< system.membus.trans_dist::ReadResp 75978 # Transaction distribution
< system.membus.trans_dist::WriteReq 30905 # Transaction distribution
< system.membus.trans_dist::WriteResp 30905 # Transaction distribution
< system.membus.trans_dist::Writeback 131050 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 75966 # Transaction distribution
> system.membus.trans_dist::ReadResp 75966 # Transaction distribution
> system.membus.trans_dist::WriteReq 30891 # Transaction distribution
> system.membus.trans_dist::WriteResp 30891 # Transaction distribution
> system.membus.trans_dist::Writeback 131104 # Transaction distribution
1391,1396c1387,1392
< system.membus.trans_dist::UpgradeReq 60385 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 40916 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 15642 # Transaction distribution
< system.membus.trans_dist::ReadExReq 196304 # Transaction distribution
< system.membus.trans_dist::ReadExResp 152218 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::UpgradeReq 60393 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 40881 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 15635 # Transaction distribution
> system.membus.trans_dist::ReadExReq 196339 # Transaction distribution
> system.membus.trans_dist::ReadExResp 152220 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes)
1399,1400c1395,1396
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652161 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 773587 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652208 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 773592 # Packet count per connected master and slave (bytes)
1403,1404c1399,1400
< system.membus.pkt_count::total 882729 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count::total 882734 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes)
1407,1408c1403,1404
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17899556 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 18089380 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17902820 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 18092602 # Cumulative packet size per connected master and slave (bytes)
1411c1407
< system.membus.pkt_size::total 22740004 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size::total 22743226 # Cumulative packet size per connected master and slave (bytes)
1413c1409
< system.membus.snoop_fanout::samples 496844 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 496901 # Request fanout histogram
1418c1414
< system.membus.snoop_fanout::1 496844 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 496901 100.00% 100.00% # Request fanout histogram
1423c1419
< system.membus.snoop_fanout::total 496844 # Request fanout histogram
---
> system.membus.snoop_fanout::total 496901 # Request fanout histogram
1455,1465c1451,1461
< system.toL2Bus.trans_dist::ReadReq 305179 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 305179 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 225760 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 60554 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 40977 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 101531 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 213725 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 213725 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117779 # Packet count per connected master and slave (bytes)
---
> system.toL2Bus.trans_dist::ReadReq 305006 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 305006 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 30891 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 30891 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 225951 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 40955 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 101503 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117662 # Packet count per connected master and slave (bytes)
1467,1470c1463,1466
< system.toL2Bus.pkt_count::total 1528440 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34662706 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425714 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 45088420 # Cumulative packet size per connected master and slave (bytes)
---
> system.toL2Bus.pkt_count::total 1528323 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664008 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10429874 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 45093882 # Cumulative packet size per connected master and slave (bytes)
1472,1474c1468,1470
< system.toL2Bus.snoop_fanout::samples 838658 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.043493 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.203965 # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::samples 838716 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 1.043490 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.203958 # Request fanout histogram
1477c1473
< system.toL2Bus.snoop_fanout::1 802182 95.65% 95.65% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::1 802240 95.65% 95.65% # Request fanout histogram
1482c1478
< system.toL2Bus.snoop_fanout::total 838658 # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::total 838716 # Request fanout histogram